193db446aSBoris Brezillon // SPDX-License-Identifier: GPL-2.0 293db446aSBoris Brezillon /* 393db446aSBoris Brezillon * Marvell NAND flash controller driver 493db446aSBoris Brezillon * 593db446aSBoris Brezillon * Copyright (C) 2017 Marvell 693db446aSBoris Brezillon * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com> 793db446aSBoris Brezillon * 833c1c5feSMiquel Raynal * 933c1c5feSMiquel Raynal * This NAND controller driver handles two versions of the hardware, 1033c1c5feSMiquel Raynal * one is called NFCv1 and is available on PXA SoCs and the other is 1133c1c5feSMiquel Raynal * called NFCv2 and is available on Armada SoCs. 1233c1c5feSMiquel Raynal * 1333c1c5feSMiquel Raynal * The main visible difference is that NFCv1 only has Hamming ECC 1433c1c5feSMiquel Raynal * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA 1533c1c5feSMiquel Raynal * is not used with NFCv2. 1633c1c5feSMiquel Raynal * 1733c1c5feSMiquel Raynal * The ECC layouts are depicted in details in Marvell AN-379, but here 1833c1c5feSMiquel Raynal * is a brief description. 1933c1c5feSMiquel Raynal * 2033c1c5feSMiquel Raynal * When using Hamming, the data is split in 512B chunks (either 1, 2 2133c1c5feSMiquel Raynal * or 4) and each chunk will have its own ECC "digest" of 6B at the 2233c1c5feSMiquel Raynal * beginning of the OOB area and eventually the remaining free OOB 2333c1c5feSMiquel Raynal * bytes (also called "spare" bytes in the driver). This engine 2433c1c5feSMiquel Raynal * corrects up to 1 bit per chunk and detects reliably an error if 2533c1c5feSMiquel Raynal * there are at most 2 bitflips. Here is the page layout used by the 2633c1c5feSMiquel Raynal * controller when Hamming is chosen: 2733c1c5feSMiquel Raynal * 2833c1c5feSMiquel Raynal * +-------------------------------------------------------------+ 2933c1c5feSMiquel Raynal * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes | 3033c1c5feSMiquel Raynal * +-------------------------------------------------------------+ 3133c1c5feSMiquel Raynal * 3233c1c5feSMiquel Raynal * When using the BCH engine, there are N identical (data + free OOB + 3333c1c5feSMiquel Raynal * ECC) sections and potentially an extra one to deal with 3433c1c5feSMiquel Raynal * configurations where the chosen (data + free OOB + ECC) sizes do 3533c1c5feSMiquel Raynal * not align with the page (data + OOB) size. ECC bytes are always 3633c1c5feSMiquel Raynal * 30B per ECC chunk. Here is the page layout used by the controller 3733c1c5feSMiquel Raynal * when BCH is chosen: 3833c1c5feSMiquel Raynal * 3933c1c5feSMiquel Raynal * +----------------------------------------- 4033c1c5feSMiquel Raynal * | Data 1 | Free OOB bytes 1 | ECC 1 | ... 4133c1c5feSMiquel Raynal * +----------------------------------------- 4233c1c5feSMiquel Raynal * 4333c1c5feSMiquel Raynal * ------------------------------------------- 4433c1c5feSMiquel Raynal * ... | Data N | Free OOB bytes N | ECC N | 4533c1c5feSMiquel Raynal * ------------------------------------------- 4633c1c5feSMiquel Raynal * 4733c1c5feSMiquel Raynal * --------------------------------------------+ 4833c1c5feSMiquel Raynal * Last Data | Last Free OOB bytes | Last ECC | 4933c1c5feSMiquel Raynal * --------------------------------------------+ 5033c1c5feSMiquel Raynal * 5133c1c5feSMiquel Raynal * In both cases, the layout seen by the user is always: all data 5233c1c5feSMiquel Raynal * first, then all free OOB bytes and finally all ECC bytes. With BCH, 5333c1c5feSMiquel Raynal * ECC bytes are 30B long and are padded with 0xFF to align on 32 5433c1c5feSMiquel Raynal * bytes. 5533c1c5feSMiquel Raynal * 5633c1c5feSMiquel Raynal * The controller has certain limitations that are handled by the 5733c1c5feSMiquel Raynal * driver: 5833c1c5feSMiquel Raynal * - It can only read 2k at a time. To overcome this limitation, the 5933c1c5feSMiquel Raynal * driver issues data cycles on the bus, without issuing new 6033c1c5feSMiquel Raynal * CMD + ADDR cycles. The Marvell term is "naked" operations. 6133c1c5feSMiquel Raynal * - The ECC strength in BCH mode cannot be tuned. It is fixed 16 6233c1c5feSMiquel Raynal * bits. What can be tuned is the ECC block size as long as it 6333c1c5feSMiquel Raynal * stays between 512B and 2kiB. It's usually chosen based on the 6433c1c5feSMiquel Raynal * chip ECC requirements. For instance, using 2kiB ECC chunks 6533c1c5feSMiquel Raynal * provides 4b/512B correctability. 6633c1c5feSMiquel Raynal * - The controller will always treat data bytes, free OOB bytes 6733c1c5feSMiquel Raynal * and ECC bytes in that order, no matter what the real layout is 6833c1c5feSMiquel Raynal * (which is usually all data then all OOB bytes). The 6933c1c5feSMiquel Raynal * marvell_nfc_layouts array below contains the currently 7033c1c5feSMiquel Raynal * supported layouts. 7133c1c5feSMiquel Raynal * - Because of these weird layouts, the Bad Block Markers can be 7233c1c5feSMiquel Raynal * located in data section. In this case, the NAND_BBT_NO_OOB_BBM 7333c1c5feSMiquel Raynal * option must be set to prevent scanning/writing bad block 7433c1c5feSMiquel Raynal * markers. 7593db446aSBoris Brezillon */ 7693db446aSBoris Brezillon 7793db446aSBoris Brezillon #include <linux/module.h> 7893db446aSBoris Brezillon #include <linux/clk.h> 7993db446aSBoris Brezillon #include <linux/mtd/rawnand.h> 8093db446aSBoris Brezillon #include <linux/of_platform.h> 8193db446aSBoris Brezillon #include <linux/iopoll.h> 8293db446aSBoris Brezillon #include <linux/interrupt.h> 8393db446aSBoris Brezillon #include <linux/slab.h> 8493db446aSBoris Brezillon #include <linux/mfd/syscon.h> 8593db446aSBoris Brezillon #include <linux/regmap.h> 8693db446aSBoris Brezillon #include <asm/unaligned.h> 8793db446aSBoris Brezillon 8893db446aSBoris Brezillon #include <linux/dmaengine.h> 8993db446aSBoris Brezillon #include <linux/dma-mapping.h> 9093db446aSBoris Brezillon #include <linux/dma/pxa-dma.h> 9193db446aSBoris Brezillon #include <linux/platform_data/mtd-nand-pxa3xx.h> 9293db446aSBoris Brezillon 9393db446aSBoris Brezillon /* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */ 9493db446aSBoris Brezillon #define FIFO_DEPTH 8 9593db446aSBoris Brezillon #define FIFO_REP(x) (x / sizeof(u32)) 9693db446aSBoris Brezillon #define BCH_SEQ_READS (32 / FIFO_DEPTH) 9793db446aSBoris Brezillon /* NFC does not support transfers of larger chunks at a time */ 9893db446aSBoris Brezillon #define MAX_CHUNK_SIZE 2112 9993db446aSBoris Brezillon /* NFCv1 cannot read more that 7 bytes of ID */ 10093db446aSBoris Brezillon #define NFCV1_READID_LEN 7 10193db446aSBoris Brezillon /* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */ 10293db446aSBoris Brezillon #define POLL_PERIOD 0 10393db446aSBoris Brezillon #define POLL_TIMEOUT 100000 10493db446aSBoris Brezillon /* Interrupt maximum wait period in ms */ 10593db446aSBoris Brezillon #define IRQ_TIMEOUT 1000 10693db446aSBoris Brezillon /* Latency in clock cycles between SoC pins and NFC logic */ 10793db446aSBoris Brezillon #define MIN_RD_DEL_CNT 3 10893db446aSBoris Brezillon /* Maximum number of contiguous address cycles */ 10993db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV1 5 11093db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV2 7 11193db446aSBoris Brezillon /* System control registers/bits to enable the NAND controller on some SoCs */ 11293db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX 0x208 11393db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0) 11493db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20) 11593db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21) 11693db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25) 11793db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL 0x220 11893db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2) 11993db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL 0x700 12093db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL_EN BIT(0) 12193db446aSBoris Brezillon 12293db446aSBoris Brezillon /* NAND controller data flash control register */ 12393db446aSBoris Brezillon #define NDCR 0x00 12493db446aSBoris Brezillon #define NDCR_ALL_INT GENMASK(11, 0) 12593db446aSBoris Brezillon #define NDCR_CS1_CMDDM BIT(7) 12693db446aSBoris Brezillon #define NDCR_CS0_CMDDM BIT(8) 12793db446aSBoris Brezillon #define NDCR_RDYM BIT(11) 12893db446aSBoris Brezillon #define NDCR_ND_ARB_EN BIT(12) 12993db446aSBoris Brezillon #define NDCR_RA_START BIT(15) 13093db446aSBoris Brezillon #define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16) 13193db446aSBoris Brezillon #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0) 13293db446aSBoris Brezillon #define NDCR_DWIDTH_M BIT(26) 13393db446aSBoris Brezillon #define NDCR_DWIDTH_C BIT(27) 13493db446aSBoris Brezillon #define NDCR_ND_RUN BIT(28) 13593db446aSBoris Brezillon #define NDCR_DMA_EN BIT(29) 13693db446aSBoris Brezillon #define NDCR_ECC_EN BIT(30) 13793db446aSBoris Brezillon #define NDCR_SPARE_EN BIT(31) 13893db446aSBoris Brezillon #define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \ 13993db446aSBoris Brezillon NDCR_DWIDTH_M | NDCR_DWIDTH_C)) 14093db446aSBoris Brezillon 14193db446aSBoris Brezillon /* NAND interface timing parameter 0 register */ 14293db446aSBoris Brezillon #define NDTR0 0x04 14393db446aSBoris Brezillon #define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0) 14493db446aSBoris Brezillon #define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3) 14593db446aSBoris Brezillon #define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3) 14693db446aSBoris Brezillon #define NDTR0_SEL_NRE_EDGE BIT(7) 14793db446aSBoris Brezillon #define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8) 14893db446aSBoris Brezillon #define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11) 14993db446aSBoris Brezillon #define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16) 15093db446aSBoris Brezillon #define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19) 15193db446aSBoris Brezillon #define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22) 15293db446aSBoris Brezillon #define NDTR0_SELCNTR BIT(26) 15393db446aSBoris Brezillon #define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27) 15493db446aSBoris Brezillon 15593db446aSBoris Brezillon /* NAND interface timing parameter 1 register */ 15693db446aSBoris Brezillon #define NDTR1 0x0C 15793db446aSBoris Brezillon #define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0) 15893db446aSBoris Brezillon #define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4) 15993db446aSBoris Brezillon #define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8) 16093db446aSBoris Brezillon #define NDTR1_PRESCALE BIT(14) 16193db446aSBoris Brezillon #define NDTR1_WAIT_MODE BIT(15) 16293db446aSBoris Brezillon #define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16) 16393db446aSBoris Brezillon 16493db446aSBoris Brezillon /* NAND controller status register */ 16593db446aSBoris Brezillon #define NDSR 0x14 16693db446aSBoris Brezillon #define NDSR_WRCMDREQ BIT(0) 16793db446aSBoris Brezillon #define NDSR_RDDREQ BIT(1) 16893db446aSBoris Brezillon #define NDSR_WRDREQ BIT(2) 16993db446aSBoris Brezillon #define NDSR_CORERR BIT(3) 17093db446aSBoris Brezillon #define NDSR_UNCERR BIT(4) 17193db446aSBoris Brezillon #define NDSR_CMDD(cs) BIT(8 - cs) 17293db446aSBoris Brezillon #define NDSR_RDY(rb) BIT(11 + rb) 17393db446aSBoris Brezillon #define NDSR_ERRCNT(x) ((x >> 16) & 0x1F) 17493db446aSBoris Brezillon 17593db446aSBoris Brezillon /* NAND ECC control register */ 17693db446aSBoris Brezillon #define NDECCCTRL 0x28 17793db446aSBoris Brezillon #define NDECCCTRL_BCH_EN BIT(0) 17893db446aSBoris Brezillon 17993db446aSBoris Brezillon /* NAND controller data buffer register */ 18093db446aSBoris Brezillon #define NDDB 0x40 18193db446aSBoris Brezillon 18293db446aSBoris Brezillon /* NAND controller command buffer 0 register */ 18393db446aSBoris Brezillon #define NDCB0 0x48 18493db446aSBoris Brezillon #define NDCB0_CMD1(x) ((x & 0xFF) << 0) 18593db446aSBoris Brezillon #define NDCB0_CMD2(x) ((x & 0xFF) << 8) 18693db446aSBoris Brezillon #define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16) 18793db446aSBoris Brezillon #define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7) 18893db446aSBoris Brezillon #define NDCB0_DBC BIT(19) 18993db446aSBoris Brezillon #define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21) 19093db446aSBoris Brezillon #define NDCB0_CSEL BIT(24) 19193db446aSBoris Brezillon #define NDCB0_RDY_BYP BIT(27) 19293db446aSBoris Brezillon #define NDCB0_LEN_OVRD BIT(28) 19393db446aSBoris Brezillon #define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29) 19493db446aSBoris Brezillon 19593db446aSBoris Brezillon /* NAND controller command buffer 1 register */ 19693db446aSBoris Brezillon #define NDCB1 0x4C 19793db446aSBoris Brezillon #define NDCB1_COLS(x) ((x & 0xFFFF) << 0) 19893db446aSBoris Brezillon #define NDCB1_ADDRS_PAGE(x) (x << 16) 19993db446aSBoris Brezillon 20093db446aSBoris Brezillon /* NAND controller command buffer 2 register */ 20193db446aSBoris Brezillon #define NDCB2 0x50 20293db446aSBoris Brezillon #define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0) 20393db446aSBoris Brezillon #define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0) 20493db446aSBoris Brezillon 20593db446aSBoris Brezillon /* NAND controller command buffer 3 register */ 20693db446aSBoris Brezillon #define NDCB3 0x54 20793db446aSBoris Brezillon #define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16) 20893db446aSBoris Brezillon #define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24) 20993db446aSBoris Brezillon 21093db446aSBoris Brezillon /* NAND controller command buffer 0 register 'type' and 'xtype' fields */ 21193db446aSBoris Brezillon #define TYPE_READ 0 21293db446aSBoris Brezillon #define TYPE_WRITE 1 21393db446aSBoris Brezillon #define TYPE_ERASE 2 21493db446aSBoris Brezillon #define TYPE_READ_ID 3 21593db446aSBoris Brezillon #define TYPE_STATUS 4 21693db446aSBoris Brezillon #define TYPE_RESET 5 21793db446aSBoris Brezillon #define TYPE_NAKED_CMD 6 21893db446aSBoris Brezillon #define TYPE_NAKED_ADDR 7 21993db446aSBoris Brezillon #define TYPE_MASK 7 22093db446aSBoris Brezillon #define XTYPE_MONOLITHIC_RW 0 22193db446aSBoris Brezillon #define XTYPE_LAST_NAKED_RW 1 22293db446aSBoris Brezillon #define XTYPE_FINAL_COMMAND 3 22393db446aSBoris Brezillon #define XTYPE_READ 4 22493db446aSBoris Brezillon #define XTYPE_WRITE_DISPATCH 4 22593db446aSBoris Brezillon #define XTYPE_NAKED_RW 5 22693db446aSBoris Brezillon #define XTYPE_COMMAND_DISPATCH 6 22793db446aSBoris Brezillon #define XTYPE_MASK 7 22893db446aSBoris Brezillon 22993db446aSBoris Brezillon /** 23093db446aSBoris Brezillon * Marvell ECC engine works differently than the others, in order to limit the 23193db446aSBoris Brezillon * size of the IP, hardware engineers chose to set a fixed strength at 16 bits 23293db446aSBoris Brezillon * per subpage, and depending on a the desired strength needed by the NAND chip, 23393db446aSBoris Brezillon * a particular layout mixing data/spare/ecc is defined, with a possible last 23493db446aSBoris Brezillon * chunk smaller that the others. 23593db446aSBoris Brezillon * 23693db446aSBoris Brezillon * @writesize: Full page size on which the layout applies 23793db446aSBoris Brezillon * @chunk: Desired ECC chunk size on which the layout applies 23893db446aSBoris Brezillon * @strength: Desired ECC strength (per chunk size bytes) on which the 23993db446aSBoris Brezillon * layout applies 24093db446aSBoris Brezillon * @nchunks: Total number of chunks 24193db446aSBoris Brezillon * @full_chunk_cnt: Number of full-sized chunks, which is the number of 24293db446aSBoris Brezillon * repetitions of the pattern: 24393db446aSBoris Brezillon * (data_bytes + spare_bytes + ecc_bytes). 24493db446aSBoris Brezillon * @data_bytes: Number of data bytes per chunk 24593db446aSBoris Brezillon * @spare_bytes: Number of spare bytes per chunk 24693db446aSBoris Brezillon * @ecc_bytes: Number of ecc bytes per chunk 24793db446aSBoris Brezillon * @last_data_bytes: Number of data bytes in the last chunk 24893db446aSBoris Brezillon * @last_spare_bytes: Number of spare bytes in the last chunk 24993db446aSBoris Brezillon * @last_ecc_bytes: Number of ecc bytes in the last chunk 25093db446aSBoris Brezillon */ 25193db446aSBoris Brezillon struct marvell_hw_ecc_layout { 25293db446aSBoris Brezillon /* Constraints */ 25393db446aSBoris Brezillon int writesize; 25493db446aSBoris Brezillon int chunk; 25593db446aSBoris Brezillon int strength; 25693db446aSBoris Brezillon /* Corresponding layout */ 25793db446aSBoris Brezillon int nchunks; 25893db446aSBoris Brezillon int full_chunk_cnt; 25993db446aSBoris Brezillon int data_bytes; 26093db446aSBoris Brezillon int spare_bytes; 26193db446aSBoris Brezillon int ecc_bytes; 26293db446aSBoris Brezillon int last_data_bytes; 26393db446aSBoris Brezillon int last_spare_bytes; 26493db446aSBoris Brezillon int last_ecc_bytes; 26593db446aSBoris Brezillon }; 26693db446aSBoris Brezillon 26793db446aSBoris Brezillon #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \ 26893db446aSBoris Brezillon { \ 26993db446aSBoris Brezillon .writesize = ws, \ 27093db446aSBoris Brezillon .chunk = dc, \ 27193db446aSBoris Brezillon .strength = ds, \ 27293db446aSBoris Brezillon .nchunks = nc, \ 27393db446aSBoris Brezillon .full_chunk_cnt = fcc, \ 27493db446aSBoris Brezillon .data_bytes = db, \ 27593db446aSBoris Brezillon .spare_bytes = sb, \ 27693db446aSBoris Brezillon .ecc_bytes = eb, \ 27793db446aSBoris Brezillon .last_data_bytes = ldb, \ 27893db446aSBoris Brezillon .last_spare_bytes = lsb, \ 27993db446aSBoris Brezillon .last_ecc_bytes = leb, \ 28093db446aSBoris Brezillon } 28193db446aSBoris Brezillon 28293db446aSBoris Brezillon /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */ 28393db446aSBoris Brezillon static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = { 28493db446aSBoris Brezillon MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0), 28593db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0), 28693db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0), 28793db446aSBoris Brezillon MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0), 28893db446aSBoris Brezillon MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30), 28993db446aSBoris Brezillon }; 29093db446aSBoris Brezillon 29193db446aSBoris Brezillon /** 29293db446aSBoris Brezillon * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection 29393db446aSBoris Brezillon * is made by a field in NDCB0 register, and in another field in NDCB2 register. 29493db446aSBoris Brezillon * The datasheet describes the logic with an error: ADDR5 field is once 29593db446aSBoris Brezillon * declared at the beginning of NDCB2, and another time at its end. Because the 29693db446aSBoris Brezillon * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical 29793db446aSBoris Brezillon * to use the last bit of this field instead of the first ones. 29893db446aSBoris Brezillon * 29993db446aSBoris Brezillon * @cs: Wanted CE lane. 30093db446aSBoris Brezillon * @ndcb0_csel: Value of the NDCB0 register with or without the flag 30193db446aSBoris Brezillon * selecting the wanted CE lane. This is set once when 30293db446aSBoris Brezillon * the Device Tree is probed. 30393db446aSBoris Brezillon * @rb: Ready/Busy pin for the flash chip 30493db446aSBoris Brezillon */ 30593db446aSBoris Brezillon struct marvell_nand_chip_sel { 30693db446aSBoris Brezillon unsigned int cs; 30793db446aSBoris Brezillon u32 ndcb0_csel; 30893db446aSBoris Brezillon unsigned int rb; 30993db446aSBoris Brezillon }; 31093db446aSBoris Brezillon 31193db446aSBoris Brezillon /** 31293db446aSBoris Brezillon * NAND chip structure: stores NAND chip device related information 31393db446aSBoris Brezillon * 31493db446aSBoris Brezillon * @chip: Base NAND chip structure 31593db446aSBoris Brezillon * @node: Used to store NAND chips into a list 31693db446aSBoris Brezillon * @layout NAND layout when using hardware ECC 31793db446aSBoris Brezillon * @ndcr: Controller register value for this NAND chip 31893db446aSBoris Brezillon * @ndtr0: Timing registers 0 value for this NAND chip 31993db446aSBoris Brezillon * @ndtr1: Timing registers 1 value for this NAND chip 32093db446aSBoris Brezillon * @selected_die: Current active CS 32193db446aSBoris Brezillon * @nsels: Number of CS lines required by the NAND chip 32293db446aSBoris Brezillon * @sels: Array of CS lines descriptions 32393db446aSBoris Brezillon */ 32493db446aSBoris Brezillon struct marvell_nand_chip { 32593db446aSBoris Brezillon struct nand_chip chip; 32693db446aSBoris Brezillon struct list_head node; 32793db446aSBoris Brezillon const struct marvell_hw_ecc_layout *layout; 32893db446aSBoris Brezillon u32 ndcr; 32993db446aSBoris Brezillon u32 ndtr0; 33093db446aSBoris Brezillon u32 ndtr1; 33193db446aSBoris Brezillon int addr_cyc; 33293db446aSBoris Brezillon int selected_die; 33393db446aSBoris Brezillon unsigned int nsels; 33493db446aSBoris Brezillon struct marvell_nand_chip_sel sels[0]; 33593db446aSBoris Brezillon }; 33693db446aSBoris Brezillon 33793db446aSBoris Brezillon static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip) 33893db446aSBoris Brezillon { 33993db446aSBoris Brezillon return container_of(chip, struct marvell_nand_chip, chip); 34093db446aSBoris Brezillon } 34193db446aSBoris Brezillon 34293db446aSBoris Brezillon static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip 34393db446aSBoris Brezillon *nand) 34493db446aSBoris Brezillon { 34593db446aSBoris Brezillon return &nand->sels[nand->selected_die]; 34693db446aSBoris Brezillon } 34793db446aSBoris Brezillon 34893db446aSBoris Brezillon /** 34993db446aSBoris Brezillon * NAND controller capabilities for distinction between compatible strings 35093db446aSBoris Brezillon * 35193db446aSBoris Brezillon * @max_cs_nb: Number of Chip Select lines available 35293db446aSBoris Brezillon * @max_rb_nb: Number of Ready/Busy lines available 35393db446aSBoris Brezillon * @need_system_controller: Indicates if the SoC needs to have access to the 35493db446aSBoris Brezillon * system controller (ie. to enable the NAND controller) 35593db446aSBoris Brezillon * @legacy_of_bindings: Indicates if DT parsing must be done using the old 35693db446aSBoris Brezillon * fashion way 35793db446aSBoris Brezillon * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie. 35893db446aSBoris Brezillon * BCH error detection and correction algorithm, 35993db446aSBoris Brezillon * NDCB3 register has been added 36093db446aSBoris Brezillon * @use_dma: Use dma for data transfers 36193db446aSBoris Brezillon */ 36293db446aSBoris Brezillon struct marvell_nfc_caps { 36393db446aSBoris Brezillon unsigned int max_cs_nb; 36493db446aSBoris Brezillon unsigned int max_rb_nb; 36593db446aSBoris Brezillon bool need_system_controller; 36693db446aSBoris Brezillon bool legacy_of_bindings; 36793db446aSBoris Brezillon bool is_nfcv2; 36893db446aSBoris Brezillon bool use_dma; 36993db446aSBoris Brezillon }; 37093db446aSBoris Brezillon 37193db446aSBoris Brezillon /** 37293db446aSBoris Brezillon * NAND controller structure: stores Marvell NAND controller information 37393db446aSBoris Brezillon * 37493db446aSBoris Brezillon * @controller: Base controller structure 37593db446aSBoris Brezillon * @dev: Parent device (used to print error messages) 37693db446aSBoris Brezillon * @regs: NAND controller registers 3776b6de654SBoris Brezillon * @core_clk: Core clock 378961ba15cSGregory CLEMENT * @reg_clk: Regiters clock 37993db446aSBoris Brezillon * @complete: Completion object to wait for NAND controller events 38093db446aSBoris Brezillon * @assigned_cs: Bitmask describing already assigned CS lines 38193db446aSBoris Brezillon * @chips: List containing all the NAND chips attached to 38293db446aSBoris Brezillon * this NAND controller 38393db446aSBoris Brezillon * @caps: NAND controller capabilities for each compatible string 38493db446aSBoris Brezillon * @dma_chan: DMA channel (NFCv1 only) 38593db446aSBoris Brezillon * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only) 38693db446aSBoris Brezillon */ 38793db446aSBoris Brezillon struct marvell_nfc { 3887da45139SMiquel Raynal struct nand_controller controller; 38993db446aSBoris Brezillon struct device *dev; 39093db446aSBoris Brezillon void __iomem *regs; 3916b6de654SBoris Brezillon struct clk *core_clk; 392961ba15cSGregory CLEMENT struct clk *reg_clk; 39393db446aSBoris Brezillon struct completion complete; 39493db446aSBoris Brezillon unsigned long assigned_cs; 39593db446aSBoris Brezillon struct list_head chips; 39693db446aSBoris Brezillon struct nand_chip *selected_chip; 39793db446aSBoris Brezillon const struct marvell_nfc_caps *caps; 39893db446aSBoris Brezillon 39993db446aSBoris Brezillon /* DMA (NFCv1 only) */ 40093db446aSBoris Brezillon bool use_dma; 40193db446aSBoris Brezillon struct dma_chan *dma_chan; 40293db446aSBoris Brezillon u8 *dma_buf; 40393db446aSBoris Brezillon }; 40493db446aSBoris Brezillon 4057da45139SMiquel Raynal static inline struct marvell_nfc *to_marvell_nfc(struct nand_controller *ctrl) 40693db446aSBoris Brezillon { 40793db446aSBoris Brezillon return container_of(ctrl, struct marvell_nfc, controller); 40893db446aSBoris Brezillon } 40993db446aSBoris Brezillon 41093db446aSBoris Brezillon /** 41193db446aSBoris Brezillon * NAND controller timings expressed in NAND Controller clock cycles 41293db446aSBoris Brezillon * 41393db446aSBoris Brezillon * @tRP: ND_nRE pulse width 41493db446aSBoris Brezillon * @tRH: ND_nRE high duration 41593db446aSBoris Brezillon * @tWP: ND_nWE pulse time 41693db446aSBoris Brezillon * @tWH: ND_nWE high duration 41793db446aSBoris Brezillon * @tCS: Enable signal setup time 41893db446aSBoris Brezillon * @tCH: Enable signal hold time 41993db446aSBoris Brezillon * @tADL: Address to write data delay 42093db446aSBoris Brezillon * @tAR: ND_ALE low to ND_nRE low delay 42193db446aSBoris Brezillon * @tWHR: ND_nWE high to ND_nRE low for status read 42293db446aSBoris Brezillon * @tRHW: ND_nRE high duration, read to write delay 42393db446aSBoris Brezillon * @tR: ND_nWE high to ND_nRE low for read 42493db446aSBoris Brezillon */ 42593db446aSBoris Brezillon struct marvell_nfc_timings { 42693db446aSBoris Brezillon /* NDTR0 fields */ 42793db446aSBoris Brezillon unsigned int tRP; 42893db446aSBoris Brezillon unsigned int tRH; 42993db446aSBoris Brezillon unsigned int tWP; 43093db446aSBoris Brezillon unsigned int tWH; 43193db446aSBoris Brezillon unsigned int tCS; 43293db446aSBoris Brezillon unsigned int tCH; 43393db446aSBoris Brezillon unsigned int tADL; 43493db446aSBoris Brezillon /* NDTR1 fields */ 43593db446aSBoris Brezillon unsigned int tAR; 43693db446aSBoris Brezillon unsigned int tWHR; 43793db446aSBoris Brezillon unsigned int tRHW; 43893db446aSBoris Brezillon unsigned int tR; 43993db446aSBoris Brezillon }; 44093db446aSBoris Brezillon 44193db446aSBoris Brezillon /** 44293db446aSBoris Brezillon * Derives a duration in numbers of clock cycles. 44393db446aSBoris Brezillon * 44493db446aSBoris Brezillon * @ps: Duration in pico-seconds 44593db446aSBoris Brezillon * @period_ns: Clock period in nano-seconds 44693db446aSBoris Brezillon * 44793db446aSBoris Brezillon * Convert the duration in nano-seconds, then divide by the period and 44893db446aSBoris Brezillon * return the number of clock periods. 44993db446aSBoris Brezillon */ 45093db446aSBoris Brezillon #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns)) 45193db446aSBoris Brezillon #define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \ 45293db446aSBoris Brezillon period_ns)) 45393db446aSBoris Brezillon 45493db446aSBoris Brezillon /** 45593db446aSBoris Brezillon * NAND driver structure filled during the parsing of the ->exec_op() subop 45693db446aSBoris Brezillon * subset of instructions. 45793db446aSBoris Brezillon * 45893db446aSBoris Brezillon * @ndcb: Array of values written to NDCBx registers 45993db446aSBoris Brezillon * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle 46093db446aSBoris Brezillon * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin 46193db446aSBoris Brezillon * @rdy_delay_ns: Optional delay after waiting for the RB pin 46293db446aSBoris Brezillon * @data_delay_ns: Optional delay after the data xfer 46393db446aSBoris Brezillon * @data_instr_idx: Index of the data instruction in the subop 46493db446aSBoris Brezillon * @data_instr: Pointer to the data instruction in the subop 46593db446aSBoris Brezillon */ 46693db446aSBoris Brezillon struct marvell_nfc_op { 46793db446aSBoris Brezillon u32 ndcb[4]; 46893db446aSBoris Brezillon unsigned int cle_ale_delay_ns; 46993db446aSBoris Brezillon unsigned int rdy_timeout_ms; 47093db446aSBoris Brezillon unsigned int rdy_delay_ns; 47193db446aSBoris Brezillon unsigned int data_delay_ns; 47293db446aSBoris Brezillon unsigned int data_instr_idx; 47393db446aSBoris Brezillon const struct nand_op_instr *data_instr; 47493db446aSBoris Brezillon }; 47593db446aSBoris Brezillon 47693db446aSBoris Brezillon /* 47793db446aSBoris Brezillon * Internal helper to conditionnally apply a delay (from the above structure, 47893db446aSBoris Brezillon * most of the time). 47993db446aSBoris Brezillon */ 48093db446aSBoris Brezillon static void cond_delay(unsigned int ns) 48193db446aSBoris Brezillon { 48293db446aSBoris Brezillon if (!ns) 48393db446aSBoris Brezillon return; 48493db446aSBoris Brezillon 48593db446aSBoris Brezillon if (ns < 10000) 48693db446aSBoris Brezillon ndelay(ns); 48793db446aSBoris Brezillon else 48893db446aSBoris Brezillon udelay(DIV_ROUND_UP(ns, 1000)); 48993db446aSBoris Brezillon } 49093db446aSBoris Brezillon 49193db446aSBoris Brezillon /* 49293db446aSBoris Brezillon * The controller has many flags that could generate interrupts, most of them 49393db446aSBoris Brezillon * are disabled and polling is used. For the very slow signals, using interrupts 49493db446aSBoris Brezillon * may relax the CPU charge. 49593db446aSBoris Brezillon */ 49693db446aSBoris Brezillon static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask) 49793db446aSBoris Brezillon { 49893db446aSBoris Brezillon u32 reg; 49993db446aSBoris Brezillon 50093db446aSBoris Brezillon /* Writing 1 disables the interrupt */ 50193db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 50293db446aSBoris Brezillon writel_relaxed(reg | int_mask, nfc->regs + NDCR); 50393db446aSBoris Brezillon } 50493db446aSBoris Brezillon 50593db446aSBoris Brezillon static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask) 50693db446aSBoris Brezillon { 50793db446aSBoris Brezillon u32 reg; 50893db446aSBoris Brezillon 50993db446aSBoris Brezillon /* Writing 0 enables the interrupt */ 51093db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 51193db446aSBoris Brezillon writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); 51293db446aSBoris Brezillon } 51393db446aSBoris Brezillon 51493db446aSBoris Brezillon static void marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask) 51593db446aSBoris Brezillon { 51693db446aSBoris Brezillon writel_relaxed(int_mask, nfc->regs + NDSR); 51793db446aSBoris Brezillon } 51893db446aSBoris Brezillon 51993db446aSBoris Brezillon static void marvell_nfc_force_byte_access(struct nand_chip *chip, 52093db446aSBoris Brezillon bool force_8bit) 52193db446aSBoris Brezillon { 52293db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 52393db446aSBoris Brezillon u32 ndcr; 52493db446aSBoris Brezillon 52593db446aSBoris Brezillon /* 52693db446aSBoris Brezillon * Callers of this function do not verify if the NAND is using a 16-bit 52793db446aSBoris Brezillon * an 8-bit bus for normal operations, so we need to take care of that 52893db446aSBoris Brezillon * here by leaving the configuration unchanged if the NAND does not have 52993db446aSBoris Brezillon * the NAND_BUSWIDTH_16 flag set. 53093db446aSBoris Brezillon */ 53193db446aSBoris Brezillon if (!(chip->options & NAND_BUSWIDTH_16)) 53293db446aSBoris Brezillon return; 53393db446aSBoris Brezillon 53493db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR); 53593db446aSBoris Brezillon 53693db446aSBoris Brezillon if (force_8bit) 53793db446aSBoris Brezillon ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C); 53893db446aSBoris Brezillon else 53993db446aSBoris Brezillon ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 54093db446aSBoris Brezillon 54193db446aSBoris Brezillon writel_relaxed(ndcr, nfc->regs + NDCR); 54293db446aSBoris Brezillon } 54393db446aSBoris Brezillon 54493db446aSBoris Brezillon static int marvell_nfc_wait_ndrun(struct nand_chip *chip) 54593db446aSBoris Brezillon { 54693db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 54793db446aSBoris Brezillon u32 val; 54893db446aSBoris Brezillon int ret; 54993db446aSBoris Brezillon 55093db446aSBoris Brezillon /* 55193db446aSBoris Brezillon * The command is being processed, wait for the ND_RUN bit to be 55293db446aSBoris Brezillon * cleared by the NFC. If not, we must clear it by hand. 55393db446aSBoris Brezillon */ 55493db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, 55593db446aSBoris Brezillon (val & NDCR_ND_RUN) == 0, 55693db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 55793db446aSBoris Brezillon if (ret) { 55893db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on NAND controller run mode\n"); 55993db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 56093db446aSBoris Brezillon nfc->regs + NDCR); 56193db446aSBoris Brezillon return ret; 56293db446aSBoris Brezillon } 56393db446aSBoris Brezillon 56493db446aSBoris Brezillon return 0; 56593db446aSBoris Brezillon } 56693db446aSBoris Brezillon 56793db446aSBoris Brezillon /* 56893db446aSBoris Brezillon * Any time a command has to be sent to the controller, the following sequence 56993db446aSBoris Brezillon * has to be followed: 57093db446aSBoris Brezillon * - call marvell_nfc_prepare_cmd() 57193db446aSBoris Brezillon * -> activate the ND_RUN bit that will kind of 'start a job' 57293db446aSBoris Brezillon * -> wait the signal indicating the NFC is waiting for a command 57393db446aSBoris Brezillon * - send the command (cmd and address cycles) 57493db446aSBoris Brezillon * - enventually send or receive the data 57593db446aSBoris Brezillon * - call marvell_nfc_end_cmd() with the corresponding flag 57693db446aSBoris Brezillon * -> wait the flag to be triggered or cancel the job with a timeout 57793db446aSBoris Brezillon * 57893db446aSBoris Brezillon * The following helpers are here to factorize the code a bit so that 57993db446aSBoris Brezillon * specialized functions responsible for executing the actual NAND 58093db446aSBoris Brezillon * operations do not have to replicate the same code blocks. 58193db446aSBoris Brezillon */ 58293db446aSBoris Brezillon static int marvell_nfc_prepare_cmd(struct nand_chip *chip) 58393db446aSBoris Brezillon { 58493db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 58593db446aSBoris Brezillon u32 ndcr, val; 58693db446aSBoris Brezillon int ret; 58793db446aSBoris Brezillon 58893db446aSBoris Brezillon /* Poll ND_RUN and clear NDSR before issuing any command */ 58993db446aSBoris Brezillon ret = marvell_nfc_wait_ndrun(chip); 59093db446aSBoris Brezillon if (ret) { 59193db446aSBoris Brezillon dev_err(nfc->dev, "Last operation did not succeed\n"); 59293db446aSBoris Brezillon return ret; 59393db446aSBoris Brezillon } 59493db446aSBoris Brezillon 59593db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR); 59693db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR); 59793db446aSBoris Brezillon 59893db446aSBoris Brezillon /* Assert ND_RUN bit and wait the NFC to be ready */ 59993db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR); 60093db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 60193db446aSBoris Brezillon val & NDSR_WRCMDREQ, 60293db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 60393db446aSBoris Brezillon if (ret) { 60493db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on WRCMDRE\n"); 60593db446aSBoris Brezillon return -ETIMEDOUT; 60693db446aSBoris Brezillon } 60793db446aSBoris Brezillon 60893db446aSBoris Brezillon /* Command may be written, clear WRCMDREQ status bit */ 60993db446aSBoris Brezillon writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR); 61093db446aSBoris Brezillon 61193db446aSBoris Brezillon return 0; 61293db446aSBoris Brezillon } 61393db446aSBoris Brezillon 61493db446aSBoris Brezillon static void marvell_nfc_send_cmd(struct nand_chip *chip, 61593db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 61693db446aSBoris Brezillon { 61793db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 61893db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 61993db446aSBoris Brezillon 62093db446aSBoris Brezillon dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n" 62193db446aSBoris Brezillon "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n", 62293db446aSBoris Brezillon (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0], 62393db446aSBoris Brezillon nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]); 62493db446aSBoris Brezillon 62593db446aSBoris Brezillon writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0], 62693db446aSBoris Brezillon nfc->regs + NDCB0); 62793db446aSBoris Brezillon writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0); 62893db446aSBoris Brezillon writel(nfc_op->ndcb[2], nfc->regs + NDCB0); 62993db446aSBoris Brezillon 63093db446aSBoris Brezillon /* 63193db446aSBoris Brezillon * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7 63293db446aSBoris Brezillon * fields are used (only available on NFCv2). 63393db446aSBoris Brezillon */ 63493db446aSBoris Brezillon if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD || 63593db446aSBoris Brezillon NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) { 63693db446aSBoris Brezillon if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2)) 63793db446aSBoris Brezillon writel(nfc_op->ndcb[3], nfc->regs + NDCB0); 63893db446aSBoris Brezillon } 63993db446aSBoris Brezillon } 64093db446aSBoris Brezillon 64193db446aSBoris Brezillon static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag, 64293db446aSBoris Brezillon const char *label) 64393db446aSBoris Brezillon { 64493db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 64593db446aSBoris Brezillon u32 val; 64693db446aSBoris Brezillon int ret; 64793db446aSBoris Brezillon 64893db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 64993db446aSBoris Brezillon val & flag, 65093db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 65193db446aSBoris Brezillon 65293db446aSBoris Brezillon if (ret) { 65393db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n", 65493db446aSBoris Brezillon label, val); 65593db446aSBoris Brezillon if (nfc->dma_chan) 65693db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 65793db446aSBoris Brezillon return ret; 65893db446aSBoris Brezillon } 65993db446aSBoris Brezillon 66093db446aSBoris Brezillon /* 66193db446aSBoris Brezillon * DMA function uses this helper to poll on CMDD bits without wanting 66293db446aSBoris Brezillon * them to be cleared. 66393db446aSBoris Brezillon */ 66493db446aSBoris Brezillon if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN)) 66593db446aSBoris Brezillon return 0; 66693db446aSBoris Brezillon 66793db446aSBoris Brezillon writel_relaxed(flag, nfc->regs + NDSR); 66893db446aSBoris Brezillon 66993db446aSBoris Brezillon return 0; 67093db446aSBoris Brezillon } 67193db446aSBoris Brezillon 67293db446aSBoris Brezillon static int marvell_nfc_wait_cmdd(struct nand_chip *chip) 67393db446aSBoris Brezillon { 67493db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 67593db446aSBoris Brezillon int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel); 67693db446aSBoris Brezillon 67793db446aSBoris Brezillon return marvell_nfc_end_cmd(chip, cs_flag, "CMDD"); 67893db446aSBoris Brezillon } 67993db446aSBoris Brezillon 68093db446aSBoris Brezillon static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms) 68193db446aSBoris Brezillon { 68293db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 68393db446aSBoris Brezillon int ret; 68493db446aSBoris Brezillon 68593db446aSBoris Brezillon /* Timeout is expressed in ms */ 68693db446aSBoris Brezillon if (!timeout_ms) 68793db446aSBoris Brezillon timeout_ms = IRQ_TIMEOUT; 68893db446aSBoris Brezillon 68993db446aSBoris Brezillon init_completion(&nfc->complete); 69093db446aSBoris Brezillon 69193db446aSBoris Brezillon marvell_nfc_enable_int(nfc, NDCR_RDYM); 69293db446aSBoris Brezillon ret = wait_for_completion_timeout(&nfc->complete, 69393db446aSBoris Brezillon msecs_to_jiffies(timeout_ms)); 69493db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_RDYM); 69593db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1)); 69693db446aSBoris Brezillon if (!ret) { 69793db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for RB signal\n"); 69893db446aSBoris Brezillon return -ETIMEDOUT; 69993db446aSBoris Brezillon } 70093db446aSBoris Brezillon 70193db446aSBoris Brezillon return 0; 70293db446aSBoris Brezillon } 70393db446aSBoris Brezillon 704758b56f5SBoris Brezillon static void marvell_nfc_select_chip(struct nand_chip *chip, int die_nr) 70593db446aSBoris Brezillon { 70693db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 70793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 70893db446aSBoris Brezillon u32 ndcr_generic; 70993db446aSBoris Brezillon 71093db446aSBoris Brezillon if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die) 71193db446aSBoris Brezillon return; 71293db446aSBoris Brezillon 71393db446aSBoris Brezillon if (die_nr < 0 || die_nr >= marvell_nand->nsels) { 71493db446aSBoris Brezillon nfc->selected_chip = NULL; 71593db446aSBoris Brezillon marvell_nand->selected_die = -1; 71693db446aSBoris Brezillon return; 71793db446aSBoris Brezillon } 71893db446aSBoris Brezillon 71993db446aSBoris Brezillon writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0); 72093db446aSBoris Brezillon writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); 72193db446aSBoris Brezillon 72293db446aSBoris Brezillon /* 72393db446aSBoris Brezillon * Reset the NDCR register to a clean state for this particular chip, 72493db446aSBoris Brezillon * also clear ND_RUN bit. 72593db446aSBoris Brezillon */ 72693db446aSBoris Brezillon ndcr_generic = readl_relaxed(nfc->regs + NDCR) & 72793db446aSBoris Brezillon NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN; 72893db446aSBoris Brezillon writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR); 72993db446aSBoris Brezillon 73093db446aSBoris Brezillon /* Also reset the interrupt status register */ 73193db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 73293db446aSBoris Brezillon 73393db446aSBoris Brezillon nfc->selected_chip = chip; 73493db446aSBoris Brezillon marvell_nand->selected_die = die_nr; 73593db446aSBoris Brezillon } 73693db446aSBoris Brezillon 73793db446aSBoris Brezillon static irqreturn_t marvell_nfc_isr(int irq, void *dev_id) 73893db446aSBoris Brezillon { 73993db446aSBoris Brezillon struct marvell_nfc *nfc = dev_id; 74093db446aSBoris Brezillon u32 st = readl_relaxed(nfc->regs + NDSR); 74193db446aSBoris Brezillon u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT; 74293db446aSBoris Brezillon 74393db446aSBoris Brezillon /* 74493db446aSBoris Brezillon * RDY interrupt mask is one bit in NDCR while there are two status 74593db446aSBoris Brezillon * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]). 74693db446aSBoris Brezillon */ 74793db446aSBoris Brezillon if (st & NDSR_RDY(1)) 74893db446aSBoris Brezillon st |= NDSR_RDY(0); 74993db446aSBoris Brezillon 75093db446aSBoris Brezillon if (!(st & ien)) 75193db446aSBoris Brezillon return IRQ_NONE; 75293db446aSBoris Brezillon 75393db446aSBoris Brezillon marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT); 75493db446aSBoris Brezillon 75593db446aSBoris Brezillon if (!(st & (NDSR_RDDREQ | NDSR_WRDREQ | NDSR_WRCMDREQ))) 75693db446aSBoris Brezillon complete(&nfc->complete); 75793db446aSBoris Brezillon 75893db446aSBoris Brezillon return IRQ_HANDLED; 75993db446aSBoris Brezillon } 76093db446aSBoris Brezillon 76193db446aSBoris Brezillon /* HW ECC related functions */ 76293db446aSBoris Brezillon static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip) 76393db446aSBoris Brezillon { 76493db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 76593db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR); 76693db446aSBoris Brezillon 76793db446aSBoris Brezillon if (!(ndcr & NDCR_ECC_EN)) { 76893db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR); 76993db446aSBoris Brezillon 77093db446aSBoris Brezillon /* 77193db446aSBoris Brezillon * When enabling BCH, set threshold to 0 to always know the 77293db446aSBoris Brezillon * number of corrected bitflips. 77393db446aSBoris Brezillon */ 77493db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_BCH) 77593db446aSBoris Brezillon writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); 77693db446aSBoris Brezillon } 77793db446aSBoris Brezillon } 77893db446aSBoris Brezillon 77993db446aSBoris Brezillon static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip) 78093db446aSBoris Brezillon { 78193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 78293db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR); 78393db446aSBoris Brezillon 78493db446aSBoris Brezillon if (ndcr & NDCR_ECC_EN) { 78593db446aSBoris Brezillon writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); 78693db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_BCH) 78793db446aSBoris Brezillon writel_relaxed(0, nfc->regs + NDECCCTRL); 78893db446aSBoris Brezillon } 78993db446aSBoris Brezillon } 79093db446aSBoris Brezillon 79193db446aSBoris Brezillon /* DMA related helpers */ 79293db446aSBoris Brezillon static void marvell_nfc_enable_dma(struct marvell_nfc *nfc) 79393db446aSBoris Brezillon { 79493db446aSBoris Brezillon u32 reg; 79593db446aSBoris Brezillon 79693db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 79793db446aSBoris Brezillon writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); 79893db446aSBoris Brezillon } 79993db446aSBoris Brezillon 80093db446aSBoris Brezillon static void marvell_nfc_disable_dma(struct marvell_nfc *nfc) 80193db446aSBoris Brezillon { 80293db446aSBoris Brezillon u32 reg; 80393db446aSBoris Brezillon 80493db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 80593db446aSBoris Brezillon writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); 80693db446aSBoris Brezillon } 80793db446aSBoris Brezillon 80893db446aSBoris Brezillon /* Read/write PIO/DMA accessors */ 80993db446aSBoris Brezillon static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc, 81093db446aSBoris Brezillon enum dma_data_direction direction, 81193db446aSBoris Brezillon unsigned int len) 81293db446aSBoris Brezillon { 81393db446aSBoris Brezillon unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE); 81493db446aSBoris Brezillon struct dma_async_tx_descriptor *tx; 81593db446aSBoris Brezillon struct scatterlist sg; 81693db446aSBoris Brezillon dma_cookie_t cookie; 81793db446aSBoris Brezillon int ret; 81893db446aSBoris Brezillon 81993db446aSBoris Brezillon marvell_nfc_enable_dma(nfc); 82093db446aSBoris Brezillon /* Prepare the DMA transfer */ 82193db446aSBoris Brezillon sg_init_one(&sg, nfc->dma_buf, dma_len); 82293db446aSBoris Brezillon dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 82393db446aSBoris Brezillon tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1, 82493db446aSBoris Brezillon direction == DMA_FROM_DEVICE ? 82593db446aSBoris Brezillon DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 82693db446aSBoris Brezillon DMA_PREP_INTERRUPT); 82793db446aSBoris Brezillon if (!tx) { 82893db446aSBoris Brezillon dev_err(nfc->dev, "Could not prepare DMA S/G list\n"); 82993db446aSBoris Brezillon return -ENXIO; 83093db446aSBoris Brezillon } 83193db446aSBoris Brezillon 83293db446aSBoris Brezillon /* Do the task and wait for it to finish */ 83393db446aSBoris Brezillon cookie = dmaengine_submit(tx); 83493db446aSBoris Brezillon ret = dma_submit_error(cookie); 83593db446aSBoris Brezillon if (ret) 83693db446aSBoris Brezillon return -EIO; 83793db446aSBoris Brezillon 83893db446aSBoris Brezillon dma_async_issue_pending(nfc->dma_chan); 83993db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(nfc->selected_chip); 84093db446aSBoris Brezillon dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 84193db446aSBoris Brezillon marvell_nfc_disable_dma(nfc); 84293db446aSBoris Brezillon if (ret) { 84393db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n", 84493db446aSBoris Brezillon dmaengine_tx_status(nfc->dma_chan, cookie, NULL)); 84593db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 84693db446aSBoris Brezillon return -ETIMEDOUT; 84793db446aSBoris Brezillon } 84893db446aSBoris Brezillon 84993db446aSBoris Brezillon return 0; 85093db446aSBoris Brezillon } 85193db446aSBoris Brezillon 85293db446aSBoris Brezillon static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in, 85393db446aSBoris Brezillon unsigned int len) 85493db446aSBoris Brezillon { 85593db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH; 85693db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 85793db446aSBoris Brezillon int i; 85893db446aSBoris Brezillon 85993db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 86093db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH)); 86193db446aSBoris Brezillon 86293db446aSBoris Brezillon if (last_len) { 86393db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH]; 86493db446aSBoris Brezillon 86593db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 86693db446aSBoris Brezillon memcpy(in + last_full_offset, tmp_buf, last_len); 86793db446aSBoris Brezillon } 86893db446aSBoris Brezillon 86993db446aSBoris Brezillon return 0; 87093db446aSBoris Brezillon } 87193db446aSBoris Brezillon 87293db446aSBoris Brezillon static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out, 87393db446aSBoris Brezillon unsigned int len) 87493db446aSBoris Brezillon { 87593db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH; 87693db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 87793db446aSBoris Brezillon int i; 87893db446aSBoris Brezillon 87993db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 88093db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH)); 88193db446aSBoris Brezillon 88293db446aSBoris Brezillon if (last_len) { 88393db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH]; 88493db446aSBoris Brezillon 88593db446aSBoris Brezillon memcpy(tmp_buf, out + last_full_offset, last_len); 88693db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 88793db446aSBoris Brezillon } 88893db446aSBoris Brezillon 88993db446aSBoris Brezillon return 0; 89093db446aSBoris Brezillon } 89193db446aSBoris Brezillon 89293db446aSBoris Brezillon static void marvell_nfc_check_empty_chunk(struct nand_chip *chip, 89393db446aSBoris Brezillon u8 *data, int data_len, 89493db446aSBoris Brezillon u8 *spare, int spare_len, 89593db446aSBoris Brezillon u8 *ecc, int ecc_len, 89693db446aSBoris Brezillon unsigned int *max_bitflips) 89793db446aSBoris Brezillon { 89893db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 89993db446aSBoris Brezillon int bf; 90093db446aSBoris Brezillon 90193db446aSBoris Brezillon /* 90293db446aSBoris Brezillon * Blank pages (all 0xFF) that have not been written may be recognized 90393db446aSBoris Brezillon * as bad if bitflips occur, so whenever an uncorrectable error occurs, 90493db446aSBoris Brezillon * check if the entire page (with ECC bytes) is actually blank or not. 90593db446aSBoris Brezillon */ 90693db446aSBoris Brezillon if (!data) 90793db446aSBoris Brezillon data_len = 0; 90893db446aSBoris Brezillon if (!spare) 90993db446aSBoris Brezillon spare_len = 0; 91093db446aSBoris Brezillon if (!ecc) 91193db446aSBoris Brezillon ecc_len = 0; 91293db446aSBoris Brezillon 91393db446aSBoris Brezillon bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len, 91493db446aSBoris Brezillon spare, spare_len, chip->ecc.strength); 91593db446aSBoris Brezillon if (bf < 0) { 91693db446aSBoris Brezillon mtd->ecc_stats.failed++; 91793db446aSBoris Brezillon return; 91893db446aSBoris Brezillon } 91993db446aSBoris Brezillon 92093db446aSBoris Brezillon /* Update the stats and max_bitflips */ 92193db446aSBoris Brezillon mtd->ecc_stats.corrected += bf; 92293db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 92393db446aSBoris Brezillon } 92493db446aSBoris Brezillon 92593db446aSBoris Brezillon /* 92693db446aSBoris Brezillon * Check a chunk is correct or not according to hardware ECC engine. 92793db446aSBoris Brezillon * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however 92893db446aSBoris Brezillon * mtd->ecc_stats.failure is not, the function will instead return a non-zero 92993db446aSBoris Brezillon * value indicating that a check on the emptyness of the subpage must be 93093db446aSBoris Brezillon * performed before declaring the subpage corrupted. 93193db446aSBoris Brezillon */ 93293db446aSBoris Brezillon static int marvell_nfc_hw_ecc_correct(struct nand_chip *chip, 93393db446aSBoris Brezillon unsigned int *max_bitflips) 93493db446aSBoris Brezillon { 93593db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 93693db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 93793db446aSBoris Brezillon int bf = 0; 93893db446aSBoris Brezillon u32 ndsr; 93993db446aSBoris Brezillon 94093db446aSBoris Brezillon ndsr = readl_relaxed(nfc->regs + NDSR); 94193db446aSBoris Brezillon 94293db446aSBoris Brezillon /* Check uncorrectable error flag */ 94393db446aSBoris Brezillon if (ndsr & NDSR_UNCERR) { 94493db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR); 94593db446aSBoris Brezillon 94693db446aSBoris Brezillon /* 94793db446aSBoris Brezillon * Do not increment ->ecc_stats.failed now, instead, return a 94893db446aSBoris Brezillon * non-zero value to indicate that this chunk was apparently 94993db446aSBoris Brezillon * bad, and it should be check to see if it empty or not. If 95093db446aSBoris Brezillon * the chunk (with ECC bytes) is not declared empty, the calling 95193db446aSBoris Brezillon * function must increment the failure count. 95293db446aSBoris Brezillon */ 95393db446aSBoris Brezillon return -EBADMSG; 95493db446aSBoris Brezillon } 95593db446aSBoris Brezillon 95693db446aSBoris Brezillon /* Check correctable error flag */ 95793db446aSBoris Brezillon if (ndsr & NDSR_CORERR) { 95893db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR); 95993db446aSBoris Brezillon 96093db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_BCH) 96193db446aSBoris Brezillon bf = NDSR_ERRCNT(ndsr); 96293db446aSBoris Brezillon else 96393db446aSBoris Brezillon bf = 1; 96493db446aSBoris Brezillon } 96593db446aSBoris Brezillon 96693db446aSBoris Brezillon /* Update the stats and max_bitflips */ 96793db446aSBoris Brezillon mtd->ecc_stats.corrected += bf; 96893db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 96993db446aSBoris Brezillon 97093db446aSBoris Brezillon return 0; 97193db446aSBoris Brezillon } 97293db446aSBoris Brezillon 97393db446aSBoris Brezillon /* Hamming read helpers */ 97493db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip, 97593db446aSBoris Brezillon u8 *data_buf, u8 *oob_buf, 97693db446aSBoris Brezillon bool raw, int page) 97793db446aSBoris Brezillon { 97893db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 97993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 98093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 98193db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 98293db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 98393db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 98493db446aSBoris Brezillon NDCB0_DBC | 98593db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) | 98693db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART), 98793db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 98893db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 98993db446aSBoris Brezillon }; 99093db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 99193db446aSBoris Brezillon int ret; 99293db446aSBoris Brezillon 99393db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */ 99493db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 99593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 99693db446aSBoris Brezillon 99793db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 99893db446aSBoris Brezillon if (ret) 99993db446aSBoris Brezillon return ret; 100093db446aSBoris Brezillon 100193db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 100293db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 100393db446aSBoris Brezillon "RDDREQ while draining FIFO (data/oob)"); 100493db446aSBoris Brezillon if (ret) 100593db446aSBoris Brezillon return ret; 100693db446aSBoris Brezillon 100793db446aSBoris Brezillon /* 100893db446aSBoris Brezillon * Read the page then the OOB area. Unlike what is shown in current 100993db446aSBoris Brezillon * documentation, spare bytes are protected by the ECC engine, and must 101093db446aSBoris Brezillon * be at the beginning of the OOB area or running this driver on legacy 101193db446aSBoris Brezillon * systems will prevent the discovery of the BBM/BBT. 101293db446aSBoris Brezillon */ 101393db446aSBoris Brezillon if (nfc->use_dma) { 101493db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE, 101593db446aSBoris Brezillon lt->data_bytes + oob_bytes); 101693db446aSBoris Brezillon memcpy(data_buf, nfc->dma_buf, lt->data_bytes); 101793db446aSBoris Brezillon memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); 101893db446aSBoris Brezillon } else { 101993db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); 102093db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes); 102193db446aSBoris Brezillon } 102293db446aSBoris Brezillon 102393db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 102493db446aSBoris Brezillon 102593db446aSBoris Brezillon return ret; 102693db446aSBoris Brezillon } 102793db446aSBoris Brezillon 1028b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct nand_chip *chip, u8 *buf, 102993db446aSBoris Brezillon int oob_required, int page) 103093db446aSBoris Brezillon { 103193db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, 103293db446aSBoris Brezillon true, page); 103393db446aSBoris Brezillon } 103493db446aSBoris Brezillon 1035b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page(struct nand_chip *chip, u8 *buf, 1036b9761687SBoris Brezillon int oob_required, int page) 103793db446aSBoris Brezillon { 103893db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 103993db446aSBoris Brezillon unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 104093db446aSBoris Brezillon int max_bitflips = 0, ret; 104193db446aSBoris Brezillon u8 *raw_buf; 104293db446aSBoris Brezillon 104393db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 104493db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false, 104593db446aSBoris Brezillon page); 104693db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips); 104793db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 104893db446aSBoris Brezillon 104993db446aSBoris Brezillon if (!ret) 105093db446aSBoris Brezillon return max_bitflips; 105193db446aSBoris Brezillon 105293db446aSBoris Brezillon /* 105393db446aSBoris Brezillon * When ECC failures are detected, check if the full page has been 105493db446aSBoris Brezillon * written or not. Ignore the failure if it is actually empty. 105593db446aSBoris Brezillon */ 105693db446aSBoris Brezillon raw_buf = kmalloc(full_sz, GFP_KERNEL); 105793db446aSBoris Brezillon if (!raw_buf) 105893db446aSBoris Brezillon return -ENOMEM; 105993db446aSBoris Brezillon 106093db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf + 106193db446aSBoris Brezillon lt->data_bytes, true, page); 106293db446aSBoris Brezillon marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0, 106393db446aSBoris Brezillon &max_bitflips); 106493db446aSBoris Brezillon kfree(raw_buf); 106593db446aSBoris Brezillon 106693db446aSBoris Brezillon return max_bitflips; 106793db446aSBoris Brezillon } 106893db446aSBoris Brezillon 106993db446aSBoris Brezillon /* 107093db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if 107193db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->read_oob_raw() function 107293db446aSBoris Brezillon * also stands for ->read_oob(). 107393db446aSBoris Brezillon */ 1074b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page) 107593db446aSBoris Brezillon { 107693db446aSBoris Brezillon /* Invalidate page cache */ 107793db446aSBoris Brezillon chip->pagebuf = -1; 107893db446aSBoris Brezillon 107993db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, chip->data_buf, 108093db446aSBoris Brezillon chip->oob_poi, true, page); 108193db446aSBoris Brezillon } 108293db446aSBoris Brezillon 108393db446aSBoris Brezillon /* Hamming write helpers */ 108493db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip, 108593db446aSBoris Brezillon const u8 *data_buf, 108693db446aSBoris Brezillon const u8 *oob_buf, bool raw, 108793db446aSBoris Brezillon int page) 108893db446aSBoris Brezillon { 108993db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 109093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 109193db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 109293db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 109393db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | 109493db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 109593db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN) | 109693db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_PAGEPROG) | 109793db446aSBoris Brezillon NDCB0_DBC, 109893db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 109993db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 110093db446aSBoris Brezillon }; 110193db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 110293db446aSBoris Brezillon int ret; 110393db446aSBoris Brezillon 110493db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */ 110593db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 110693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 110793db446aSBoris Brezillon 110893db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 110993db446aSBoris Brezillon if (ret) 111093db446aSBoris Brezillon return ret; 111193db446aSBoris Brezillon 111293db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 111393db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 111493db446aSBoris Brezillon "WRDREQ while loading FIFO (data)"); 111593db446aSBoris Brezillon if (ret) 111693db446aSBoris Brezillon return ret; 111793db446aSBoris Brezillon 111893db446aSBoris Brezillon /* Write the page then the OOB area */ 111993db446aSBoris Brezillon if (nfc->use_dma) { 112093db446aSBoris Brezillon memcpy(nfc->dma_buf, data_buf, lt->data_bytes); 112193db446aSBoris Brezillon memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); 112293db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + 112393db446aSBoris Brezillon lt->ecc_bytes + lt->spare_bytes); 112493db446aSBoris Brezillon } else { 112593db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); 112693db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes); 112793db446aSBoris Brezillon } 112893db446aSBoris Brezillon 112993db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 113093db446aSBoris Brezillon if (ret) 113193db446aSBoris Brezillon return ret; 113293db446aSBoris Brezillon 113393db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, 1134b76401fcSChris Packham PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); 113593db446aSBoris Brezillon return ret; 113693db446aSBoris Brezillon } 113793db446aSBoris Brezillon 1138767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip *chip, 113993db446aSBoris Brezillon const u8 *buf, 114093db446aSBoris Brezillon int oob_required, int page) 114193db446aSBoris Brezillon { 114293db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 114393db446aSBoris Brezillon true, page); 114493db446aSBoris Brezillon } 114593db446aSBoris Brezillon 1146767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page(struct nand_chip *chip, 114793db446aSBoris Brezillon const u8 *buf, 114893db446aSBoris Brezillon int oob_required, int page) 114993db446aSBoris Brezillon { 115093db446aSBoris Brezillon int ret; 115193db446aSBoris Brezillon 115293db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 115393db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 115493db446aSBoris Brezillon false, page); 115593db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 115693db446aSBoris Brezillon 115793db446aSBoris Brezillon return ret; 115893db446aSBoris Brezillon } 115993db446aSBoris Brezillon 116093db446aSBoris Brezillon /* 116193db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if 116293db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->write_oob_raw() function 116393db446aSBoris Brezillon * also stands for ->write_oob(). 116493db446aSBoris Brezillon */ 1165767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct nand_chip *chip, 116693db446aSBoris Brezillon int page) 116793db446aSBoris Brezillon { 1168767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 1169767eb6fbSBoris Brezillon 117093db446aSBoris Brezillon /* Invalidate page cache */ 117193db446aSBoris Brezillon chip->pagebuf = -1; 117293db446aSBoris Brezillon 117393db446aSBoris Brezillon memset(chip->data_buf, 0xFF, mtd->writesize); 117493db446aSBoris Brezillon 117593db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, chip->data_buf, 117693db446aSBoris Brezillon chip->oob_poi, true, page); 117793db446aSBoris Brezillon } 117893db446aSBoris Brezillon 117993db446aSBoris Brezillon /* BCH read helpers */ 1180b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page_raw(struct nand_chip *chip, u8 *buf, 118193db446aSBoris Brezillon int oob_required, int page) 118293db446aSBoris Brezillon { 1183b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 118493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 118593db446aSBoris Brezillon u8 *oob = chip->oob_poi; 118693db446aSBoris Brezillon int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 118793db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 118893db446aSBoris Brezillon lt->last_spare_bytes; 118993db446aSBoris Brezillon int data_len = lt->data_bytes; 119093db446aSBoris Brezillon int spare_len = lt->spare_bytes; 119193db446aSBoris Brezillon int ecc_len = lt->ecc_bytes; 119293db446aSBoris Brezillon int chunk; 119393db446aSBoris Brezillon 119493db446aSBoris Brezillon if (oob_required) 119593db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 119693db446aSBoris Brezillon 119793db446aSBoris Brezillon nand_read_page_op(chip, page, 0, NULL, 0); 119893db446aSBoris Brezillon 119993db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 120093db446aSBoris Brezillon /* Update last chunk length */ 120193db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 120293db446aSBoris Brezillon data_len = lt->last_data_bytes; 120393db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 120493db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes; 120593db446aSBoris Brezillon } 120693db446aSBoris Brezillon 120793db446aSBoris Brezillon /* Read data bytes*/ 120893db446aSBoris Brezillon nand_change_read_column_op(chip, chunk * chunk_size, 120993db446aSBoris Brezillon buf + (lt->data_bytes * chunk), 121093db446aSBoris Brezillon data_len, false); 121193db446aSBoris Brezillon 121293db446aSBoris Brezillon /* Read spare bytes */ 121393db446aSBoris Brezillon nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), 121493db446aSBoris Brezillon spare_len, false); 121593db446aSBoris Brezillon 121693db446aSBoris Brezillon /* Read ECC bytes */ 121793db446aSBoris Brezillon nand_read_data_op(chip, oob + ecc_offset + 121893db446aSBoris Brezillon (ALIGN(lt->ecc_bytes, 32) * chunk), 121993db446aSBoris Brezillon ecc_len, false); 122093db446aSBoris Brezillon } 122193db446aSBoris Brezillon 122293db446aSBoris Brezillon return 0; 122393db446aSBoris Brezillon } 122493db446aSBoris Brezillon 122593db446aSBoris Brezillon static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk, 122693db446aSBoris Brezillon u8 *data, unsigned int data_len, 122793db446aSBoris Brezillon u8 *spare, unsigned int spare_len, 122893db446aSBoris Brezillon int page) 122993db446aSBoris Brezillon { 123093db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 123193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 123293db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 123393db446aSBoris Brezillon int i, ret; 123493db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 123593db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 123693db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 123793db446aSBoris Brezillon NDCB0_LEN_OVRD, 123893db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 123993db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 124093db446aSBoris Brezillon .ndcb[3] = data_len + spare_len, 124193db446aSBoris Brezillon }; 124293db446aSBoris Brezillon 124393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 124493db446aSBoris Brezillon if (ret) 124593db446aSBoris Brezillon return; 124693db446aSBoris Brezillon 124793db446aSBoris Brezillon if (chunk == 0) 124893db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_DBC | 124993db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) | 125093db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART); 125193db446aSBoris Brezillon 125293db446aSBoris Brezillon /* 125390d61763SBoris Brezillon * Trigger the monolithic read on the first chunk, then naked read on 125490d61763SBoris Brezillon * intermediate chunks and finally a last naked read on the last chunk. 125593db446aSBoris Brezillon */ 125690d61763SBoris Brezillon if (chunk == 0) 125793db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 125890d61763SBoris Brezillon else if (chunk < lt->nchunks - 1) 125990d61763SBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 126093db446aSBoris Brezillon else 126193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 126293db446aSBoris Brezillon 126393db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 126493db446aSBoris Brezillon 126593db446aSBoris Brezillon /* 126693db446aSBoris Brezillon * According to the datasheet, when reading from NDDB 126793db446aSBoris Brezillon * with BCH enabled, after each 32 bytes reads, we 126893db446aSBoris Brezillon * have to make sure that the NDSR.RDDREQ bit is set. 126993db446aSBoris Brezillon * 127093db446aSBoris Brezillon * Drain the FIFO, 8 32-bit reads at a time, and skip 127193db446aSBoris Brezillon * the polling on the last read. 127293db446aSBoris Brezillon * 127393db446aSBoris Brezillon * Length is a multiple of 32 bytes, hence it is a multiple of 8 too. 127493db446aSBoris Brezillon */ 127593db446aSBoris Brezillon for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 127693db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 127793db446aSBoris Brezillon "RDDREQ while draining FIFO (data)"); 127893db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data, 127993db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS); 128093db446aSBoris Brezillon data += FIFO_DEPTH * BCH_SEQ_READS; 128193db446aSBoris Brezillon } 128293db446aSBoris Brezillon 128393db446aSBoris Brezillon for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 128493db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 128593db446aSBoris Brezillon "RDDREQ while draining FIFO (OOB)"); 128693db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, spare, 128793db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS); 128893db446aSBoris Brezillon spare += FIFO_DEPTH * BCH_SEQ_READS; 128993db446aSBoris Brezillon } 129093db446aSBoris Brezillon } 129193db446aSBoris Brezillon 1292b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page(struct nand_chip *chip, 129393db446aSBoris Brezillon u8 *buf, int oob_required, 129493db446aSBoris Brezillon int page) 129593db446aSBoris Brezillon { 1296b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 129793db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1298dbfc6718SMiquel Raynal int data_len = lt->data_bytes, spare_len = lt->spare_bytes; 1299dbfc6718SMiquel Raynal u8 *data = buf, *spare = chip->oob_poi; 130093db446aSBoris Brezillon int max_bitflips = 0; 130193db446aSBoris Brezillon u32 failure_mask = 0; 1302dbfc6718SMiquel Raynal int chunk, ret; 130393db446aSBoris Brezillon 130493db446aSBoris Brezillon /* 130593db446aSBoris Brezillon * With BCH, OOB is not fully used (and thus not read entirely), not 130693db446aSBoris Brezillon * expected bytes could show up at the end of the OOB buffer if not 130793db446aSBoris Brezillon * explicitly erased. 130893db446aSBoris Brezillon */ 130993db446aSBoris Brezillon if (oob_required) 131093db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 131193db446aSBoris Brezillon 131293db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 131393db446aSBoris Brezillon 131493db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 131593db446aSBoris Brezillon /* Update length for the last chunk */ 131693db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 131793db446aSBoris Brezillon data_len = lt->last_data_bytes; 131893db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 131993db446aSBoris Brezillon } 132093db446aSBoris Brezillon 132193db446aSBoris Brezillon /* Read the chunk and detect number of bitflips */ 132293db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len, 132393db446aSBoris Brezillon spare, spare_len, page); 132493db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips); 132593db446aSBoris Brezillon if (ret) 132693db446aSBoris Brezillon failure_mask |= BIT(chunk); 132793db446aSBoris Brezillon 132893db446aSBoris Brezillon data += data_len; 132993db446aSBoris Brezillon spare += spare_len; 133093db446aSBoris Brezillon } 133193db446aSBoris Brezillon 133293db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 133393db446aSBoris Brezillon 133493db446aSBoris Brezillon if (!failure_mask) 133593db446aSBoris Brezillon return max_bitflips; 133693db446aSBoris Brezillon 133793db446aSBoris Brezillon /* 133893db446aSBoris Brezillon * Please note that dumping the ECC bytes during a normal read with OOB 133993db446aSBoris Brezillon * area would add a significant overhead as ECC bytes are "consumed" by 134093db446aSBoris Brezillon * the controller in normal mode and must be re-read in raw mode. To 134193db446aSBoris Brezillon * avoid dropping the performances, we prefer not to include them. The 134293db446aSBoris Brezillon * user should re-read the page in raw mode if ECC bytes are required. 1343dbfc6718SMiquel Raynal */ 1344dbfc6718SMiquel Raynal 1345dbfc6718SMiquel Raynal /* 1346dbfc6718SMiquel Raynal * In case there is any subpage read error reported by ->correct(), we 1347dbfc6718SMiquel Raynal * usually re-read only ECC bytes in raw mode and check if the whole 1348dbfc6718SMiquel Raynal * page is empty. In this case, it is normal that the ECC check failed 1349dbfc6718SMiquel Raynal * and we just ignore the error. 135093db446aSBoris Brezillon * 135193db446aSBoris Brezillon * However, for any subpage read error reported by ->correct(), the ECC 135293db446aSBoris Brezillon * bytes must be read in raw mode and the full subpage must be checked 135393db446aSBoris Brezillon * to see if it is entirely empty of if there was an actual error. 135493db446aSBoris Brezillon */ 135593db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 1356dbfc6718SMiquel Raynal int data_off_in_page, spare_off_in_page, ecc_off_in_page; 1357dbfc6718SMiquel Raynal int data_off, spare_off, ecc_off; 1358dbfc6718SMiquel Raynal int data_len, spare_len, ecc_len; 1359dbfc6718SMiquel Raynal 136093db446aSBoris Brezillon /* No failure reported for this chunk, move to the next one */ 136193db446aSBoris Brezillon if (!(failure_mask & BIT(chunk))) 136293db446aSBoris Brezillon continue; 136393db446aSBoris Brezillon 1364dbfc6718SMiquel Raynal data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes + 1365dbfc6718SMiquel Raynal lt->ecc_bytes); 1366dbfc6718SMiquel Raynal spare_off_in_page = data_off_in_page + 1367dbfc6718SMiquel Raynal (chunk < lt->full_chunk_cnt ? lt->data_bytes : 1368dbfc6718SMiquel Raynal lt->last_data_bytes); 1369dbfc6718SMiquel Raynal ecc_off_in_page = spare_off_in_page + 1370dbfc6718SMiquel Raynal (chunk < lt->full_chunk_cnt ? lt->spare_bytes : 1371dbfc6718SMiquel Raynal lt->last_spare_bytes); 1372dbfc6718SMiquel Raynal 1373dbfc6718SMiquel Raynal data_off = chunk * lt->data_bytes; 1374dbfc6718SMiquel Raynal spare_off = chunk * lt->spare_bytes; 1375dbfc6718SMiquel Raynal ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) + 137693db446aSBoris Brezillon lt->last_spare_bytes + 1377dbfc6718SMiquel Raynal (chunk * (lt->ecc_bytes + 2)); 137893db446aSBoris Brezillon 1379dbfc6718SMiquel Raynal data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes : 1380dbfc6718SMiquel Raynal lt->last_data_bytes; 1381dbfc6718SMiquel Raynal spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes : 1382dbfc6718SMiquel Raynal lt->last_spare_bytes; 1383dbfc6718SMiquel Raynal ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes : 1384dbfc6718SMiquel Raynal lt->last_ecc_bytes; 138593db446aSBoris Brezillon 1386dbfc6718SMiquel Raynal nand_change_read_column_op(chip, ecc_off_in_page, 1387dbfc6718SMiquel Raynal chip->oob_poi + ecc_off, ecc_len, 1388dbfc6718SMiquel Raynal false); 138993db446aSBoris Brezillon 139093db446aSBoris Brezillon /* Check the entire chunk (data + spare + ecc) for emptyness */ 1391dbfc6718SMiquel Raynal marvell_nfc_check_empty_chunk(chip, buf + data_off, data_len, 1392dbfc6718SMiquel Raynal chip->oob_poi + spare_off, spare_len, 1393dbfc6718SMiquel Raynal chip->oob_poi + ecc_off, ecc_len, 139493db446aSBoris Brezillon &max_bitflips); 139593db446aSBoris Brezillon } 139693db446aSBoris Brezillon 139793db446aSBoris Brezillon return max_bitflips; 139893db446aSBoris Brezillon } 139993db446aSBoris Brezillon 1400b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page) 140193db446aSBoris Brezillon { 140293db446aSBoris Brezillon /* Invalidate page cache */ 140393db446aSBoris Brezillon chip->pagebuf = -1; 140493db446aSBoris Brezillon 1405b9761687SBoris Brezillon return chip->ecc.read_page_raw(chip, chip->data_buf, true, page); 140693db446aSBoris Brezillon } 140793db446aSBoris Brezillon 1408b9761687SBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page) 140993db446aSBoris Brezillon { 141093db446aSBoris Brezillon /* Invalidate page cache */ 141193db446aSBoris Brezillon chip->pagebuf = -1; 141293db446aSBoris Brezillon 1413b9761687SBoris Brezillon return chip->ecc.read_page(chip, chip->data_buf, true, page); 141493db446aSBoris Brezillon } 141593db446aSBoris Brezillon 141693db446aSBoris Brezillon /* BCH write helpers */ 1417767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page_raw(struct nand_chip *chip, 141893db446aSBoris Brezillon const u8 *buf, 141993db446aSBoris Brezillon int oob_required, int page) 142093db446aSBoris Brezillon { 142193db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 142293db446aSBoris Brezillon int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 142393db446aSBoris Brezillon int data_len = lt->data_bytes; 142493db446aSBoris Brezillon int spare_len = lt->spare_bytes; 142593db446aSBoris Brezillon int ecc_len = lt->ecc_bytes; 142693db446aSBoris Brezillon int spare_offset = 0; 142793db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 142893db446aSBoris Brezillon lt->last_spare_bytes; 142993db446aSBoris Brezillon int chunk; 143093db446aSBoris Brezillon 143193db446aSBoris Brezillon nand_prog_page_begin_op(chip, page, 0, NULL, 0); 143293db446aSBoris Brezillon 143393db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 143493db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 143593db446aSBoris Brezillon data_len = lt->last_data_bytes; 143693db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 143793db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes; 143893db446aSBoris Brezillon } 143993db446aSBoris Brezillon 144093db446aSBoris Brezillon /* Point to the column of the next chunk */ 144193db446aSBoris Brezillon nand_change_write_column_op(chip, chunk * full_chunk_size, 144293db446aSBoris Brezillon NULL, 0, false); 144393db446aSBoris Brezillon 144493db446aSBoris Brezillon /* Write the data */ 144593db446aSBoris Brezillon nand_write_data_op(chip, buf + (chunk * lt->data_bytes), 144693db446aSBoris Brezillon data_len, false); 144793db446aSBoris Brezillon 144893db446aSBoris Brezillon if (!oob_required) 144993db446aSBoris Brezillon continue; 145093db446aSBoris Brezillon 145193db446aSBoris Brezillon /* Write the spare bytes */ 145293db446aSBoris Brezillon if (spare_len) 145393db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + spare_offset, 145493db446aSBoris Brezillon spare_len, false); 145593db446aSBoris Brezillon 145693db446aSBoris Brezillon /* Write the ECC bytes */ 145793db446aSBoris Brezillon if (ecc_len) 145893db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + ecc_offset, 145993db446aSBoris Brezillon ecc_len, false); 146093db446aSBoris Brezillon 146193db446aSBoris Brezillon spare_offset += spare_len; 146293db446aSBoris Brezillon ecc_offset += ALIGN(ecc_len, 32); 146393db446aSBoris Brezillon } 146493db446aSBoris Brezillon 146593db446aSBoris Brezillon return nand_prog_page_end_op(chip); 146693db446aSBoris Brezillon } 146793db446aSBoris Brezillon 146893db446aSBoris Brezillon static int 146993db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, 147093db446aSBoris Brezillon const u8 *data, unsigned int data_len, 147193db446aSBoris Brezillon const u8 *spare, unsigned int spare_len, 147293db446aSBoris Brezillon int page) 147393db446aSBoris Brezillon { 147493db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 147593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 147693db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1477a2ee41fdSMiquel Raynal u32 xtype; 147893db446aSBoris Brezillon int ret; 147993db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 148093db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD, 148193db446aSBoris Brezillon .ndcb[3] = data_len + spare_len, 148293db446aSBoris Brezillon }; 148393db446aSBoris Brezillon 148493db446aSBoris Brezillon /* 148593db446aSBoris Brezillon * First operation dispatches the CMD_SEQIN command, issue the address 148693db446aSBoris Brezillon * cycles and asks for the first chunk of data. 148793db446aSBoris Brezillon * All operations in the middle (if any) will issue a naked write and 148893db446aSBoris Brezillon * also ask for data. 148993db446aSBoris Brezillon * Last operation (if any) asks for the last chunk of data through a 149093db446aSBoris Brezillon * last naked write. 149193db446aSBoris Brezillon */ 149293db446aSBoris Brezillon if (chunk == 0) { 1493a2ee41fdSMiquel Raynal if (lt->nchunks == 1) 1494a2ee41fdSMiquel Raynal xtype = XTYPE_MONOLITHIC_RW; 1495a2ee41fdSMiquel Raynal else 1496a2ee41fdSMiquel Raynal xtype = XTYPE_WRITE_DISPATCH; 1497a2ee41fdSMiquel Raynal 1498a2ee41fdSMiquel Raynal nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) | 149993db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 150093db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN); 150193db446aSBoris Brezillon nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page); 150293db446aSBoris Brezillon nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page); 150393db446aSBoris Brezillon } else if (chunk < lt->nchunks - 1) { 150493db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 150593db446aSBoris Brezillon } else { 150693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 150793db446aSBoris Brezillon } 150893db446aSBoris Brezillon 150993db446aSBoris Brezillon /* Always dispatch the PAGEPROG command on the last chunk */ 151093db446aSBoris Brezillon if (chunk == lt->nchunks - 1) 151193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC; 151293db446aSBoris Brezillon 151393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 151493db446aSBoris Brezillon if (ret) 151593db446aSBoris Brezillon return ret; 151693db446aSBoris Brezillon 151793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 151893db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 151993db446aSBoris Brezillon "WRDREQ while loading FIFO (data)"); 152093db446aSBoris Brezillon if (ret) 152193db446aSBoris Brezillon return ret; 152293db446aSBoris Brezillon 152393db446aSBoris Brezillon /* Transfer the contents */ 152493db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len)); 152593db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len)); 152693db446aSBoris Brezillon 152793db446aSBoris Brezillon return 0; 152893db446aSBoris Brezillon } 152993db446aSBoris Brezillon 1530767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip, 153193db446aSBoris Brezillon const u8 *buf, 153293db446aSBoris Brezillon int oob_required, int page) 153393db446aSBoris Brezillon { 1534767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 153593db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 153693db446aSBoris Brezillon const u8 *data = buf; 153793db446aSBoris Brezillon const u8 *spare = chip->oob_poi; 153893db446aSBoris Brezillon int data_len = lt->data_bytes; 153993db446aSBoris Brezillon int spare_len = lt->spare_bytes; 154093db446aSBoris Brezillon int chunk, ret; 154193db446aSBoris Brezillon 154293db446aSBoris Brezillon /* Spare data will be written anyway, so clear it to avoid garbage */ 154393db446aSBoris Brezillon if (!oob_required) 154493db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 154593db446aSBoris Brezillon 154693db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 154793db446aSBoris Brezillon 154893db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 154993db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 155093db446aSBoris Brezillon data_len = lt->last_data_bytes; 155193db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 155293db446aSBoris Brezillon } 155393db446aSBoris Brezillon 155493db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len, 155593db446aSBoris Brezillon spare, spare_len, page); 155693db446aSBoris Brezillon data += data_len; 155793db446aSBoris Brezillon spare += spare_len; 155893db446aSBoris Brezillon 155993db446aSBoris Brezillon /* 156093db446aSBoris Brezillon * Waiting only for CMDD or PAGED is not enough, ECC are 156193db446aSBoris Brezillon * partially written. No flag is set once the operation is 156293db446aSBoris Brezillon * really finished but the ND_RUN bit is cleared, so wait for it 156393db446aSBoris Brezillon * before stepping into the next command. 156493db446aSBoris Brezillon */ 156593db446aSBoris Brezillon marvell_nfc_wait_ndrun(chip); 156693db446aSBoris Brezillon } 156793db446aSBoris Brezillon 156893db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, 1569b76401fcSChris Packham PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); 157093db446aSBoris Brezillon 157193db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 157293db446aSBoris Brezillon 157393db446aSBoris Brezillon if (ret) 157493db446aSBoris Brezillon return ret; 157593db446aSBoris Brezillon 157693db446aSBoris Brezillon return 0; 157793db446aSBoris Brezillon } 157893db446aSBoris Brezillon 1579767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip *chip, 158093db446aSBoris Brezillon int page) 158193db446aSBoris Brezillon { 1582767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 1583767eb6fbSBoris Brezillon 158493db446aSBoris Brezillon /* Invalidate page cache */ 158593db446aSBoris Brezillon chip->pagebuf = -1; 158693db446aSBoris Brezillon 158793db446aSBoris Brezillon memset(chip->data_buf, 0xFF, mtd->writesize); 158893db446aSBoris Brezillon 1589767eb6fbSBoris Brezillon return chip->ecc.write_page_raw(chip, chip->data_buf, true, page); 159093db446aSBoris Brezillon } 159193db446aSBoris Brezillon 1592767eb6fbSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page) 159393db446aSBoris Brezillon { 1594767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 1595767eb6fbSBoris Brezillon 159693db446aSBoris Brezillon /* Invalidate page cache */ 159793db446aSBoris Brezillon chip->pagebuf = -1; 159893db446aSBoris Brezillon 159993db446aSBoris Brezillon memset(chip->data_buf, 0xFF, mtd->writesize); 160093db446aSBoris Brezillon 1601767eb6fbSBoris Brezillon return chip->ecc.write_page(chip, chip->data_buf, true, page); 160293db446aSBoris Brezillon } 160393db446aSBoris Brezillon 160493db446aSBoris Brezillon /* NAND framework ->exec_op() hooks and related helpers */ 160593db446aSBoris Brezillon static void marvell_nfc_parse_instructions(struct nand_chip *chip, 160693db446aSBoris Brezillon const struct nand_subop *subop, 160793db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 160893db446aSBoris Brezillon { 160993db446aSBoris Brezillon const struct nand_op_instr *instr = NULL; 161093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 161193db446aSBoris Brezillon bool first_cmd = true; 161293db446aSBoris Brezillon unsigned int op_id; 161393db446aSBoris Brezillon int i; 161493db446aSBoris Brezillon 161593db446aSBoris Brezillon /* Reset the input structure as most of its fields will be OR'ed */ 161693db446aSBoris Brezillon memset(nfc_op, 0, sizeof(struct marvell_nfc_op)); 161793db446aSBoris Brezillon 161893db446aSBoris Brezillon for (op_id = 0; op_id < subop->ninstrs; op_id++) { 161993db446aSBoris Brezillon unsigned int offset, naddrs; 162093db446aSBoris Brezillon const u8 *addrs; 162193db446aSBoris Brezillon int len = nand_subop_get_data_len(subop, op_id); 162293db446aSBoris Brezillon 162393db446aSBoris Brezillon instr = &subop->instrs[op_id]; 162493db446aSBoris Brezillon 162593db446aSBoris Brezillon switch (instr->type) { 162693db446aSBoris Brezillon case NAND_OP_CMD_INSTR: 162793db446aSBoris Brezillon if (first_cmd) 162893db446aSBoris Brezillon nfc_op->ndcb[0] |= 162993db446aSBoris Brezillon NDCB0_CMD1(instr->ctx.cmd.opcode); 163093db446aSBoris Brezillon else 163193db446aSBoris Brezillon nfc_op->ndcb[0] |= 163293db446aSBoris Brezillon NDCB0_CMD2(instr->ctx.cmd.opcode) | 163393db446aSBoris Brezillon NDCB0_DBC; 163493db446aSBoris Brezillon 163593db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns; 163693db446aSBoris Brezillon first_cmd = false; 163793db446aSBoris Brezillon break; 163893db446aSBoris Brezillon 163993db446aSBoris Brezillon case NAND_OP_ADDR_INSTR: 164093db446aSBoris Brezillon offset = nand_subop_get_addr_start_off(subop, op_id); 164193db446aSBoris Brezillon naddrs = nand_subop_get_num_addr_cyc(subop, op_id); 164293db446aSBoris Brezillon addrs = &instr->ctx.addr.addrs[offset]; 164393db446aSBoris Brezillon 164493db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs); 164593db446aSBoris Brezillon 164693db446aSBoris Brezillon for (i = 0; i < min_t(unsigned int, 4, naddrs); i++) 164793db446aSBoris Brezillon nfc_op->ndcb[1] |= addrs[i] << (8 * i); 164893db446aSBoris Brezillon 164993db446aSBoris Brezillon if (naddrs >= 5) 165093db446aSBoris Brezillon nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]); 165193db446aSBoris Brezillon if (naddrs >= 6) 165293db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]); 165393db446aSBoris Brezillon if (naddrs == 7) 165493db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]); 165593db446aSBoris Brezillon 165693db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns; 165793db446aSBoris Brezillon break; 165893db446aSBoris Brezillon 165993db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR: 166093db446aSBoris Brezillon nfc_op->data_instr = instr; 166193db446aSBoris Brezillon nfc_op->data_instr_idx = op_id; 166293db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ); 166393db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 166493db446aSBoris Brezillon nfc_op->ndcb[0] |= 166593db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 166693db446aSBoris Brezillon NDCB0_LEN_OVRD; 166793db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 166893db446aSBoris Brezillon } 166993db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns; 167093db446aSBoris Brezillon break; 167193db446aSBoris Brezillon 167293db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR: 167393db446aSBoris Brezillon nfc_op->data_instr = instr; 167493db446aSBoris Brezillon nfc_op->data_instr_idx = op_id; 167593db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE); 167693db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 167793db446aSBoris Brezillon nfc_op->ndcb[0] |= 167893db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 167993db446aSBoris Brezillon NDCB0_LEN_OVRD; 168093db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 168193db446aSBoris Brezillon } 168293db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns; 168393db446aSBoris Brezillon break; 168493db446aSBoris Brezillon 168593db446aSBoris Brezillon case NAND_OP_WAITRDY_INSTR: 168693db446aSBoris Brezillon nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; 168793db446aSBoris Brezillon nfc_op->rdy_delay_ns = instr->delay_ns; 168893db446aSBoris Brezillon break; 168993db446aSBoris Brezillon } 169093db446aSBoris Brezillon } 169193db446aSBoris Brezillon } 169293db446aSBoris Brezillon 169393db446aSBoris Brezillon static int marvell_nfc_xfer_data_pio(struct nand_chip *chip, 169493db446aSBoris Brezillon const struct nand_subop *subop, 169593db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 169693db446aSBoris Brezillon { 169793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 169893db446aSBoris Brezillon const struct nand_op_instr *instr = nfc_op->data_instr; 169993db446aSBoris Brezillon unsigned int op_id = nfc_op->data_instr_idx; 170093db446aSBoris Brezillon unsigned int len = nand_subop_get_data_len(subop, op_id); 170193db446aSBoris Brezillon unsigned int offset = nand_subop_get_data_start_off(subop, op_id); 170293db446aSBoris Brezillon bool reading = (instr->type == NAND_OP_DATA_IN_INSTR); 170393db446aSBoris Brezillon int ret; 170493db446aSBoris Brezillon 170593db446aSBoris Brezillon if (instr->ctx.data.force_8bit) 170693db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, true); 170793db446aSBoris Brezillon 170893db446aSBoris Brezillon if (reading) { 170993db446aSBoris Brezillon u8 *in = instr->ctx.data.buf.in + offset; 171093db446aSBoris Brezillon 171193db446aSBoris Brezillon ret = marvell_nfc_xfer_data_in_pio(nfc, in, len); 171293db446aSBoris Brezillon } else { 171393db446aSBoris Brezillon const u8 *out = instr->ctx.data.buf.out + offset; 171493db446aSBoris Brezillon 171593db446aSBoris Brezillon ret = marvell_nfc_xfer_data_out_pio(nfc, out, len); 171693db446aSBoris Brezillon } 171793db446aSBoris Brezillon 171893db446aSBoris Brezillon if (instr->ctx.data.force_8bit) 171993db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, false); 172093db446aSBoris Brezillon 172193db446aSBoris Brezillon return ret; 172293db446aSBoris Brezillon } 172393db446aSBoris Brezillon 172493db446aSBoris Brezillon static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip, 172593db446aSBoris Brezillon const struct nand_subop *subop) 172693db446aSBoris Brezillon { 172793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 172893db446aSBoris Brezillon bool reading; 172993db446aSBoris Brezillon int ret; 173093db446aSBoris Brezillon 173193db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 173293db446aSBoris Brezillon reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR); 173393db446aSBoris Brezillon 173493db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 173593db446aSBoris Brezillon if (ret) 173693db446aSBoris Brezillon return ret; 173793db446aSBoris Brezillon 173893db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 173993db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 174093db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data"); 174193db446aSBoris Brezillon if (ret) 174293db446aSBoris Brezillon return ret; 174393db446aSBoris Brezillon 174493db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 174593db446aSBoris Brezillon 174693db446aSBoris Brezillon if (reading) { 174793db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 174893db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 174993db446aSBoris Brezillon if (ret) 175093db446aSBoris Brezillon return ret; 175193db446aSBoris Brezillon } 175293db446aSBoris Brezillon 175393db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 175493db446aSBoris Brezillon } 175593db446aSBoris Brezillon 175693db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 175793db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 175893db446aSBoris Brezillon if (ret) 175993db446aSBoris Brezillon return ret; 176093db446aSBoris Brezillon 176193db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 176293db446aSBoris Brezillon 176393db446aSBoris Brezillon if (!reading) { 176493db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 176593db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 176693db446aSBoris Brezillon if (ret) 176793db446aSBoris Brezillon return ret; 176893db446aSBoris Brezillon } 176993db446aSBoris Brezillon 177093db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 177193db446aSBoris Brezillon } 177293db446aSBoris Brezillon 177393db446aSBoris Brezillon /* 177493db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each 177593db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it 177693db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case. 177793db446aSBoris Brezillon */ 177893db446aSBoris Brezillon if (!reading) { 177993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 178093db446aSBoris Brezillon 178193db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 178293db446aSBoris Brezillon nfc->regs + NDCR); 178393db446aSBoris Brezillon } 178493db446aSBoris Brezillon 178593db446aSBoris Brezillon return 0; 178693db446aSBoris Brezillon } 178793db446aSBoris Brezillon 178893db446aSBoris Brezillon static int marvell_nfc_naked_access_exec(struct nand_chip *chip, 178993db446aSBoris Brezillon const struct nand_subop *subop) 179093db446aSBoris Brezillon { 179193db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 179293db446aSBoris Brezillon int ret; 179393db446aSBoris Brezillon 179493db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 179593db446aSBoris Brezillon 179693db446aSBoris Brezillon /* 179793db446aSBoris Brezillon * Naked access are different in that they need to be flagged as naked 179893db446aSBoris Brezillon * by the controller. Reset the controller registers fields that inform 179993db446aSBoris Brezillon * on the type and refill them according to the ongoing operation. 180093db446aSBoris Brezillon */ 180193db446aSBoris Brezillon nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) | 180293db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MASK)); 180393db446aSBoris Brezillon switch (subop->instrs[0].type) { 180493db446aSBoris Brezillon case NAND_OP_CMD_INSTR: 180593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD); 180693db446aSBoris Brezillon break; 180793db446aSBoris Brezillon case NAND_OP_ADDR_INSTR: 180893db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR); 180993db446aSBoris Brezillon break; 181093db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR: 181193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) | 181293db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 181393db446aSBoris Brezillon break; 181493db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR: 181593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) | 181693db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 181793db446aSBoris Brezillon break; 181893db446aSBoris Brezillon default: 181993db446aSBoris Brezillon /* This should never happen */ 182093db446aSBoris Brezillon break; 182193db446aSBoris Brezillon } 182293db446aSBoris Brezillon 182393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 182493db446aSBoris Brezillon if (ret) 182593db446aSBoris Brezillon return ret; 182693db446aSBoris Brezillon 182793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 182893db446aSBoris Brezillon 182993db446aSBoris Brezillon if (!nfc_op.data_instr) { 183093db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 183193db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 183293db446aSBoris Brezillon return ret; 183393db446aSBoris Brezillon } 183493db446aSBoris Brezillon 183593db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 183693db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data"); 183793db446aSBoris Brezillon if (ret) 183893db446aSBoris Brezillon return ret; 183993db446aSBoris Brezillon 184093db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 184193db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 184293db446aSBoris Brezillon if (ret) 184393db446aSBoris Brezillon return ret; 184493db446aSBoris Brezillon 184593db446aSBoris Brezillon /* 184693db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each 184793db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it 184893db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case. 184993db446aSBoris Brezillon */ 185093db446aSBoris Brezillon if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { 185193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 185293db446aSBoris Brezillon 185393db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 185493db446aSBoris Brezillon nfc->regs + NDCR); 185593db446aSBoris Brezillon } 185693db446aSBoris Brezillon 185793db446aSBoris Brezillon return 0; 185893db446aSBoris Brezillon } 185993db446aSBoris Brezillon 186093db446aSBoris Brezillon static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip, 186193db446aSBoris Brezillon const struct nand_subop *subop) 186293db446aSBoris Brezillon { 186393db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 186493db446aSBoris Brezillon int ret; 186593db446aSBoris Brezillon 186693db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 186793db446aSBoris Brezillon 186893db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 186993db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 187093db446aSBoris Brezillon 187193db446aSBoris Brezillon return ret; 187293db446aSBoris Brezillon } 187393db446aSBoris Brezillon 187493db446aSBoris Brezillon static int marvell_nfc_read_id_type_exec(struct nand_chip *chip, 187593db446aSBoris Brezillon const struct nand_subop *subop) 187693db446aSBoris Brezillon { 187793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 187893db446aSBoris Brezillon int ret; 187993db446aSBoris Brezillon 188093db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 188193db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 188293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID); 188393db446aSBoris Brezillon 188493db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 188593db446aSBoris Brezillon if (ret) 188693db446aSBoris Brezillon return ret; 188793db446aSBoris Brezillon 188893db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 188993db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 189093db446aSBoris Brezillon "RDDREQ while reading ID"); 189193db446aSBoris Brezillon if (ret) 189293db446aSBoris Brezillon return ret; 189393db446aSBoris Brezillon 189493db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 189593db446aSBoris Brezillon 189693db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 189793db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 189893db446aSBoris Brezillon if (ret) 189993db446aSBoris Brezillon return ret; 190093db446aSBoris Brezillon } 190193db446aSBoris Brezillon 190293db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 190393db446aSBoris Brezillon 190493db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 190593db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 190693db446aSBoris Brezillon if (ret) 190793db446aSBoris Brezillon return ret; 190893db446aSBoris Brezillon 190993db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 191093db446aSBoris Brezillon 191193db446aSBoris Brezillon return 0; 191293db446aSBoris Brezillon } 191393db446aSBoris Brezillon 191493db446aSBoris Brezillon static int marvell_nfc_read_status_exec(struct nand_chip *chip, 191593db446aSBoris Brezillon const struct nand_subop *subop) 191693db446aSBoris Brezillon { 191793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 191893db446aSBoris Brezillon int ret; 191993db446aSBoris Brezillon 192093db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 192193db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 192293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS); 192393db446aSBoris Brezillon 192493db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 192593db446aSBoris Brezillon if (ret) 192693db446aSBoris Brezillon return ret; 192793db446aSBoris Brezillon 192893db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 192993db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 193093db446aSBoris Brezillon "RDDREQ while reading status"); 193193db446aSBoris Brezillon if (ret) 193293db446aSBoris Brezillon return ret; 193393db446aSBoris Brezillon 193493db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 193593db446aSBoris Brezillon 193693db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 193793db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 193893db446aSBoris Brezillon if (ret) 193993db446aSBoris Brezillon return ret; 194093db446aSBoris Brezillon } 194193db446aSBoris Brezillon 194293db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 194393db446aSBoris Brezillon 194493db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 194593db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 194693db446aSBoris Brezillon if (ret) 194793db446aSBoris Brezillon return ret; 194893db446aSBoris Brezillon 194993db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 195093db446aSBoris Brezillon 195193db446aSBoris Brezillon return 0; 195293db446aSBoris Brezillon } 195393db446aSBoris Brezillon 195493db446aSBoris Brezillon static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip, 195593db446aSBoris Brezillon const struct nand_subop *subop) 195693db446aSBoris Brezillon { 195793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 195893db446aSBoris Brezillon int ret; 195993db446aSBoris Brezillon 196093db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 196193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET); 196293db446aSBoris Brezillon 196393db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 196493db446aSBoris Brezillon if (ret) 196593db446aSBoris Brezillon return ret; 196693db446aSBoris Brezillon 196793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 196893db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 196993db446aSBoris Brezillon if (ret) 197093db446aSBoris Brezillon return ret; 197193db446aSBoris Brezillon 197293db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 197393db446aSBoris Brezillon 197493db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 197593db446aSBoris Brezillon if (ret) 197693db446aSBoris Brezillon return ret; 197793db446aSBoris Brezillon 197893db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 197993db446aSBoris Brezillon 198093db446aSBoris Brezillon return 0; 198193db446aSBoris Brezillon } 198293db446aSBoris Brezillon 198393db446aSBoris Brezillon static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip, 198493db446aSBoris Brezillon const struct nand_subop *subop) 198593db446aSBoris Brezillon { 198693db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 198793db446aSBoris Brezillon int ret; 198893db446aSBoris Brezillon 198993db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 199093db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE); 199193db446aSBoris Brezillon 199293db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 199393db446aSBoris Brezillon if (ret) 199493db446aSBoris Brezillon return ret; 199593db446aSBoris Brezillon 199693db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 199793db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 199893db446aSBoris Brezillon if (ret) 199993db446aSBoris Brezillon return ret; 200093db446aSBoris Brezillon 200193db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 200293db446aSBoris Brezillon 200393db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 200493db446aSBoris Brezillon if (ret) 200593db446aSBoris Brezillon return ret; 200693db446aSBoris Brezillon 200793db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 200893db446aSBoris Brezillon 200993db446aSBoris Brezillon return 0; 201093db446aSBoris Brezillon } 201193db446aSBoris Brezillon 201293db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER( 201393db446aSBoris Brezillon /* Monolithic reads/writes */ 201493db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 201593db446aSBoris Brezillon marvell_nfc_monolithic_access_exec, 201693db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 201793db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2), 201893db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true), 201993db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 202093db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 202193db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 202293db446aSBoris Brezillon marvell_nfc_monolithic_access_exec, 202393db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 202493db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2), 202593db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE), 202693db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true), 202793db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 202893db446aSBoris Brezillon /* Naked commands */ 202993db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 203093db446aSBoris Brezillon marvell_nfc_naked_access_exec, 203193db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false)), 203293db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 203393db446aSBoris Brezillon marvell_nfc_naked_access_exec, 203493db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)), 203593db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 203693db446aSBoris Brezillon marvell_nfc_naked_access_exec, 203793db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 203893db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 203993db446aSBoris Brezillon marvell_nfc_naked_access_exec, 204093db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)), 204193db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 204293db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec, 204393db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 204493db446aSBoris Brezillon ); 204593db446aSBoris Brezillon 204693db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER( 204793db446aSBoris Brezillon /* Naked commands not supported, use a function for each pattern */ 204893db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 204993db446aSBoris Brezillon marvell_nfc_read_id_type_exec, 205093db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 205193db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 205293db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)), 205393db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 205493db446aSBoris Brezillon marvell_nfc_erase_cmd_type_exec, 205593db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 205693db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 205793db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 205893db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 205993db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 206093db446aSBoris Brezillon marvell_nfc_read_status_exec, 206193db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 206293db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)), 206393db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 206493db446aSBoris Brezillon marvell_nfc_reset_cmd_type_exec, 206593db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 206693db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 206793db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 206893db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec, 206993db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 207093db446aSBoris Brezillon ); 207193db446aSBoris Brezillon 207293db446aSBoris Brezillon static int marvell_nfc_exec_op(struct nand_chip *chip, 207393db446aSBoris Brezillon const struct nand_operation *op, 207493db446aSBoris Brezillon bool check_only) 207593db446aSBoris Brezillon { 207693db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 207793db446aSBoris Brezillon 207893db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 207993db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser, 208093db446aSBoris Brezillon op, check_only); 208193db446aSBoris Brezillon else 208293db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser, 208393db446aSBoris Brezillon op, check_only); 208493db446aSBoris Brezillon } 208593db446aSBoris Brezillon 208693db446aSBoris Brezillon /* 208793db446aSBoris Brezillon * Layouts were broken in old pxa3xx_nand driver, these are supposed to be 208893db446aSBoris Brezillon * usable. 208993db446aSBoris Brezillon */ 209093db446aSBoris Brezillon static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section, 209193db446aSBoris Brezillon struct mtd_oob_region *oobregion) 209293db446aSBoris Brezillon { 209393db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 209493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 209593db446aSBoris Brezillon 209693db446aSBoris Brezillon if (section) 209793db446aSBoris Brezillon return -ERANGE; 209893db446aSBoris Brezillon 209993db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + 210093db446aSBoris Brezillon lt->last_ecc_bytes; 210193db446aSBoris Brezillon oobregion->offset = mtd->oobsize - oobregion->length; 210293db446aSBoris Brezillon 210393db446aSBoris Brezillon return 0; 210493db446aSBoris Brezillon } 210593db446aSBoris Brezillon 210693db446aSBoris Brezillon static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section, 210793db446aSBoris Brezillon struct mtd_oob_region *oobregion) 210893db446aSBoris Brezillon { 210993db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 211093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 211193db446aSBoris Brezillon 211293db446aSBoris Brezillon if (section) 211393db446aSBoris Brezillon return -ERANGE; 211493db446aSBoris Brezillon 211593db446aSBoris Brezillon /* 211693db446aSBoris Brezillon * Bootrom looks in bytes 0 & 5 for bad blocks for the 211793db446aSBoris Brezillon * 4KB page / 4bit BCH combination. 211893db446aSBoris Brezillon */ 211993db446aSBoris Brezillon if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) 212093db446aSBoris Brezillon oobregion->offset = 6; 212193db446aSBoris Brezillon else 212293db446aSBoris Brezillon oobregion->offset = 2; 212393db446aSBoris Brezillon 212493db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + 212593db446aSBoris Brezillon lt->last_spare_bytes - oobregion->offset; 212693db446aSBoris Brezillon 212793db446aSBoris Brezillon return 0; 212893db446aSBoris Brezillon } 212993db446aSBoris Brezillon 213093db446aSBoris Brezillon static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = { 213193db446aSBoris Brezillon .ecc = marvell_nand_ooblayout_ecc, 213293db446aSBoris Brezillon .free = marvell_nand_ooblayout_free, 213393db446aSBoris Brezillon }; 213493db446aSBoris Brezillon 213593db446aSBoris Brezillon static int marvell_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, 213693db446aSBoris Brezillon struct nand_ecc_ctrl *ecc) 213793db446aSBoris Brezillon { 213893db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 213993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 214093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *l; 214193db446aSBoris Brezillon int i; 214293db446aSBoris Brezillon 214393db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 && 214493db446aSBoris Brezillon (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) { 214593db446aSBoris Brezillon dev_err(nfc->dev, 214693db446aSBoris Brezillon "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n", 214793db446aSBoris Brezillon mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize); 214893db446aSBoris Brezillon return -ENOTSUPP; 214993db446aSBoris Brezillon } 215093db446aSBoris Brezillon 215193db446aSBoris Brezillon to_marvell_nand(chip)->layout = NULL; 215293db446aSBoris Brezillon for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) { 215393db446aSBoris Brezillon l = &marvell_nfc_layouts[i]; 215493db446aSBoris Brezillon if (mtd->writesize == l->writesize && 215593db446aSBoris Brezillon ecc->size == l->chunk && ecc->strength == l->strength) { 215693db446aSBoris Brezillon to_marvell_nand(chip)->layout = l; 215793db446aSBoris Brezillon break; 215893db446aSBoris Brezillon } 215993db446aSBoris Brezillon } 216093db446aSBoris Brezillon 216193db446aSBoris Brezillon if (!to_marvell_nand(chip)->layout || 216293db446aSBoris Brezillon (!nfc->caps->is_nfcv2 && ecc->strength > 1)) { 216393db446aSBoris Brezillon dev_err(nfc->dev, 216493db446aSBoris Brezillon "ECC strength %d at page size %d is not supported\n", 216593db446aSBoris Brezillon ecc->strength, mtd->writesize); 216693db446aSBoris Brezillon return -ENOTSUPP; 216793db446aSBoris Brezillon } 216893db446aSBoris Brezillon 216993db446aSBoris Brezillon mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops); 217093db446aSBoris Brezillon ecc->steps = l->nchunks; 217193db446aSBoris Brezillon ecc->size = l->data_bytes; 217293db446aSBoris Brezillon 217393db446aSBoris Brezillon if (ecc->strength == 1) { 217493db446aSBoris Brezillon chip->ecc.algo = NAND_ECC_HAMMING; 217593db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; 217693db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; 217793db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; 217893db446aSBoris Brezillon ecc->read_oob = ecc->read_oob_raw; 217993db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw; 218093db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page; 218193db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; 218293db446aSBoris Brezillon ecc->write_oob = ecc->write_oob_raw; 218393db446aSBoris Brezillon } else { 218493db446aSBoris Brezillon chip->ecc.algo = NAND_ECC_BCH; 218593db446aSBoris Brezillon ecc->strength = 16; 218693db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; 218793db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; 218893db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw; 218993db446aSBoris Brezillon ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob; 219093db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw; 219193db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_bch_write_page; 219293db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw; 219393db446aSBoris Brezillon ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob; 219493db446aSBoris Brezillon } 219593db446aSBoris Brezillon 219693db446aSBoris Brezillon return 0; 219793db446aSBoris Brezillon } 219893db446aSBoris Brezillon 219993db446aSBoris Brezillon static int marvell_nand_ecc_init(struct mtd_info *mtd, 220093db446aSBoris Brezillon struct nand_ecc_ctrl *ecc) 220193db446aSBoris Brezillon { 220293db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 220393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 220493db446aSBoris Brezillon int ret; 220593db446aSBoris Brezillon 220693db446aSBoris Brezillon if (ecc->mode != NAND_ECC_NONE && (!ecc->size || !ecc->strength)) { 220793db446aSBoris Brezillon if (chip->ecc_step_ds && chip->ecc_strength_ds) { 220893db446aSBoris Brezillon ecc->size = chip->ecc_step_ds; 220993db446aSBoris Brezillon ecc->strength = chip->ecc_strength_ds; 221093db446aSBoris Brezillon } else { 221193db446aSBoris Brezillon dev_info(nfc->dev, 221293db446aSBoris Brezillon "No minimum ECC strength, using 1b/512B\n"); 221393db446aSBoris Brezillon ecc->size = 512; 221493db446aSBoris Brezillon ecc->strength = 1; 221593db446aSBoris Brezillon } 221693db446aSBoris Brezillon } 221793db446aSBoris Brezillon 221893db446aSBoris Brezillon switch (ecc->mode) { 221993db446aSBoris Brezillon case NAND_ECC_HW: 222093db446aSBoris Brezillon ret = marvell_nand_hw_ecc_ctrl_init(mtd, ecc); 222193db446aSBoris Brezillon if (ret) 222293db446aSBoris Brezillon return ret; 222393db446aSBoris Brezillon break; 222493db446aSBoris Brezillon case NAND_ECC_NONE: 222593db446aSBoris Brezillon case NAND_ECC_SOFT: 2226ed6d0285SChris Packham case NAND_ECC_ON_DIE: 222793db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && 222893db446aSBoris Brezillon mtd->writesize != SZ_2K) { 222993db446aSBoris Brezillon dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", 223093db446aSBoris Brezillon mtd->writesize); 223193db446aSBoris Brezillon return -EINVAL; 223293db446aSBoris Brezillon } 223393db446aSBoris Brezillon break; 223493db446aSBoris Brezillon default: 223593db446aSBoris Brezillon return -EINVAL; 223693db446aSBoris Brezillon } 223793db446aSBoris Brezillon 223893db446aSBoris Brezillon return 0; 223993db446aSBoris Brezillon } 224093db446aSBoris Brezillon 224193db446aSBoris Brezillon static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; 224293db446aSBoris Brezillon static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; 224393db446aSBoris Brezillon 224493db446aSBoris Brezillon static struct nand_bbt_descr bbt_main_descr = { 224593db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 224693db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION, 224793db446aSBoris Brezillon .offs = 8, 224893db446aSBoris Brezillon .len = 6, 224993db446aSBoris Brezillon .veroffs = 14, 225093db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */ 225193db446aSBoris Brezillon .pattern = bbt_pattern 225293db446aSBoris Brezillon }; 225393db446aSBoris Brezillon 225493db446aSBoris Brezillon static struct nand_bbt_descr bbt_mirror_descr = { 225593db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 225693db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION, 225793db446aSBoris Brezillon .offs = 8, 225893db446aSBoris Brezillon .len = 6, 225993db446aSBoris Brezillon .veroffs = 14, 226093db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */ 226193db446aSBoris Brezillon .pattern = bbt_mirror_pattern 226293db446aSBoris Brezillon }; 226393db446aSBoris Brezillon 2264858838b8SBoris Brezillon static int marvell_nfc_setup_data_interface(struct nand_chip *chip, int chipnr, 226593db446aSBoris Brezillon const struct nand_data_interface 226693db446aSBoris Brezillon *conf) 226793db446aSBoris Brezillon { 226893db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 226993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 22706b6de654SBoris Brezillon unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2; 227193db446aSBoris Brezillon const struct nand_sdr_timings *sdr; 227293db446aSBoris Brezillon struct marvell_nfc_timings nfc_tmg; 227393db446aSBoris Brezillon int read_delay; 227493db446aSBoris Brezillon 227593db446aSBoris Brezillon sdr = nand_get_sdr_timings(conf); 227693db446aSBoris Brezillon if (IS_ERR(sdr)) 227793db446aSBoris Brezillon return PTR_ERR(sdr); 227893db446aSBoris Brezillon 227993db446aSBoris Brezillon /* 228093db446aSBoris Brezillon * SDR timings are given in pico-seconds while NFC timings must be 228193db446aSBoris Brezillon * expressed in NAND controller clock cycles, which is half of the 228293db446aSBoris Brezillon * frequency of the accessible ECC clock retrieved by clk_get_rate(). 228393db446aSBoris Brezillon * This is not written anywhere in the datasheet but was observed 228493db446aSBoris Brezillon * with an oscilloscope. 228593db446aSBoris Brezillon * 228693db446aSBoris Brezillon * NFC datasheet gives equations from which thoses calculations 228793db446aSBoris Brezillon * are derived, they tend to be slightly more restrictives than the 228893db446aSBoris Brezillon * given core timings and may improve the overall speed. 228993db446aSBoris Brezillon */ 229093db446aSBoris Brezillon nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; 229193db446aSBoris Brezillon nfc_tmg.tRH = nfc_tmg.tRP; 229293db446aSBoris Brezillon nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; 229393db446aSBoris Brezillon nfc_tmg.tWH = nfc_tmg.tWP; 229493db446aSBoris Brezillon nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); 229593db446aSBoris Brezillon nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; 229693db446aSBoris Brezillon nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); 229793db446aSBoris Brezillon /* 229893db446aSBoris Brezillon * Read delay is the time of propagation from SoC pins to NFC internal 229993db446aSBoris Brezillon * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In 230093db446aSBoris Brezillon * EDO mode, an additional delay of tRH must be taken into account so 230193db446aSBoris Brezillon * the data is sampled on the falling edge instead of the rising edge. 230293db446aSBoris Brezillon */ 230393db446aSBoris Brezillon read_delay = sdr->tRC_min >= 30000 ? 230493db446aSBoris Brezillon MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH; 230593db446aSBoris Brezillon 230693db446aSBoris Brezillon nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); 230793db446aSBoris Brezillon /* 230893db446aSBoris Brezillon * tWHR and tRHW are supposed to be read to write delays (and vice 230993db446aSBoris Brezillon * versa) but in some cases, ie. when doing a change column, they must 231093db446aSBoris Brezillon * be greater than that to be sure tCCS delay is respected. 231193db446aSBoris Brezillon */ 231293db446aSBoris Brezillon nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), 231393db446aSBoris Brezillon period_ns) - 2, 231493db446aSBoris Brezillon nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), 231593db446aSBoris Brezillon period_ns); 231693db446aSBoris Brezillon 231793db446aSBoris Brezillon /* 231893db446aSBoris Brezillon * NFCv2: Use WAIT_MODE (wait for RB line), do not rely only on delays. 231993db446aSBoris Brezillon * NFCv1: No WAIT_MODE, tR must be maximal. 232093db446aSBoris Brezillon */ 232193db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 232293db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); 232393db446aSBoris Brezillon } else { 232493db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, 232593db446aSBoris Brezillon period_ns); 232693db446aSBoris Brezillon if (nfc_tmg.tR + 3 > nfc_tmg.tCH) 232793db446aSBoris Brezillon nfc_tmg.tR = nfc_tmg.tCH - 3; 232893db446aSBoris Brezillon else 232993db446aSBoris Brezillon nfc_tmg.tR = 0; 233093db446aSBoris Brezillon } 233193db446aSBoris Brezillon 233293db446aSBoris Brezillon if (chipnr < 0) 233393db446aSBoris Brezillon return 0; 233493db446aSBoris Brezillon 233593db446aSBoris Brezillon marvell_nand->ndtr0 = 233693db446aSBoris Brezillon NDTR0_TRP(nfc_tmg.tRP) | 233793db446aSBoris Brezillon NDTR0_TRH(nfc_tmg.tRH) | 233893db446aSBoris Brezillon NDTR0_ETRP(nfc_tmg.tRP) | 233993db446aSBoris Brezillon NDTR0_TWP(nfc_tmg.tWP) | 234093db446aSBoris Brezillon NDTR0_TWH(nfc_tmg.tWH) | 234193db446aSBoris Brezillon NDTR0_TCS(nfc_tmg.tCS) | 234293db446aSBoris Brezillon NDTR0_TCH(nfc_tmg.tCH); 234393db446aSBoris Brezillon 234493db446aSBoris Brezillon marvell_nand->ndtr1 = 234593db446aSBoris Brezillon NDTR1_TAR(nfc_tmg.tAR) | 234693db446aSBoris Brezillon NDTR1_TWHR(nfc_tmg.tWHR) | 234793db446aSBoris Brezillon NDTR1_TR(nfc_tmg.tR); 234893db446aSBoris Brezillon 234993db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 235093db446aSBoris Brezillon marvell_nand->ndtr0 |= 235193db446aSBoris Brezillon NDTR0_RD_CNT_DEL(read_delay) | 235293db446aSBoris Brezillon NDTR0_SELCNTR | 235393db446aSBoris Brezillon NDTR0_TADL(nfc_tmg.tADL); 235493db446aSBoris Brezillon 235593db446aSBoris Brezillon marvell_nand->ndtr1 |= 235693db446aSBoris Brezillon NDTR1_TRHW(nfc_tmg.tRHW) | 235793db446aSBoris Brezillon NDTR1_WAIT_MODE; 235893db446aSBoris Brezillon } 235993db446aSBoris Brezillon 236093db446aSBoris Brezillon return 0; 236193db446aSBoris Brezillon } 236293db446aSBoris Brezillon 23638831e48bSMiquel Raynal static int marvell_nand_attach_chip(struct nand_chip *chip) 23648831e48bSMiquel Raynal { 23658831e48bSMiquel Raynal struct mtd_info *mtd = nand_to_mtd(chip); 23668831e48bSMiquel Raynal struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 23678831e48bSMiquel Raynal struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 23688831e48bSMiquel Raynal struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev); 23698831e48bSMiquel Raynal int ret; 23708831e48bSMiquel Raynal 23718831e48bSMiquel Raynal if (pdata && pdata->flash_bbt) 23728831e48bSMiquel Raynal chip->bbt_options |= NAND_BBT_USE_FLASH; 23738831e48bSMiquel Raynal 23748831e48bSMiquel Raynal if (chip->bbt_options & NAND_BBT_USE_FLASH) { 23758831e48bSMiquel Raynal /* 23768831e48bSMiquel Raynal * We'll use a bad block table stored in-flash and don't 23778831e48bSMiquel Raynal * allow writing the bad block marker to the flash. 23788831e48bSMiquel Raynal */ 23798831e48bSMiquel Raynal chip->bbt_options |= NAND_BBT_NO_OOB_BBM; 23808831e48bSMiquel Raynal chip->bbt_td = &bbt_main_descr; 23818831e48bSMiquel Raynal chip->bbt_md = &bbt_mirror_descr; 23828831e48bSMiquel Raynal } 23838831e48bSMiquel Raynal 23848831e48bSMiquel Raynal /* Save the chip-specific fields of NDCR */ 23858831e48bSMiquel Raynal marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize); 23868831e48bSMiquel Raynal if (chip->options & NAND_BUSWIDTH_16) 23878831e48bSMiquel Raynal marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 23888831e48bSMiquel Raynal 23898831e48bSMiquel Raynal /* 23908831e48bSMiquel Raynal * On small page NANDs, only one cycle is needed to pass the 23918831e48bSMiquel Raynal * column address. 23928831e48bSMiquel Raynal */ 23938831e48bSMiquel Raynal if (mtd->writesize <= 512) { 23948831e48bSMiquel Raynal marvell_nand->addr_cyc = 1; 23958831e48bSMiquel Raynal } else { 23968831e48bSMiquel Raynal marvell_nand->addr_cyc = 2; 23978831e48bSMiquel Raynal marvell_nand->ndcr |= NDCR_RA_START; 23988831e48bSMiquel Raynal } 23998831e48bSMiquel Raynal 24008831e48bSMiquel Raynal /* 24018831e48bSMiquel Raynal * Now add the number of cycles needed to pass the row 24028831e48bSMiquel Raynal * address. 24038831e48bSMiquel Raynal * 24048831e48bSMiquel Raynal * Addressing a chip using CS 2 or 3 should also need the third row 24058831e48bSMiquel Raynal * cycle but due to inconsistance in the documentation and lack of 24068831e48bSMiquel Raynal * hardware to test this situation, this case is not supported. 24078831e48bSMiquel Raynal */ 24088831e48bSMiquel Raynal if (chip->options & NAND_ROW_ADDR_3) 24098831e48bSMiquel Raynal marvell_nand->addr_cyc += 3; 24108831e48bSMiquel Raynal else 24118831e48bSMiquel Raynal marvell_nand->addr_cyc += 2; 24128831e48bSMiquel Raynal 24138831e48bSMiquel Raynal if (pdata) { 24148831e48bSMiquel Raynal chip->ecc.size = pdata->ecc_step_size; 24158831e48bSMiquel Raynal chip->ecc.strength = pdata->ecc_strength; 24168831e48bSMiquel Raynal } 24178831e48bSMiquel Raynal 24188831e48bSMiquel Raynal ret = marvell_nand_ecc_init(mtd, &chip->ecc); 24198831e48bSMiquel Raynal if (ret) { 24208831e48bSMiquel Raynal dev_err(nfc->dev, "ECC init failed: %d\n", ret); 24218831e48bSMiquel Raynal return ret; 24228831e48bSMiquel Raynal } 24238831e48bSMiquel Raynal 24248831e48bSMiquel Raynal if (chip->ecc.mode == NAND_ECC_HW) { 24258831e48bSMiquel Raynal /* 24268831e48bSMiquel Raynal * Subpage write not available with hardware ECC, prohibit also 24278831e48bSMiquel Raynal * subpage read as in userspace subpage access would still be 24288831e48bSMiquel Raynal * allowed and subpage write, if used, would lead to numerous 24298831e48bSMiquel Raynal * uncorrectable ECC errors. 24308831e48bSMiquel Raynal */ 24318831e48bSMiquel Raynal chip->options |= NAND_NO_SUBPAGE_WRITE; 24328831e48bSMiquel Raynal } 24338831e48bSMiquel Raynal 24348831e48bSMiquel Raynal if (pdata || nfc->caps->legacy_of_bindings) { 24358831e48bSMiquel Raynal /* 24368831e48bSMiquel Raynal * We keep the MTD name unchanged to avoid breaking platforms 24378831e48bSMiquel Raynal * where the MTD cmdline parser is used and the bootloader 24388831e48bSMiquel Raynal * has not been updated to use the new naming scheme. 24398831e48bSMiquel Raynal */ 24408831e48bSMiquel Raynal mtd->name = "pxa3xx_nand-0"; 24418831e48bSMiquel Raynal } else if (!mtd->name) { 24428831e48bSMiquel Raynal /* 24438831e48bSMiquel Raynal * If the new bindings are used and the bootloader has not been 24448831e48bSMiquel Raynal * updated to pass a new mtdparts parameter on the cmdline, you 24458831e48bSMiquel Raynal * should define the following property in your NAND node, ie: 24468831e48bSMiquel Raynal * 24478831e48bSMiquel Raynal * label = "main-storage"; 24488831e48bSMiquel Raynal * 24498831e48bSMiquel Raynal * This way, mtd->name will be set by the core when 24508831e48bSMiquel Raynal * nand_set_flash_node() is called. 24518831e48bSMiquel Raynal */ 24528831e48bSMiquel Raynal mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, 24538831e48bSMiquel Raynal "%s:nand.%d", dev_name(nfc->dev), 24548831e48bSMiquel Raynal marvell_nand->sels[0].cs); 24558831e48bSMiquel Raynal if (!mtd->name) { 24568831e48bSMiquel Raynal dev_err(nfc->dev, "Failed to allocate mtd->name\n"); 24578831e48bSMiquel Raynal return -ENOMEM; 24588831e48bSMiquel Raynal } 24598831e48bSMiquel Raynal } 24608831e48bSMiquel Raynal 24618831e48bSMiquel Raynal return 0; 24628831e48bSMiquel Raynal } 24638831e48bSMiquel Raynal 24648831e48bSMiquel Raynal static const struct nand_controller_ops marvell_nand_controller_ops = { 24658831e48bSMiquel Raynal .attach_chip = marvell_nand_attach_chip, 24668831e48bSMiquel Raynal }; 24678831e48bSMiquel Raynal 246893db446aSBoris Brezillon static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc, 246993db446aSBoris Brezillon struct device_node *np) 247093db446aSBoris Brezillon { 247193db446aSBoris Brezillon struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev); 247293db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand; 247393db446aSBoris Brezillon struct mtd_info *mtd; 247493db446aSBoris Brezillon struct nand_chip *chip; 247593db446aSBoris Brezillon int nsels, ret, i; 247693db446aSBoris Brezillon u32 cs, rb; 247793db446aSBoris Brezillon 247893db446aSBoris Brezillon /* 247993db446aSBoris Brezillon * The legacy "num-cs" property indicates the number of CS on the only 248093db446aSBoris Brezillon * chip connected to the controller (legacy bindings does not support 2481f6997becSMiquel Raynal * more than one chip). The CS and RB pins are always the #0. 248293db446aSBoris Brezillon * 248393db446aSBoris Brezillon * When not using legacy bindings, a couple of "reg" and "nand-rb" 248493db446aSBoris Brezillon * properties must be filled. For each chip, expressed as a subnode, 248593db446aSBoris Brezillon * "reg" points to the CS lines and "nand-rb" to the RB line. 248693db446aSBoris Brezillon */ 2487f6997becSMiquel Raynal if (pdata || nfc->caps->legacy_of_bindings) { 248893db446aSBoris Brezillon nsels = 1; 2489f6997becSMiquel Raynal } else { 2490f6997becSMiquel Raynal nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32)); 2491f6997becSMiquel Raynal if (nsels <= 0) { 2492f6997becSMiquel Raynal dev_err(dev, "missing/invalid reg property\n"); 249393db446aSBoris Brezillon return -EINVAL; 249493db446aSBoris Brezillon } 249593db446aSBoris Brezillon } 249693db446aSBoris Brezillon 249793db446aSBoris Brezillon /* Alloc the nand chip structure */ 249893db446aSBoris Brezillon marvell_nand = devm_kzalloc(dev, sizeof(*marvell_nand) + 249993db446aSBoris Brezillon (nsels * 250093db446aSBoris Brezillon sizeof(struct marvell_nand_chip_sel)), 250193db446aSBoris Brezillon GFP_KERNEL); 250293db446aSBoris Brezillon if (!marvell_nand) { 250393db446aSBoris Brezillon dev_err(dev, "could not allocate chip structure\n"); 250493db446aSBoris Brezillon return -ENOMEM; 250593db446aSBoris Brezillon } 250693db446aSBoris Brezillon 250793db446aSBoris Brezillon marvell_nand->nsels = nsels; 250893db446aSBoris Brezillon marvell_nand->selected_die = -1; 250993db446aSBoris Brezillon 251093db446aSBoris Brezillon for (i = 0; i < nsels; i++) { 251193db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) { 251293db446aSBoris Brezillon /* 251393db446aSBoris Brezillon * Legacy bindings use the CS lines in natural 251493db446aSBoris Brezillon * order (0, 1, ...) 251593db446aSBoris Brezillon */ 251693db446aSBoris Brezillon cs = i; 251793db446aSBoris Brezillon } else { 251893db446aSBoris Brezillon /* Retrieve CS id */ 251993db446aSBoris Brezillon ret = of_property_read_u32_index(np, "reg", i, &cs); 252093db446aSBoris Brezillon if (ret) { 252193db446aSBoris Brezillon dev_err(dev, "could not retrieve reg property: %d\n", 252293db446aSBoris Brezillon ret); 252393db446aSBoris Brezillon return ret; 252493db446aSBoris Brezillon } 252593db446aSBoris Brezillon } 252693db446aSBoris Brezillon 252793db446aSBoris Brezillon if (cs >= nfc->caps->max_cs_nb) { 252893db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max CS = %d)\n", 252993db446aSBoris Brezillon cs, nfc->caps->max_cs_nb); 253093db446aSBoris Brezillon return -EINVAL; 253193db446aSBoris Brezillon } 253293db446aSBoris Brezillon 253393db446aSBoris Brezillon if (test_and_set_bit(cs, &nfc->assigned_cs)) { 253493db446aSBoris Brezillon dev_err(dev, "CS %d already assigned\n", cs); 253593db446aSBoris Brezillon return -EINVAL; 253693db446aSBoris Brezillon } 253793db446aSBoris Brezillon 253893db446aSBoris Brezillon /* 253993db446aSBoris Brezillon * The cs variable represents the chip select id, which must be 254093db446aSBoris Brezillon * converted in bit fields for NDCB0 and NDCB2 to select the 254193db446aSBoris Brezillon * right chip. Unfortunately, due to a lack of information on 254293db446aSBoris Brezillon * the subject and incoherent documentation, the user should not 254393db446aSBoris Brezillon * use CS1 and CS3 at all as asserting them is not supported in 254493db446aSBoris Brezillon * a reliable way (due to multiplexing inside ADDR5 field). 254593db446aSBoris Brezillon */ 254693db446aSBoris Brezillon marvell_nand->sels[i].cs = cs; 254793db446aSBoris Brezillon switch (cs) { 254893db446aSBoris Brezillon case 0: 254993db446aSBoris Brezillon case 2: 255093db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = 0; 255193db446aSBoris Brezillon break; 255293db446aSBoris Brezillon case 1: 255393db446aSBoris Brezillon case 3: 255493db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL; 255593db446aSBoris Brezillon break; 255693db446aSBoris Brezillon default: 255793db446aSBoris Brezillon return -EINVAL; 255893db446aSBoris Brezillon } 255993db446aSBoris Brezillon 256093db446aSBoris Brezillon /* Retrieve RB id */ 256193db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) { 256293db446aSBoris Brezillon /* Legacy bindings always use RB #0 */ 256393db446aSBoris Brezillon rb = 0; 256493db446aSBoris Brezillon } else { 256593db446aSBoris Brezillon ret = of_property_read_u32_index(np, "nand-rb", i, 256693db446aSBoris Brezillon &rb); 256793db446aSBoris Brezillon if (ret) { 256893db446aSBoris Brezillon dev_err(dev, 256993db446aSBoris Brezillon "could not retrieve RB property: %d\n", 257093db446aSBoris Brezillon ret); 257193db446aSBoris Brezillon return ret; 257293db446aSBoris Brezillon } 257393db446aSBoris Brezillon } 257493db446aSBoris Brezillon 257593db446aSBoris Brezillon if (rb >= nfc->caps->max_rb_nb) { 257693db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max RB = %d)\n", 257793db446aSBoris Brezillon rb, nfc->caps->max_rb_nb); 257893db446aSBoris Brezillon return -EINVAL; 257993db446aSBoris Brezillon } 258093db446aSBoris Brezillon 258193db446aSBoris Brezillon marvell_nand->sels[i].rb = rb; 258293db446aSBoris Brezillon } 258393db446aSBoris Brezillon 258493db446aSBoris Brezillon chip = &marvell_nand->chip; 258593db446aSBoris Brezillon chip->controller = &nfc->controller; 258693db446aSBoris Brezillon nand_set_flash_node(chip, np); 258793db446aSBoris Brezillon 258893db446aSBoris Brezillon chip->exec_op = marvell_nfc_exec_op; 258993db446aSBoris Brezillon chip->select_chip = marvell_nfc_select_chip; 259093db446aSBoris Brezillon if (!of_property_read_bool(np, "marvell,nand-keep-config")) 259193db446aSBoris Brezillon chip->setup_data_interface = marvell_nfc_setup_data_interface; 259293db446aSBoris Brezillon 259393db446aSBoris Brezillon mtd = nand_to_mtd(chip); 259493db446aSBoris Brezillon mtd->dev.parent = dev; 259593db446aSBoris Brezillon 259693db446aSBoris Brezillon /* 259793db446aSBoris Brezillon * Default to HW ECC engine mode. If the nand-ecc-mode property is given 259893db446aSBoris Brezillon * in the DT node, this entry will be overwritten in nand_scan_ident(). 259993db446aSBoris Brezillon */ 260093db446aSBoris Brezillon chip->ecc.mode = NAND_ECC_HW; 260193db446aSBoris Brezillon 260293db446aSBoris Brezillon /* 260393db446aSBoris Brezillon * Save a reference value for timing registers before 260493db446aSBoris Brezillon * ->setup_data_interface() is called. 260593db446aSBoris Brezillon */ 260693db446aSBoris Brezillon marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0); 260793db446aSBoris Brezillon marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); 260893db446aSBoris Brezillon 260993db446aSBoris Brezillon chip->options |= NAND_BUSWIDTH_AUTO; 26108831e48bSMiquel Raynal 261100ad378fSBoris Brezillon ret = nand_scan(chip, marvell_nand->nsels); 261293db446aSBoris Brezillon if (ret) { 26138831e48bSMiquel Raynal dev_err(dev, "could not scan the nand chip\n"); 261493db446aSBoris Brezillon return ret; 261593db446aSBoris Brezillon } 261693db446aSBoris Brezillon 261793db446aSBoris Brezillon if (pdata) 261893db446aSBoris Brezillon /* Legacy bindings support only one chip */ 26193383fb35SBoris Brezillon ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); 262093db446aSBoris Brezillon else 262193db446aSBoris Brezillon ret = mtd_device_register(mtd, NULL, 0); 262293db446aSBoris Brezillon if (ret) { 262393db446aSBoris Brezillon dev_err(dev, "failed to register mtd device: %d\n", ret); 262459ac276fSBoris Brezillon nand_release(chip); 262593db446aSBoris Brezillon return ret; 262693db446aSBoris Brezillon } 262793db446aSBoris Brezillon 262893db446aSBoris Brezillon list_add_tail(&marvell_nand->node, &nfc->chips); 262993db446aSBoris Brezillon 263093db446aSBoris Brezillon return 0; 263193db446aSBoris Brezillon } 263293db446aSBoris Brezillon 263393db446aSBoris Brezillon static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc) 263493db446aSBoris Brezillon { 263593db446aSBoris Brezillon struct device_node *np = dev->of_node; 263693db446aSBoris Brezillon struct device_node *nand_np; 263793db446aSBoris Brezillon int max_cs = nfc->caps->max_cs_nb; 263893db446aSBoris Brezillon int nchips; 263993db446aSBoris Brezillon int ret; 264093db446aSBoris Brezillon 264193db446aSBoris Brezillon if (!np) 264293db446aSBoris Brezillon nchips = 1; 264393db446aSBoris Brezillon else 264493db446aSBoris Brezillon nchips = of_get_child_count(np); 264593db446aSBoris Brezillon 264693db446aSBoris Brezillon if (nchips > max_cs) { 264793db446aSBoris Brezillon dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips, 264893db446aSBoris Brezillon max_cs); 264993db446aSBoris Brezillon return -EINVAL; 265093db446aSBoris Brezillon } 265193db446aSBoris Brezillon 265293db446aSBoris Brezillon /* 265393db446aSBoris Brezillon * Legacy bindings do not use child nodes to exhibit NAND chip 265493db446aSBoris Brezillon * properties and layout. Instead, NAND properties are mixed with the 265593db446aSBoris Brezillon * controller ones, and partitions are defined as direct subnodes of the 265693db446aSBoris Brezillon * NAND controller node. 265793db446aSBoris Brezillon */ 265893db446aSBoris Brezillon if (nfc->caps->legacy_of_bindings) { 265993db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, np); 266093db446aSBoris Brezillon return ret; 266193db446aSBoris Brezillon } 266293db446aSBoris Brezillon 266393db446aSBoris Brezillon for_each_child_of_node(np, nand_np) { 266493db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, nand_np); 266593db446aSBoris Brezillon if (ret) { 266693db446aSBoris Brezillon of_node_put(nand_np); 266793db446aSBoris Brezillon return ret; 266893db446aSBoris Brezillon } 266993db446aSBoris Brezillon } 267093db446aSBoris Brezillon 267193db446aSBoris Brezillon return 0; 267293db446aSBoris Brezillon } 267393db446aSBoris Brezillon 267493db446aSBoris Brezillon static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc) 267593db446aSBoris Brezillon { 267693db446aSBoris Brezillon struct marvell_nand_chip *entry, *temp; 267793db446aSBoris Brezillon 267893db446aSBoris Brezillon list_for_each_entry_safe(entry, temp, &nfc->chips, node) { 267959ac276fSBoris Brezillon nand_release(&entry->chip); 268093db446aSBoris Brezillon list_del(&entry->node); 268193db446aSBoris Brezillon } 268293db446aSBoris Brezillon } 268393db446aSBoris Brezillon 268493db446aSBoris Brezillon static int marvell_nfc_init_dma(struct marvell_nfc *nfc) 268593db446aSBoris Brezillon { 268693db446aSBoris Brezillon struct platform_device *pdev = container_of(nfc->dev, 268793db446aSBoris Brezillon struct platform_device, 268893db446aSBoris Brezillon dev); 268993db446aSBoris Brezillon struct dma_slave_config config = {}; 269093db446aSBoris Brezillon struct resource *r; 269193db446aSBoris Brezillon int ret; 269293db446aSBoris Brezillon 269393db446aSBoris Brezillon if (!IS_ENABLED(CONFIG_PXA_DMA)) { 269493db446aSBoris Brezillon dev_warn(nfc->dev, 269593db446aSBoris Brezillon "DMA not enabled in configuration\n"); 269693db446aSBoris Brezillon return -ENOTSUPP; 269793db446aSBoris Brezillon } 269893db446aSBoris Brezillon 269993db446aSBoris Brezillon ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32)); 270093db446aSBoris Brezillon if (ret) 270193db446aSBoris Brezillon return ret; 270293db446aSBoris Brezillon 2703ac75a50bSRobert Jarzmik nfc->dma_chan = dma_request_slave_channel(nfc->dev, "data"); 270493db446aSBoris Brezillon if (!nfc->dma_chan) { 270593db446aSBoris Brezillon dev_err(nfc->dev, 270693db446aSBoris Brezillon "Unable to request data DMA channel\n"); 270793db446aSBoris Brezillon return -ENODEV; 270893db446aSBoris Brezillon } 270993db446aSBoris Brezillon 271093db446aSBoris Brezillon r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 271193db446aSBoris Brezillon if (!r) 271293db446aSBoris Brezillon return -ENXIO; 271393db446aSBoris Brezillon 271493db446aSBoris Brezillon config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 271593db446aSBoris Brezillon config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 271693db446aSBoris Brezillon config.src_addr = r->start + NDDB; 271793db446aSBoris Brezillon config.dst_addr = r->start + NDDB; 271893db446aSBoris Brezillon config.src_maxburst = 32; 271993db446aSBoris Brezillon config.dst_maxburst = 32; 272093db446aSBoris Brezillon ret = dmaengine_slave_config(nfc->dma_chan, &config); 272193db446aSBoris Brezillon if (ret < 0) { 272293db446aSBoris Brezillon dev_err(nfc->dev, "Failed to configure DMA channel\n"); 272393db446aSBoris Brezillon return ret; 272493db446aSBoris Brezillon } 272593db446aSBoris Brezillon 272693db446aSBoris Brezillon /* 272793db446aSBoris Brezillon * DMA must act on length multiple of 32 and this length may be 272893db446aSBoris Brezillon * bigger than the destination buffer. Use this buffer instead 272993db446aSBoris Brezillon * for DMA transfers and then copy the desired amount of data to 273093db446aSBoris Brezillon * the provided buffer. 273193db446aSBoris Brezillon */ 273293db446aSBoris Brezillon nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); 273393db446aSBoris Brezillon if (!nfc->dma_buf) 273493db446aSBoris Brezillon return -ENOMEM; 273593db446aSBoris Brezillon 273693db446aSBoris Brezillon nfc->use_dma = true; 273793db446aSBoris Brezillon 273893db446aSBoris Brezillon return 0; 273993db446aSBoris Brezillon } 274093db446aSBoris Brezillon 2741bd9c3f9bSDaniel Mack static void marvell_nfc_reset(struct marvell_nfc *nfc) 2742bd9c3f9bSDaniel Mack { 2743bd9c3f9bSDaniel Mack /* 2744bd9c3f9bSDaniel Mack * ECC operations and interruptions are only enabled when specifically 2745bd9c3f9bSDaniel Mack * needed. ECC shall not be activated in the early stages (fails probe). 2746bd9c3f9bSDaniel Mack * Arbiter flag, even if marked as "reserved", must be set (empirical). 2747bd9c3f9bSDaniel Mack * SPARE_EN bit must always be set or ECC bytes will not be at the same 2748bd9c3f9bSDaniel Mack * offset in the read page and this will fail the protection. 2749bd9c3f9bSDaniel Mack */ 2750bd9c3f9bSDaniel Mack writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN | 2751bd9c3f9bSDaniel Mack NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR); 2752bd9c3f9bSDaniel Mack writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR); 2753bd9c3f9bSDaniel Mack writel_relaxed(0, nfc->regs + NDECCCTRL); 2754bd9c3f9bSDaniel Mack } 2755bd9c3f9bSDaniel Mack 275693db446aSBoris Brezillon static int marvell_nfc_init(struct marvell_nfc *nfc) 275793db446aSBoris Brezillon { 275893db446aSBoris Brezillon struct device_node *np = nfc->dev->of_node; 275993db446aSBoris Brezillon 276093db446aSBoris Brezillon /* 276193db446aSBoris Brezillon * Some SoCs like A7k/A8k need to enable manually the NAND 276293db446aSBoris Brezillon * controller, gated clocks and reset bits to avoid being bootloader 276393db446aSBoris Brezillon * dependent. This is done through the use of the System Functions 276493db446aSBoris Brezillon * registers. 276593db446aSBoris Brezillon */ 276693db446aSBoris Brezillon if (nfc->caps->need_system_controller) { 276793db446aSBoris Brezillon struct regmap *sysctrl_base = 276893db446aSBoris Brezillon syscon_regmap_lookup_by_phandle(np, 276993db446aSBoris Brezillon "marvell,system-controller"); 277093db446aSBoris Brezillon 277193db446aSBoris Brezillon if (IS_ERR(sysctrl_base)) 277293db446aSBoris Brezillon return PTR_ERR(sysctrl_base); 277393db446aSBoris Brezillon 277488aa3bbfSThomas Petazzoni regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, 277588aa3bbfSThomas Petazzoni GENCONF_SOC_DEVICE_MUX_NFC_EN | 277693db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST | 277793db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST | 277888aa3bbfSThomas Petazzoni GENCONF_SOC_DEVICE_MUX_NFC_INT_EN); 277993db446aSBoris Brezillon 278088aa3bbfSThomas Petazzoni regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL, 278188aa3bbfSThomas Petazzoni GENCONF_CLK_GATING_CTRL_ND_GATE, 278288aa3bbfSThomas Petazzoni GENCONF_CLK_GATING_CTRL_ND_GATE); 278393db446aSBoris Brezillon 278488aa3bbfSThomas Petazzoni regmap_update_bits(sysctrl_base, GENCONF_ND_CLK_CTRL, 278588aa3bbfSThomas Petazzoni GENCONF_ND_CLK_CTRL_EN, 278688aa3bbfSThomas Petazzoni GENCONF_ND_CLK_CTRL_EN); 278793db446aSBoris Brezillon } 278893db446aSBoris Brezillon 278993db446aSBoris Brezillon /* Configure the DMA if appropriate */ 279093db446aSBoris Brezillon if (!nfc->caps->is_nfcv2) 279193db446aSBoris Brezillon marvell_nfc_init_dma(nfc); 279293db446aSBoris Brezillon 2793bd9c3f9bSDaniel Mack marvell_nfc_reset(nfc); 279493db446aSBoris Brezillon 279593db446aSBoris Brezillon return 0; 279693db446aSBoris Brezillon } 279793db446aSBoris Brezillon 279893db446aSBoris Brezillon static int marvell_nfc_probe(struct platform_device *pdev) 279993db446aSBoris Brezillon { 280093db446aSBoris Brezillon struct device *dev = &pdev->dev; 280193db446aSBoris Brezillon struct resource *r; 280293db446aSBoris Brezillon struct marvell_nfc *nfc; 280393db446aSBoris Brezillon int ret; 280493db446aSBoris Brezillon int irq; 280593db446aSBoris Brezillon 280693db446aSBoris Brezillon nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc), 280793db446aSBoris Brezillon GFP_KERNEL); 280893db446aSBoris Brezillon if (!nfc) 280993db446aSBoris Brezillon return -ENOMEM; 281093db446aSBoris Brezillon 281193db446aSBoris Brezillon nfc->dev = dev; 28127da45139SMiquel Raynal nand_controller_init(&nfc->controller); 28138831e48bSMiquel Raynal nfc->controller.ops = &marvell_nand_controller_ops; 281493db446aSBoris Brezillon INIT_LIST_HEAD(&nfc->chips); 281593db446aSBoris Brezillon 281693db446aSBoris Brezillon r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 281793db446aSBoris Brezillon nfc->regs = devm_ioremap_resource(dev, r); 281893db446aSBoris Brezillon if (IS_ERR(nfc->regs)) 281993db446aSBoris Brezillon return PTR_ERR(nfc->regs); 282093db446aSBoris Brezillon 282193db446aSBoris Brezillon irq = platform_get_irq(pdev, 0); 282293db446aSBoris Brezillon if (irq < 0) { 282393db446aSBoris Brezillon dev_err(dev, "failed to retrieve irq\n"); 282493db446aSBoris Brezillon return irq; 282593db446aSBoris Brezillon } 282693db446aSBoris Brezillon 28276b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, "core"); 2828961ba15cSGregory CLEMENT 2829961ba15cSGregory CLEMENT /* Managed the legacy case (when the first clock was not named) */ 28306b6de654SBoris Brezillon if (nfc->core_clk == ERR_PTR(-ENOENT)) 28316b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, NULL); 2832961ba15cSGregory CLEMENT 28336b6de654SBoris Brezillon if (IS_ERR(nfc->core_clk)) 28346b6de654SBoris Brezillon return PTR_ERR(nfc->core_clk); 283593db446aSBoris Brezillon 28366b6de654SBoris Brezillon ret = clk_prepare_enable(nfc->core_clk); 283793db446aSBoris Brezillon if (ret) 283893db446aSBoris Brezillon return ret; 283993db446aSBoris Brezillon 2840961ba15cSGregory CLEMENT nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); 2841f9e64d61SDaniel Mack if (IS_ERR(nfc->reg_clk)) { 2842961ba15cSGregory CLEMENT if (PTR_ERR(nfc->reg_clk) != -ENOENT) { 2843961ba15cSGregory CLEMENT ret = PTR_ERR(nfc->reg_clk); 28446b6de654SBoris Brezillon goto unprepare_core_clk; 2845961ba15cSGregory CLEMENT } 2846f9e64d61SDaniel Mack 2847f9e64d61SDaniel Mack nfc->reg_clk = NULL; 2848961ba15cSGregory CLEMENT } 2849961ba15cSGregory CLEMENT 2850f9e64d61SDaniel Mack ret = clk_prepare_enable(nfc->reg_clk); 2851f9e64d61SDaniel Mack if (ret) 2852f9e64d61SDaniel Mack goto unprepare_core_clk; 2853f9e64d61SDaniel Mack 285493db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_ALL_INT); 285593db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 285693db446aSBoris Brezillon ret = devm_request_irq(dev, irq, marvell_nfc_isr, 285793db446aSBoris Brezillon 0, "marvell-nfc", nfc); 285893db446aSBoris Brezillon if (ret) 2859961ba15cSGregory CLEMENT goto unprepare_reg_clk; 286093db446aSBoris Brezillon 286193db446aSBoris Brezillon /* Get NAND controller capabilities */ 286293db446aSBoris Brezillon if (pdev->id_entry) 286393db446aSBoris Brezillon nfc->caps = (void *)pdev->id_entry->driver_data; 286493db446aSBoris Brezillon else 286593db446aSBoris Brezillon nfc->caps = of_device_get_match_data(&pdev->dev); 286693db446aSBoris Brezillon 286793db446aSBoris Brezillon if (!nfc->caps) { 286893db446aSBoris Brezillon dev_err(dev, "Could not retrieve NFC caps\n"); 286993db446aSBoris Brezillon ret = -EINVAL; 2870961ba15cSGregory CLEMENT goto unprepare_reg_clk; 287193db446aSBoris Brezillon } 287293db446aSBoris Brezillon 287393db446aSBoris Brezillon /* Init the controller and then probe the chips */ 287493db446aSBoris Brezillon ret = marvell_nfc_init(nfc); 287593db446aSBoris Brezillon if (ret) 2876961ba15cSGregory CLEMENT goto unprepare_reg_clk; 287793db446aSBoris Brezillon 287893db446aSBoris Brezillon platform_set_drvdata(pdev, nfc); 287993db446aSBoris Brezillon 288093db446aSBoris Brezillon ret = marvell_nand_chips_init(dev, nfc); 288193db446aSBoris Brezillon if (ret) 2882961ba15cSGregory CLEMENT goto unprepare_reg_clk; 288393db446aSBoris Brezillon 288493db446aSBoris Brezillon return 0; 288593db446aSBoris Brezillon 2886961ba15cSGregory CLEMENT unprepare_reg_clk: 2887961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk); 28886b6de654SBoris Brezillon unprepare_core_clk: 28896b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk); 289093db446aSBoris Brezillon 289193db446aSBoris Brezillon return ret; 289293db446aSBoris Brezillon } 289393db446aSBoris Brezillon 289493db446aSBoris Brezillon static int marvell_nfc_remove(struct platform_device *pdev) 289593db446aSBoris Brezillon { 289693db446aSBoris Brezillon struct marvell_nfc *nfc = platform_get_drvdata(pdev); 289793db446aSBoris Brezillon 289893db446aSBoris Brezillon marvell_nand_chips_cleanup(nfc); 289993db446aSBoris Brezillon 290093db446aSBoris Brezillon if (nfc->use_dma) { 290193db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 290293db446aSBoris Brezillon dma_release_channel(nfc->dma_chan); 290393db446aSBoris Brezillon } 290493db446aSBoris Brezillon 2905961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk); 29066b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk); 290793db446aSBoris Brezillon 290893db446aSBoris Brezillon return 0; 290993db446aSBoris Brezillon } 291093db446aSBoris Brezillon 2911bd9c3f9bSDaniel Mack static int __maybe_unused marvell_nfc_suspend(struct device *dev) 2912bd9c3f9bSDaniel Mack { 2913bd9c3f9bSDaniel Mack struct marvell_nfc *nfc = dev_get_drvdata(dev); 2914bd9c3f9bSDaniel Mack struct marvell_nand_chip *chip; 2915bd9c3f9bSDaniel Mack 2916bd9c3f9bSDaniel Mack list_for_each_entry(chip, &nfc->chips, node) 2917bd9c3f9bSDaniel Mack marvell_nfc_wait_ndrun(&chip->chip); 2918bd9c3f9bSDaniel Mack 2919bd9c3f9bSDaniel Mack clk_disable_unprepare(nfc->reg_clk); 2920bd9c3f9bSDaniel Mack clk_disable_unprepare(nfc->core_clk); 2921bd9c3f9bSDaniel Mack 2922bd9c3f9bSDaniel Mack return 0; 2923bd9c3f9bSDaniel Mack } 2924bd9c3f9bSDaniel Mack 2925bd9c3f9bSDaniel Mack static int __maybe_unused marvell_nfc_resume(struct device *dev) 2926bd9c3f9bSDaniel Mack { 2927bd9c3f9bSDaniel Mack struct marvell_nfc *nfc = dev_get_drvdata(dev); 2928bd9c3f9bSDaniel Mack int ret; 2929bd9c3f9bSDaniel Mack 2930bd9c3f9bSDaniel Mack ret = clk_prepare_enable(nfc->core_clk); 2931bd9c3f9bSDaniel Mack if (ret < 0) 2932bd9c3f9bSDaniel Mack return ret; 2933bd9c3f9bSDaniel Mack 2934bd9c3f9bSDaniel Mack ret = clk_prepare_enable(nfc->reg_clk); 2935bd9c3f9bSDaniel Mack if (ret < 0) 2936bd9c3f9bSDaniel Mack return ret; 2937bd9c3f9bSDaniel Mack 2938bd9c3f9bSDaniel Mack /* 2939bd9c3f9bSDaniel Mack * Reset nfc->selected_chip so the next command will cause the timing 2940bd9c3f9bSDaniel Mack * registers to be restored in marvell_nfc_select_chip(). 2941bd9c3f9bSDaniel Mack */ 2942bd9c3f9bSDaniel Mack nfc->selected_chip = NULL; 2943bd9c3f9bSDaniel Mack 2944bd9c3f9bSDaniel Mack /* Reset registers that have lost their contents */ 2945bd9c3f9bSDaniel Mack marvell_nfc_reset(nfc); 2946bd9c3f9bSDaniel Mack 2947bd9c3f9bSDaniel Mack return 0; 2948bd9c3f9bSDaniel Mack } 2949bd9c3f9bSDaniel Mack 2950bd9c3f9bSDaniel Mack static const struct dev_pm_ops marvell_nfc_pm_ops = { 2951bd9c3f9bSDaniel Mack SET_SYSTEM_SLEEP_PM_OPS(marvell_nfc_suspend, marvell_nfc_resume) 2952bd9c3f9bSDaniel Mack }; 2953bd9c3f9bSDaniel Mack 295493db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { 295593db446aSBoris Brezillon .max_cs_nb = 4, 295693db446aSBoris Brezillon .max_rb_nb = 2, 295793db446aSBoris Brezillon .need_system_controller = true, 295893db446aSBoris Brezillon .is_nfcv2 = true, 295993db446aSBoris Brezillon }; 296093db446aSBoris Brezillon 296193db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { 296293db446aSBoris Brezillon .max_cs_nb = 4, 296393db446aSBoris Brezillon .max_rb_nb = 2, 296493db446aSBoris Brezillon .is_nfcv2 = true, 296593db446aSBoris Brezillon }; 296693db446aSBoris Brezillon 296793db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = { 296893db446aSBoris Brezillon .max_cs_nb = 2, 296993db446aSBoris Brezillon .max_rb_nb = 1, 297093db446aSBoris Brezillon .use_dma = true, 297193db446aSBoris Brezillon }; 297293db446aSBoris Brezillon 297393db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = { 297493db446aSBoris Brezillon .max_cs_nb = 4, 297593db446aSBoris Brezillon .max_rb_nb = 2, 297693db446aSBoris Brezillon .need_system_controller = true, 297793db446aSBoris Brezillon .legacy_of_bindings = true, 297893db446aSBoris Brezillon .is_nfcv2 = true, 297993db446aSBoris Brezillon }; 298093db446aSBoris Brezillon 298193db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = { 298293db446aSBoris Brezillon .max_cs_nb = 4, 298393db446aSBoris Brezillon .max_rb_nb = 2, 298493db446aSBoris Brezillon .legacy_of_bindings = true, 298593db446aSBoris Brezillon .is_nfcv2 = true, 298693db446aSBoris Brezillon }; 298793db446aSBoris Brezillon 298893db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = { 298993db446aSBoris Brezillon .max_cs_nb = 2, 299093db446aSBoris Brezillon .max_rb_nb = 1, 299193db446aSBoris Brezillon .legacy_of_bindings = true, 299293db446aSBoris Brezillon .use_dma = true, 299393db446aSBoris Brezillon }; 299493db446aSBoris Brezillon 299593db446aSBoris Brezillon static const struct platform_device_id marvell_nfc_platform_ids[] = { 299693db446aSBoris Brezillon { 299793db446aSBoris Brezillon .name = "pxa3xx-nand", 299893db446aSBoris Brezillon .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps, 299993db446aSBoris Brezillon }, 300093db446aSBoris Brezillon { /* sentinel */ }, 300193db446aSBoris Brezillon }; 300293db446aSBoris Brezillon MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids); 300393db446aSBoris Brezillon 300493db446aSBoris Brezillon static const struct of_device_id marvell_nfc_of_ids[] = { 300593db446aSBoris Brezillon { 300693db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand-controller", 300793db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_caps, 300893db446aSBoris Brezillon }, 300993db446aSBoris Brezillon { 301093db446aSBoris Brezillon .compatible = "marvell,armada370-nand-controller", 301193db446aSBoris Brezillon .data = &marvell_armada370_nfc_caps, 301293db446aSBoris Brezillon }, 301393db446aSBoris Brezillon { 301493db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand-controller", 301593db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_caps, 301693db446aSBoris Brezillon }, 301793db446aSBoris Brezillon /* Support for old/deprecated bindings: */ 301893db446aSBoris Brezillon { 301993db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand", 302093db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_legacy_caps, 302193db446aSBoris Brezillon }, 302293db446aSBoris Brezillon { 302393db446aSBoris Brezillon .compatible = "marvell,armada370-nand", 302493db446aSBoris Brezillon .data = &marvell_armada370_nfc_legacy_caps, 302593db446aSBoris Brezillon }, 302693db446aSBoris Brezillon { 302793db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand", 302893db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_legacy_caps, 302993db446aSBoris Brezillon }, 303093db446aSBoris Brezillon { /* sentinel */ }, 303193db446aSBoris Brezillon }; 303293db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids); 303393db446aSBoris Brezillon 303493db446aSBoris Brezillon static struct platform_driver marvell_nfc_driver = { 303593db446aSBoris Brezillon .driver = { 303693db446aSBoris Brezillon .name = "marvell-nfc", 303793db446aSBoris Brezillon .of_match_table = marvell_nfc_of_ids, 3038bd9c3f9bSDaniel Mack .pm = &marvell_nfc_pm_ops, 303993db446aSBoris Brezillon }, 304093db446aSBoris Brezillon .id_table = marvell_nfc_platform_ids, 304193db446aSBoris Brezillon .probe = marvell_nfc_probe, 304293db446aSBoris Brezillon .remove = marvell_nfc_remove, 304393db446aSBoris Brezillon }; 304493db446aSBoris Brezillon module_platform_driver(marvell_nfc_driver); 304593db446aSBoris Brezillon 304693db446aSBoris Brezillon MODULE_LICENSE("GPL"); 304793db446aSBoris Brezillon MODULE_DESCRIPTION("Marvell NAND controller driver"); 3048