193db446aSBoris Brezillon // SPDX-License-Identifier: GPL-2.0 293db446aSBoris Brezillon /* 393db446aSBoris Brezillon * Marvell NAND flash controller driver 493db446aSBoris Brezillon * 593db446aSBoris Brezillon * Copyright (C) 2017 Marvell 693db446aSBoris Brezillon * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com> 793db446aSBoris Brezillon * 893db446aSBoris Brezillon */ 993db446aSBoris Brezillon 1093db446aSBoris Brezillon #include <linux/module.h> 1193db446aSBoris Brezillon #include <linux/clk.h> 1293db446aSBoris Brezillon #include <linux/mtd/rawnand.h> 1393db446aSBoris Brezillon #include <linux/of_platform.h> 1493db446aSBoris Brezillon #include <linux/iopoll.h> 1593db446aSBoris Brezillon #include <linux/interrupt.h> 1693db446aSBoris Brezillon #include <linux/slab.h> 1793db446aSBoris Brezillon #include <linux/mfd/syscon.h> 1893db446aSBoris Brezillon #include <linux/regmap.h> 1993db446aSBoris Brezillon #include <asm/unaligned.h> 2093db446aSBoris Brezillon 2193db446aSBoris Brezillon #include <linux/dmaengine.h> 2293db446aSBoris Brezillon #include <linux/dma-mapping.h> 2393db446aSBoris Brezillon #include <linux/dma/pxa-dma.h> 2493db446aSBoris Brezillon #include <linux/platform_data/mtd-nand-pxa3xx.h> 2593db446aSBoris Brezillon 2693db446aSBoris Brezillon /* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */ 2793db446aSBoris Brezillon #define FIFO_DEPTH 8 2893db446aSBoris Brezillon #define FIFO_REP(x) (x / sizeof(u32)) 2993db446aSBoris Brezillon #define BCH_SEQ_READS (32 / FIFO_DEPTH) 3093db446aSBoris Brezillon /* NFC does not support transfers of larger chunks at a time */ 3193db446aSBoris Brezillon #define MAX_CHUNK_SIZE 2112 3293db446aSBoris Brezillon /* NFCv1 cannot read more that 7 bytes of ID */ 3393db446aSBoris Brezillon #define NFCV1_READID_LEN 7 3493db446aSBoris Brezillon /* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */ 3593db446aSBoris Brezillon #define POLL_PERIOD 0 3693db446aSBoris Brezillon #define POLL_TIMEOUT 100000 3793db446aSBoris Brezillon /* Interrupt maximum wait period in ms */ 3893db446aSBoris Brezillon #define IRQ_TIMEOUT 1000 3993db446aSBoris Brezillon /* Latency in clock cycles between SoC pins and NFC logic */ 4093db446aSBoris Brezillon #define MIN_RD_DEL_CNT 3 4193db446aSBoris Brezillon /* Maximum number of contiguous address cycles */ 4293db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV1 5 4393db446aSBoris Brezillon #define MAX_ADDRESS_CYC_NFCV2 7 4493db446aSBoris Brezillon /* System control registers/bits to enable the NAND controller on some SoCs */ 4593db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX 0x208 4693db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0) 4793db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20) 4893db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21) 4993db446aSBoris Brezillon #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25) 5093db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL 0x220 5193db446aSBoris Brezillon #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2) 5293db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL 0x700 5393db446aSBoris Brezillon #define GENCONF_ND_CLK_CTRL_EN BIT(0) 5493db446aSBoris Brezillon 5593db446aSBoris Brezillon /* NAND controller data flash control register */ 5693db446aSBoris Brezillon #define NDCR 0x00 5793db446aSBoris Brezillon #define NDCR_ALL_INT GENMASK(11, 0) 5893db446aSBoris Brezillon #define NDCR_CS1_CMDDM BIT(7) 5993db446aSBoris Brezillon #define NDCR_CS0_CMDDM BIT(8) 6093db446aSBoris Brezillon #define NDCR_RDYM BIT(11) 6193db446aSBoris Brezillon #define NDCR_ND_ARB_EN BIT(12) 6293db446aSBoris Brezillon #define NDCR_RA_START BIT(15) 6393db446aSBoris Brezillon #define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16) 6493db446aSBoris Brezillon #define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0) 6593db446aSBoris Brezillon #define NDCR_DWIDTH_M BIT(26) 6693db446aSBoris Brezillon #define NDCR_DWIDTH_C BIT(27) 6793db446aSBoris Brezillon #define NDCR_ND_RUN BIT(28) 6893db446aSBoris Brezillon #define NDCR_DMA_EN BIT(29) 6993db446aSBoris Brezillon #define NDCR_ECC_EN BIT(30) 7093db446aSBoris Brezillon #define NDCR_SPARE_EN BIT(31) 7193db446aSBoris Brezillon #define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \ 7293db446aSBoris Brezillon NDCR_DWIDTH_M | NDCR_DWIDTH_C)) 7393db446aSBoris Brezillon 7493db446aSBoris Brezillon /* NAND interface timing parameter 0 register */ 7593db446aSBoris Brezillon #define NDTR0 0x04 7693db446aSBoris Brezillon #define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0) 7793db446aSBoris Brezillon #define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3) 7893db446aSBoris Brezillon #define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3) 7993db446aSBoris Brezillon #define NDTR0_SEL_NRE_EDGE BIT(7) 8093db446aSBoris Brezillon #define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8) 8193db446aSBoris Brezillon #define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11) 8293db446aSBoris Brezillon #define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16) 8393db446aSBoris Brezillon #define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19) 8493db446aSBoris Brezillon #define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22) 8593db446aSBoris Brezillon #define NDTR0_SELCNTR BIT(26) 8693db446aSBoris Brezillon #define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27) 8793db446aSBoris Brezillon 8893db446aSBoris Brezillon /* NAND interface timing parameter 1 register */ 8993db446aSBoris Brezillon #define NDTR1 0x0C 9093db446aSBoris Brezillon #define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0) 9193db446aSBoris Brezillon #define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4) 9293db446aSBoris Brezillon #define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8) 9393db446aSBoris Brezillon #define NDTR1_PRESCALE BIT(14) 9493db446aSBoris Brezillon #define NDTR1_WAIT_MODE BIT(15) 9593db446aSBoris Brezillon #define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16) 9693db446aSBoris Brezillon 9793db446aSBoris Brezillon /* NAND controller status register */ 9893db446aSBoris Brezillon #define NDSR 0x14 9993db446aSBoris Brezillon #define NDSR_WRCMDREQ BIT(0) 10093db446aSBoris Brezillon #define NDSR_RDDREQ BIT(1) 10193db446aSBoris Brezillon #define NDSR_WRDREQ BIT(2) 10293db446aSBoris Brezillon #define NDSR_CORERR BIT(3) 10393db446aSBoris Brezillon #define NDSR_UNCERR BIT(4) 10493db446aSBoris Brezillon #define NDSR_CMDD(cs) BIT(8 - cs) 10593db446aSBoris Brezillon #define NDSR_RDY(rb) BIT(11 + rb) 10693db446aSBoris Brezillon #define NDSR_ERRCNT(x) ((x >> 16) & 0x1F) 10793db446aSBoris Brezillon 10893db446aSBoris Brezillon /* NAND ECC control register */ 10993db446aSBoris Brezillon #define NDECCCTRL 0x28 11093db446aSBoris Brezillon #define NDECCCTRL_BCH_EN BIT(0) 11193db446aSBoris Brezillon 11293db446aSBoris Brezillon /* NAND controller data buffer register */ 11393db446aSBoris Brezillon #define NDDB 0x40 11493db446aSBoris Brezillon 11593db446aSBoris Brezillon /* NAND controller command buffer 0 register */ 11693db446aSBoris Brezillon #define NDCB0 0x48 11793db446aSBoris Brezillon #define NDCB0_CMD1(x) ((x & 0xFF) << 0) 11893db446aSBoris Brezillon #define NDCB0_CMD2(x) ((x & 0xFF) << 8) 11993db446aSBoris Brezillon #define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16) 12093db446aSBoris Brezillon #define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7) 12193db446aSBoris Brezillon #define NDCB0_DBC BIT(19) 12293db446aSBoris Brezillon #define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21) 12393db446aSBoris Brezillon #define NDCB0_CSEL BIT(24) 12493db446aSBoris Brezillon #define NDCB0_RDY_BYP BIT(27) 12593db446aSBoris Brezillon #define NDCB0_LEN_OVRD BIT(28) 12693db446aSBoris Brezillon #define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29) 12793db446aSBoris Brezillon 12893db446aSBoris Brezillon /* NAND controller command buffer 1 register */ 12993db446aSBoris Brezillon #define NDCB1 0x4C 13093db446aSBoris Brezillon #define NDCB1_COLS(x) ((x & 0xFFFF) << 0) 13193db446aSBoris Brezillon #define NDCB1_ADDRS_PAGE(x) (x << 16) 13293db446aSBoris Brezillon 13393db446aSBoris Brezillon /* NAND controller command buffer 2 register */ 13493db446aSBoris Brezillon #define NDCB2 0x50 13593db446aSBoris Brezillon #define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0) 13693db446aSBoris Brezillon #define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0) 13793db446aSBoris Brezillon 13893db446aSBoris Brezillon /* NAND controller command buffer 3 register */ 13993db446aSBoris Brezillon #define NDCB3 0x54 14093db446aSBoris Brezillon #define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16) 14193db446aSBoris Brezillon #define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24) 14293db446aSBoris Brezillon 14393db446aSBoris Brezillon /* NAND controller command buffer 0 register 'type' and 'xtype' fields */ 14493db446aSBoris Brezillon #define TYPE_READ 0 14593db446aSBoris Brezillon #define TYPE_WRITE 1 14693db446aSBoris Brezillon #define TYPE_ERASE 2 14793db446aSBoris Brezillon #define TYPE_READ_ID 3 14893db446aSBoris Brezillon #define TYPE_STATUS 4 14993db446aSBoris Brezillon #define TYPE_RESET 5 15093db446aSBoris Brezillon #define TYPE_NAKED_CMD 6 15193db446aSBoris Brezillon #define TYPE_NAKED_ADDR 7 15293db446aSBoris Brezillon #define TYPE_MASK 7 15393db446aSBoris Brezillon #define XTYPE_MONOLITHIC_RW 0 15493db446aSBoris Brezillon #define XTYPE_LAST_NAKED_RW 1 15593db446aSBoris Brezillon #define XTYPE_FINAL_COMMAND 3 15693db446aSBoris Brezillon #define XTYPE_READ 4 15793db446aSBoris Brezillon #define XTYPE_WRITE_DISPATCH 4 15893db446aSBoris Brezillon #define XTYPE_NAKED_RW 5 15993db446aSBoris Brezillon #define XTYPE_COMMAND_DISPATCH 6 16093db446aSBoris Brezillon #define XTYPE_MASK 7 16193db446aSBoris Brezillon 16293db446aSBoris Brezillon /** 16393db446aSBoris Brezillon * Marvell ECC engine works differently than the others, in order to limit the 16493db446aSBoris Brezillon * size of the IP, hardware engineers chose to set a fixed strength at 16 bits 16593db446aSBoris Brezillon * per subpage, and depending on a the desired strength needed by the NAND chip, 16693db446aSBoris Brezillon * a particular layout mixing data/spare/ecc is defined, with a possible last 16793db446aSBoris Brezillon * chunk smaller that the others. 16893db446aSBoris Brezillon * 16993db446aSBoris Brezillon * @writesize: Full page size on which the layout applies 17093db446aSBoris Brezillon * @chunk: Desired ECC chunk size on which the layout applies 17193db446aSBoris Brezillon * @strength: Desired ECC strength (per chunk size bytes) on which the 17293db446aSBoris Brezillon * layout applies 17393db446aSBoris Brezillon * @nchunks: Total number of chunks 17493db446aSBoris Brezillon * @full_chunk_cnt: Number of full-sized chunks, which is the number of 17593db446aSBoris Brezillon * repetitions of the pattern: 17693db446aSBoris Brezillon * (data_bytes + spare_bytes + ecc_bytes). 17793db446aSBoris Brezillon * @data_bytes: Number of data bytes per chunk 17893db446aSBoris Brezillon * @spare_bytes: Number of spare bytes per chunk 17993db446aSBoris Brezillon * @ecc_bytes: Number of ecc bytes per chunk 18093db446aSBoris Brezillon * @last_data_bytes: Number of data bytes in the last chunk 18193db446aSBoris Brezillon * @last_spare_bytes: Number of spare bytes in the last chunk 18293db446aSBoris Brezillon * @last_ecc_bytes: Number of ecc bytes in the last chunk 18393db446aSBoris Brezillon */ 18493db446aSBoris Brezillon struct marvell_hw_ecc_layout { 18593db446aSBoris Brezillon /* Constraints */ 18693db446aSBoris Brezillon int writesize; 18793db446aSBoris Brezillon int chunk; 18893db446aSBoris Brezillon int strength; 18993db446aSBoris Brezillon /* Corresponding layout */ 19093db446aSBoris Brezillon int nchunks; 19193db446aSBoris Brezillon int full_chunk_cnt; 19293db446aSBoris Brezillon int data_bytes; 19393db446aSBoris Brezillon int spare_bytes; 19493db446aSBoris Brezillon int ecc_bytes; 19593db446aSBoris Brezillon int last_data_bytes; 19693db446aSBoris Brezillon int last_spare_bytes; 19793db446aSBoris Brezillon int last_ecc_bytes; 19893db446aSBoris Brezillon }; 19993db446aSBoris Brezillon 20093db446aSBoris Brezillon #define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \ 20193db446aSBoris Brezillon { \ 20293db446aSBoris Brezillon .writesize = ws, \ 20393db446aSBoris Brezillon .chunk = dc, \ 20493db446aSBoris Brezillon .strength = ds, \ 20593db446aSBoris Brezillon .nchunks = nc, \ 20693db446aSBoris Brezillon .full_chunk_cnt = fcc, \ 20793db446aSBoris Brezillon .data_bytes = db, \ 20893db446aSBoris Brezillon .spare_bytes = sb, \ 20993db446aSBoris Brezillon .ecc_bytes = eb, \ 21093db446aSBoris Brezillon .last_data_bytes = ldb, \ 21193db446aSBoris Brezillon .last_spare_bytes = lsb, \ 21293db446aSBoris Brezillon .last_ecc_bytes = leb, \ 21393db446aSBoris Brezillon } 21493db446aSBoris Brezillon 21593db446aSBoris Brezillon /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */ 21693db446aSBoris Brezillon static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = { 21793db446aSBoris Brezillon MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0), 21893db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0), 21993db446aSBoris Brezillon MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0), 22093db446aSBoris Brezillon MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0), 22193db446aSBoris Brezillon MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30), 22293db446aSBoris Brezillon }; 22393db446aSBoris Brezillon 22493db446aSBoris Brezillon /** 22593db446aSBoris Brezillon * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection 22693db446aSBoris Brezillon * is made by a field in NDCB0 register, and in another field in NDCB2 register. 22793db446aSBoris Brezillon * The datasheet describes the logic with an error: ADDR5 field is once 22893db446aSBoris Brezillon * declared at the beginning of NDCB2, and another time at its end. Because the 22993db446aSBoris Brezillon * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical 23093db446aSBoris Brezillon * to use the last bit of this field instead of the first ones. 23193db446aSBoris Brezillon * 23293db446aSBoris Brezillon * @cs: Wanted CE lane. 23393db446aSBoris Brezillon * @ndcb0_csel: Value of the NDCB0 register with or without the flag 23493db446aSBoris Brezillon * selecting the wanted CE lane. This is set once when 23593db446aSBoris Brezillon * the Device Tree is probed. 23693db446aSBoris Brezillon * @rb: Ready/Busy pin for the flash chip 23793db446aSBoris Brezillon */ 23893db446aSBoris Brezillon struct marvell_nand_chip_sel { 23993db446aSBoris Brezillon unsigned int cs; 24093db446aSBoris Brezillon u32 ndcb0_csel; 24193db446aSBoris Brezillon unsigned int rb; 24293db446aSBoris Brezillon }; 24393db446aSBoris Brezillon 24493db446aSBoris Brezillon /** 24593db446aSBoris Brezillon * NAND chip structure: stores NAND chip device related information 24693db446aSBoris Brezillon * 24793db446aSBoris Brezillon * @chip: Base NAND chip structure 24893db446aSBoris Brezillon * @node: Used to store NAND chips into a list 24993db446aSBoris Brezillon * @layout NAND layout when using hardware ECC 25093db446aSBoris Brezillon * @ndcr: Controller register value for this NAND chip 25193db446aSBoris Brezillon * @ndtr0: Timing registers 0 value for this NAND chip 25293db446aSBoris Brezillon * @ndtr1: Timing registers 1 value for this NAND chip 25393db446aSBoris Brezillon * @selected_die: Current active CS 25493db446aSBoris Brezillon * @nsels: Number of CS lines required by the NAND chip 25593db446aSBoris Brezillon * @sels: Array of CS lines descriptions 25693db446aSBoris Brezillon */ 25793db446aSBoris Brezillon struct marvell_nand_chip { 25893db446aSBoris Brezillon struct nand_chip chip; 25993db446aSBoris Brezillon struct list_head node; 26093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *layout; 26193db446aSBoris Brezillon u32 ndcr; 26293db446aSBoris Brezillon u32 ndtr0; 26393db446aSBoris Brezillon u32 ndtr1; 26493db446aSBoris Brezillon int addr_cyc; 26593db446aSBoris Brezillon int selected_die; 26693db446aSBoris Brezillon unsigned int nsels; 26793db446aSBoris Brezillon struct marvell_nand_chip_sel sels[0]; 26893db446aSBoris Brezillon }; 26993db446aSBoris Brezillon 27093db446aSBoris Brezillon static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip) 27193db446aSBoris Brezillon { 27293db446aSBoris Brezillon return container_of(chip, struct marvell_nand_chip, chip); 27393db446aSBoris Brezillon } 27493db446aSBoris Brezillon 27593db446aSBoris Brezillon static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip 27693db446aSBoris Brezillon *nand) 27793db446aSBoris Brezillon { 27893db446aSBoris Brezillon return &nand->sels[nand->selected_die]; 27993db446aSBoris Brezillon } 28093db446aSBoris Brezillon 28193db446aSBoris Brezillon /** 28293db446aSBoris Brezillon * NAND controller capabilities for distinction between compatible strings 28393db446aSBoris Brezillon * 28493db446aSBoris Brezillon * @max_cs_nb: Number of Chip Select lines available 28593db446aSBoris Brezillon * @max_rb_nb: Number of Ready/Busy lines available 28693db446aSBoris Brezillon * @need_system_controller: Indicates if the SoC needs to have access to the 28793db446aSBoris Brezillon * system controller (ie. to enable the NAND controller) 28893db446aSBoris Brezillon * @legacy_of_bindings: Indicates if DT parsing must be done using the old 28993db446aSBoris Brezillon * fashion way 29093db446aSBoris Brezillon * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie. 29193db446aSBoris Brezillon * BCH error detection and correction algorithm, 29293db446aSBoris Brezillon * NDCB3 register has been added 29393db446aSBoris Brezillon * @use_dma: Use dma for data transfers 29493db446aSBoris Brezillon */ 29593db446aSBoris Brezillon struct marvell_nfc_caps { 29693db446aSBoris Brezillon unsigned int max_cs_nb; 29793db446aSBoris Brezillon unsigned int max_rb_nb; 29893db446aSBoris Brezillon bool need_system_controller; 29993db446aSBoris Brezillon bool legacy_of_bindings; 30093db446aSBoris Brezillon bool is_nfcv2; 30193db446aSBoris Brezillon bool use_dma; 30293db446aSBoris Brezillon }; 30393db446aSBoris Brezillon 30493db446aSBoris Brezillon /** 30593db446aSBoris Brezillon * NAND controller structure: stores Marvell NAND controller information 30693db446aSBoris Brezillon * 30793db446aSBoris Brezillon * @controller: Base controller structure 30893db446aSBoris Brezillon * @dev: Parent device (used to print error messages) 30993db446aSBoris Brezillon * @regs: NAND controller registers 3106b6de654SBoris Brezillon * @core_clk: Core clock 311961ba15cSGregory CLEMENT * @reg_clk: Regiters clock 31293db446aSBoris Brezillon * @complete: Completion object to wait for NAND controller events 31393db446aSBoris Brezillon * @assigned_cs: Bitmask describing already assigned CS lines 31493db446aSBoris Brezillon * @chips: List containing all the NAND chips attached to 31593db446aSBoris Brezillon * this NAND controller 31693db446aSBoris Brezillon * @caps: NAND controller capabilities for each compatible string 31793db446aSBoris Brezillon * @dma_chan: DMA channel (NFCv1 only) 31893db446aSBoris Brezillon * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only) 31993db446aSBoris Brezillon */ 32093db446aSBoris Brezillon struct marvell_nfc { 32193db446aSBoris Brezillon struct nand_hw_control controller; 32293db446aSBoris Brezillon struct device *dev; 32393db446aSBoris Brezillon void __iomem *regs; 3246b6de654SBoris Brezillon struct clk *core_clk; 325961ba15cSGregory CLEMENT struct clk *reg_clk; 32693db446aSBoris Brezillon struct completion complete; 32793db446aSBoris Brezillon unsigned long assigned_cs; 32893db446aSBoris Brezillon struct list_head chips; 32993db446aSBoris Brezillon struct nand_chip *selected_chip; 33093db446aSBoris Brezillon const struct marvell_nfc_caps *caps; 33193db446aSBoris Brezillon 33293db446aSBoris Brezillon /* DMA (NFCv1 only) */ 33393db446aSBoris Brezillon bool use_dma; 33493db446aSBoris Brezillon struct dma_chan *dma_chan; 33593db446aSBoris Brezillon u8 *dma_buf; 33693db446aSBoris Brezillon }; 33793db446aSBoris Brezillon 33893db446aSBoris Brezillon static inline struct marvell_nfc *to_marvell_nfc(struct nand_hw_control *ctrl) 33993db446aSBoris Brezillon { 34093db446aSBoris Brezillon return container_of(ctrl, struct marvell_nfc, controller); 34193db446aSBoris Brezillon } 34293db446aSBoris Brezillon 34393db446aSBoris Brezillon /** 34493db446aSBoris Brezillon * NAND controller timings expressed in NAND Controller clock cycles 34593db446aSBoris Brezillon * 34693db446aSBoris Brezillon * @tRP: ND_nRE pulse width 34793db446aSBoris Brezillon * @tRH: ND_nRE high duration 34893db446aSBoris Brezillon * @tWP: ND_nWE pulse time 34993db446aSBoris Brezillon * @tWH: ND_nWE high duration 35093db446aSBoris Brezillon * @tCS: Enable signal setup time 35193db446aSBoris Brezillon * @tCH: Enable signal hold time 35293db446aSBoris Brezillon * @tADL: Address to write data delay 35393db446aSBoris Brezillon * @tAR: ND_ALE low to ND_nRE low delay 35493db446aSBoris Brezillon * @tWHR: ND_nWE high to ND_nRE low for status read 35593db446aSBoris Brezillon * @tRHW: ND_nRE high duration, read to write delay 35693db446aSBoris Brezillon * @tR: ND_nWE high to ND_nRE low for read 35793db446aSBoris Brezillon */ 35893db446aSBoris Brezillon struct marvell_nfc_timings { 35993db446aSBoris Brezillon /* NDTR0 fields */ 36093db446aSBoris Brezillon unsigned int tRP; 36193db446aSBoris Brezillon unsigned int tRH; 36293db446aSBoris Brezillon unsigned int tWP; 36393db446aSBoris Brezillon unsigned int tWH; 36493db446aSBoris Brezillon unsigned int tCS; 36593db446aSBoris Brezillon unsigned int tCH; 36693db446aSBoris Brezillon unsigned int tADL; 36793db446aSBoris Brezillon /* NDTR1 fields */ 36893db446aSBoris Brezillon unsigned int tAR; 36993db446aSBoris Brezillon unsigned int tWHR; 37093db446aSBoris Brezillon unsigned int tRHW; 37193db446aSBoris Brezillon unsigned int tR; 37293db446aSBoris Brezillon }; 37393db446aSBoris Brezillon 37493db446aSBoris Brezillon /** 37593db446aSBoris Brezillon * Derives a duration in numbers of clock cycles. 37693db446aSBoris Brezillon * 37793db446aSBoris Brezillon * @ps: Duration in pico-seconds 37893db446aSBoris Brezillon * @period_ns: Clock period in nano-seconds 37993db446aSBoris Brezillon * 38093db446aSBoris Brezillon * Convert the duration in nano-seconds, then divide by the period and 38193db446aSBoris Brezillon * return the number of clock periods. 38293db446aSBoris Brezillon */ 38393db446aSBoris Brezillon #define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns)) 38493db446aSBoris Brezillon #define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \ 38593db446aSBoris Brezillon period_ns)) 38693db446aSBoris Brezillon 38793db446aSBoris Brezillon /** 38893db446aSBoris Brezillon * NAND driver structure filled during the parsing of the ->exec_op() subop 38993db446aSBoris Brezillon * subset of instructions. 39093db446aSBoris Brezillon * 39193db446aSBoris Brezillon * @ndcb: Array of values written to NDCBx registers 39293db446aSBoris Brezillon * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle 39393db446aSBoris Brezillon * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin 39493db446aSBoris Brezillon * @rdy_delay_ns: Optional delay after waiting for the RB pin 39593db446aSBoris Brezillon * @data_delay_ns: Optional delay after the data xfer 39693db446aSBoris Brezillon * @data_instr_idx: Index of the data instruction in the subop 39793db446aSBoris Brezillon * @data_instr: Pointer to the data instruction in the subop 39893db446aSBoris Brezillon */ 39993db446aSBoris Brezillon struct marvell_nfc_op { 40093db446aSBoris Brezillon u32 ndcb[4]; 40193db446aSBoris Brezillon unsigned int cle_ale_delay_ns; 40293db446aSBoris Brezillon unsigned int rdy_timeout_ms; 40393db446aSBoris Brezillon unsigned int rdy_delay_ns; 40493db446aSBoris Brezillon unsigned int data_delay_ns; 40593db446aSBoris Brezillon unsigned int data_instr_idx; 40693db446aSBoris Brezillon const struct nand_op_instr *data_instr; 40793db446aSBoris Brezillon }; 40893db446aSBoris Brezillon 40993db446aSBoris Brezillon /* 41093db446aSBoris Brezillon * Internal helper to conditionnally apply a delay (from the above structure, 41193db446aSBoris Brezillon * most of the time). 41293db446aSBoris Brezillon */ 41393db446aSBoris Brezillon static void cond_delay(unsigned int ns) 41493db446aSBoris Brezillon { 41593db446aSBoris Brezillon if (!ns) 41693db446aSBoris Brezillon return; 41793db446aSBoris Brezillon 41893db446aSBoris Brezillon if (ns < 10000) 41993db446aSBoris Brezillon ndelay(ns); 42093db446aSBoris Brezillon else 42193db446aSBoris Brezillon udelay(DIV_ROUND_UP(ns, 1000)); 42293db446aSBoris Brezillon } 42393db446aSBoris Brezillon 42493db446aSBoris Brezillon /* 42593db446aSBoris Brezillon * The controller has many flags that could generate interrupts, most of them 42693db446aSBoris Brezillon * are disabled and polling is used. For the very slow signals, using interrupts 42793db446aSBoris Brezillon * may relax the CPU charge. 42893db446aSBoris Brezillon */ 42993db446aSBoris Brezillon static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask) 43093db446aSBoris Brezillon { 43193db446aSBoris Brezillon u32 reg; 43293db446aSBoris Brezillon 43393db446aSBoris Brezillon /* Writing 1 disables the interrupt */ 43493db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 43593db446aSBoris Brezillon writel_relaxed(reg | int_mask, nfc->regs + NDCR); 43693db446aSBoris Brezillon } 43793db446aSBoris Brezillon 43893db446aSBoris Brezillon static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask) 43993db446aSBoris Brezillon { 44093db446aSBoris Brezillon u32 reg; 44193db446aSBoris Brezillon 44293db446aSBoris Brezillon /* Writing 0 enables the interrupt */ 44393db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 44493db446aSBoris Brezillon writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); 44593db446aSBoris Brezillon } 44693db446aSBoris Brezillon 44793db446aSBoris Brezillon static void marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask) 44893db446aSBoris Brezillon { 44993db446aSBoris Brezillon writel_relaxed(int_mask, nfc->regs + NDSR); 45093db446aSBoris Brezillon } 45193db446aSBoris Brezillon 45293db446aSBoris Brezillon static void marvell_nfc_force_byte_access(struct nand_chip *chip, 45393db446aSBoris Brezillon bool force_8bit) 45493db446aSBoris Brezillon { 45593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 45693db446aSBoris Brezillon u32 ndcr; 45793db446aSBoris Brezillon 45893db446aSBoris Brezillon /* 45993db446aSBoris Brezillon * Callers of this function do not verify if the NAND is using a 16-bit 46093db446aSBoris Brezillon * an 8-bit bus for normal operations, so we need to take care of that 46193db446aSBoris Brezillon * here by leaving the configuration unchanged if the NAND does not have 46293db446aSBoris Brezillon * the NAND_BUSWIDTH_16 flag set. 46393db446aSBoris Brezillon */ 46493db446aSBoris Brezillon if (!(chip->options & NAND_BUSWIDTH_16)) 46593db446aSBoris Brezillon return; 46693db446aSBoris Brezillon 46793db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR); 46893db446aSBoris Brezillon 46993db446aSBoris Brezillon if (force_8bit) 47093db446aSBoris Brezillon ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C); 47193db446aSBoris Brezillon else 47293db446aSBoris Brezillon ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 47393db446aSBoris Brezillon 47493db446aSBoris Brezillon writel_relaxed(ndcr, nfc->regs + NDCR); 47593db446aSBoris Brezillon } 47693db446aSBoris Brezillon 47793db446aSBoris Brezillon static int marvell_nfc_wait_ndrun(struct nand_chip *chip) 47893db446aSBoris Brezillon { 47993db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 48093db446aSBoris Brezillon u32 val; 48193db446aSBoris Brezillon int ret; 48293db446aSBoris Brezillon 48393db446aSBoris Brezillon /* 48493db446aSBoris Brezillon * The command is being processed, wait for the ND_RUN bit to be 48593db446aSBoris Brezillon * cleared by the NFC. If not, we must clear it by hand. 48693db446aSBoris Brezillon */ 48793db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, 48893db446aSBoris Brezillon (val & NDCR_ND_RUN) == 0, 48993db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 49093db446aSBoris Brezillon if (ret) { 49193db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on NAND controller run mode\n"); 49293db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 49393db446aSBoris Brezillon nfc->regs + NDCR); 49493db446aSBoris Brezillon return ret; 49593db446aSBoris Brezillon } 49693db446aSBoris Brezillon 49793db446aSBoris Brezillon return 0; 49893db446aSBoris Brezillon } 49993db446aSBoris Brezillon 50093db446aSBoris Brezillon /* 50193db446aSBoris Brezillon * Any time a command has to be sent to the controller, the following sequence 50293db446aSBoris Brezillon * has to be followed: 50393db446aSBoris Brezillon * - call marvell_nfc_prepare_cmd() 50493db446aSBoris Brezillon * -> activate the ND_RUN bit that will kind of 'start a job' 50593db446aSBoris Brezillon * -> wait the signal indicating the NFC is waiting for a command 50693db446aSBoris Brezillon * - send the command (cmd and address cycles) 50793db446aSBoris Brezillon * - enventually send or receive the data 50893db446aSBoris Brezillon * - call marvell_nfc_end_cmd() with the corresponding flag 50993db446aSBoris Brezillon * -> wait the flag to be triggered or cancel the job with a timeout 51093db446aSBoris Brezillon * 51193db446aSBoris Brezillon * The following helpers are here to factorize the code a bit so that 51293db446aSBoris Brezillon * specialized functions responsible for executing the actual NAND 51393db446aSBoris Brezillon * operations do not have to replicate the same code blocks. 51493db446aSBoris Brezillon */ 51593db446aSBoris Brezillon static int marvell_nfc_prepare_cmd(struct nand_chip *chip) 51693db446aSBoris Brezillon { 51793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 51893db446aSBoris Brezillon u32 ndcr, val; 51993db446aSBoris Brezillon int ret; 52093db446aSBoris Brezillon 52193db446aSBoris Brezillon /* Poll ND_RUN and clear NDSR before issuing any command */ 52293db446aSBoris Brezillon ret = marvell_nfc_wait_ndrun(chip); 52393db446aSBoris Brezillon if (ret) { 52493db446aSBoris Brezillon dev_err(nfc->dev, "Last operation did not succeed\n"); 52593db446aSBoris Brezillon return ret; 52693db446aSBoris Brezillon } 52793db446aSBoris Brezillon 52893db446aSBoris Brezillon ndcr = readl_relaxed(nfc->regs + NDCR); 52993db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR); 53093db446aSBoris Brezillon 53193db446aSBoris Brezillon /* Assert ND_RUN bit and wait the NFC to be ready */ 53293db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR); 53393db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 53493db446aSBoris Brezillon val & NDSR_WRCMDREQ, 53593db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 53693db446aSBoris Brezillon if (ret) { 53793db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on WRCMDRE\n"); 53893db446aSBoris Brezillon return -ETIMEDOUT; 53993db446aSBoris Brezillon } 54093db446aSBoris Brezillon 54193db446aSBoris Brezillon /* Command may be written, clear WRCMDREQ status bit */ 54293db446aSBoris Brezillon writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR); 54393db446aSBoris Brezillon 54493db446aSBoris Brezillon return 0; 54593db446aSBoris Brezillon } 54693db446aSBoris Brezillon 54793db446aSBoris Brezillon static void marvell_nfc_send_cmd(struct nand_chip *chip, 54893db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 54993db446aSBoris Brezillon { 55093db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 55193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 55293db446aSBoris Brezillon 55393db446aSBoris Brezillon dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n" 55493db446aSBoris Brezillon "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n", 55593db446aSBoris Brezillon (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0], 55693db446aSBoris Brezillon nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]); 55793db446aSBoris Brezillon 55893db446aSBoris Brezillon writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0], 55993db446aSBoris Brezillon nfc->regs + NDCB0); 56093db446aSBoris Brezillon writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0); 56193db446aSBoris Brezillon writel(nfc_op->ndcb[2], nfc->regs + NDCB0); 56293db446aSBoris Brezillon 56393db446aSBoris Brezillon /* 56493db446aSBoris Brezillon * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7 56593db446aSBoris Brezillon * fields are used (only available on NFCv2). 56693db446aSBoris Brezillon */ 56793db446aSBoris Brezillon if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD || 56893db446aSBoris Brezillon NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) { 56993db446aSBoris Brezillon if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2)) 57093db446aSBoris Brezillon writel(nfc_op->ndcb[3], nfc->regs + NDCB0); 57193db446aSBoris Brezillon } 57293db446aSBoris Brezillon } 57393db446aSBoris Brezillon 57493db446aSBoris Brezillon static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag, 57593db446aSBoris Brezillon const char *label) 57693db446aSBoris Brezillon { 57793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 57893db446aSBoris Brezillon u32 val; 57993db446aSBoris Brezillon int ret; 58093db446aSBoris Brezillon 58193db446aSBoris Brezillon ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, 58293db446aSBoris Brezillon val & flag, 58393db446aSBoris Brezillon POLL_PERIOD, POLL_TIMEOUT); 58493db446aSBoris Brezillon 58593db446aSBoris Brezillon if (ret) { 58693db446aSBoris Brezillon dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n", 58793db446aSBoris Brezillon label, val); 58893db446aSBoris Brezillon if (nfc->dma_chan) 58993db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 59093db446aSBoris Brezillon return ret; 59193db446aSBoris Brezillon } 59293db446aSBoris Brezillon 59393db446aSBoris Brezillon /* 59493db446aSBoris Brezillon * DMA function uses this helper to poll on CMDD bits without wanting 59593db446aSBoris Brezillon * them to be cleared. 59693db446aSBoris Brezillon */ 59793db446aSBoris Brezillon if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN)) 59893db446aSBoris Brezillon return 0; 59993db446aSBoris Brezillon 60093db446aSBoris Brezillon writel_relaxed(flag, nfc->regs + NDSR); 60193db446aSBoris Brezillon 60293db446aSBoris Brezillon return 0; 60393db446aSBoris Brezillon } 60493db446aSBoris Brezillon 60593db446aSBoris Brezillon static int marvell_nfc_wait_cmdd(struct nand_chip *chip) 60693db446aSBoris Brezillon { 60793db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 60893db446aSBoris Brezillon int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel); 60993db446aSBoris Brezillon 61093db446aSBoris Brezillon return marvell_nfc_end_cmd(chip, cs_flag, "CMDD"); 61193db446aSBoris Brezillon } 61293db446aSBoris Brezillon 61393db446aSBoris Brezillon static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms) 61493db446aSBoris Brezillon { 61593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 61693db446aSBoris Brezillon int ret; 61793db446aSBoris Brezillon 61893db446aSBoris Brezillon /* Timeout is expressed in ms */ 61993db446aSBoris Brezillon if (!timeout_ms) 62093db446aSBoris Brezillon timeout_ms = IRQ_TIMEOUT; 62193db446aSBoris Brezillon 62293db446aSBoris Brezillon init_completion(&nfc->complete); 62393db446aSBoris Brezillon 62493db446aSBoris Brezillon marvell_nfc_enable_int(nfc, NDCR_RDYM); 62593db446aSBoris Brezillon ret = wait_for_completion_timeout(&nfc->complete, 62693db446aSBoris Brezillon msecs_to_jiffies(timeout_ms)); 62793db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_RDYM); 62893db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1)); 62993db446aSBoris Brezillon if (!ret) { 63093db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for RB signal\n"); 63193db446aSBoris Brezillon return -ETIMEDOUT; 63293db446aSBoris Brezillon } 63393db446aSBoris Brezillon 63493db446aSBoris Brezillon return 0; 63593db446aSBoris Brezillon } 63693db446aSBoris Brezillon 63793db446aSBoris Brezillon static void marvell_nfc_select_chip(struct mtd_info *mtd, int die_nr) 63893db446aSBoris Brezillon { 63993db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 64093db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 64193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 64293db446aSBoris Brezillon u32 ndcr_generic; 64393db446aSBoris Brezillon 64493db446aSBoris Brezillon if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die) 64593db446aSBoris Brezillon return; 64693db446aSBoris Brezillon 64793db446aSBoris Brezillon if (die_nr < 0 || die_nr >= marvell_nand->nsels) { 64893db446aSBoris Brezillon nfc->selected_chip = NULL; 64993db446aSBoris Brezillon marvell_nand->selected_die = -1; 65093db446aSBoris Brezillon return; 65193db446aSBoris Brezillon } 65293db446aSBoris Brezillon 65393db446aSBoris Brezillon /* 65493db446aSBoris Brezillon * Do not change the timing registers when using the DT property 65593db446aSBoris Brezillon * marvell,nand-keep-config; in that case ->ndtr0 and ->ndtr1 from the 65693db446aSBoris Brezillon * marvell_nand structure are supposedly empty. 65793db446aSBoris Brezillon */ 65893db446aSBoris Brezillon writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0); 65993db446aSBoris Brezillon writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); 66093db446aSBoris Brezillon 66193db446aSBoris Brezillon /* 66293db446aSBoris Brezillon * Reset the NDCR register to a clean state for this particular chip, 66393db446aSBoris Brezillon * also clear ND_RUN bit. 66493db446aSBoris Brezillon */ 66593db446aSBoris Brezillon ndcr_generic = readl_relaxed(nfc->regs + NDCR) & 66693db446aSBoris Brezillon NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN; 66793db446aSBoris Brezillon writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR); 66893db446aSBoris Brezillon 66993db446aSBoris Brezillon /* Also reset the interrupt status register */ 67093db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 67193db446aSBoris Brezillon 67293db446aSBoris Brezillon nfc->selected_chip = chip; 67393db446aSBoris Brezillon marvell_nand->selected_die = die_nr; 67493db446aSBoris Brezillon } 67593db446aSBoris Brezillon 67693db446aSBoris Brezillon static irqreturn_t marvell_nfc_isr(int irq, void *dev_id) 67793db446aSBoris Brezillon { 67893db446aSBoris Brezillon struct marvell_nfc *nfc = dev_id; 67993db446aSBoris Brezillon u32 st = readl_relaxed(nfc->regs + NDSR); 68093db446aSBoris Brezillon u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT; 68193db446aSBoris Brezillon 68293db446aSBoris Brezillon /* 68393db446aSBoris Brezillon * RDY interrupt mask is one bit in NDCR while there are two status 68493db446aSBoris Brezillon * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]). 68593db446aSBoris Brezillon */ 68693db446aSBoris Brezillon if (st & NDSR_RDY(1)) 68793db446aSBoris Brezillon st |= NDSR_RDY(0); 68893db446aSBoris Brezillon 68993db446aSBoris Brezillon if (!(st & ien)) 69093db446aSBoris Brezillon return IRQ_NONE; 69193db446aSBoris Brezillon 69293db446aSBoris Brezillon marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT); 69393db446aSBoris Brezillon 69493db446aSBoris Brezillon if (!(st & (NDSR_RDDREQ | NDSR_WRDREQ | NDSR_WRCMDREQ))) 69593db446aSBoris Brezillon complete(&nfc->complete); 69693db446aSBoris Brezillon 69793db446aSBoris Brezillon return IRQ_HANDLED; 69893db446aSBoris Brezillon } 69993db446aSBoris Brezillon 70093db446aSBoris Brezillon /* HW ECC related functions */ 70193db446aSBoris Brezillon static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip) 70293db446aSBoris Brezillon { 70393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 70493db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR); 70593db446aSBoris Brezillon 70693db446aSBoris Brezillon if (!(ndcr & NDCR_ECC_EN)) { 70793db446aSBoris Brezillon writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR); 70893db446aSBoris Brezillon 70993db446aSBoris Brezillon /* 71093db446aSBoris Brezillon * When enabling BCH, set threshold to 0 to always know the 71193db446aSBoris Brezillon * number of corrected bitflips. 71293db446aSBoris Brezillon */ 71393db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_BCH) 71493db446aSBoris Brezillon writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); 71593db446aSBoris Brezillon } 71693db446aSBoris Brezillon } 71793db446aSBoris Brezillon 71893db446aSBoris Brezillon static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip) 71993db446aSBoris Brezillon { 72093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 72193db446aSBoris Brezillon u32 ndcr = readl_relaxed(nfc->regs + NDCR); 72293db446aSBoris Brezillon 72393db446aSBoris Brezillon if (ndcr & NDCR_ECC_EN) { 72493db446aSBoris Brezillon writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); 72593db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_BCH) 72693db446aSBoris Brezillon writel_relaxed(0, nfc->regs + NDECCCTRL); 72793db446aSBoris Brezillon } 72893db446aSBoris Brezillon } 72993db446aSBoris Brezillon 73093db446aSBoris Brezillon /* DMA related helpers */ 73193db446aSBoris Brezillon static void marvell_nfc_enable_dma(struct marvell_nfc *nfc) 73293db446aSBoris Brezillon { 73393db446aSBoris Brezillon u32 reg; 73493db446aSBoris Brezillon 73593db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 73693db446aSBoris Brezillon writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); 73793db446aSBoris Brezillon } 73893db446aSBoris Brezillon 73993db446aSBoris Brezillon static void marvell_nfc_disable_dma(struct marvell_nfc *nfc) 74093db446aSBoris Brezillon { 74193db446aSBoris Brezillon u32 reg; 74293db446aSBoris Brezillon 74393db446aSBoris Brezillon reg = readl_relaxed(nfc->regs + NDCR); 74493db446aSBoris Brezillon writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); 74593db446aSBoris Brezillon } 74693db446aSBoris Brezillon 74793db446aSBoris Brezillon /* Read/write PIO/DMA accessors */ 74893db446aSBoris Brezillon static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc, 74993db446aSBoris Brezillon enum dma_data_direction direction, 75093db446aSBoris Brezillon unsigned int len) 75193db446aSBoris Brezillon { 75293db446aSBoris Brezillon unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE); 75393db446aSBoris Brezillon struct dma_async_tx_descriptor *tx; 75493db446aSBoris Brezillon struct scatterlist sg; 75593db446aSBoris Brezillon dma_cookie_t cookie; 75693db446aSBoris Brezillon int ret; 75793db446aSBoris Brezillon 75893db446aSBoris Brezillon marvell_nfc_enable_dma(nfc); 75993db446aSBoris Brezillon /* Prepare the DMA transfer */ 76093db446aSBoris Brezillon sg_init_one(&sg, nfc->dma_buf, dma_len); 76193db446aSBoris Brezillon dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 76293db446aSBoris Brezillon tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1, 76393db446aSBoris Brezillon direction == DMA_FROM_DEVICE ? 76493db446aSBoris Brezillon DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 76593db446aSBoris Brezillon DMA_PREP_INTERRUPT); 76693db446aSBoris Brezillon if (!tx) { 76793db446aSBoris Brezillon dev_err(nfc->dev, "Could not prepare DMA S/G list\n"); 76893db446aSBoris Brezillon return -ENXIO; 76993db446aSBoris Brezillon } 77093db446aSBoris Brezillon 77193db446aSBoris Brezillon /* Do the task and wait for it to finish */ 77293db446aSBoris Brezillon cookie = dmaengine_submit(tx); 77393db446aSBoris Brezillon ret = dma_submit_error(cookie); 77493db446aSBoris Brezillon if (ret) 77593db446aSBoris Brezillon return -EIO; 77693db446aSBoris Brezillon 77793db446aSBoris Brezillon dma_async_issue_pending(nfc->dma_chan); 77893db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(nfc->selected_chip); 77993db446aSBoris Brezillon dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); 78093db446aSBoris Brezillon marvell_nfc_disable_dma(nfc); 78193db446aSBoris Brezillon if (ret) { 78293db446aSBoris Brezillon dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n", 78393db446aSBoris Brezillon dmaengine_tx_status(nfc->dma_chan, cookie, NULL)); 78493db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 78593db446aSBoris Brezillon return -ETIMEDOUT; 78693db446aSBoris Brezillon } 78793db446aSBoris Brezillon 78893db446aSBoris Brezillon return 0; 78993db446aSBoris Brezillon } 79093db446aSBoris Brezillon 79193db446aSBoris Brezillon static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in, 79293db446aSBoris Brezillon unsigned int len) 79393db446aSBoris Brezillon { 79493db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH; 79593db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 79693db446aSBoris Brezillon int i; 79793db446aSBoris Brezillon 79893db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 79993db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH)); 80093db446aSBoris Brezillon 80193db446aSBoris Brezillon if (last_len) { 80293db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH]; 80393db446aSBoris Brezillon 80493db446aSBoris Brezillon ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 80593db446aSBoris Brezillon memcpy(in + last_full_offset, tmp_buf, last_len); 80693db446aSBoris Brezillon } 80793db446aSBoris Brezillon 80893db446aSBoris Brezillon return 0; 80993db446aSBoris Brezillon } 81093db446aSBoris Brezillon 81193db446aSBoris Brezillon static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out, 81293db446aSBoris Brezillon unsigned int len) 81393db446aSBoris Brezillon { 81493db446aSBoris Brezillon unsigned int last_len = len % FIFO_DEPTH; 81593db446aSBoris Brezillon unsigned int last_full_offset = round_down(len, FIFO_DEPTH); 81693db446aSBoris Brezillon int i; 81793db446aSBoris Brezillon 81893db446aSBoris Brezillon for (i = 0; i < last_full_offset; i += FIFO_DEPTH) 81993db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH)); 82093db446aSBoris Brezillon 82193db446aSBoris Brezillon if (last_len) { 82293db446aSBoris Brezillon u8 tmp_buf[FIFO_DEPTH]; 82393db446aSBoris Brezillon 82493db446aSBoris Brezillon memcpy(tmp_buf, out + last_full_offset, last_len); 82593db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); 82693db446aSBoris Brezillon } 82793db446aSBoris Brezillon 82893db446aSBoris Brezillon return 0; 82993db446aSBoris Brezillon } 83093db446aSBoris Brezillon 83193db446aSBoris Brezillon static void marvell_nfc_check_empty_chunk(struct nand_chip *chip, 83293db446aSBoris Brezillon u8 *data, int data_len, 83393db446aSBoris Brezillon u8 *spare, int spare_len, 83493db446aSBoris Brezillon u8 *ecc, int ecc_len, 83593db446aSBoris Brezillon unsigned int *max_bitflips) 83693db446aSBoris Brezillon { 83793db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 83893db446aSBoris Brezillon int bf; 83993db446aSBoris Brezillon 84093db446aSBoris Brezillon /* 84193db446aSBoris Brezillon * Blank pages (all 0xFF) that have not been written may be recognized 84293db446aSBoris Brezillon * as bad if bitflips occur, so whenever an uncorrectable error occurs, 84393db446aSBoris Brezillon * check if the entire page (with ECC bytes) is actually blank or not. 84493db446aSBoris Brezillon */ 84593db446aSBoris Brezillon if (!data) 84693db446aSBoris Brezillon data_len = 0; 84793db446aSBoris Brezillon if (!spare) 84893db446aSBoris Brezillon spare_len = 0; 84993db446aSBoris Brezillon if (!ecc) 85093db446aSBoris Brezillon ecc_len = 0; 85193db446aSBoris Brezillon 85293db446aSBoris Brezillon bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len, 85393db446aSBoris Brezillon spare, spare_len, chip->ecc.strength); 85493db446aSBoris Brezillon if (bf < 0) { 85593db446aSBoris Brezillon mtd->ecc_stats.failed++; 85693db446aSBoris Brezillon return; 85793db446aSBoris Brezillon } 85893db446aSBoris Brezillon 85993db446aSBoris Brezillon /* Update the stats and max_bitflips */ 86093db446aSBoris Brezillon mtd->ecc_stats.corrected += bf; 86193db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 86293db446aSBoris Brezillon } 86393db446aSBoris Brezillon 86493db446aSBoris Brezillon /* 86593db446aSBoris Brezillon * Check a chunk is correct or not according to hardware ECC engine. 86693db446aSBoris Brezillon * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however 86793db446aSBoris Brezillon * mtd->ecc_stats.failure is not, the function will instead return a non-zero 86893db446aSBoris Brezillon * value indicating that a check on the emptyness of the subpage must be 86993db446aSBoris Brezillon * performed before declaring the subpage corrupted. 87093db446aSBoris Brezillon */ 87193db446aSBoris Brezillon static int marvell_nfc_hw_ecc_correct(struct nand_chip *chip, 87293db446aSBoris Brezillon unsigned int *max_bitflips) 87393db446aSBoris Brezillon { 87493db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip); 87593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 87693db446aSBoris Brezillon int bf = 0; 87793db446aSBoris Brezillon u32 ndsr; 87893db446aSBoris Brezillon 87993db446aSBoris Brezillon ndsr = readl_relaxed(nfc->regs + NDSR); 88093db446aSBoris Brezillon 88193db446aSBoris Brezillon /* Check uncorrectable error flag */ 88293db446aSBoris Brezillon if (ndsr & NDSR_UNCERR) { 88393db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR); 88493db446aSBoris Brezillon 88593db446aSBoris Brezillon /* 88693db446aSBoris Brezillon * Do not increment ->ecc_stats.failed now, instead, return a 88793db446aSBoris Brezillon * non-zero value to indicate that this chunk was apparently 88893db446aSBoris Brezillon * bad, and it should be check to see if it empty or not. If 88993db446aSBoris Brezillon * the chunk (with ECC bytes) is not declared empty, the calling 89093db446aSBoris Brezillon * function must increment the failure count. 89193db446aSBoris Brezillon */ 89293db446aSBoris Brezillon return -EBADMSG; 89393db446aSBoris Brezillon } 89493db446aSBoris Brezillon 89593db446aSBoris Brezillon /* Check correctable error flag */ 89693db446aSBoris Brezillon if (ndsr & NDSR_CORERR) { 89793db446aSBoris Brezillon writel_relaxed(ndsr, nfc->regs + NDSR); 89893db446aSBoris Brezillon 89993db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_BCH) 90093db446aSBoris Brezillon bf = NDSR_ERRCNT(ndsr); 90193db446aSBoris Brezillon else 90293db446aSBoris Brezillon bf = 1; 90393db446aSBoris Brezillon } 90493db446aSBoris Brezillon 90593db446aSBoris Brezillon /* Update the stats and max_bitflips */ 90693db446aSBoris Brezillon mtd->ecc_stats.corrected += bf; 90793db446aSBoris Brezillon *max_bitflips = max_t(unsigned int, *max_bitflips, bf); 90893db446aSBoris Brezillon 90993db446aSBoris Brezillon return 0; 91093db446aSBoris Brezillon } 91193db446aSBoris Brezillon 91293db446aSBoris Brezillon /* Hamming read helpers */ 91393db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip, 91493db446aSBoris Brezillon u8 *data_buf, u8 *oob_buf, 91593db446aSBoris Brezillon bool raw, int page) 91693db446aSBoris Brezillon { 91793db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 91893db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 91993db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 92093db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 92193db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 92293db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 92393db446aSBoris Brezillon NDCB0_DBC | 92493db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) | 92593db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART), 92693db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 92793db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 92893db446aSBoris Brezillon }; 92993db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 93093db446aSBoris Brezillon int ret; 93193db446aSBoris Brezillon 93293db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */ 93393db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 93493db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 93593db446aSBoris Brezillon 93693db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 93793db446aSBoris Brezillon if (ret) 93893db446aSBoris Brezillon return ret; 93993db446aSBoris Brezillon 94093db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 94193db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 94293db446aSBoris Brezillon "RDDREQ while draining FIFO (data/oob)"); 94393db446aSBoris Brezillon if (ret) 94493db446aSBoris Brezillon return ret; 94593db446aSBoris Brezillon 94693db446aSBoris Brezillon /* 94793db446aSBoris Brezillon * Read the page then the OOB area. Unlike what is shown in current 94893db446aSBoris Brezillon * documentation, spare bytes are protected by the ECC engine, and must 94993db446aSBoris Brezillon * be at the beginning of the OOB area or running this driver on legacy 95093db446aSBoris Brezillon * systems will prevent the discovery of the BBM/BBT. 95193db446aSBoris Brezillon */ 95293db446aSBoris Brezillon if (nfc->use_dma) { 95393db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE, 95493db446aSBoris Brezillon lt->data_bytes + oob_bytes); 95593db446aSBoris Brezillon memcpy(data_buf, nfc->dma_buf, lt->data_bytes); 95693db446aSBoris Brezillon memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); 95793db446aSBoris Brezillon } else { 95893db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); 95993db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes); 96093db446aSBoris Brezillon } 96193db446aSBoris Brezillon 96293db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 96393db446aSBoris Brezillon 96493db446aSBoris Brezillon return ret; 96593db446aSBoris Brezillon } 96693db446aSBoris Brezillon 96793db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct mtd_info *mtd, 96893db446aSBoris Brezillon struct nand_chip *chip, u8 *buf, 96993db446aSBoris Brezillon int oob_required, int page) 97093db446aSBoris Brezillon { 97193db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, 97293db446aSBoris Brezillon true, page); 97393db446aSBoris Brezillon } 97493db446aSBoris Brezillon 97593db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_page(struct mtd_info *mtd, 97693db446aSBoris Brezillon struct nand_chip *chip, 97793db446aSBoris Brezillon u8 *buf, int oob_required, 97893db446aSBoris Brezillon int page) 97993db446aSBoris Brezillon { 98093db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 98193db446aSBoris Brezillon unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 98293db446aSBoris Brezillon int max_bitflips = 0, ret; 98393db446aSBoris Brezillon u8 *raw_buf; 98493db446aSBoris Brezillon 98593db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 98693db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false, 98793db446aSBoris Brezillon page); 98893db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips); 98993db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 99093db446aSBoris Brezillon 99193db446aSBoris Brezillon if (!ret) 99293db446aSBoris Brezillon return max_bitflips; 99393db446aSBoris Brezillon 99493db446aSBoris Brezillon /* 99593db446aSBoris Brezillon * When ECC failures are detected, check if the full page has been 99693db446aSBoris Brezillon * written or not. Ignore the failure if it is actually empty. 99793db446aSBoris Brezillon */ 99893db446aSBoris Brezillon raw_buf = kmalloc(full_sz, GFP_KERNEL); 99993db446aSBoris Brezillon if (!raw_buf) 100093db446aSBoris Brezillon return -ENOMEM; 100193db446aSBoris Brezillon 100293db446aSBoris Brezillon marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf + 100393db446aSBoris Brezillon lt->data_bytes, true, page); 100493db446aSBoris Brezillon marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0, 100593db446aSBoris Brezillon &max_bitflips); 100693db446aSBoris Brezillon kfree(raw_buf); 100793db446aSBoris Brezillon 100893db446aSBoris Brezillon return max_bitflips; 100993db446aSBoris Brezillon } 101093db446aSBoris Brezillon 101193db446aSBoris Brezillon /* 101293db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if 101393db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->read_oob_raw() function 101493db446aSBoris Brezillon * also stands for ->read_oob(). 101593db446aSBoris Brezillon */ 101693db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct mtd_info *mtd, 101793db446aSBoris Brezillon struct nand_chip *chip, int page) 101893db446aSBoris Brezillon { 101993db446aSBoris Brezillon /* Invalidate page cache */ 102093db446aSBoris Brezillon chip->pagebuf = -1; 102193db446aSBoris Brezillon 102293db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_read_page(chip, chip->data_buf, 102393db446aSBoris Brezillon chip->oob_poi, true, page); 102493db446aSBoris Brezillon } 102593db446aSBoris Brezillon 102693db446aSBoris Brezillon /* Hamming write helpers */ 102793db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip, 102893db446aSBoris Brezillon const u8 *data_buf, 102993db446aSBoris Brezillon const u8 *oob_buf, bool raw, 103093db446aSBoris Brezillon int page) 103193db446aSBoris Brezillon { 103293db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 103393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 103493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 103593db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 103693db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | 103793db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 103893db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN) | 103993db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_PAGEPROG) | 104093db446aSBoris Brezillon NDCB0_DBC, 104193db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 104293db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 104393db446aSBoris Brezillon }; 104493db446aSBoris Brezillon unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); 104593db446aSBoris Brezillon int ret; 104693db446aSBoris Brezillon 104793db446aSBoris Brezillon /* NFCv2 needs more information about the operation being executed */ 104893db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 104993db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 105093db446aSBoris Brezillon 105193db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 105293db446aSBoris Brezillon if (ret) 105393db446aSBoris Brezillon return ret; 105493db446aSBoris Brezillon 105593db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 105693db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 105793db446aSBoris Brezillon "WRDREQ while loading FIFO (data)"); 105893db446aSBoris Brezillon if (ret) 105993db446aSBoris Brezillon return ret; 106093db446aSBoris Brezillon 106193db446aSBoris Brezillon /* Write the page then the OOB area */ 106293db446aSBoris Brezillon if (nfc->use_dma) { 106393db446aSBoris Brezillon memcpy(nfc->dma_buf, data_buf, lt->data_bytes); 106493db446aSBoris Brezillon memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); 106593db446aSBoris Brezillon marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + 106693db446aSBoris Brezillon lt->ecc_bytes + lt->spare_bytes); 106793db446aSBoris Brezillon } else { 106893db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); 106993db446aSBoris Brezillon marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes); 107093db446aSBoris Brezillon } 107193db446aSBoris Brezillon 107293db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 107393db446aSBoris Brezillon if (ret) 107493db446aSBoris Brezillon return ret; 107593db446aSBoris Brezillon 107693db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, 1077b76401fcSChris Packham PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); 107893db446aSBoris Brezillon return ret; 107993db446aSBoris Brezillon } 108093db446aSBoris Brezillon 108193db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct mtd_info *mtd, 108293db446aSBoris Brezillon struct nand_chip *chip, 108393db446aSBoris Brezillon const u8 *buf, 108493db446aSBoris Brezillon int oob_required, int page) 108593db446aSBoris Brezillon { 108693db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 108793db446aSBoris Brezillon true, page); 108893db446aSBoris Brezillon } 108993db446aSBoris Brezillon 109093db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_page(struct mtd_info *mtd, 109193db446aSBoris Brezillon struct nand_chip *chip, 109293db446aSBoris Brezillon const u8 *buf, 109393db446aSBoris Brezillon int oob_required, int page) 109493db446aSBoris Brezillon { 109593db446aSBoris Brezillon int ret; 109693db446aSBoris Brezillon 109793db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 109893db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, 109993db446aSBoris Brezillon false, page); 110093db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 110193db446aSBoris Brezillon 110293db446aSBoris Brezillon return ret; 110393db446aSBoris Brezillon } 110493db446aSBoris Brezillon 110593db446aSBoris Brezillon /* 110693db446aSBoris Brezillon * Spare area in Hamming layouts is not protected by the ECC engine (even if 110793db446aSBoris Brezillon * it appears before the ECC bytes when reading), the ->write_oob_raw() function 110893db446aSBoris Brezillon * also stands for ->write_oob(). 110993db446aSBoris Brezillon */ 111093db446aSBoris Brezillon static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct mtd_info *mtd, 111193db446aSBoris Brezillon struct nand_chip *chip, 111293db446aSBoris Brezillon int page) 111393db446aSBoris Brezillon { 111493db446aSBoris Brezillon /* Invalidate page cache */ 111593db446aSBoris Brezillon chip->pagebuf = -1; 111693db446aSBoris Brezillon 111793db446aSBoris Brezillon memset(chip->data_buf, 0xFF, mtd->writesize); 111893db446aSBoris Brezillon 111993db446aSBoris Brezillon return marvell_nfc_hw_ecc_hmg_do_write_page(chip, chip->data_buf, 112093db446aSBoris Brezillon chip->oob_poi, true, page); 112193db446aSBoris Brezillon } 112293db446aSBoris Brezillon 112393db446aSBoris Brezillon /* BCH read helpers */ 112493db446aSBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page_raw(struct mtd_info *mtd, 112593db446aSBoris Brezillon struct nand_chip *chip, u8 *buf, 112693db446aSBoris Brezillon int oob_required, int page) 112793db446aSBoris Brezillon { 112893db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 112993db446aSBoris Brezillon u8 *oob = chip->oob_poi; 113093db446aSBoris Brezillon int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 113193db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 113293db446aSBoris Brezillon lt->last_spare_bytes; 113393db446aSBoris Brezillon int data_len = lt->data_bytes; 113493db446aSBoris Brezillon int spare_len = lt->spare_bytes; 113593db446aSBoris Brezillon int ecc_len = lt->ecc_bytes; 113693db446aSBoris Brezillon int chunk; 113793db446aSBoris Brezillon 113893db446aSBoris Brezillon if (oob_required) 113993db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 114093db446aSBoris Brezillon 114193db446aSBoris Brezillon nand_read_page_op(chip, page, 0, NULL, 0); 114293db446aSBoris Brezillon 114393db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 114493db446aSBoris Brezillon /* Update last chunk length */ 114593db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 114693db446aSBoris Brezillon data_len = lt->last_data_bytes; 114793db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 114893db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes; 114993db446aSBoris Brezillon } 115093db446aSBoris Brezillon 115193db446aSBoris Brezillon /* Read data bytes*/ 115293db446aSBoris Brezillon nand_change_read_column_op(chip, chunk * chunk_size, 115393db446aSBoris Brezillon buf + (lt->data_bytes * chunk), 115493db446aSBoris Brezillon data_len, false); 115593db446aSBoris Brezillon 115693db446aSBoris Brezillon /* Read spare bytes */ 115793db446aSBoris Brezillon nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), 115893db446aSBoris Brezillon spare_len, false); 115993db446aSBoris Brezillon 116093db446aSBoris Brezillon /* Read ECC bytes */ 116193db446aSBoris Brezillon nand_read_data_op(chip, oob + ecc_offset + 116293db446aSBoris Brezillon (ALIGN(lt->ecc_bytes, 32) * chunk), 116393db446aSBoris Brezillon ecc_len, false); 116493db446aSBoris Brezillon } 116593db446aSBoris Brezillon 116693db446aSBoris Brezillon return 0; 116793db446aSBoris Brezillon } 116893db446aSBoris Brezillon 116993db446aSBoris Brezillon static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk, 117093db446aSBoris Brezillon u8 *data, unsigned int data_len, 117193db446aSBoris Brezillon u8 *spare, unsigned int spare_len, 117293db446aSBoris Brezillon int page) 117393db446aSBoris Brezillon { 117493db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 117593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 117693db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 117793db446aSBoris Brezillon int i, ret; 117893db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 117993db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) | 118093db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 118193db446aSBoris Brezillon NDCB0_LEN_OVRD, 118293db446aSBoris Brezillon .ndcb[1] = NDCB1_ADDRS_PAGE(page), 118393db446aSBoris Brezillon .ndcb[2] = NDCB2_ADDR5_PAGE(page), 118493db446aSBoris Brezillon .ndcb[3] = data_len + spare_len, 118593db446aSBoris Brezillon }; 118693db446aSBoris Brezillon 118793db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 118893db446aSBoris Brezillon if (ret) 118993db446aSBoris Brezillon return; 119093db446aSBoris Brezillon 119193db446aSBoris Brezillon if (chunk == 0) 119293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_DBC | 119393db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_READ0) | 119493db446aSBoris Brezillon NDCB0_CMD2(NAND_CMD_READSTART); 119593db446aSBoris Brezillon 119693db446aSBoris Brezillon /* 119790d61763SBoris Brezillon * Trigger the monolithic read on the first chunk, then naked read on 119890d61763SBoris Brezillon * intermediate chunks and finally a last naked read on the last chunk. 119993db446aSBoris Brezillon */ 120090d61763SBoris Brezillon if (chunk == 0) 120193db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); 120290d61763SBoris Brezillon else if (chunk < lt->nchunks - 1) 120390d61763SBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 120493db446aSBoris Brezillon else 120593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 120693db446aSBoris Brezillon 120793db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 120893db446aSBoris Brezillon 120993db446aSBoris Brezillon /* 121093db446aSBoris Brezillon * According to the datasheet, when reading from NDDB 121193db446aSBoris Brezillon * with BCH enabled, after each 32 bytes reads, we 121293db446aSBoris Brezillon * have to make sure that the NDSR.RDDREQ bit is set. 121393db446aSBoris Brezillon * 121493db446aSBoris Brezillon * Drain the FIFO, 8 32-bit reads at a time, and skip 121593db446aSBoris Brezillon * the polling on the last read. 121693db446aSBoris Brezillon * 121793db446aSBoris Brezillon * Length is a multiple of 32 bytes, hence it is a multiple of 8 too. 121893db446aSBoris Brezillon */ 121993db446aSBoris Brezillon for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 122093db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 122193db446aSBoris Brezillon "RDDREQ while draining FIFO (data)"); 122293db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, data, 122393db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS); 122493db446aSBoris Brezillon data += FIFO_DEPTH * BCH_SEQ_READS; 122593db446aSBoris Brezillon } 122693db446aSBoris Brezillon 122793db446aSBoris Brezillon for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) { 122893db446aSBoris Brezillon marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 122993db446aSBoris Brezillon "RDDREQ while draining FIFO (OOB)"); 123093db446aSBoris Brezillon marvell_nfc_xfer_data_in_pio(nfc, spare, 123193db446aSBoris Brezillon FIFO_DEPTH * BCH_SEQ_READS); 123293db446aSBoris Brezillon spare += FIFO_DEPTH * BCH_SEQ_READS; 123393db446aSBoris Brezillon } 123493db446aSBoris Brezillon } 123593db446aSBoris Brezillon 123693db446aSBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_page(struct mtd_info *mtd, 123793db446aSBoris Brezillon struct nand_chip *chip, 123893db446aSBoris Brezillon u8 *buf, int oob_required, 123993db446aSBoris Brezillon int page) 124093db446aSBoris Brezillon { 124193db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 124293db446aSBoris Brezillon int data_len = lt->data_bytes, spare_len = lt->spare_bytes, ecc_len; 124393db446aSBoris Brezillon u8 *data = buf, *spare = chip->oob_poi, *ecc; 124493db446aSBoris Brezillon int max_bitflips = 0; 124593db446aSBoris Brezillon u32 failure_mask = 0; 124693db446aSBoris Brezillon int chunk, ecc_offset_in_page, ret; 124793db446aSBoris Brezillon 124893db446aSBoris Brezillon /* 124993db446aSBoris Brezillon * With BCH, OOB is not fully used (and thus not read entirely), not 125093db446aSBoris Brezillon * expected bytes could show up at the end of the OOB buffer if not 125193db446aSBoris Brezillon * explicitly erased. 125293db446aSBoris Brezillon */ 125393db446aSBoris Brezillon if (oob_required) 125493db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 125593db446aSBoris Brezillon 125693db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 125793db446aSBoris Brezillon 125893db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 125993db446aSBoris Brezillon /* Update length for the last chunk */ 126093db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 126193db446aSBoris Brezillon data_len = lt->last_data_bytes; 126293db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 126393db446aSBoris Brezillon } 126493db446aSBoris Brezillon 126593db446aSBoris Brezillon /* Read the chunk and detect number of bitflips */ 126693db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len, 126793db446aSBoris Brezillon spare, spare_len, page); 126893db446aSBoris Brezillon ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips); 126993db446aSBoris Brezillon if (ret) 127093db446aSBoris Brezillon failure_mask |= BIT(chunk); 127193db446aSBoris Brezillon 127293db446aSBoris Brezillon data += data_len; 127393db446aSBoris Brezillon spare += spare_len; 127493db446aSBoris Brezillon } 127593db446aSBoris Brezillon 127693db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 127793db446aSBoris Brezillon 127893db446aSBoris Brezillon if (!failure_mask) 127993db446aSBoris Brezillon return max_bitflips; 128093db446aSBoris Brezillon 128193db446aSBoris Brezillon /* 128293db446aSBoris Brezillon * Please note that dumping the ECC bytes during a normal read with OOB 128393db446aSBoris Brezillon * area would add a significant overhead as ECC bytes are "consumed" by 128493db446aSBoris Brezillon * the controller in normal mode and must be re-read in raw mode. To 128593db446aSBoris Brezillon * avoid dropping the performances, we prefer not to include them. The 128693db446aSBoris Brezillon * user should re-read the page in raw mode if ECC bytes are required. 128793db446aSBoris Brezillon * 128893db446aSBoris Brezillon * However, for any subpage read error reported by ->correct(), the ECC 128993db446aSBoris Brezillon * bytes must be read in raw mode and the full subpage must be checked 129093db446aSBoris Brezillon * to see if it is entirely empty of if there was an actual error. 129193db446aSBoris Brezillon */ 129293db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 129393db446aSBoris Brezillon /* No failure reported for this chunk, move to the next one */ 129493db446aSBoris Brezillon if (!(failure_mask & BIT(chunk))) 129593db446aSBoris Brezillon continue; 129693db446aSBoris Brezillon 129793db446aSBoris Brezillon /* Derive ECC bytes positions (in page/buffer) and length */ 129893db446aSBoris Brezillon ecc = chip->oob_poi + 129993db446aSBoris Brezillon (lt->full_chunk_cnt * lt->spare_bytes) + 130093db446aSBoris Brezillon lt->last_spare_bytes + 130193db446aSBoris Brezillon (chunk * ALIGN(lt->ecc_bytes, 32)); 130293db446aSBoris Brezillon ecc_offset_in_page = 130393db446aSBoris Brezillon (chunk * (lt->data_bytes + lt->spare_bytes + 130493db446aSBoris Brezillon lt->ecc_bytes)) + 130593db446aSBoris Brezillon (chunk < lt->full_chunk_cnt ? 130693db446aSBoris Brezillon lt->data_bytes + lt->spare_bytes : 130793db446aSBoris Brezillon lt->last_data_bytes + lt->last_spare_bytes); 130893db446aSBoris Brezillon ecc_len = chunk < lt->full_chunk_cnt ? 130993db446aSBoris Brezillon lt->ecc_bytes : lt->last_ecc_bytes; 131093db446aSBoris Brezillon 131193db446aSBoris Brezillon /* Do the actual raw read of the ECC bytes */ 131293db446aSBoris Brezillon nand_change_read_column_op(chip, ecc_offset_in_page, 131393db446aSBoris Brezillon ecc, ecc_len, false); 131493db446aSBoris Brezillon 131593db446aSBoris Brezillon /* Derive data/spare bytes positions (in buffer) and length */ 131693db446aSBoris Brezillon data = buf + (chunk * lt->data_bytes); 131793db446aSBoris Brezillon data_len = chunk < lt->full_chunk_cnt ? 131893db446aSBoris Brezillon lt->data_bytes : lt->last_data_bytes; 131993db446aSBoris Brezillon spare = chip->oob_poi + (chunk * (lt->spare_bytes + 132093db446aSBoris Brezillon lt->ecc_bytes)); 132193db446aSBoris Brezillon spare_len = chunk < lt->full_chunk_cnt ? 132293db446aSBoris Brezillon lt->spare_bytes : lt->last_spare_bytes; 132393db446aSBoris Brezillon 132493db446aSBoris Brezillon /* Check the entire chunk (data + spare + ecc) for emptyness */ 132593db446aSBoris Brezillon marvell_nfc_check_empty_chunk(chip, data, data_len, spare, 132693db446aSBoris Brezillon spare_len, ecc, ecc_len, 132793db446aSBoris Brezillon &max_bitflips); 132893db446aSBoris Brezillon } 132993db446aSBoris Brezillon 133093db446aSBoris Brezillon return max_bitflips; 133193db446aSBoris Brezillon } 133293db446aSBoris Brezillon 133393db446aSBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct mtd_info *mtd, 133493db446aSBoris Brezillon struct nand_chip *chip, int page) 133593db446aSBoris Brezillon { 133693db446aSBoris Brezillon /* Invalidate page cache */ 133793db446aSBoris Brezillon chip->pagebuf = -1; 133893db446aSBoris Brezillon 133993db446aSBoris Brezillon return chip->ecc.read_page_raw(mtd, chip, chip->data_buf, true, page); 134093db446aSBoris Brezillon } 134193db446aSBoris Brezillon 134293db446aSBoris Brezillon static int marvell_nfc_hw_ecc_bch_read_oob(struct mtd_info *mtd, 134393db446aSBoris Brezillon struct nand_chip *chip, int page) 134493db446aSBoris Brezillon { 134593db446aSBoris Brezillon /* Invalidate page cache */ 134693db446aSBoris Brezillon chip->pagebuf = -1; 134793db446aSBoris Brezillon 134893db446aSBoris Brezillon return chip->ecc.read_page(mtd, chip, chip->data_buf, true, page); 134993db446aSBoris Brezillon } 135093db446aSBoris Brezillon 135193db446aSBoris Brezillon /* BCH write helpers */ 135293db446aSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page_raw(struct mtd_info *mtd, 135393db446aSBoris Brezillon struct nand_chip *chip, 135493db446aSBoris Brezillon const u8 *buf, 135593db446aSBoris Brezillon int oob_required, int page) 135693db446aSBoris Brezillon { 135793db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 135893db446aSBoris Brezillon int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; 135993db446aSBoris Brezillon int data_len = lt->data_bytes; 136093db446aSBoris Brezillon int spare_len = lt->spare_bytes; 136193db446aSBoris Brezillon int ecc_len = lt->ecc_bytes; 136293db446aSBoris Brezillon int spare_offset = 0; 136393db446aSBoris Brezillon int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + 136493db446aSBoris Brezillon lt->last_spare_bytes; 136593db446aSBoris Brezillon int chunk; 136693db446aSBoris Brezillon 136793db446aSBoris Brezillon nand_prog_page_begin_op(chip, page, 0, NULL, 0); 136893db446aSBoris Brezillon 136993db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 137093db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 137193db446aSBoris Brezillon data_len = lt->last_data_bytes; 137293db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 137393db446aSBoris Brezillon ecc_len = lt->last_ecc_bytes; 137493db446aSBoris Brezillon } 137593db446aSBoris Brezillon 137693db446aSBoris Brezillon /* Point to the column of the next chunk */ 137793db446aSBoris Brezillon nand_change_write_column_op(chip, chunk * full_chunk_size, 137893db446aSBoris Brezillon NULL, 0, false); 137993db446aSBoris Brezillon 138093db446aSBoris Brezillon /* Write the data */ 138193db446aSBoris Brezillon nand_write_data_op(chip, buf + (chunk * lt->data_bytes), 138293db446aSBoris Brezillon data_len, false); 138393db446aSBoris Brezillon 138493db446aSBoris Brezillon if (!oob_required) 138593db446aSBoris Brezillon continue; 138693db446aSBoris Brezillon 138793db446aSBoris Brezillon /* Write the spare bytes */ 138893db446aSBoris Brezillon if (spare_len) 138993db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + spare_offset, 139093db446aSBoris Brezillon spare_len, false); 139193db446aSBoris Brezillon 139293db446aSBoris Brezillon /* Write the ECC bytes */ 139393db446aSBoris Brezillon if (ecc_len) 139493db446aSBoris Brezillon nand_write_data_op(chip, chip->oob_poi + ecc_offset, 139593db446aSBoris Brezillon ecc_len, false); 139693db446aSBoris Brezillon 139793db446aSBoris Brezillon spare_offset += spare_len; 139893db446aSBoris Brezillon ecc_offset += ALIGN(ecc_len, 32); 139993db446aSBoris Brezillon } 140093db446aSBoris Brezillon 140193db446aSBoris Brezillon return nand_prog_page_end_op(chip); 140293db446aSBoris Brezillon } 140393db446aSBoris Brezillon 140493db446aSBoris Brezillon static int 140593db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, 140693db446aSBoris Brezillon const u8 *data, unsigned int data_len, 140793db446aSBoris Brezillon const u8 *spare, unsigned int spare_len, 140893db446aSBoris Brezillon int page) 140993db446aSBoris Brezillon { 141093db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 141193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 141293db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 1413a2ee41fdSMiquel Raynal u32 xtype; 141493db446aSBoris Brezillon int ret; 141593db446aSBoris Brezillon struct marvell_nfc_op nfc_op = { 141693db446aSBoris Brezillon .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD, 141793db446aSBoris Brezillon .ndcb[3] = data_len + spare_len, 141893db446aSBoris Brezillon }; 141993db446aSBoris Brezillon 142093db446aSBoris Brezillon /* 142193db446aSBoris Brezillon * First operation dispatches the CMD_SEQIN command, issue the address 142293db446aSBoris Brezillon * cycles and asks for the first chunk of data. 142393db446aSBoris Brezillon * All operations in the middle (if any) will issue a naked write and 142493db446aSBoris Brezillon * also ask for data. 142593db446aSBoris Brezillon * Last operation (if any) asks for the last chunk of data through a 142693db446aSBoris Brezillon * last naked write. 142793db446aSBoris Brezillon */ 142893db446aSBoris Brezillon if (chunk == 0) { 1429a2ee41fdSMiquel Raynal if (lt->nchunks == 1) 1430a2ee41fdSMiquel Raynal xtype = XTYPE_MONOLITHIC_RW; 1431a2ee41fdSMiquel Raynal else 1432a2ee41fdSMiquel Raynal xtype = XTYPE_WRITE_DISPATCH; 1433a2ee41fdSMiquel Raynal 1434a2ee41fdSMiquel Raynal nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) | 143593db446aSBoris Brezillon NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | 143693db446aSBoris Brezillon NDCB0_CMD1(NAND_CMD_SEQIN); 143793db446aSBoris Brezillon nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page); 143893db446aSBoris Brezillon nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page); 143993db446aSBoris Brezillon } else if (chunk < lt->nchunks - 1) { 144093db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); 144193db446aSBoris Brezillon } else { 144293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 144393db446aSBoris Brezillon } 144493db446aSBoris Brezillon 144593db446aSBoris Brezillon /* Always dispatch the PAGEPROG command on the last chunk */ 144693db446aSBoris Brezillon if (chunk == lt->nchunks - 1) 144793db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC; 144893db446aSBoris Brezillon 144993db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 145093db446aSBoris Brezillon if (ret) 145193db446aSBoris Brezillon return ret; 145293db446aSBoris Brezillon 145393db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 145493db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ, 145593db446aSBoris Brezillon "WRDREQ while loading FIFO (data)"); 145693db446aSBoris Brezillon if (ret) 145793db446aSBoris Brezillon return ret; 145893db446aSBoris Brezillon 145993db446aSBoris Brezillon /* Transfer the contents */ 146093db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len)); 146193db446aSBoris Brezillon iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len)); 146293db446aSBoris Brezillon 146393db446aSBoris Brezillon return 0; 146493db446aSBoris Brezillon } 146593db446aSBoris Brezillon 146693db446aSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_page(struct mtd_info *mtd, 146793db446aSBoris Brezillon struct nand_chip *chip, 146893db446aSBoris Brezillon const u8 *buf, 146993db446aSBoris Brezillon int oob_required, int page) 147093db446aSBoris Brezillon { 147193db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 147293db446aSBoris Brezillon const u8 *data = buf; 147393db446aSBoris Brezillon const u8 *spare = chip->oob_poi; 147493db446aSBoris Brezillon int data_len = lt->data_bytes; 147593db446aSBoris Brezillon int spare_len = lt->spare_bytes; 147693db446aSBoris Brezillon int chunk, ret; 147793db446aSBoris Brezillon 147893db446aSBoris Brezillon /* Spare data will be written anyway, so clear it to avoid garbage */ 147993db446aSBoris Brezillon if (!oob_required) 148093db446aSBoris Brezillon memset(chip->oob_poi, 0xFF, mtd->oobsize); 148193db446aSBoris Brezillon 148293db446aSBoris Brezillon marvell_nfc_enable_hw_ecc(chip); 148393db446aSBoris Brezillon 148493db446aSBoris Brezillon for (chunk = 0; chunk < lt->nchunks; chunk++) { 148593db446aSBoris Brezillon if (chunk >= lt->full_chunk_cnt) { 148693db446aSBoris Brezillon data_len = lt->last_data_bytes; 148793db446aSBoris Brezillon spare_len = lt->last_spare_bytes; 148893db446aSBoris Brezillon } 148993db446aSBoris Brezillon 149093db446aSBoris Brezillon marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len, 149193db446aSBoris Brezillon spare, spare_len, page); 149293db446aSBoris Brezillon data += data_len; 149393db446aSBoris Brezillon spare += spare_len; 149493db446aSBoris Brezillon 149593db446aSBoris Brezillon /* 149693db446aSBoris Brezillon * Waiting only for CMDD or PAGED is not enough, ECC are 149793db446aSBoris Brezillon * partially written. No flag is set once the operation is 149893db446aSBoris Brezillon * really finished but the ND_RUN bit is cleared, so wait for it 149993db446aSBoris Brezillon * before stepping into the next command. 150093db446aSBoris Brezillon */ 150193db446aSBoris Brezillon marvell_nfc_wait_ndrun(chip); 150293db446aSBoris Brezillon } 150393db446aSBoris Brezillon 150493db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, 1505b76401fcSChris Packham PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max)); 150693db446aSBoris Brezillon 150793db446aSBoris Brezillon marvell_nfc_disable_hw_ecc(chip); 150893db446aSBoris Brezillon 150993db446aSBoris Brezillon if (ret) 151093db446aSBoris Brezillon return ret; 151193db446aSBoris Brezillon 151293db446aSBoris Brezillon return 0; 151393db446aSBoris Brezillon } 151493db446aSBoris Brezillon 151593db446aSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct mtd_info *mtd, 151693db446aSBoris Brezillon struct nand_chip *chip, 151793db446aSBoris Brezillon int page) 151893db446aSBoris Brezillon { 151993db446aSBoris Brezillon /* Invalidate page cache */ 152093db446aSBoris Brezillon chip->pagebuf = -1; 152193db446aSBoris Brezillon 152293db446aSBoris Brezillon memset(chip->data_buf, 0xFF, mtd->writesize); 152393db446aSBoris Brezillon 152493db446aSBoris Brezillon return chip->ecc.write_page_raw(mtd, chip, chip->data_buf, true, page); 152593db446aSBoris Brezillon } 152693db446aSBoris Brezillon 152793db446aSBoris Brezillon static int marvell_nfc_hw_ecc_bch_write_oob(struct mtd_info *mtd, 152893db446aSBoris Brezillon struct nand_chip *chip, int page) 152993db446aSBoris Brezillon { 153093db446aSBoris Brezillon /* Invalidate page cache */ 153193db446aSBoris Brezillon chip->pagebuf = -1; 153293db446aSBoris Brezillon 153393db446aSBoris Brezillon memset(chip->data_buf, 0xFF, mtd->writesize); 153493db446aSBoris Brezillon 153593db446aSBoris Brezillon return chip->ecc.write_page(mtd, chip, chip->data_buf, true, page); 153693db446aSBoris Brezillon } 153793db446aSBoris Brezillon 153893db446aSBoris Brezillon /* NAND framework ->exec_op() hooks and related helpers */ 153993db446aSBoris Brezillon static void marvell_nfc_parse_instructions(struct nand_chip *chip, 154093db446aSBoris Brezillon const struct nand_subop *subop, 154193db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 154293db446aSBoris Brezillon { 154393db446aSBoris Brezillon const struct nand_op_instr *instr = NULL; 154493db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 154593db446aSBoris Brezillon bool first_cmd = true; 154693db446aSBoris Brezillon unsigned int op_id; 154793db446aSBoris Brezillon int i; 154893db446aSBoris Brezillon 154993db446aSBoris Brezillon /* Reset the input structure as most of its fields will be OR'ed */ 155093db446aSBoris Brezillon memset(nfc_op, 0, sizeof(struct marvell_nfc_op)); 155193db446aSBoris Brezillon 155293db446aSBoris Brezillon for (op_id = 0; op_id < subop->ninstrs; op_id++) { 155393db446aSBoris Brezillon unsigned int offset, naddrs; 155493db446aSBoris Brezillon const u8 *addrs; 155593db446aSBoris Brezillon int len = nand_subop_get_data_len(subop, op_id); 155693db446aSBoris Brezillon 155793db446aSBoris Brezillon instr = &subop->instrs[op_id]; 155893db446aSBoris Brezillon 155993db446aSBoris Brezillon switch (instr->type) { 156093db446aSBoris Brezillon case NAND_OP_CMD_INSTR: 156193db446aSBoris Brezillon if (first_cmd) 156293db446aSBoris Brezillon nfc_op->ndcb[0] |= 156393db446aSBoris Brezillon NDCB0_CMD1(instr->ctx.cmd.opcode); 156493db446aSBoris Brezillon else 156593db446aSBoris Brezillon nfc_op->ndcb[0] |= 156693db446aSBoris Brezillon NDCB0_CMD2(instr->ctx.cmd.opcode) | 156793db446aSBoris Brezillon NDCB0_DBC; 156893db446aSBoris Brezillon 156993db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns; 157093db446aSBoris Brezillon first_cmd = false; 157193db446aSBoris Brezillon break; 157293db446aSBoris Brezillon 157393db446aSBoris Brezillon case NAND_OP_ADDR_INSTR: 157493db446aSBoris Brezillon offset = nand_subop_get_addr_start_off(subop, op_id); 157593db446aSBoris Brezillon naddrs = nand_subop_get_num_addr_cyc(subop, op_id); 157693db446aSBoris Brezillon addrs = &instr->ctx.addr.addrs[offset]; 157793db446aSBoris Brezillon 157893db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs); 157993db446aSBoris Brezillon 158093db446aSBoris Brezillon for (i = 0; i < min_t(unsigned int, 4, naddrs); i++) 158193db446aSBoris Brezillon nfc_op->ndcb[1] |= addrs[i] << (8 * i); 158293db446aSBoris Brezillon 158393db446aSBoris Brezillon if (naddrs >= 5) 158493db446aSBoris Brezillon nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]); 158593db446aSBoris Brezillon if (naddrs >= 6) 158693db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]); 158793db446aSBoris Brezillon if (naddrs == 7) 158893db446aSBoris Brezillon nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]); 158993db446aSBoris Brezillon 159093db446aSBoris Brezillon nfc_op->cle_ale_delay_ns = instr->delay_ns; 159193db446aSBoris Brezillon break; 159293db446aSBoris Brezillon 159393db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR: 159493db446aSBoris Brezillon nfc_op->data_instr = instr; 159593db446aSBoris Brezillon nfc_op->data_instr_idx = op_id; 159693db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ); 159793db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 159893db446aSBoris Brezillon nfc_op->ndcb[0] |= 159993db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 160093db446aSBoris Brezillon NDCB0_LEN_OVRD; 160193db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 160293db446aSBoris Brezillon } 160393db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns; 160493db446aSBoris Brezillon break; 160593db446aSBoris Brezillon 160693db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR: 160793db446aSBoris Brezillon nfc_op->data_instr = instr; 160893db446aSBoris Brezillon nfc_op->data_instr_idx = op_id; 160993db446aSBoris Brezillon nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE); 161093db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 161193db446aSBoris Brezillon nfc_op->ndcb[0] |= 161293db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) | 161393db446aSBoris Brezillon NDCB0_LEN_OVRD; 161493db446aSBoris Brezillon nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); 161593db446aSBoris Brezillon } 161693db446aSBoris Brezillon nfc_op->data_delay_ns = instr->delay_ns; 161793db446aSBoris Brezillon break; 161893db446aSBoris Brezillon 161993db446aSBoris Brezillon case NAND_OP_WAITRDY_INSTR: 162093db446aSBoris Brezillon nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; 162193db446aSBoris Brezillon nfc_op->rdy_delay_ns = instr->delay_ns; 162293db446aSBoris Brezillon break; 162393db446aSBoris Brezillon } 162493db446aSBoris Brezillon } 162593db446aSBoris Brezillon } 162693db446aSBoris Brezillon 162793db446aSBoris Brezillon static int marvell_nfc_xfer_data_pio(struct nand_chip *chip, 162893db446aSBoris Brezillon const struct nand_subop *subop, 162993db446aSBoris Brezillon struct marvell_nfc_op *nfc_op) 163093db446aSBoris Brezillon { 163193db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 163293db446aSBoris Brezillon const struct nand_op_instr *instr = nfc_op->data_instr; 163393db446aSBoris Brezillon unsigned int op_id = nfc_op->data_instr_idx; 163493db446aSBoris Brezillon unsigned int len = nand_subop_get_data_len(subop, op_id); 163593db446aSBoris Brezillon unsigned int offset = nand_subop_get_data_start_off(subop, op_id); 163693db446aSBoris Brezillon bool reading = (instr->type == NAND_OP_DATA_IN_INSTR); 163793db446aSBoris Brezillon int ret; 163893db446aSBoris Brezillon 163993db446aSBoris Brezillon if (instr->ctx.data.force_8bit) 164093db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, true); 164193db446aSBoris Brezillon 164293db446aSBoris Brezillon if (reading) { 164393db446aSBoris Brezillon u8 *in = instr->ctx.data.buf.in + offset; 164493db446aSBoris Brezillon 164593db446aSBoris Brezillon ret = marvell_nfc_xfer_data_in_pio(nfc, in, len); 164693db446aSBoris Brezillon } else { 164793db446aSBoris Brezillon const u8 *out = instr->ctx.data.buf.out + offset; 164893db446aSBoris Brezillon 164993db446aSBoris Brezillon ret = marvell_nfc_xfer_data_out_pio(nfc, out, len); 165093db446aSBoris Brezillon } 165193db446aSBoris Brezillon 165293db446aSBoris Brezillon if (instr->ctx.data.force_8bit) 165393db446aSBoris Brezillon marvell_nfc_force_byte_access(chip, false); 165493db446aSBoris Brezillon 165593db446aSBoris Brezillon return ret; 165693db446aSBoris Brezillon } 165793db446aSBoris Brezillon 165893db446aSBoris Brezillon static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip, 165993db446aSBoris Brezillon const struct nand_subop *subop) 166093db446aSBoris Brezillon { 166193db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 166293db446aSBoris Brezillon bool reading; 166393db446aSBoris Brezillon int ret; 166493db446aSBoris Brezillon 166593db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 166693db446aSBoris Brezillon reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR); 166793db446aSBoris Brezillon 166893db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 166993db446aSBoris Brezillon if (ret) 167093db446aSBoris Brezillon return ret; 167193db446aSBoris Brezillon 167293db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 167393db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 167493db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data"); 167593db446aSBoris Brezillon if (ret) 167693db446aSBoris Brezillon return ret; 167793db446aSBoris Brezillon 167893db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 167993db446aSBoris Brezillon 168093db446aSBoris Brezillon if (reading) { 168193db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 168293db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 168393db446aSBoris Brezillon if (ret) 168493db446aSBoris Brezillon return ret; 168593db446aSBoris Brezillon } 168693db446aSBoris Brezillon 168793db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 168893db446aSBoris Brezillon } 168993db446aSBoris Brezillon 169093db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 169193db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 169293db446aSBoris Brezillon if (ret) 169393db446aSBoris Brezillon return ret; 169493db446aSBoris Brezillon 169593db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 169693db446aSBoris Brezillon 169793db446aSBoris Brezillon if (!reading) { 169893db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 169993db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 170093db446aSBoris Brezillon if (ret) 170193db446aSBoris Brezillon return ret; 170293db446aSBoris Brezillon } 170393db446aSBoris Brezillon 170493db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 170593db446aSBoris Brezillon } 170693db446aSBoris Brezillon 170793db446aSBoris Brezillon /* 170893db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each 170993db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it 171093db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case. 171193db446aSBoris Brezillon */ 171293db446aSBoris Brezillon if (!reading) { 171393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 171493db446aSBoris Brezillon 171593db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 171693db446aSBoris Brezillon nfc->regs + NDCR); 171793db446aSBoris Brezillon } 171893db446aSBoris Brezillon 171993db446aSBoris Brezillon return 0; 172093db446aSBoris Brezillon } 172193db446aSBoris Brezillon 172293db446aSBoris Brezillon static int marvell_nfc_naked_access_exec(struct nand_chip *chip, 172393db446aSBoris Brezillon const struct nand_subop *subop) 172493db446aSBoris Brezillon { 172593db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 172693db446aSBoris Brezillon int ret; 172793db446aSBoris Brezillon 172893db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 172993db446aSBoris Brezillon 173093db446aSBoris Brezillon /* 173193db446aSBoris Brezillon * Naked access are different in that they need to be flagged as naked 173293db446aSBoris Brezillon * by the controller. Reset the controller registers fields that inform 173393db446aSBoris Brezillon * on the type and refill them according to the ongoing operation. 173493db446aSBoris Brezillon */ 173593db446aSBoris Brezillon nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) | 173693db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_MASK)); 173793db446aSBoris Brezillon switch (subop->instrs[0].type) { 173893db446aSBoris Brezillon case NAND_OP_CMD_INSTR: 173993db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD); 174093db446aSBoris Brezillon break; 174193db446aSBoris Brezillon case NAND_OP_ADDR_INSTR: 174293db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR); 174393db446aSBoris Brezillon break; 174493db446aSBoris Brezillon case NAND_OP_DATA_IN_INSTR: 174593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) | 174693db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 174793db446aSBoris Brezillon break; 174893db446aSBoris Brezillon case NAND_OP_DATA_OUT_INSTR: 174993db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) | 175093db446aSBoris Brezillon NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW); 175193db446aSBoris Brezillon break; 175293db446aSBoris Brezillon default: 175393db446aSBoris Brezillon /* This should never happen */ 175493db446aSBoris Brezillon break; 175593db446aSBoris Brezillon } 175693db446aSBoris Brezillon 175793db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 175893db446aSBoris Brezillon if (ret) 175993db446aSBoris Brezillon return ret; 176093db446aSBoris Brezillon 176193db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 176293db446aSBoris Brezillon 176393db446aSBoris Brezillon if (!nfc_op.data_instr) { 176493db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 176593db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 176693db446aSBoris Brezillon return ret; 176793db446aSBoris Brezillon } 176893db446aSBoris Brezillon 176993db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ, 177093db446aSBoris Brezillon "RDDREQ/WRDREQ while draining raw data"); 177193db446aSBoris Brezillon if (ret) 177293db446aSBoris Brezillon return ret; 177393db446aSBoris Brezillon 177493db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 177593db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 177693db446aSBoris Brezillon if (ret) 177793db446aSBoris Brezillon return ret; 177893db446aSBoris Brezillon 177993db446aSBoris Brezillon /* 178093db446aSBoris Brezillon * NDCR ND_RUN bit should be cleared automatically at the end of each 178193db446aSBoris Brezillon * operation but experience shows that the behavior is buggy when it 178293db446aSBoris Brezillon * comes to writes (with LEN_OVRD). Clear it by hand in this case. 178393db446aSBoris Brezillon */ 178493db446aSBoris Brezillon if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { 178593db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 178693db446aSBoris Brezillon 178793db446aSBoris Brezillon writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, 178893db446aSBoris Brezillon nfc->regs + NDCR); 178993db446aSBoris Brezillon } 179093db446aSBoris Brezillon 179193db446aSBoris Brezillon return 0; 179293db446aSBoris Brezillon } 179393db446aSBoris Brezillon 179493db446aSBoris Brezillon static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip, 179593db446aSBoris Brezillon const struct nand_subop *subop) 179693db446aSBoris Brezillon { 179793db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 179893db446aSBoris Brezillon int ret; 179993db446aSBoris Brezillon 180093db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 180193db446aSBoris Brezillon 180293db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 180393db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 180493db446aSBoris Brezillon 180593db446aSBoris Brezillon return ret; 180693db446aSBoris Brezillon } 180793db446aSBoris Brezillon 180893db446aSBoris Brezillon static int marvell_nfc_read_id_type_exec(struct nand_chip *chip, 180993db446aSBoris Brezillon const struct nand_subop *subop) 181093db446aSBoris Brezillon { 181193db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 181293db446aSBoris Brezillon int ret; 181393db446aSBoris Brezillon 181493db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 181593db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 181693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID); 181793db446aSBoris Brezillon 181893db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 181993db446aSBoris Brezillon if (ret) 182093db446aSBoris Brezillon return ret; 182193db446aSBoris Brezillon 182293db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 182393db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 182493db446aSBoris Brezillon "RDDREQ while reading ID"); 182593db446aSBoris Brezillon if (ret) 182693db446aSBoris Brezillon return ret; 182793db446aSBoris Brezillon 182893db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 182993db446aSBoris Brezillon 183093db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 183193db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 183293db446aSBoris Brezillon if (ret) 183393db446aSBoris Brezillon return ret; 183493db446aSBoris Brezillon } 183593db446aSBoris Brezillon 183693db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 183793db446aSBoris Brezillon 183893db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 183993db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 184093db446aSBoris Brezillon if (ret) 184193db446aSBoris Brezillon return ret; 184293db446aSBoris Brezillon 184393db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 184493db446aSBoris Brezillon 184593db446aSBoris Brezillon return 0; 184693db446aSBoris Brezillon } 184793db446aSBoris Brezillon 184893db446aSBoris Brezillon static int marvell_nfc_read_status_exec(struct nand_chip *chip, 184993db446aSBoris Brezillon const struct nand_subop *subop) 185093db446aSBoris Brezillon { 185193db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 185293db446aSBoris Brezillon int ret; 185393db446aSBoris Brezillon 185493db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 185593db446aSBoris Brezillon nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ); 185693db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS); 185793db446aSBoris Brezillon 185893db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 185993db446aSBoris Brezillon if (ret) 186093db446aSBoris Brezillon return ret; 186193db446aSBoris Brezillon 186293db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 186393db446aSBoris Brezillon ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ, 186493db446aSBoris Brezillon "RDDREQ while reading status"); 186593db446aSBoris Brezillon if (ret) 186693db446aSBoris Brezillon return ret; 186793db446aSBoris Brezillon 186893db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 186993db446aSBoris Brezillon 187093db446aSBoris Brezillon if (nfc_op.rdy_timeout_ms) { 187193db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 187293db446aSBoris Brezillon if (ret) 187393db446aSBoris Brezillon return ret; 187493db446aSBoris Brezillon } 187593db446aSBoris Brezillon 187693db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 187793db446aSBoris Brezillon 187893db446aSBoris Brezillon marvell_nfc_xfer_data_pio(chip, subop, &nfc_op); 187993db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 188093db446aSBoris Brezillon if (ret) 188193db446aSBoris Brezillon return ret; 188293db446aSBoris Brezillon 188393db446aSBoris Brezillon cond_delay(nfc_op.data_delay_ns); 188493db446aSBoris Brezillon 188593db446aSBoris Brezillon return 0; 188693db446aSBoris Brezillon } 188793db446aSBoris Brezillon 188893db446aSBoris Brezillon static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip, 188993db446aSBoris Brezillon const struct nand_subop *subop) 189093db446aSBoris Brezillon { 189193db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 189293db446aSBoris Brezillon int ret; 189393db446aSBoris Brezillon 189493db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 189593db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET); 189693db446aSBoris Brezillon 189793db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 189893db446aSBoris Brezillon if (ret) 189993db446aSBoris Brezillon return ret; 190093db446aSBoris Brezillon 190193db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 190293db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 190393db446aSBoris Brezillon if (ret) 190493db446aSBoris Brezillon return ret; 190593db446aSBoris Brezillon 190693db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 190793db446aSBoris Brezillon 190893db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 190993db446aSBoris Brezillon if (ret) 191093db446aSBoris Brezillon return ret; 191193db446aSBoris Brezillon 191293db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 191393db446aSBoris Brezillon 191493db446aSBoris Brezillon return 0; 191593db446aSBoris Brezillon } 191693db446aSBoris Brezillon 191793db446aSBoris Brezillon static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip, 191893db446aSBoris Brezillon const struct nand_subop *subop) 191993db446aSBoris Brezillon { 192093db446aSBoris Brezillon struct marvell_nfc_op nfc_op; 192193db446aSBoris Brezillon int ret; 192293db446aSBoris Brezillon 192393db446aSBoris Brezillon marvell_nfc_parse_instructions(chip, subop, &nfc_op); 192493db446aSBoris Brezillon nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE); 192593db446aSBoris Brezillon 192693db446aSBoris Brezillon ret = marvell_nfc_prepare_cmd(chip); 192793db446aSBoris Brezillon if (ret) 192893db446aSBoris Brezillon return ret; 192993db446aSBoris Brezillon 193093db446aSBoris Brezillon marvell_nfc_send_cmd(chip, &nfc_op); 193193db446aSBoris Brezillon ret = marvell_nfc_wait_cmdd(chip); 193293db446aSBoris Brezillon if (ret) 193393db446aSBoris Brezillon return ret; 193493db446aSBoris Brezillon 193593db446aSBoris Brezillon cond_delay(nfc_op.cle_ale_delay_ns); 193693db446aSBoris Brezillon 193793db446aSBoris Brezillon ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms); 193893db446aSBoris Brezillon if (ret) 193993db446aSBoris Brezillon return ret; 194093db446aSBoris Brezillon 194193db446aSBoris Brezillon cond_delay(nfc_op.rdy_delay_ns); 194293db446aSBoris Brezillon 194393db446aSBoris Brezillon return 0; 194493db446aSBoris Brezillon } 194593db446aSBoris Brezillon 194693db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER( 194793db446aSBoris Brezillon /* Monolithic reads/writes */ 194893db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 194993db446aSBoris Brezillon marvell_nfc_monolithic_access_exec, 195093db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 195193db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2), 195293db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true), 195393db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 195493db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 195593db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 195693db446aSBoris Brezillon marvell_nfc_monolithic_access_exec, 195793db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 195893db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2), 195993db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE), 196093db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(true), 196193db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 196293db446aSBoris Brezillon /* Naked commands */ 196393db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 196493db446aSBoris Brezillon marvell_nfc_naked_access_exec, 196593db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false)), 196693db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 196793db446aSBoris Brezillon marvell_nfc_naked_access_exec, 196893db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)), 196993db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 197093db446aSBoris Brezillon marvell_nfc_naked_access_exec, 197193db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)), 197293db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 197393db446aSBoris Brezillon marvell_nfc_naked_access_exec, 197493db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)), 197593db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 197693db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec, 197793db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 197893db446aSBoris Brezillon ); 197993db446aSBoris Brezillon 198093db446aSBoris Brezillon static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER( 198193db446aSBoris Brezillon /* Naked commands not supported, use a function for each pattern */ 198293db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 198393db446aSBoris Brezillon marvell_nfc_read_id_type_exec, 198493db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 198593db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 198693db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)), 198793db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 198893db446aSBoris Brezillon marvell_nfc_erase_cmd_type_exec, 198993db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 199093db446aSBoris Brezillon NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1), 199193db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 199293db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 199393db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 199493db446aSBoris Brezillon marvell_nfc_read_status_exec, 199593db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 199693db446aSBoris Brezillon NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)), 199793db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 199893db446aSBoris Brezillon marvell_nfc_reset_cmd_type_exec, 199993db446aSBoris Brezillon NAND_OP_PARSER_PAT_CMD_ELEM(false), 200093db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 200193db446aSBoris Brezillon NAND_OP_PARSER_PATTERN( 200293db446aSBoris Brezillon marvell_nfc_naked_waitrdy_exec, 200393db446aSBoris Brezillon NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 200493db446aSBoris Brezillon ); 200593db446aSBoris Brezillon 200693db446aSBoris Brezillon static int marvell_nfc_exec_op(struct nand_chip *chip, 200793db446aSBoris Brezillon const struct nand_operation *op, 200893db446aSBoris Brezillon bool check_only) 200993db446aSBoris Brezillon { 201093db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 201193db446aSBoris Brezillon 201293db446aSBoris Brezillon if (nfc->caps->is_nfcv2) 201393db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser, 201493db446aSBoris Brezillon op, check_only); 201593db446aSBoris Brezillon else 201693db446aSBoris Brezillon return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser, 201793db446aSBoris Brezillon op, check_only); 201893db446aSBoris Brezillon } 201993db446aSBoris Brezillon 202093db446aSBoris Brezillon /* 202193db446aSBoris Brezillon * Layouts were broken in old pxa3xx_nand driver, these are supposed to be 202293db446aSBoris Brezillon * usable. 202393db446aSBoris Brezillon */ 202493db446aSBoris Brezillon static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section, 202593db446aSBoris Brezillon struct mtd_oob_region *oobregion) 202693db446aSBoris Brezillon { 202793db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 202893db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 202993db446aSBoris Brezillon 203093db446aSBoris Brezillon if (section) 203193db446aSBoris Brezillon return -ERANGE; 203293db446aSBoris Brezillon 203393db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + 203493db446aSBoris Brezillon lt->last_ecc_bytes; 203593db446aSBoris Brezillon oobregion->offset = mtd->oobsize - oobregion->length; 203693db446aSBoris Brezillon 203793db446aSBoris Brezillon return 0; 203893db446aSBoris Brezillon } 203993db446aSBoris Brezillon 204093db446aSBoris Brezillon static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section, 204193db446aSBoris Brezillon struct mtd_oob_region *oobregion) 204293db446aSBoris Brezillon { 204393db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 204493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; 204593db446aSBoris Brezillon 204693db446aSBoris Brezillon if (section) 204793db446aSBoris Brezillon return -ERANGE; 204893db446aSBoris Brezillon 204993db446aSBoris Brezillon /* 205093db446aSBoris Brezillon * Bootrom looks in bytes 0 & 5 for bad blocks for the 205193db446aSBoris Brezillon * 4KB page / 4bit BCH combination. 205293db446aSBoris Brezillon */ 205393db446aSBoris Brezillon if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) 205493db446aSBoris Brezillon oobregion->offset = 6; 205593db446aSBoris Brezillon else 205693db446aSBoris Brezillon oobregion->offset = 2; 205793db446aSBoris Brezillon 205893db446aSBoris Brezillon oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + 205993db446aSBoris Brezillon lt->last_spare_bytes - oobregion->offset; 206093db446aSBoris Brezillon 206193db446aSBoris Brezillon return 0; 206293db446aSBoris Brezillon } 206393db446aSBoris Brezillon 206493db446aSBoris Brezillon static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = { 206593db446aSBoris Brezillon .ecc = marvell_nand_ooblayout_ecc, 206693db446aSBoris Brezillon .free = marvell_nand_ooblayout_free, 206793db446aSBoris Brezillon }; 206893db446aSBoris Brezillon 206993db446aSBoris Brezillon static int marvell_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, 207093db446aSBoris Brezillon struct nand_ecc_ctrl *ecc) 207193db446aSBoris Brezillon { 207293db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 207393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 207493db446aSBoris Brezillon const struct marvell_hw_ecc_layout *l; 207593db446aSBoris Brezillon int i; 207693db446aSBoris Brezillon 207793db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 && 207893db446aSBoris Brezillon (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) { 207993db446aSBoris Brezillon dev_err(nfc->dev, 208093db446aSBoris Brezillon "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n", 208193db446aSBoris Brezillon mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize); 208293db446aSBoris Brezillon return -ENOTSUPP; 208393db446aSBoris Brezillon } 208493db446aSBoris Brezillon 208593db446aSBoris Brezillon to_marvell_nand(chip)->layout = NULL; 208693db446aSBoris Brezillon for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) { 208793db446aSBoris Brezillon l = &marvell_nfc_layouts[i]; 208893db446aSBoris Brezillon if (mtd->writesize == l->writesize && 208993db446aSBoris Brezillon ecc->size == l->chunk && ecc->strength == l->strength) { 209093db446aSBoris Brezillon to_marvell_nand(chip)->layout = l; 209193db446aSBoris Brezillon break; 209293db446aSBoris Brezillon } 209393db446aSBoris Brezillon } 209493db446aSBoris Brezillon 209593db446aSBoris Brezillon if (!to_marvell_nand(chip)->layout || 209693db446aSBoris Brezillon (!nfc->caps->is_nfcv2 && ecc->strength > 1)) { 209793db446aSBoris Brezillon dev_err(nfc->dev, 209893db446aSBoris Brezillon "ECC strength %d at page size %d is not supported\n", 209993db446aSBoris Brezillon ecc->strength, mtd->writesize); 210093db446aSBoris Brezillon return -ENOTSUPP; 210193db446aSBoris Brezillon } 210293db446aSBoris Brezillon 210393db446aSBoris Brezillon mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops); 210493db446aSBoris Brezillon ecc->steps = l->nchunks; 210593db446aSBoris Brezillon ecc->size = l->data_bytes; 210693db446aSBoris Brezillon 210793db446aSBoris Brezillon if (ecc->strength == 1) { 210893db446aSBoris Brezillon chip->ecc.algo = NAND_ECC_HAMMING; 210993db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; 211093db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; 211193db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; 211293db446aSBoris Brezillon ecc->read_oob = ecc->read_oob_raw; 211393db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw; 211493db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page; 211593db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; 211693db446aSBoris Brezillon ecc->write_oob = ecc->write_oob_raw; 211793db446aSBoris Brezillon } else { 211893db446aSBoris Brezillon chip->ecc.algo = NAND_ECC_BCH; 211993db446aSBoris Brezillon ecc->strength = 16; 212093db446aSBoris Brezillon ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; 212193db446aSBoris Brezillon ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; 212293db446aSBoris Brezillon ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw; 212393db446aSBoris Brezillon ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob; 212493db446aSBoris Brezillon ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw; 212593db446aSBoris Brezillon ecc->write_page = marvell_nfc_hw_ecc_bch_write_page; 212693db446aSBoris Brezillon ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw; 212793db446aSBoris Brezillon ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob; 212893db446aSBoris Brezillon } 212993db446aSBoris Brezillon 213093db446aSBoris Brezillon return 0; 213193db446aSBoris Brezillon } 213293db446aSBoris Brezillon 213393db446aSBoris Brezillon static int marvell_nand_ecc_init(struct mtd_info *mtd, 213493db446aSBoris Brezillon struct nand_ecc_ctrl *ecc) 213593db446aSBoris Brezillon { 213693db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 213793db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 213893db446aSBoris Brezillon int ret; 213993db446aSBoris Brezillon 214093db446aSBoris Brezillon if (ecc->mode != NAND_ECC_NONE && (!ecc->size || !ecc->strength)) { 214193db446aSBoris Brezillon if (chip->ecc_step_ds && chip->ecc_strength_ds) { 214293db446aSBoris Brezillon ecc->size = chip->ecc_step_ds; 214393db446aSBoris Brezillon ecc->strength = chip->ecc_strength_ds; 214493db446aSBoris Brezillon } else { 214593db446aSBoris Brezillon dev_info(nfc->dev, 214693db446aSBoris Brezillon "No minimum ECC strength, using 1b/512B\n"); 214793db446aSBoris Brezillon ecc->size = 512; 214893db446aSBoris Brezillon ecc->strength = 1; 214993db446aSBoris Brezillon } 215093db446aSBoris Brezillon } 215193db446aSBoris Brezillon 215293db446aSBoris Brezillon switch (ecc->mode) { 215393db446aSBoris Brezillon case NAND_ECC_HW: 215493db446aSBoris Brezillon ret = marvell_nand_hw_ecc_ctrl_init(mtd, ecc); 215593db446aSBoris Brezillon if (ret) 215693db446aSBoris Brezillon return ret; 215793db446aSBoris Brezillon break; 215893db446aSBoris Brezillon case NAND_ECC_NONE: 215993db446aSBoris Brezillon case NAND_ECC_SOFT: 216093db446aSBoris Brezillon if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && 216193db446aSBoris Brezillon mtd->writesize != SZ_2K) { 216293db446aSBoris Brezillon dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", 216393db446aSBoris Brezillon mtd->writesize); 216493db446aSBoris Brezillon return -EINVAL; 216593db446aSBoris Brezillon } 216693db446aSBoris Brezillon break; 216793db446aSBoris Brezillon default: 216893db446aSBoris Brezillon return -EINVAL; 216993db446aSBoris Brezillon } 217093db446aSBoris Brezillon 217193db446aSBoris Brezillon return 0; 217293db446aSBoris Brezillon } 217393db446aSBoris Brezillon 217493db446aSBoris Brezillon static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; 217593db446aSBoris Brezillon static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; 217693db446aSBoris Brezillon 217793db446aSBoris Brezillon static struct nand_bbt_descr bbt_main_descr = { 217893db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 217993db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION, 218093db446aSBoris Brezillon .offs = 8, 218193db446aSBoris Brezillon .len = 6, 218293db446aSBoris Brezillon .veroffs = 14, 218393db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */ 218493db446aSBoris Brezillon .pattern = bbt_pattern 218593db446aSBoris Brezillon }; 218693db446aSBoris Brezillon 218793db446aSBoris Brezillon static struct nand_bbt_descr bbt_mirror_descr = { 218893db446aSBoris Brezillon .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 218993db446aSBoris Brezillon NAND_BBT_2BIT | NAND_BBT_VERSION, 219093db446aSBoris Brezillon .offs = 8, 219193db446aSBoris Brezillon .len = 6, 219293db446aSBoris Brezillon .veroffs = 14, 219393db446aSBoris Brezillon .maxblocks = 8, /* Last 8 blocks in each chip */ 219493db446aSBoris Brezillon .pattern = bbt_mirror_pattern 219593db446aSBoris Brezillon }; 219693db446aSBoris Brezillon 219793db446aSBoris Brezillon static int marvell_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr, 219893db446aSBoris Brezillon const struct nand_data_interface 219993db446aSBoris Brezillon *conf) 220093db446aSBoris Brezillon { 220193db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 220293db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); 220393db446aSBoris Brezillon struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 22046b6de654SBoris Brezillon unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2; 220593db446aSBoris Brezillon const struct nand_sdr_timings *sdr; 220693db446aSBoris Brezillon struct marvell_nfc_timings nfc_tmg; 220793db446aSBoris Brezillon int read_delay; 220893db446aSBoris Brezillon 220993db446aSBoris Brezillon sdr = nand_get_sdr_timings(conf); 221093db446aSBoris Brezillon if (IS_ERR(sdr)) 221193db446aSBoris Brezillon return PTR_ERR(sdr); 221293db446aSBoris Brezillon 221393db446aSBoris Brezillon /* 221493db446aSBoris Brezillon * SDR timings are given in pico-seconds while NFC timings must be 221593db446aSBoris Brezillon * expressed in NAND controller clock cycles, which is half of the 221693db446aSBoris Brezillon * frequency of the accessible ECC clock retrieved by clk_get_rate(). 221793db446aSBoris Brezillon * This is not written anywhere in the datasheet but was observed 221893db446aSBoris Brezillon * with an oscilloscope. 221993db446aSBoris Brezillon * 222093db446aSBoris Brezillon * NFC datasheet gives equations from which thoses calculations 222193db446aSBoris Brezillon * are derived, they tend to be slightly more restrictives than the 222293db446aSBoris Brezillon * given core timings and may improve the overall speed. 222393db446aSBoris Brezillon */ 222493db446aSBoris Brezillon nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; 222593db446aSBoris Brezillon nfc_tmg.tRH = nfc_tmg.tRP; 222693db446aSBoris Brezillon nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; 222793db446aSBoris Brezillon nfc_tmg.tWH = nfc_tmg.tWP; 222893db446aSBoris Brezillon nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); 222993db446aSBoris Brezillon nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; 223093db446aSBoris Brezillon nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); 223193db446aSBoris Brezillon /* 223293db446aSBoris Brezillon * Read delay is the time of propagation from SoC pins to NFC internal 223393db446aSBoris Brezillon * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In 223493db446aSBoris Brezillon * EDO mode, an additional delay of tRH must be taken into account so 223593db446aSBoris Brezillon * the data is sampled on the falling edge instead of the rising edge. 223693db446aSBoris Brezillon */ 223793db446aSBoris Brezillon read_delay = sdr->tRC_min >= 30000 ? 223893db446aSBoris Brezillon MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH; 223993db446aSBoris Brezillon 224093db446aSBoris Brezillon nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); 224193db446aSBoris Brezillon /* 224293db446aSBoris Brezillon * tWHR and tRHW are supposed to be read to write delays (and vice 224393db446aSBoris Brezillon * versa) but in some cases, ie. when doing a change column, they must 224493db446aSBoris Brezillon * be greater than that to be sure tCCS delay is respected. 224593db446aSBoris Brezillon */ 224693db446aSBoris Brezillon nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), 224793db446aSBoris Brezillon period_ns) - 2, 224893db446aSBoris Brezillon nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), 224993db446aSBoris Brezillon period_ns); 225093db446aSBoris Brezillon 225193db446aSBoris Brezillon /* 225293db446aSBoris Brezillon * NFCv2: Use WAIT_MODE (wait for RB line), do not rely only on delays. 225393db446aSBoris Brezillon * NFCv1: No WAIT_MODE, tR must be maximal. 225493db446aSBoris Brezillon */ 225593db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 225693db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); 225793db446aSBoris Brezillon } else { 225893db446aSBoris Brezillon nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, 225993db446aSBoris Brezillon period_ns); 226093db446aSBoris Brezillon if (nfc_tmg.tR + 3 > nfc_tmg.tCH) 226193db446aSBoris Brezillon nfc_tmg.tR = nfc_tmg.tCH - 3; 226293db446aSBoris Brezillon else 226393db446aSBoris Brezillon nfc_tmg.tR = 0; 226493db446aSBoris Brezillon } 226593db446aSBoris Brezillon 226693db446aSBoris Brezillon if (chipnr < 0) 226793db446aSBoris Brezillon return 0; 226893db446aSBoris Brezillon 226993db446aSBoris Brezillon marvell_nand->ndtr0 = 227093db446aSBoris Brezillon NDTR0_TRP(nfc_tmg.tRP) | 227193db446aSBoris Brezillon NDTR0_TRH(nfc_tmg.tRH) | 227293db446aSBoris Brezillon NDTR0_ETRP(nfc_tmg.tRP) | 227393db446aSBoris Brezillon NDTR0_TWP(nfc_tmg.tWP) | 227493db446aSBoris Brezillon NDTR0_TWH(nfc_tmg.tWH) | 227593db446aSBoris Brezillon NDTR0_TCS(nfc_tmg.tCS) | 227693db446aSBoris Brezillon NDTR0_TCH(nfc_tmg.tCH); 227793db446aSBoris Brezillon 227893db446aSBoris Brezillon marvell_nand->ndtr1 = 227993db446aSBoris Brezillon NDTR1_TAR(nfc_tmg.tAR) | 228093db446aSBoris Brezillon NDTR1_TWHR(nfc_tmg.tWHR) | 228193db446aSBoris Brezillon NDTR1_TR(nfc_tmg.tR); 228293db446aSBoris Brezillon 228393db446aSBoris Brezillon if (nfc->caps->is_nfcv2) { 228493db446aSBoris Brezillon marvell_nand->ndtr0 |= 228593db446aSBoris Brezillon NDTR0_RD_CNT_DEL(read_delay) | 228693db446aSBoris Brezillon NDTR0_SELCNTR | 228793db446aSBoris Brezillon NDTR0_TADL(nfc_tmg.tADL); 228893db446aSBoris Brezillon 228993db446aSBoris Brezillon marvell_nand->ndtr1 |= 229093db446aSBoris Brezillon NDTR1_TRHW(nfc_tmg.tRHW) | 229193db446aSBoris Brezillon NDTR1_WAIT_MODE; 229293db446aSBoris Brezillon } 229393db446aSBoris Brezillon 229493db446aSBoris Brezillon return 0; 229593db446aSBoris Brezillon } 229693db446aSBoris Brezillon 229793db446aSBoris Brezillon static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc, 229893db446aSBoris Brezillon struct device_node *np) 229993db446aSBoris Brezillon { 230093db446aSBoris Brezillon struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev); 230193db446aSBoris Brezillon struct marvell_nand_chip *marvell_nand; 230293db446aSBoris Brezillon struct mtd_info *mtd; 230393db446aSBoris Brezillon struct nand_chip *chip; 230493db446aSBoris Brezillon int nsels, ret, i; 230593db446aSBoris Brezillon u32 cs, rb; 230693db446aSBoris Brezillon 230793db446aSBoris Brezillon /* 230893db446aSBoris Brezillon * The legacy "num-cs" property indicates the number of CS on the only 230993db446aSBoris Brezillon * chip connected to the controller (legacy bindings does not support 2310f6997becSMiquel Raynal * more than one chip). The CS and RB pins are always the #0. 231193db446aSBoris Brezillon * 231293db446aSBoris Brezillon * When not using legacy bindings, a couple of "reg" and "nand-rb" 231393db446aSBoris Brezillon * properties must be filled. For each chip, expressed as a subnode, 231493db446aSBoris Brezillon * "reg" points to the CS lines and "nand-rb" to the RB line. 231593db446aSBoris Brezillon */ 2316f6997becSMiquel Raynal if (pdata || nfc->caps->legacy_of_bindings) { 231793db446aSBoris Brezillon nsels = 1; 2318f6997becSMiquel Raynal } else { 2319f6997becSMiquel Raynal nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32)); 2320f6997becSMiquel Raynal if (nsels <= 0) { 2321f6997becSMiquel Raynal dev_err(dev, "missing/invalid reg property\n"); 232293db446aSBoris Brezillon return -EINVAL; 232393db446aSBoris Brezillon } 232493db446aSBoris Brezillon } 232593db446aSBoris Brezillon 232693db446aSBoris Brezillon /* Alloc the nand chip structure */ 232793db446aSBoris Brezillon marvell_nand = devm_kzalloc(dev, sizeof(*marvell_nand) + 232893db446aSBoris Brezillon (nsels * 232993db446aSBoris Brezillon sizeof(struct marvell_nand_chip_sel)), 233093db446aSBoris Brezillon GFP_KERNEL); 233193db446aSBoris Brezillon if (!marvell_nand) { 233293db446aSBoris Brezillon dev_err(dev, "could not allocate chip structure\n"); 233393db446aSBoris Brezillon return -ENOMEM; 233493db446aSBoris Brezillon } 233593db446aSBoris Brezillon 233693db446aSBoris Brezillon marvell_nand->nsels = nsels; 233793db446aSBoris Brezillon marvell_nand->selected_die = -1; 233893db446aSBoris Brezillon 233993db446aSBoris Brezillon for (i = 0; i < nsels; i++) { 234093db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) { 234193db446aSBoris Brezillon /* 234293db446aSBoris Brezillon * Legacy bindings use the CS lines in natural 234393db446aSBoris Brezillon * order (0, 1, ...) 234493db446aSBoris Brezillon */ 234593db446aSBoris Brezillon cs = i; 234693db446aSBoris Brezillon } else { 234793db446aSBoris Brezillon /* Retrieve CS id */ 234893db446aSBoris Brezillon ret = of_property_read_u32_index(np, "reg", i, &cs); 234993db446aSBoris Brezillon if (ret) { 235093db446aSBoris Brezillon dev_err(dev, "could not retrieve reg property: %d\n", 235193db446aSBoris Brezillon ret); 235293db446aSBoris Brezillon return ret; 235393db446aSBoris Brezillon } 235493db446aSBoris Brezillon } 235593db446aSBoris Brezillon 235693db446aSBoris Brezillon if (cs >= nfc->caps->max_cs_nb) { 235793db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max CS = %d)\n", 235893db446aSBoris Brezillon cs, nfc->caps->max_cs_nb); 235993db446aSBoris Brezillon return -EINVAL; 236093db446aSBoris Brezillon } 236193db446aSBoris Brezillon 236293db446aSBoris Brezillon if (test_and_set_bit(cs, &nfc->assigned_cs)) { 236393db446aSBoris Brezillon dev_err(dev, "CS %d already assigned\n", cs); 236493db446aSBoris Brezillon return -EINVAL; 236593db446aSBoris Brezillon } 236693db446aSBoris Brezillon 236793db446aSBoris Brezillon /* 236893db446aSBoris Brezillon * The cs variable represents the chip select id, which must be 236993db446aSBoris Brezillon * converted in bit fields for NDCB0 and NDCB2 to select the 237093db446aSBoris Brezillon * right chip. Unfortunately, due to a lack of information on 237193db446aSBoris Brezillon * the subject and incoherent documentation, the user should not 237293db446aSBoris Brezillon * use CS1 and CS3 at all as asserting them is not supported in 237393db446aSBoris Brezillon * a reliable way (due to multiplexing inside ADDR5 field). 237493db446aSBoris Brezillon */ 237593db446aSBoris Brezillon marvell_nand->sels[i].cs = cs; 237693db446aSBoris Brezillon switch (cs) { 237793db446aSBoris Brezillon case 0: 237893db446aSBoris Brezillon case 2: 237993db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = 0; 238093db446aSBoris Brezillon break; 238193db446aSBoris Brezillon case 1: 238293db446aSBoris Brezillon case 3: 238393db446aSBoris Brezillon marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL; 238493db446aSBoris Brezillon break; 238593db446aSBoris Brezillon default: 238693db446aSBoris Brezillon return -EINVAL; 238793db446aSBoris Brezillon } 238893db446aSBoris Brezillon 238993db446aSBoris Brezillon /* Retrieve RB id */ 239093db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) { 239193db446aSBoris Brezillon /* Legacy bindings always use RB #0 */ 239293db446aSBoris Brezillon rb = 0; 239393db446aSBoris Brezillon } else { 239493db446aSBoris Brezillon ret = of_property_read_u32_index(np, "nand-rb", i, 239593db446aSBoris Brezillon &rb); 239693db446aSBoris Brezillon if (ret) { 239793db446aSBoris Brezillon dev_err(dev, 239893db446aSBoris Brezillon "could not retrieve RB property: %d\n", 239993db446aSBoris Brezillon ret); 240093db446aSBoris Brezillon return ret; 240193db446aSBoris Brezillon } 240293db446aSBoris Brezillon } 240393db446aSBoris Brezillon 240493db446aSBoris Brezillon if (rb >= nfc->caps->max_rb_nb) { 240593db446aSBoris Brezillon dev_err(dev, "invalid reg value: %u (max RB = %d)\n", 240693db446aSBoris Brezillon rb, nfc->caps->max_rb_nb); 240793db446aSBoris Brezillon return -EINVAL; 240893db446aSBoris Brezillon } 240993db446aSBoris Brezillon 241093db446aSBoris Brezillon marvell_nand->sels[i].rb = rb; 241193db446aSBoris Brezillon } 241293db446aSBoris Brezillon 241393db446aSBoris Brezillon chip = &marvell_nand->chip; 241493db446aSBoris Brezillon chip->controller = &nfc->controller; 241593db446aSBoris Brezillon nand_set_flash_node(chip, np); 241693db446aSBoris Brezillon 241793db446aSBoris Brezillon chip->exec_op = marvell_nfc_exec_op; 241893db446aSBoris Brezillon chip->select_chip = marvell_nfc_select_chip; 241993db446aSBoris Brezillon if (!of_property_read_bool(np, "marvell,nand-keep-config")) 242093db446aSBoris Brezillon chip->setup_data_interface = marvell_nfc_setup_data_interface; 242193db446aSBoris Brezillon 242293db446aSBoris Brezillon mtd = nand_to_mtd(chip); 242393db446aSBoris Brezillon mtd->dev.parent = dev; 242493db446aSBoris Brezillon 242593db446aSBoris Brezillon /* 242693db446aSBoris Brezillon * Default to HW ECC engine mode. If the nand-ecc-mode property is given 242793db446aSBoris Brezillon * in the DT node, this entry will be overwritten in nand_scan_ident(). 242893db446aSBoris Brezillon */ 242993db446aSBoris Brezillon chip->ecc.mode = NAND_ECC_HW; 243093db446aSBoris Brezillon 243193db446aSBoris Brezillon /* 243293db446aSBoris Brezillon * Save a reference value for timing registers before 243393db446aSBoris Brezillon * ->setup_data_interface() is called. 243493db446aSBoris Brezillon */ 243593db446aSBoris Brezillon marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0); 243693db446aSBoris Brezillon marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); 243793db446aSBoris Brezillon 243893db446aSBoris Brezillon chip->options |= NAND_BUSWIDTH_AUTO; 243993db446aSBoris Brezillon ret = nand_scan_ident(mtd, marvell_nand->nsels, NULL); 244093db446aSBoris Brezillon if (ret) { 244193db446aSBoris Brezillon dev_err(dev, "could not identify the nand chip\n"); 244293db446aSBoris Brezillon return ret; 244393db446aSBoris Brezillon } 244493db446aSBoris Brezillon 244593db446aSBoris Brezillon if (pdata && pdata->flash_bbt) 244693db446aSBoris Brezillon chip->bbt_options |= NAND_BBT_USE_FLASH; 244793db446aSBoris Brezillon 244893db446aSBoris Brezillon if (chip->bbt_options & NAND_BBT_USE_FLASH) { 244993db446aSBoris Brezillon /* 245093db446aSBoris Brezillon * We'll use a bad block table stored in-flash and don't 245193db446aSBoris Brezillon * allow writing the bad block marker to the flash. 245293db446aSBoris Brezillon */ 245393db446aSBoris Brezillon chip->bbt_options |= NAND_BBT_NO_OOB_BBM; 245493db446aSBoris Brezillon chip->bbt_td = &bbt_main_descr; 245593db446aSBoris Brezillon chip->bbt_md = &bbt_mirror_descr; 245693db446aSBoris Brezillon } 245793db446aSBoris Brezillon 245893db446aSBoris Brezillon /* Save the chip-specific fields of NDCR */ 245993db446aSBoris Brezillon marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize); 246093db446aSBoris Brezillon if (chip->options & NAND_BUSWIDTH_16) 246193db446aSBoris Brezillon marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; 246293db446aSBoris Brezillon 246393db446aSBoris Brezillon /* 246493db446aSBoris Brezillon * On small page NANDs, only one cycle is needed to pass the 246593db446aSBoris Brezillon * column address. 246693db446aSBoris Brezillon */ 246793db446aSBoris Brezillon if (mtd->writesize <= 512) { 246893db446aSBoris Brezillon marvell_nand->addr_cyc = 1; 246993db446aSBoris Brezillon } else { 247093db446aSBoris Brezillon marvell_nand->addr_cyc = 2; 247193db446aSBoris Brezillon marvell_nand->ndcr |= NDCR_RA_START; 247293db446aSBoris Brezillon } 247393db446aSBoris Brezillon 247493db446aSBoris Brezillon /* 247593db446aSBoris Brezillon * Now add the number of cycles needed to pass the row 247693db446aSBoris Brezillon * address. 247793db446aSBoris Brezillon * 247893db446aSBoris Brezillon * Addressing a chip using CS 2 or 3 should also need the third row 247993db446aSBoris Brezillon * cycle but due to inconsistance in the documentation and lack of 248093db446aSBoris Brezillon * hardware to test this situation, this case is not supported. 248193db446aSBoris Brezillon */ 248293db446aSBoris Brezillon if (chip->options & NAND_ROW_ADDR_3) 248393db446aSBoris Brezillon marvell_nand->addr_cyc += 3; 248493db446aSBoris Brezillon else 248593db446aSBoris Brezillon marvell_nand->addr_cyc += 2; 248693db446aSBoris Brezillon 248793db446aSBoris Brezillon if (pdata) { 248893db446aSBoris Brezillon chip->ecc.size = pdata->ecc_step_size; 248993db446aSBoris Brezillon chip->ecc.strength = pdata->ecc_strength; 249093db446aSBoris Brezillon } 249193db446aSBoris Brezillon 249293db446aSBoris Brezillon ret = marvell_nand_ecc_init(mtd, &chip->ecc); 249393db446aSBoris Brezillon if (ret) { 249493db446aSBoris Brezillon dev_err(dev, "ECC init failed: %d\n", ret); 249593db446aSBoris Brezillon return ret; 249693db446aSBoris Brezillon } 249793db446aSBoris Brezillon 249893db446aSBoris Brezillon if (chip->ecc.mode == NAND_ECC_HW) { 249993db446aSBoris Brezillon /* 250093db446aSBoris Brezillon * Subpage write not available with hardware ECC, prohibit also 250193db446aSBoris Brezillon * subpage read as in userspace subpage access would still be 250293db446aSBoris Brezillon * allowed and subpage write, if used, would lead to numerous 250393db446aSBoris Brezillon * uncorrectable ECC errors. 250493db446aSBoris Brezillon */ 250593db446aSBoris Brezillon chip->options |= NAND_NO_SUBPAGE_WRITE; 250693db446aSBoris Brezillon } 250793db446aSBoris Brezillon 250893db446aSBoris Brezillon if (pdata || nfc->caps->legacy_of_bindings) { 250993db446aSBoris Brezillon /* 251093db446aSBoris Brezillon * We keep the MTD name unchanged to avoid breaking platforms 251193db446aSBoris Brezillon * where the MTD cmdline parser is used and the bootloader 251293db446aSBoris Brezillon * has not been updated to use the new naming scheme. 251393db446aSBoris Brezillon */ 251493db446aSBoris Brezillon mtd->name = "pxa3xx_nand-0"; 251593db446aSBoris Brezillon } else if (!mtd->name) { 251693db446aSBoris Brezillon /* 251793db446aSBoris Brezillon * If the new bindings are used and the bootloader has not been 251893db446aSBoris Brezillon * updated to pass a new mtdparts parameter on the cmdline, you 251993db446aSBoris Brezillon * should define the following property in your NAND node, ie: 252093db446aSBoris Brezillon * 252193db446aSBoris Brezillon * label = "main-storage"; 252293db446aSBoris Brezillon * 252393db446aSBoris Brezillon * This way, mtd->name will be set by the core when 252493db446aSBoris Brezillon * nand_set_flash_node() is called. 252593db446aSBoris Brezillon */ 252693db446aSBoris Brezillon mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, 252793db446aSBoris Brezillon "%s:nand.%d", dev_name(nfc->dev), 252893db446aSBoris Brezillon marvell_nand->sels[0].cs); 252993db446aSBoris Brezillon if (!mtd->name) { 253093db446aSBoris Brezillon dev_err(nfc->dev, "Failed to allocate mtd->name\n"); 253193db446aSBoris Brezillon return -ENOMEM; 253293db446aSBoris Brezillon } 253393db446aSBoris Brezillon } 253493db446aSBoris Brezillon 253593db446aSBoris Brezillon ret = nand_scan_tail(mtd); 253693db446aSBoris Brezillon if (ret) { 253793db446aSBoris Brezillon dev_err(dev, "nand_scan_tail failed: %d\n", ret); 253893db446aSBoris Brezillon return ret; 253993db446aSBoris Brezillon } 254093db446aSBoris Brezillon 254193db446aSBoris Brezillon if (pdata) 254293db446aSBoris Brezillon /* Legacy bindings support only one chip */ 25433383fb35SBoris Brezillon ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); 254493db446aSBoris Brezillon else 254593db446aSBoris Brezillon ret = mtd_device_register(mtd, NULL, 0); 254693db446aSBoris Brezillon if (ret) { 254793db446aSBoris Brezillon dev_err(dev, "failed to register mtd device: %d\n", ret); 254893db446aSBoris Brezillon nand_release(mtd); 254993db446aSBoris Brezillon return ret; 255093db446aSBoris Brezillon } 255193db446aSBoris Brezillon 255293db446aSBoris Brezillon list_add_tail(&marvell_nand->node, &nfc->chips); 255393db446aSBoris Brezillon 255493db446aSBoris Brezillon return 0; 255593db446aSBoris Brezillon } 255693db446aSBoris Brezillon 255793db446aSBoris Brezillon static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc) 255893db446aSBoris Brezillon { 255993db446aSBoris Brezillon struct device_node *np = dev->of_node; 256093db446aSBoris Brezillon struct device_node *nand_np; 256193db446aSBoris Brezillon int max_cs = nfc->caps->max_cs_nb; 256293db446aSBoris Brezillon int nchips; 256393db446aSBoris Brezillon int ret; 256493db446aSBoris Brezillon 256593db446aSBoris Brezillon if (!np) 256693db446aSBoris Brezillon nchips = 1; 256793db446aSBoris Brezillon else 256893db446aSBoris Brezillon nchips = of_get_child_count(np); 256993db446aSBoris Brezillon 257093db446aSBoris Brezillon if (nchips > max_cs) { 257193db446aSBoris Brezillon dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips, 257293db446aSBoris Brezillon max_cs); 257393db446aSBoris Brezillon return -EINVAL; 257493db446aSBoris Brezillon } 257593db446aSBoris Brezillon 257693db446aSBoris Brezillon /* 257793db446aSBoris Brezillon * Legacy bindings do not use child nodes to exhibit NAND chip 257893db446aSBoris Brezillon * properties and layout. Instead, NAND properties are mixed with the 257993db446aSBoris Brezillon * controller ones, and partitions are defined as direct subnodes of the 258093db446aSBoris Brezillon * NAND controller node. 258193db446aSBoris Brezillon */ 258293db446aSBoris Brezillon if (nfc->caps->legacy_of_bindings) { 258393db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, np); 258493db446aSBoris Brezillon return ret; 258593db446aSBoris Brezillon } 258693db446aSBoris Brezillon 258793db446aSBoris Brezillon for_each_child_of_node(np, nand_np) { 258893db446aSBoris Brezillon ret = marvell_nand_chip_init(dev, nfc, nand_np); 258993db446aSBoris Brezillon if (ret) { 259093db446aSBoris Brezillon of_node_put(nand_np); 259193db446aSBoris Brezillon return ret; 259293db446aSBoris Brezillon } 259393db446aSBoris Brezillon } 259493db446aSBoris Brezillon 259593db446aSBoris Brezillon return 0; 259693db446aSBoris Brezillon } 259793db446aSBoris Brezillon 259893db446aSBoris Brezillon static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc) 259993db446aSBoris Brezillon { 260093db446aSBoris Brezillon struct marvell_nand_chip *entry, *temp; 260193db446aSBoris Brezillon 260293db446aSBoris Brezillon list_for_each_entry_safe(entry, temp, &nfc->chips, node) { 260393db446aSBoris Brezillon nand_release(nand_to_mtd(&entry->chip)); 260493db446aSBoris Brezillon list_del(&entry->node); 260593db446aSBoris Brezillon } 260693db446aSBoris Brezillon } 260793db446aSBoris Brezillon 260893db446aSBoris Brezillon static int marvell_nfc_init_dma(struct marvell_nfc *nfc) 260993db446aSBoris Brezillon { 261093db446aSBoris Brezillon struct platform_device *pdev = container_of(nfc->dev, 261193db446aSBoris Brezillon struct platform_device, 261293db446aSBoris Brezillon dev); 261393db446aSBoris Brezillon struct dma_slave_config config = {}; 261493db446aSBoris Brezillon struct resource *r; 261593db446aSBoris Brezillon dma_cap_mask_t mask; 261693db446aSBoris Brezillon struct pxad_param param; 261793db446aSBoris Brezillon int ret; 261893db446aSBoris Brezillon 261993db446aSBoris Brezillon if (!IS_ENABLED(CONFIG_PXA_DMA)) { 262093db446aSBoris Brezillon dev_warn(nfc->dev, 262193db446aSBoris Brezillon "DMA not enabled in configuration\n"); 262293db446aSBoris Brezillon return -ENOTSUPP; 262393db446aSBoris Brezillon } 262493db446aSBoris Brezillon 262593db446aSBoris Brezillon ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32)); 262693db446aSBoris Brezillon if (ret) 262793db446aSBoris Brezillon return ret; 262893db446aSBoris Brezillon 262993db446aSBoris Brezillon r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 263093db446aSBoris Brezillon if (!r) { 263193db446aSBoris Brezillon dev_err(nfc->dev, "No resource defined for data DMA\n"); 263293db446aSBoris Brezillon return -ENXIO; 263393db446aSBoris Brezillon } 263493db446aSBoris Brezillon 263593db446aSBoris Brezillon param.drcmr = r->start; 263693db446aSBoris Brezillon param.prio = PXAD_PRIO_LOWEST; 263793db446aSBoris Brezillon dma_cap_zero(mask); 263893db446aSBoris Brezillon dma_cap_set(DMA_SLAVE, mask); 263993db446aSBoris Brezillon nfc->dma_chan = 264093db446aSBoris Brezillon dma_request_slave_channel_compat(mask, pxad_filter_fn, 264193db446aSBoris Brezillon ¶m, nfc->dev, 264293db446aSBoris Brezillon "data"); 264393db446aSBoris Brezillon if (!nfc->dma_chan) { 264493db446aSBoris Brezillon dev_err(nfc->dev, 264593db446aSBoris Brezillon "Unable to request data DMA channel\n"); 264693db446aSBoris Brezillon return -ENODEV; 264793db446aSBoris Brezillon } 264893db446aSBoris Brezillon 264993db446aSBoris Brezillon r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 265093db446aSBoris Brezillon if (!r) 265193db446aSBoris Brezillon return -ENXIO; 265293db446aSBoris Brezillon 265393db446aSBoris Brezillon config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 265493db446aSBoris Brezillon config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 265593db446aSBoris Brezillon config.src_addr = r->start + NDDB; 265693db446aSBoris Brezillon config.dst_addr = r->start + NDDB; 265793db446aSBoris Brezillon config.src_maxburst = 32; 265893db446aSBoris Brezillon config.dst_maxburst = 32; 265993db446aSBoris Brezillon ret = dmaengine_slave_config(nfc->dma_chan, &config); 266093db446aSBoris Brezillon if (ret < 0) { 266193db446aSBoris Brezillon dev_err(nfc->dev, "Failed to configure DMA channel\n"); 266293db446aSBoris Brezillon return ret; 266393db446aSBoris Brezillon } 266493db446aSBoris Brezillon 266593db446aSBoris Brezillon /* 266693db446aSBoris Brezillon * DMA must act on length multiple of 32 and this length may be 266793db446aSBoris Brezillon * bigger than the destination buffer. Use this buffer instead 266893db446aSBoris Brezillon * for DMA transfers and then copy the desired amount of data to 266993db446aSBoris Brezillon * the provided buffer. 267093db446aSBoris Brezillon */ 267193db446aSBoris Brezillon nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); 267293db446aSBoris Brezillon if (!nfc->dma_buf) 267393db446aSBoris Brezillon return -ENOMEM; 267493db446aSBoris Brezillon 267593db446aSBoris Brezillon nfc->use_dma = true; 267693db446aSBoris Brezillon 267793db446aSBoris Brezillon return 0; 267893db446aSBoris Brezillon } 267993db446aSBoris Brezillon 268093db446aSBoris Brezillon static int marvell_nfc_init(struct marvell_nfc *nfc) 268193db446aSBoris Brezillon { 268293db446aSBoris Brezillon struct device_node *np = nfc->dev->of_node; 268393db446aSBoris Brezillon 268493db446aSBoris Brezillon /* 268593db446aSBoris Brezillon * Some SoCs like A7k/A8k need to enable manually the NAND 268693db446aSBoris Brezillon * controller, gated clocks and reset bits to avoid being bootloader 268793db446aSBoris Brezillon * dependent. This is done through the use of the System Functions 268893db446aSBoris Brezillon * registers. 268993db446aSBoris Brezillon */ 269093db446aSBoris Brezillon if (nfc->caps->need_system_controller) { 269193db446aSBoris Brezillon struct regmap *sysctrl_base = 269293db446aSBoris Brezillon syscon_regmap_lookup_by_phandle(np, 269393db446aSBoris Brezillon "marvell,system-controller"); 269493db446aSBoris Brezillon u32 reg; 269593db446aSBoris Brezillon 269693db446aSBoris Brezillon if (IS_ERR(sysctrl_base)) 269793db446aSBoris Brezillon return PTR_ERR(sysctrl_base); 269893db446aSBoris Brezillon 269993db446aSBoris Brezillon reg = GENCONF_SOC_DEVICE_MUX_NFC_EN | 270093db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST | 270193db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST | 270293db446aSBoris Brezillon GENCONF_SOC_DEVICE_MUX_NFC_INT_EN; 270393db446aSBoris Brezillon regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg); 270493db446aSBoris Brezillon 270593db446aSBoris Brezillon regmap_read(sysctrl_base, GENCONF_CLK_GATING_CTRL, ®); 270693db446aSBoris Brezillon reg |= GENCONF_CLK_GATING_CTRL_ND_GATE; 270793db446aSBoris Brezillon regmap_write(sysctrl_base, GENCONF_CLK_GATING_CTRL, reg); 270893db446aSBoris Brezillon 270993db446aSBoris Brezillon regmap_read(sysctrl_base, GENCONF_ND_CLK_CTRL, ®); 271093db446aSBoris Brezillon reg |= GENCONF_ND_CLK_CTRL_EN; 271193db446aSBoris Brezillon regmap_write(sysctrl_base, GENCONF_ND_CLK_CTRL, reg); 271293db446aSBoris Brezillon } 271393db446aSBoris Brezillon 271493db446aSBoris Brezillon /* Configure the DMA if appropriate */ 271593db446aSBoris Brezillon if (!nfc->caps->is_nfcv2) 271693db446aSBoris Brezillon marvell_nfc_init_dma(nfc); 271793db446aSBoris Brezillon 271893db446aSBoris Brezillon /* 271993db446aSBoris Brezillon * ECC operations and interruptions are only enabled when specifically 272093db446aSBoris Brezillon * needed. ECC shall not be activated in the early stages (fails probe). 272193db446aSBoris Brezillon * Arbiter flag, even if marked as "reserved", must be set (empirical). 272293db446aSBoris Brezillon * SPARE_EN bit must always be set or ECC bytes will not be at the same 272393db446aSBoris Brezillon * offset in the read page and this will fail the protection. 272493db446aSBoris Brezillon */ 272593db446aSBoris Brezillon writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN | 272693db446aSBoris Brezillon NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR); 272793db446aSBoris Brezillon writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR); 272893db446aSBoris Brezillon writel_relaxed(0, nfc->regs + NDECCCTRL); 272993db446aSBoris Brezillon 273093db446aSBoris Brezillon return 0; 273193db446aSBoris Brezillon } 273293db446aSBoris Brezillon 273393db446aSBoris Brezillon static int marvell_nfc_probe(struct platform_device *pdev) 273493db446aSBoris Brezillon { 273593db446aSBoris Brezillon struct device *dev = &pdev->dev; 273693db446aSBoris Brezillon struct resource *r; 273793db446aSBoris Brezillon struct marvell_nfc *nfc; 273893db446aSBoris Brezillon int ret; 273993db446aSBoris Brezillon int irq; 274093db446aSBoris Brezillon 274193db446aSBoris Brezillon nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc), 274293db446aSBoris Brezillon GFP_KERNEL); 274393db446aSBoris Brezillon if (!nfc) 274493db446aSBoris Brezillon return -ENOMEM; 274593db446aSBoris Brezillon 274693db446aSBoris Brezillon nfc->dev = dev; 274793db446aSBoris Brezillon nand_hw_control_init(&nfc->controller); 274893db446aSBoris Brezillon INIT_LIST_HEAD(&nfc->chips); 274993db446aSBoris Brezillon 275093db446aSBoris Brezillon r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 275193db446aSBoris Brezillon nfc->regs = devm_ioremap_resource(dev, r); 275293db446aSBoris Brezillon if (IS_ERR(nfc->regs)) 275393db446aSBoris Brezillon return PTR_ERR(nfc->regs); 275493db446aSBoris Brezillon 275593db446aSBoris Brezillon irq = platform_get_irq(pdev, 0); 275693db446aSBoris Brezillon if (irq < 0) { 275793db446aSBoris Brezillon dev_err(dev, "failed to retrieve irq\n"); 275893db446aSBoris Brezillon return irq; 275993db446aSBoris Brezillon } 276093db446aSBoris Brezillon 27616b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, "core"); 2762961ba15cSGregory CLEMENT 2763961ba15cSGregory CLEMENT /* Managed the legacy case (when the first clock was not named) */ 27646b6de654SBoris Brezillon if (nfc->core_clk == ERR_PTR(-ENOENT)) 27656b6de654SBoris Brezillon nfc->core_clk = devm_clk_get(&pdev->dev, NULL); 2766961ba15cSGregory CLEMENT 27676b6de654SBoris Brezillon if (IS_ERR(nfc->core_clk)) 27686b6de654SBoris Brezillon return PTR_ERR(nfc->core_clk); 276993db446aSBoris Brezillon 27706b6de654SBoris Brezillon ret = clk_prepare_enable(nfc->core_clk); 277193db446aSBoris Brezillon if (ret) 277293db446aSBoris Brezillon return ret; 277393db446aSBoris Brezillon 2774961ba15cSGregory CLEMENT nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); 2775961ba15cSGregory CLEMENT if (PTR_ERR(nfc->reg_clk) != -ENOENT) { 2776961ba15cSGregory CLEMENT if (!IS_ERR(nfc->reg_clk)) { 2777961ba15cSGregory CLEMENT ret = clk_prepare_enable(nfc->reg_clk); 2778961ba15cSGregory CLEMENT if (ret) 27796b6de654SBoris Brezillon goto unprepare_core_clk; 2780961ba15cSGregory CLEMENT } else { 2781961ba15cSGregory CLEMENT ret = PTR_ERR(nfc->reg_clk); 27826b6de654SBoris Brezillon goto unprepare_core_clk; 2783961ba15cSGregory CLEMENT } 2784961ba15cSGregory CLEMENT } 2785961ba15cSGregory CLEMENT 278693db446aSBoris Brezillon marvell_nfc_disable_int(nfc, NDCR_ALL_INT); 278793db446aSBoris Brezillon marvell_nfc_clear_int(nfc, NDCR_ALL_INT); 278893db446aSBoris Brezillon ret = devm_request_irq(dev, irq, marvell_nfc_isr, 278993db446aSBoris Brezillon 0, "marvell-nfc", nfc); 279093db446aSBoris Brezillon if (ret) 2791961ba15cSGregory CLEMENT goto unprepare_reg_clk; 279293db446aSBoris Brezillon 279393db446aSBoris Brezillon /* Get NAND controller capabilities */ 279493db446aSBoris Brezillon if (pdev->id_entry) 279593db446aSBoris Brezillon nfc->caps = (void *)pdev->id_entry->driver_data; 279693db446aSBoris Brezillon else 279793db446aSBoris Brezillon nfc->caps = of_device_get_match_data(&pdev->dev); 279893db446aSBoris Brezillon 279993db446aSBoris Brezillon if (!nfc->caps) { 280093db446aSBoris Brezillon dev_err(dev, "Could not retrieve NFC caps\n"); 280193db446aSBoris Brezillon ret = -EINVAL; 2802961ba15cSGregory CLEMENT goto unprepare_reg_clk; 280393db446aSBoris Brezillon } 280493db446aSBoris Brezillon 280593db446aSBoris Brezillon /* Init the controller and then probe the chips */ 280693db446aSBoris Brezillon ret = marvell_nfc_init(nfc); 280793db446aSBoris Brezillon if (ret) 2808961ba15cSGregory CLEMENT goto unprepare_reg_clk; 280993db446aSBoris Brezillon 281093db446aSBoris Brezillon platform_set_drvdata(pdev, nfc); 281193db446aSBoris Brezillon 281293db446aSBoris Brezillon ret = marvell_nand_chips_init(dev, nfc); 281393db446aSBoris Brezillon if (ret) 2814961ba15cSGregory CLEMENT goto unprepare_reg_clk; 281593db446aSBoris Brezillon 281693db446aSBoris Brezillon return 0; 281793db446aSBoris Brezillon 2818961ba15cSGregory CLEMENT unprepare_reg_clk: 2819961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk); 28206b6de654SBoris Brezillon unprepare_core_clk: 28216b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk); 282293db446aSBoris Brezillon 282393db446aSBoris Brezillon return ret; 282493db446aSBoris Brezillon } 282593db446aSBoris Brezillon 282693db446aSBoris Brezillon static int marvell_nfc_remove(struct platform_device *pdev) 282793db446aSBoris Brezillon { 282893db446aSBoris Brezillon struct marvell_nfc *nfc = platform_get_drvdata(pdev); 282993db446aSBoris Brezillon 283093db446aSBoris Brezillon marvell_nand_chips_cleanup(nfc); 283193db446aSBoris Brezillon 283293db446aSBoris Brezillon if (nfc->use_dma) { 283393db446aSBoris Brezillon dmaengine_terminate_all(nfc->dma_chan); 283493db446aSBoris Brezillon dma_release_channel(nfc->dma_chan); 283593db446aSBoris Brezillon } 283693db446aSBoris Brezillon 2837961ba15cSGregory CLEMENT clk_disable_unprepare(nfc->reg_clk); 28386b6de654SBoris Brezillon clk_disable_unprepare(nfc->core_clk); 283993db446aSBoris Brezillon 284093db446aSBoris Brezillon return 0; 284193db446aSBoris Brezillon } 284293db446aSBoris Brezillon 284393db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { 284493db446aSBoris Brezillon .max_cs_nb = 4, 284593db446aSBoris Brezillon .max_rb_nb = 2, 284693db446aSBoris Brezillon .need_system_controller = true, 284793db446aSBoris Brezillon .is_nfcv2 = true, 284893db446aSBoris Brezillon }; 284993db446aSBoris Brezillon 285093db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { 285193db446aSBoris Brezillon .max_cs_nb = 4, 285293db446aSBoris Brezillon .max_rb_nb = 2, 285393db446aSBoris Brezillon .is_nfcv2 = true, 285493db446aSBoris Brezillon }; 285593db446aSBoris Brezillon 285693db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = { 285793db446aSBoris Brezillon .max_cs_nb = 2, 285893db446aSBoris Brezillon .max_rb_nb = 1, 285993db446aSBoris Brezillon .use_dma = true, 286093db446aSBoris Brezillon }; 286193db446aSBoris Brezillon 286293db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = { 286393db446aSBoris Brezillon .max_cs_nb = 4, 286493db446aSBoris Brezillon .max_rb_nb = 2, 286593db446aSBoris Brezillon .need_system_controller = true, 286693db446aSBoris Brezillon .legacy_of_bindings = true, 286793db446aSBoris Brezillon .is_nfcv2 = true, 286893db446aSBoris Brezillon }; 286993db446aSBoris Brezillon 287093db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = { 287193db446aSBoris Brezillon .max_cs_nb = 4, 287293db446aSBoris Brezillon .max_rb_nb = 2, 287393db446aSBoris Brezillon .legacy_of_bindings = true, 287493db446aSBoris Brezillon .is_nfcv2 = true, 287593db446aSBoris Brezillon }; 287693db446aSBoris Brezillon 287793db446aSBoris Brezillon static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = { 287893db446aSBoris Brezillon .max_cs_nb = 2, 287993db446aSBoris Brezillon .max_rb_nb = 1, 288093db446aSBoris Brezillon .legacy_of_bindings = true, 288193db446aSBoris Brezillon .use_dma = true, 288293db446aSBoris Brezillon }; 288393db446aSBoris Brezillon 288493db446aSBoris Brezillon static const struct platform_device_id marvell_nfc_platform_ids[] = { 288593db446aSBoris Brezillon { 288693db446aSBoris Brezillon .name = "pxa3xx-nand", 288793db446aSBoris Brezillon .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps, 288893db446aSBoris Brezillon }, 288993db446aSBoris Brezillon { /* sentinel */ }, 289093db446aSBoris Brezillon }; 289193db446aSBoris Brezillon MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids); 289293db446aSBoris Brezillon 289393db446aSBoris Brezillon static const struct of_device_id marvell_nfc_of_ids[] = { 289493db446aSBoris Brezillon { 289593db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand-controller", 289693db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_caps, 289793db446aSBoris Brezillon }, 289893db446aSBoris Brezillon { 289993db446aSBoris Brezillon .compatible = "marvell,armada370-nand-controller", 290093db446aSBoris Brezillon .data = &marvell_armada370_nfc_caps, 290193db446aSBoris Brezillon }, 290293db446aSBoris Brezillon { 290393db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand-controller", 290493db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_caps, 290593db446aSBoris Brezillon }, 290693db446aSBoris Brezillon /* Support for old/deprecated bindings: */ 290793db446aSBoris Brezillon { 290893db446aSBoris Brezillon .compatible = "marvell,armada-8k-nand", 290993db446aSBoris Brezillon .data = &marvell_armada_8k_nfc_legacy_caps, 291093db446aSBoris Brezillon }, 291193db446aSBoris Brezillon { 291293db446aSBoris Brezillon .compatible = "marvell,armada370-nand", 291393db446aSBoris Brezillon .data = &marvell_armada370_nfc_legacy_caps, 291493db446aSBoris Brezillon }, 291593db446aSBoris Brezillon { 291693db446aSBoris Brezillon .compatible = "marvell,pxa3xx-nand", 291793db446aSBoris Brezillon .data = &marvell_pxa3xx_nfc_legacy_caps, 291893db446aSBoris Brezillon }, 291993db446aSBoris Brezillon { /* sentinel */ }, 292093db446aSBoris Brezillon }; 292193db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids); 292293db446aSBoris Brezillon 292393db446aSBoris Brezillon static struct platform_driver marvell_nfc_driver = { 292493db446aSBoris Brezillon .driver = { 292593db446aSBoris Brezillon .name = "marvell-nfc", 292693db446aSBoris Brezillon .of_match_table = marvell_nfc_of_ids, 292793db446aSBoris Brezillon }, 292893db446aSBoris Brezillon .id_table = marvell_nfc_platform_ids, 292993db446aSBoris Brezillon .probe = marvell_nfc_probe, 293093db446aSBoris Brezillon .remove = marvell_nfc_remove, 293193db446aSBoris Brezillon }; 293293db446aSBoris Brezillon module_platform_driver(marvell_nfc_driver); 293393db446aSBoris Brezillon 293493db446aSBoris Brezillon MODULE_LICENSE("GPL"); 293593db446aSBoris Brezillon MODULE_DESCRIPTION("Marvell NAND controller driver"); 2936