1 /* 2 * NXP LPC32XX NAND SLC driver 3 * 4 * Authors: 5 * Kevin Wells <kevin.wells@nxp.com> 6 * Roland Stigge <stigge@antcom.de> 7 * 8 * Copyright © 2011 NXP Semiconductors 9 * Copyright © 2012 Roland Stigge 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/mtd/mtd.h> 26 #include <linux/mtd/rawnand.h> 27 #include <linux/mtd/partitions.h> 28 #include <linux/clk.h> 29 #include <linux/err.h> 30 #include <linux/delay.h> 31 #include <linux/io.h> 32 #include <linux/mm.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/dmaengine.h> 35 #include <linux/mtd/nand_ecc.h> 36 #include <linux/gpio.h> 37 #include <linux/of.h> 38 #include <linux/of_gpio.h> 39 #include <linux/mtd/lpc32xx_slc.h> 40 41 #define LPC32XX_MODNAME "lpc32xx-nand" 42 43 /********************************************************************** 44 * SLC NAND controller register offsets 45 **********************************************************************/ 46 47 #define SLC_DATA(x) (x + 0x000) 48 #define SLC_ADDR(x) (x + 0x004) 49 #define SLC_CMD(x) (x + 0x008) 50 #define SLC_STOP(x) (x + 0x00C) 51 #define SLC_CTRL(x) (x + 0x010) 52 #define SLC_CFG(x) (x + 0x014) 53 #define SLC_STAT(x) (x + 0x018) 54 #define SLC_INT_STAT(x) (x + 0x01C) 55 #define SLC_IEN(x) (x + 0x020) 56 #define SLC_ISR(x) (x + 0x024) 57 #define SLC_ICR(x) (x + 0x028) 58 #define SLC_TAC(x) (x + 0x02C) 59 #define SLC_TC(x) (x + 0x030) 60 #define SLC_ECC(x) (x + 0x034) 61 #define SLC_DMA_DATA(x) (x + 0x038) 62 63 /********************************************************************** 64 * slc_ctrl register definitions 65 **********************************************************************/ 66 #define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */ 67 #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ 68 #define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */ 69 70 /********************************************************************** 71 * slc_cfg register definitions 72 **********************************************************************/ 73 #define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */ 74 #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ 75 #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */ 76 #define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */ 77 #define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ 78 #define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */ 79 80 /********************************************************************** 81 * slc_stat register definitions 82 **********************************************************************/ 83 #define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ 84 #define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */ 85 #define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */ 86 87 /********************************************************************** 88 * slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions 89 **********************************************************************/ 90 #define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */ 91 #define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */ 92 93 /********************************************************************** 94 * slc_tac register definitions 95 **********************************************************************/ 96 /* Computation of clock cycles on basis of controller and device clock rates */ 97 #define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s) 98 99 /* Clock setting for RDY write sample wait time in 2*n clocks */ 100 #define SLCTAC_WDR(n) (((n) & 0xF) << 28) 101 /* Write pulse width in clock cycles, 1 to 16 clocks */ 102 #define SLCTAC_WWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 24)) 103 /* Write hold time of control and data signals, 1 to 16 clocks */ 104 #define SLCTAC_WHOLD(c, n) (SLCTAC_CLOCKS(c, n, 20)) 105 /* Write setup time of control and data signals, 1 to 16 clocks */ 106 #define SLCTAC_WSETUP(c, n) (SLCTAC_CLOCKS(c, n, 16)) 107 /* Clock setting for RDY read sample wait time in 2*n clocks */ 108 #define SLCTAC_RDR(n) (((n) & 0xF) << 12) 109 /* Read pulse width in clock cycles, 1 to 16 clocks */ 110 #define SLCTAC_RWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 8)) 111 /* Read hold time of control and data signals, 1 to 16 clocks */ 112 #define SLCTAC_RHOLD(c, n) (SLCTAC_CLOCKS(c, n, 4)) 113 /* Read setup time of control and data signals, 1 to 16 clocks */ 114 #define SLCTAC_RSETUP(c, n) (SLCTAC_CLOCKS(c, n, 0)) 115 116 /********************************************************************** 117 * slc_ecc register definitions 118 **********************************************************************/ 119 /* ECC line party fetch macro */ 120 #define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF) 121 #define SLCECC_TO_COLPAR(n) ((n) & 0x3F) 122 123 /* 124 * DMA requires storage space for the DMA local buffer and the hardware ECC 125 * storage area. The DMA local buffer is only used if DMA mapping fails 126 * during runtime. 127 */ 128 #define LPC32XX_DMA_DATA_SIZE 4096 129 #define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4) 130 131 /* Number of bytes used for ECC stored in NAND per 256 bytes */ 132 #define LPC32XX_SLC_DEV_ECC_BYTES 3 133 134 /* 135 * If the NAND base clock frequency can't be fetched, this frequency will be 136 * used instead as the base. This rate is used to setup the timing registers 137 * used for NAND accesses. 138 */ 139 #define LPC32XX_DEF_BUS_RATE 133250000 140 141 /* Milliseconds for DMA FIFO timeout (unlikely anyway) */ 142 #define LPC32XX_DMA_TIMEOUT 100 143 144 /* 145 * NAND ECC Layout for small page NAND devices 146 * Note: For large and huge page devices, the default layouts are used 147 */ 148 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section, 149 struct mtd_oob_region *oobregion) 150 { 151 if (section) 152 return -ERANGE; 153 154 oobregion->length = 6; 155 oobregion->offset = 10; 156 157 return 0; 158 } 159 160 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section, 161 struct mtd_oob_region *oobregion) 162 { 163 if (section > 1) 164 return -ERANGE; 165 166 if (!section) { 167 oobregion->offset = 0; 168 oobregion->length = 4; 169 } else { 170 oobregion->offset = 6; 171 oobregion->length = 4; 172 } 173 174 return 0; 175 } 176 177 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = { 178 .ecc = lpc32xx_ooblayout_ecc, 179 .free = lpc32xx_ooblayout_free, 180 }; 181 182 static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 183 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 184 185 /* 186 * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6 187 * Note: Large page devices used the default layout 188 */ 189 static struct nand_bbt_descr bbt_smallpage_main_descr = { 190 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 191 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 192 .offs = 0, 193 .len = 4, 194 .veroffs = 6, 195 .maxblocks = 4, 196 .pattern = bbt_pattern 197 }; 198 199 static struct nand_bbt_descr bbt_smallpage_mirror_descr = { 200 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 201 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 202 .offs = 0, 203 .len = 4, 204 .veroffs = 6, 205 .maxblocks = 4, 206 .pattern = mirror_pattern 207 }; 208 209 /* 210 * NAND platform configuration structure 211 */ 212 struct lpc32xx_nand_cfg_slc { 213 uint32_t wdr_clks; 214 uint32_t wwidth; 215 uint32_t whold; 216 uint32_t wsetup; 217 uint32_t rdr_clks; 218 uint32_t rwidth; 219 uint32_t rhold; 220 uint32_t rsetup; 221 int wp_gpio; 222 struct mtd_partition *parts; 223 unsigned num_parts; 224 }; 225 226 struct lpc32xx_nand_host { 227 struct nand_chip nand_chip; 228 struct lpc32xx_slc_platform_data *pdata; 229 struct clk *clk; 230 void __iomem *io_base; 231 struct lpc32xx_nand_cfg_slc *ncfg; 232 233 struct completion comp; 234 struct dma_chan *dma_chan; 235 uint32_t dma_buf_len; 236 struct dma_slave_config dma_slave_config; 237 struct scatterlist sgl; 238 239 /* 240 * DMA and CPU addresses of ECC work area and data buffer 241 */ 242 uint32_t *ecc_buf; 243 uint8_t *data_buf; 244 dma_addr_t io_base_dma; 245 }; 246 247 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) 248 { 249 uint32_t clkrate, tmp; 250 251 /* Reset SLC controller */ 252 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); 253 udelay(1000); 254 255 /* Basic setup */ 256 writel(0, SLC_CFG(host->io_base)); 257 writel(0, SLC_IEN(host->io_base)); 258 writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN), 259 SLC_ICR(host->io_base)); 260 261 /* Get base clock for SLC block */ 262 clkrate = clk_get_rate(host->clk); 263 if (clkrate == 0) 264 clkrate = LPC32XX_DEF_BUS_RATE; 265 266 /* Compute clock setup values */ 267 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) | 268 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) | 269 SLCTAC_WHOLD(clkrate, host->ncfg->whold) | 270 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) | 271 SLCTAC_RDR(host->ncfg->rdr_clks) | 272 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) | 273 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) | 274 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup); 275 writel(tmp, SLC_TAC(host->io_base)); 276 } 277 278 /* 279 * Hardware specific access to control lines 280 */ 281 static void lpc32xx_nand_cmd_ctrl(struct nand_chip *chip, int cmd, 282 unsigned int ctrl) 283 { 284 uint32_t tmp; 285 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 286 287 /* Does CE state need to be changed? */ 288 tmp = readl(SLC_CFG(host->io_base)); 289 if (ctrl & NAND_NCE) 290 tmp |= SLCCFG_CE_LOW; 291 else 292 tmp &= ~SLCCFG_CE_LOW; 293 writel(tmp, SLC_CFG(host->io_base)); 294 295 if (cmd != NAND_CMD_NONE) { 296 if (ctrl & NAND_CLE) 297 writel(cmd, SLC_CMD(host->io_base)); 298 else 299 writel(cmd, SLC_ADDR(host->io_base)); 300 } 301 } 302 303 /* 304 * Read the Device Ready pin 305 */ 306 static int lpc32xx_nand_device_ready(struct nand_chip *chip) 307 { 308 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 309 int rdy = 0; 310 311 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0) 312 rdy = 1; 313 314 return rdy; 315 } 316 317 /* 318 * Enable NAND write protect 319 */ 320 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) 321 { 322 if (gpio_is_valid(host->ncfg->wp_gpio)) 323 gpio_set_value(host->ncfg->wp_gpio, 0); 324 } 325 326 /* 327 * Disable NAND write protect 328 */ 329 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) 330 { 331 if (gpio_is_valid(host->ncfg->wp_gpio)) 332 gpio_set_value(host->ncfg->wp_gpio, 1); 333 } 334 335 /* 336 * Prepares SLC for transfers with H/W ECC enabled 337 */ 338 static void lpc32xx_nand_ecc_enable(struct nand_chip *chip, int mode) 339 { 340 /* Hardware ECC is enabled automatically in hardware as needed */ 341 } 342 343 /* 344 * Calculates the ECC for the data 345 */ 346 static int lpc32xx_nand_ecc_calculate(struct nand_chip *chip, 347 const unsigned char *buf, 348 unsigned char *code) 349 { 350 /* 351 * ECC is calculated automatically in hardware during syndrome read 352 * and write operations, so it doesn't need to be calculated here. 353 */ 354 return 0; 355 } 356 357 /* 358 * Read a single byte from NAND device 359 */ 360 static uint8_t lpc32xx_nand_read_byte(struct nand_chip *chip) 361 { 362 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 363 364 return (uint8_t)readl(SLC_DATA(host->io_base)); 365 } 366 367 /* 368 * Simple device read without ECC 369 */ 370 static void lpc32xx_nand_read_buf(struct nand_chip *chip, u_char *buf, int len) 371 { 372 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 373 374 /* Direct device read with no ECC */ 375 while (len-- > 0) 376 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base)); 377 } 378 379 /* 380 * Simple device write without ECC 381 */ 382 static void lpc32xx_nand_write_buf(struct nand_chip *chip, const uint8_t *buf, 383 int len) 384 { 385 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 386 387 /* Direct device write with no ECC */ 388 while (len-- > 0) 389 writel((uint32_t)*buf++, SLC_DATA(host->io_base)); 390 } 391 392 /* 393 * Read the OOB data from the device without ECC using FIFO method 394 */ 395 static int lpc32xx_nand_read_oob_syndrome(struct nand_chip *chip, int page) 396 { 397 struct mtd_info *mtd = nand_to_mtd(chip); 398 399 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 400 } 401 402 /* 403 * Write the OOB data to the device without ECC using FIFO method 404 */ 405 static int lpc32xx_nand_write_oob_syndrome(struct nand_chip *chip, int page) 406 { 407 struct mtd_info *mtd = nand_to_mtd(chip); 408 409 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, 410 mtd->oobsize); 411 } 412 413 /* 414 * Fills in the ECC fields in the OOB buffer with the hardware generated ECC 415 */ 416 static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) 417 { 418 int i; 419 420 for (i = 0; i < (count * 3); i += 3) { 421 uint32_t ce = ecc[i / 3]; 422 ce = ~(ce << 2) & 0xFFFFFF; 423 spare[i + 2] = (uint8_t)(ce & 0xFF); 424 ce >>= 8; 425 spare[i + 1] = (uint8_t)(ce & 0xFF); 426 ce >>= 8; 427 spare[i] = (uint8_t)(ce & 0xFF); 428 } 429 } 430 431 static void lpc32xx_dma_complete_func(void *completion) 432 { 433 complete(completion); 434 } 435 436 static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma, 437 void *mem, int len, enum dma_transfer_direction dir) 438 { 439 struct nand_chip *chip = mtd_to_nand(mtd); 440 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 441 struct dma_async_tx_descriptor *desc; 442 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 443 int res; 444 445 host->dma_slave_config.direction = dir; 446 host->dma_slave_config.src_addr = dma; 447 host->dma_slave_config.dst_addr = dma; 448 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 449 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 450 host->dma_slave_config.src_maxburst = 4; 451 host->dma_slave_config.dst_maxburst = 4; 452 /* DMA controller does flow control: */ 453 host->dma_slave_config.device_fc = false; 454 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { 455 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); 456 return -ENXIO; 457 } 458 459 sg_init_one(&host->sgl, mem, len); 460 461 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, 462 DMA_BIDIRECTIONAL); 463 if (res != 1) { 464 dev_err(mtd->dev.parent, "Failed to map sg list\n"); 465 return -ENXIO; 466 } 467 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, 468 flags); 469 if (!desc) { 470 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); 471 goto out1; 472 } 473 474 init_completion(&host->comp); 475 desc->callback = lpc32xx_dma_complete_func; 476 desc->callback_param = &host->comp; 477 478 dmaengine_submit(desc); 479 dma_async_issue_pending(host->dma_chan); 480 481 wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000)); 482 483 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, 484 DMA_BIDIRECTIONAL); 485 486 return 0; 487 out1: 488 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, 489 DMA_BIDIRECTIONAL); 490 return -ENXIO; 491 } 492 493 /* 494 * DMA read/write transfers with ECC support 495 */ 496 static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages, 497 int read) 498 { 499 struct nand_chip *chip = mtd_to_nand(mtd); 500 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 501 int i, status = 0; 502 unsigned long timeout; 503 int res; 504 enum dma_transfer_direction dir = 505 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 506 uint8_t *dma_buf; 507 bool dma_mapped; 508 509 if ((void *)buf <= high_memory) { 510 dma_buf = buf; 511 dma_mapped = true; 512 } else { 513 dma_buf = host->data_buf; 514 dma_mapped = false; 515 if (!read) 516 memcpy(host->data_buf, buf, mtd->writesize); 517 } 518 519 if (read) { 520 writel(readl(SLC_CFG(host->io_base)) | 521 SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | 522 SLCCFG_DMA_BURST, SLC_CFG(host->io_base)); 523 } else { 524 writel((readl(SLC_CFG(host->io_base)) | 525 SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) & 526 ~SLCCFG_DMA_DIR, 527 SLC_CFG(host->io_base)); 528 } 529 530 /* Clear initial ECC */ 531 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base)); 532 533 /* Transfer size is data area only */ 534 writel(mtd->writesize, SLC_TC(host->io_base)); 535 536 /* Start transfer in the NAND controller */ 537 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START, 538 SLC_CTRL(host->io_base)); 539 540 for (i = 0; i < chip->ecc.steps; i++) { 541 /* Data */ 542 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma), 543 dma_buf + i * chip->ecc.size, 544 mtd->writesize / chip->ecc.steps, dir); 545 if (res) 546 return res; 547 548 /* Always _read_ ECC */ 549 if (i == chip->ecc.steps - 1) 550 break; 551 if (!read) /* ECC availability delayed on write */ 552 udelay(10); 553 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma), 554 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM); 555 if (res) 556 return res; 557 } 558 559 /* 560 * According to NXP, the DMA can be finished here, but the NAND 561 * controller may still have buffered data. After porting to using the 562 * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty) 563 * appears to be always true, according to tests. Keeping the check for 564 * safety reasons for now. 565 */ 566 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) { 567 dev_warn(mtd->dev.parent, "FIFO not empty!\n"); 568 timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT); 569 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) && 570 time_before(jiffies, timeout)) 571 cpu_relax(); 572 if (!time_before(jiffies, timeout)) { 573 dev_err(mtd->dev.parent, "FIFO held data too long\n"); 574 status = -EIO; 575 } 576 } 577 578 /* Read last calculated ECC value */ 579 if (!read) 580 udelay(10); 581 host->ecc_buf[chip->ecc.steps - 1] = 582 readl(SLC_ECC(host->io_base)); 583 584 /* Flush DMA */ 585 dmaengine_terminate_all(host->dma_chan); 586 587 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO || 588 readl(SLC_TC(host->io_base))) { 589 /* Something is left in the FIFO, something is wrong */ 590 dev_err(mtd->dev.parent, "DMA FIFO failure\n"); 591 status = -EIO; 592 } 593 594 /* Stop DMA & HW ECC */ 595 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START, 596 SLC_CTRL(host->io_base)); 597 writel(readl(SLC_CFG(host->io_base)) & 598 ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | 599 SLCCFG_DMA_BURST), SLC_CFG(host->io_base)); 600 601 if (!dma_mapped && read) 602 memcpy(buf, host->data_buf, mtd->writesize); 603 604 return status; 605 } 606 607 /* 608 * Read the data and OOB data from the device, use ECC correction with the 609 * data, disable ECC for the OOB data 610 */ 611 static int lpc32xx_nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf, 612 int oob_required, int page) 613 { 614 struct mtd_info *mtd = nand_to_mtd(chip); 615 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 616 struct mtd_oob_region oobregion = { }; 617 int stat, i, status, error; 618 uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE]; 619 620 /* Issue read command */ 621 nand_read_page_op(chip, page, 0, NULL, 0); 622 623 /* Read data and oob, calculate ECC */ 624 status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1); 625 626 /* Get OOB data */ 627 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize); 628 629 /* Convert to stored ECC format */ 630 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps); 631 632 /* Pointer to ECC data retrieved from NAND spare area */ 633 error = mtd_ooblayout_ecc(mtd, 0, &oobregion); 634 if (error) 635 return error; 636 637 oobecc = chip->oob_poi + oobregion.offset; 638 639 for (i = 0; i < chip->ecc.steps; i++) { 640 stat = chip->ecc.correct(chip, buf, oobecc, 641 &tmpecc[i * chip->ecc.bytes]); 642 if (stat < 0) 643 mtd->ecc_stats.failed++; 644 else 645 mtd->ecc_stats.corrected += stat; 646 647 buf += chip->ecc.size; 648 oobecc += chip->ecc.bytes; 649 } 650 651 return status; 652 } 653 654 /* 655 * Read the data and OOB data from the device, no ECC correction with the 656 * data or OOB data 657 */ 658 static int lpc32xx_nand_read_page_raw_syndrome(struct nand_chip *chip, 659 uint8_t *buf, int oob_required, 660 int page) 661 { 662 struct mtd_info *mtd = nand_to_mtd(chip); 663 664 /* Issue read command */ 665 nand_read_page_op(chip, page, 0, NULL, 0); 666 667 /* Raw reads can just use the FIFO interface */ 668 chip->legacy.read_buf(chip, buf, chip->ecc.size * chip->ecc.steps); 669 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize); 670 671 return 0; 672 } 673 674 /* 675 * Write the data and OOB data to the device, use ECC with the data, 676 * disable ECC for the OOB data 677 */ 678 static int lpc32xx_nand_write_page_syndrome(struct nand_chip *chip, 679 const uint8_t *buf, 680 int oob_required, int page) 681 { 682 struct mtd_info *mtd = nand_to_mtd(chip); 683 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 684 struct mtd_oob_region oobregion = { }; 685 uint8_t *pb; 686 int error; 687 688 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 689 690 /* Write data, calculate ECC on outbound data */ 691 error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0); 692 if (error) 693 return error; 694 695 /* 696 * The calculated ECC needs some manual work done to it before 697 * committing it to NAND. Process the calculated ECC and place 698 * the resultant values directly into the OOB buffer. */ 699 error = mtd_ooblayout_ecc(mtd, 0, &oobregion); 700 if (error) 701 return error; 702 703 pb = chip->oob_poi + oobregion.offset; 704 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps); 705 706 /* Write ECC data to device */ 707 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); 708 709 return nand_prog_page_end_op(chip); 710 } 711 712 /* 713 * Write the data and OOB data to the device, no ECC correction with the 714 * data or OOB data 715 */ 716 static int lpc32xx_nand_write_page_raw_syndrome(struct nand_chip *chip, 717 const uint8_t *buf, 718 int oob_required, int page) 719 { 720 struct mtd_info *mtd = nand_to_mtd(chip); 721 722 /* Raw writes can just use the FIFO interface */ 723 nand_prog_page_begin_op(chip, page, 0, buf, 724 chip->ecc.size * chip->ecc.steps); 725 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); 726 727 return nand_prog_page_end_op(chip); 728 } 729 730 static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) 731 { 732 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip); 733 dma_cap_mask_t mask; 734 735 if (!host->pdata || !host->pdata->dma_filter) { 736 dev_err(mtd->dev.parent, "no DMA platform data\n"); 737 return -ENOENT; 738 } 739 740 dma_cap_zero(mask); 741 dma_cap_set(DMA_SLAVE, mask); 742 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, 743 "nand-slc"); 744 if (!host->dma_chan) { 745 dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); 746 return -EBUSY; 747 } 748 749 return 0; 750 } 751 752 static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) 753 { 754 struct lpc32xx_nand_cfg_slc *ncfg; 755 struct device_node *np = dev->of_node; 756 757 ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL); 758 if (!ncfg) 759 return NULL; 760 761 of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks); 762 of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth); 763 of_property_read_u32(np, "nxp,whold", &ncfg->whold); 764 of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup); 765 of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks); 766 of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth); 767 of_property_read_u32(np, "nxp,rhold", &ncfg->rhold); 768 of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup); 769 770 if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold || 771 !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth || 772 !ncfg->rhold || !ncfg->rsetup) { 773 dev_err(dev, "chip parameters not specified correctly\n"); 774 return NULL; 775 } 776 777 ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0); 778 779 return ncfg; 780 } 781 782 static int lpc32xx_nand_attach_chip(struct nand_chip *chip) 783 { 784 struct mtd_info *mtd = nand_to_mtd(chip); 785 struct lpc32xx_nand_host *host = nand_get_controller_data(chip); 786 787 /* OOB and ECC CPU and DMA work areas */ 788 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE); 789 790 /* 791 * Small page FLASH has a unique OOB layout, but large and huge 792 * page FLASH use the standard layout. Small page FLASH uses a 793 * custom BBT marker layout. 794 */ 795 if (mtd->writesize <= 512) 796 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops); 797 798 /* These sizes remain the same regardless of page size */ 799 chip->ecc.size = 256; 800 chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES; 801 chip->ecc.prepad = 0; 802 chip->ecc.postpad = 0; 803 804 /* 805 * Use a custom BBT marker setup for small page FLASH that 806 * won't interfere with the ECC layout. Large and huge page 807 * FLASH use the standard layout. 808 */ 809 if ((chip->bbt_options & NAND_BBT_USE_FLASH) && 810 mtd->writesize <= 512) { 811 chip->bbt_td = &bbt_smallpage_main_descr; 812 chip->bbt_md = &bbt_smallpage_mirror_descr; 813 } 814 815 return 0; 816 } 817 818 static const struct nand_controller_ops lpc32xx_nand_controller_ops = { 819 .attach_chip = lpc32xx_nand_attach_chip, 820 }; 821 822 /* 823 * Probe for NAND controller 824 */ 825 static int lpc32xx_nand_probe(struct platform_device *pdev) 826 { 827 struct lpc32xx_nand_host *host; 828 struct mtd_info *mtd; 829 struct nand_chip *chip; 830 struct resource *rc; 831 int res; 832 833 /* Allocate memory for the device structure (and zero it) */ 834 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 835 if (!host) 836 return -ENOMEM; 837 838 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); 839 host->io_base = devm_ioremap_resource(&pdev->dev, rc); 840 if (IS_ERR(host->io_base)) 841 return PTR_ERR(host->io_base); 842 843 host->io_base_dma = rc->start; 844 if (pdev->dev.of_node) 845 host->ncfg = lpc32xx_parse_dt(&pdev->dev); 846 if (!host->ncfg) { 847 dev_err(&pdev->dev, 848 "Missing or bad NAND config from device tree\n"); 849 return -ENOENT; 850 } 851 if (host->ncfg->wp_gpio == -EPROBE_DEFER) 852 return -EPROBE_DEFER; 853 if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev, 854 host->ncfg->wp_gpio, "NAND WP")) { 855 dev_err(&pdev->dev, "GPIO not available\n"); 856 return -EBUSY; 857 } 858 lpc32xx_wp_disable(host); 859 860 host->pdata = dev_get_platdata(&pdev->dev); 861 862 chip = &host->nand_chip; 863 mtd = nand_to_mtd(chip); 864 nand_set_controller_data(chip, host); 865 nand_set_flash_node(chip, pdev->dev.of_node); 866 mtd->owner = THIS_MODULE; 867 mtd->dev.parent = &pdev->dev; 868 869 /* Get NAND clock */ 870 host->clk = devm_clk_get(&pdev->dev, NULL); 871 if (IS_ERR(host->clk)) { 872 dev_err(&pdev->dev, "Clock failure\n"); 873 res = -ENOENT; 874 goto enable_wp; 875 } 876 res = clk_prepare_enable(host->clk); 877 if (res) 878 goto enable_wp; 879 880 /* Set NAND IO addresses and command/ready functions */ 881 chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base); 882 chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base); 883 chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl; 884 chip->legacy.dev_ready = lpc32xx_nand_device_ready; 885 chip->legacy.chip_delay = 20; /* 20us command delay time */ 886 887 /* Init NAND controller */ 888 lpc32xx_nand_setup(host); 889 890 platform_set_drvdata(pdev, host); 891 892 /* NAND callbacks for LPC32xx SLC hardware */ 893 chip->ecc.mode = NAND_ECC_HW_SYNDROME; 894 chip->legacy.read_byte = lpc32xx_nand_read_byte; 895 chip->legacy.read_buf = lpc32xx_nand_read_buf; 896 chip->legacy.write_buf = lpc32xx_nand_write_buf; 897 chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome; 898 chip->ecc.read_page = lpc32xx_nand_read_page_syndrome; 899 chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome; 900 chip->ecc.write_page = lpc32xx_nand_write_page_syndrome; 901 chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome; 902 chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome; 903 chip->ecc.calculate = lpc32xx_nand_ecc_calculate; 904 chip->ecc.correct = nand_correct_data; 905 chip->ecc.strength = 1; 906 chip->ecc.hwctl = lpc32xx_nand_ecc_enable; 907 908 /* 909 * Allocate a large enough buffer for a single huge page plus 910 * extra space for the spare area and ECC storage area 911 */ 912 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE; 913 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len, 914 GFP_KERNEL); 915 if (host->data_buf == NULL) { 916 res = -ENOMEM; 917 goto unprepare_clk; 918 } 919 920 res = lpc32xx_nand_dma_setup(host); 921 if (res) { 922 res = -EIO; 923 goto unprepare_clk; 924 } 925 926 /* Find NAND device */ 927 chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops; 928 res = nand_scan(chip, 1); 929 if (res) 930 goto release_dma; 931 932 mtd->name = "nxp_lpc3220_slc"; 933 res = mtd_device_register(mtd, host->ncfg->parts, 934 host->ncfg->num_parts); 935 if (res) 936 goto cleanup_nand; 937 938 return 0; 939 940 cleanup_nand: 941 nand_cleanup(chip); 942 release_dma: 943 dma_release_channel(host->dma_chan); 944 unprepare_clk: 945 clk_disable_unprepare(host->clk); 946 enable_wp: 947 lpc32xx_wp_enable(host); 948 949 return res; 950 } 951 952 /* 953 * Remove NAND device. 954 */ 955 static int lpc32xx_nand_remove(struct platform_device *pdev) 956 { 957 uint32_t tmp; 958 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); 959 960 nand_release(&host->nand_chip); 961 dma_release_channel(host->dma_chan); 962 963 /* Force CE high */ 964 tmp = readl(SLC_CTRL(host->io_base)); 965 tmp &= ~SLCCFG_CE_LOW; 966 writel(tmp, SLC_CTRL(host->io_base)); 967 968 clk_disable_unprepare(host->clk); 969 lpc32xx_wp_enable(host); 970 971 return 0; 972 } 973 974 #ifdef CONFIG_PM 975 static int lpc32xx_nand_resume(struct platform_device *pdev) 976 { 977 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); 978 int ret; 979 980 /* Re-enable NAND clock */ 981 ret = clk_prepare_enable(host->clk); 982 if (ret) 983 return ret; 984 985 /* Fresh init of NAND controller */ 986 lpc32xx_nand_setup(host); 987 988 /* Disable write protect */ 989 lpc32xx_wp_disable(host); 990 991 return 0; 992 } 993 994 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) 995 { 996 uint32_t tmp; 997 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); 998 999 /* Force CE high */ 1000 tmp = readl(SLC_CTRL(host->io_base)); 1001 tmp &= ~SLCCFG_CE_LOW; 1002 writel(tmp, SLC_CTRL(host->io_base)); 1003 1004 /* Enable write protect for safety */ 1005 lpc32xx_wp_enable(host); 1006 1007 /* Disable clock */ 1008 clk_disable_unprepare(host->clk); 1009 1010 return 0; 1011 } 1012 1013 #else 1014 #define lpc32xx_nand_resume NULL 1015 #define lpc32xx_nand_suspend NULL 1016 #endif 1017 1018 static const struct of_device_id lpc32xx_nand_match[] = { 1019 { .compatible = "nxp,lpc3220-slc" }, 1020 { /* sentinel */ }, 1021 }; 1022 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); 1023 1024 static struct platform_driver lpc32xx_nand_driver = { 1025 .probe = lpc32xx_nand_probe, 1026 .remove = lpc32xx_nand_remove, 1027 .resume = lpc32xx_nand_resume, 1028 .suspend = lpc32xx_nand_suspend, 1029 .driver = { 1030 .name = LPC32XX_MODNAME, 1031 .of_match_table = lpc32xx_nand_match, 1032 }, 1033 }; 1034 1035 module_platform_driver(lpc32xx_nand_driver); 1036 1037 MODULE_LICENSE("GPL"); 1038 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 1039 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 1040 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller"); 1041