1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2020 Intel Corporation. */
3 
4 #include <linux/clk.h>
5 #include <linux/completion.h>
6 #include <linux/dmaengine.h>
7 #include <linux/dma-direction.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/err.h>
10 #include <linux/init.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/nand.h>
18 
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/units.h>
25 #include <asm/unaligned.h>
26 
27 #define EBU_CLC			0x000
28 #define EBU_CLC_RST		0x00000000u
29 
30 #define EBU_ADDR_SEL(n)		(0x020 + (n) * 4)
31 /* 5 bits 26:22 included for comparison in the ADDR_SELx */
32 #define EBU_ADDR_MASK(x)	((x) << 4)
33 #define EBU_ADDR_SEL_REGEN	0x1
34 
35 #define EBU_BUSCON(n)		(0x060 + (n) * 4)
36 #define EBU_BUSCON_CMULT_V4	0x1
37 #define EBU_BUSCON_RECOVC(n)	((n) << 2)
38 #define EBU_BUSCON_HOLDC(n)	((n) << 4)
39 #define EBU_BUSCON_WAITRDC(n)	((n) << 6)
40 #define EBU_BUSCON_WAITWRC(n)	((n) << 8)
41 #define EBU_BUSCON_BCGEN_CS	0x0
42 #define EBU_BUSCON_SETUP_EN	BIT(22)
43 #define EBU_BUSCON_ALEC		0xC000
44 
45 #define EBU_CON			0x0B0
46 #define EBU_CON_NANDM_EN	BIT(0)
47 #define EBU_CON_NANDM_DIS	0x0
48 #define EBU_CON_CSMUX_E_EN	BIT(1)
49 #define EBU_CON_ALE_P_LOW	BIT(2)
50 #define EBU_CON_CLE_P_LOW	BIT(3)
51 #define EBU_CON_CS_P_LOW	BIT(4)
52 #define EBU_CON_SE_P_LOW	BIT(5)
53 #define EBU_CON_WP_P_LOW	BIT(6)
54 #define EBU_CON_PRE_P_LOW	BIT(7)
55 #define EBU_CON_IN_CS_S(n)	((n) << 8)
56 #define EBU_CON_OUT_CS_S(n)	((n) << 10)
57 #define EBU_CON_LAT_EN_CS_P	((0x3D) << 18)
58 
59 #define EBU_WAIT		0x0B4
60 #define EBU_WAIT_RDBY		BIT(0)
61 #define EBU_WAIT_WR_C		BIT(3)
62 
63 #define HSNAND_CTL1		0x110
64 #define HSNAND_CTL1_ADDR_SHIFT	24
65 
66 #define HSNAND_CTL2		0x114
67 #define HSNAND_CTL2_ADDR_SHIFT	8
68 #define HSNAND_CTL2_CYC_N_V5	(0x2 << 16)
69 
70 #define HSNAND_INT_MSK_CTL	0x124
71 #define HSNAND_INT_MSK_CTL_WR_C	BIT(4)
72 
73 #define HSNAND_INT_STA		0x128
74 #define HSNAND_INT_STA_WR_C	BIT(4)
75 
76 #define HSNAND_CTL		0x130
77 #define HSNAND_CTL_ENABLE_ECC	BIT(0)
78 #define HSNAND_CTL_GO		BIT(2)
79 #define HSNAND_CTL_CE_SEL_CS(n)	BIT(3 + (n))
80 #define HSNAND_CTL_RW_READ	0x0
81 #define HSNAND_CTL_RW_WRITE	BIT(10)
82 #define HSNAND_CTL_ECC_OFF_V8TH	BIT(11)
83 #define HSNAND_CTL_CKFF_EN	0x0
84 #define HSNAND_CTL_MSG_EN	BIT(17)
85 
86 #define HSNAND_PARA0		0x13c
87 #define HSNAND_PARA0_PAGE_V8192	0x3
88 #define HSNAND_PARA0_PIB_V256	(0x3 << 4)
89 #define HSNAND_PARA0_BYP_EN_NP	0x0
90 #define HSNAND_PARA0_BYP_DEC_NP	0x0
91 #define HSNAND_PARA0_TYPE_ONFI	BIT(18)
92 #define HSNAND_PARA0_ADEP_EN	BIT(21)
93 
94 #define HSNAND_CMSG_0		0x150
95 #define HSNAND_CMSG_1		0x154
96 
97 #define HSNAND_ALE_OFFS		BIT(2)
98 #define HSNAND_CLE_OFFS		BIT(3)
99 #define HSNAND_CS_OFFS		BIT(4)
100 
101 #define HSNAND_ECC_OFFSET	0x008
102 
103 #define MAX_CS	2
104 
105 #define USEC_PER_SEC	1000000L
106 
107 struct ebu_nand_cs {
108 	void __iomem *chipaddr;
109 	u32 addr_sel;
110 };
111 
112 struct ebu_nand_controller {
113 	struct nand_controller controller;
114 	struct nand_chip chip;
115 	struct device *dev;
116 	void __iomem *ebu;
117 	void __iomem *hsnand;
118 	struct dma_chan *dma_tx;
119 	struct dma_chan *dma_rx;
120 	struct completion dma_access_complete;
121 	struct clk *clk;
122 	u32 nd_para0;
123 	u8 cs_num;
124 	struct ebu_nand_cs cs[MAX_CS];
125 };
126 
127 static inline struct ebu_nand_controller *nand_to_ebu(struct nand_chip *chip)
128 {
129 	return container_of(chip, struct ebu_nand_controller, chip);
130 }
131 
132 static int ebu_nand_waitrdy(struct nand_chip *chip, int timeout_ms)
133 {
134 	struct ebu_nand_controller *ctrl = nand_to_ebu(chip);
135 	u32 status;
136 
137 	return readl_poll_timeout(ctrl->ebu + EBU_WAIT, status,
138 				  (status & EBU_WAIT_RDBY) ||
139 				  (status & EBU_WAIT_WR_C), 20, timeout_ms);
140 }
141 
142 static u8 ebu_nand_readb(struct nand_chip *chip)
143 {
144 	struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
145 	u8 cs_num = ebu_host->cs_num;
146 	u8 val;
147 
148 	val = readb(ebu_host->cs[cs_num].chipaddr + HSNAND_CS_OFFS);
149 	ebu_nand_waitrdy(chip, 1000);
150 	return val;
151 }
152 
153 static void ebu_nand_writeb(struct nand_chip *chip, u32 offset, u8 value)
154 {
155 	struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
156 	u8 cs_num = ebu_host->cs_num;
157 
158 	writeb(value, ebu_host->cs[cs_num].chipaddr + offset);
159 	ebu_nand_waitrdy(chip, 1000);
160 }
161 
162 static void ebu_read_buf(struct nand_chip *chip, u_char *buf, unsigned int len)
163 {
164 	int i;
165 
166 	for (i = 0; i < len; i++)
167 		buf[i] = ebu_nand_readb(chip);
168 }
169 
170 static void ebu_write_buf(struct nand_chip *chip, const u_char *buf, int len)
171 {
172 	int i;
173 
174 	for (i = 0; i < len; i++)
175 		ebu_nand_writeb(chip, HSNAND_CS_OFFS, buf[i]);
176 }
177 
178 static void ebu_nand_disable(struct nand_chip *chip)
179 {
180 	struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
181 
182 	writel(0, ebu_host->ebu + EBU_CON);
183 }
184 
185 static void ebu_select_chip(struct nand_chip *chip)
186 {
187 	struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
188 	void __iomem *nand_con = ebu_host->ebu + EBU_CON;
189 	u32 cs = ebu_host->cs_num;
190 
191 	writel(EBU_CON_NANDM_EN | EBU_CON_CSMUX_E_EN | EBU_CON_CS_P_LOW |
192 	       EBU_CON_SE_P_LOW | EBU_CON_WP_P_LOW | EBU_CON_PRE_P_LOW |
193 	       EBU_CON_IN_CS_S(cs) | EBU_CON_OUT_CS_S(cs) |
194 	       EBU_CON_LAT_EN_CS_P, nand_con);
195 }
196 
197 static int ebu_nand_set_timings(struct nand_chip *chip, int csline,
198 				const struct nand_interface_config *conf)
199 {
200 	struct ebu_nand_controller *ctrl = nand_to_ebu(chip);
201 	unsigned int rate = clk_get_rate(ctrl->clk) / HZ_PER_MHZ;
202 	unsigned int period = DIV_ROUND_UP(USEC_PER_SEC, rate);
203 	const struct nand_sdr_timings *timings;
204 	u32 trecov, thold, twrwait, trdwait;
205 	u32 reg = 0;
206 
207 	timings = nand_get_sdr_timings(conf);
208 	if (IS_ERR(timings))
209 		return PTR_ERR(timings);
210 
211 	if (csline == NAND_DATA_IFACE_CHECK_ONLY)
212 		return 0;
213 
214 	trecov = DIV_ROUND_UP(max(timings->tREA_max, timings->tREH_min),
215 			      period);
216 	reg |= EBU_BUSCON_RECOVC(trecov);
217 
218 	thold = DIV_ROUND_UP(max(timings->tDH_min, timings->tDS_min), period);
219 	reg |= EBU_BUSCON_HOLDC(thold);
220 
221 	trdwait = DIV_ROUND_UP(max(timings->tRC_min, timings->tREH_min),
222 			       period);
223 	reg |= EBU_BUSCON_WAITRDC(trdwait);
224 
225 	twrwait = DIV_ROUND_UP(max(timings->tWC_min, timings->tWH_min), period);
226 	reg |= EBU_BUSCON_WAITWRC(twrwait);
227 
228 	reg |= EBU_BUSCON_CMULT_V4 | EBU_BUSCON_BCGEN_CS | EBU_BUSCON_ALEC |
229 		EBU_BUSCON_SETUP_EN;
230 
231 	writel(reg, ctrl->ebu + EBU_BUSCON(ctrl->cs_num));
232 
233 	return 0;
234 }
235 
236 static int ebu_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
237 				  struct mtd_oob_region *oobregion)
238 {
239 	struct nand_chip *chip = mtd_to_nand(mtd);
240 
241 	if (section)
242 		return -ERANGE;
243 
244 	oobregion->offset = HSNAND_ECC_OFFSET;
245 	oobregion->length = chip->ecc.total;
246 
247 	return 0;
248 }
249 
250 static int ebu_nand_ooblayout_free(struct mtd_info *mtd, int section,
251 				   struct mtd_oob_region *oobregion)
252 {
253 	struct nand_chip *chip = mtd_to_nand(mtd);
254 
255 	if (section)
256 		return -ERANGE;
257 
258 	oobregion->offset = chip->ecc.total + HSNAND_ECC_OFFSET;
259 	oobregion->length = mtd->oobsize - oobregion->offset;
260 
261 	return 0;
262 }
263 
264 static const struct mtd_ooblayout_ops ebu_nand_ooblayout_ops = {
265 	.ecc = ebu_nand_ooblayout_ecc,
266 	.free = ebu_nand_ooblayout_free,
267 };
268 
269 static void ebu_dma_rx_callback(void *cookie)
270 {
271 	struct ebu_nand_controller *ebu_host = cookie;
272 
273 	dmaengine_terminate_async(ebu_host->dma_rx);
274 
275 	complete(&ebu_host->dma_access_complete);
276 }
277 
278 static void ebu_dma_tx_callback(void *cookie)
279 {
280 	struct ebu_nand_controller *ebu_host = cookie;
281 
282 	dmaengine_terminate_async(ebu_host->dma_tx);
283 
284 	complete(&ebu_host->dma_access_complete);
285 }
286 
287 static int ebu_dma_start(struct ebu_nand_controller *ebu_host, u32 dir,
288 			 const u8 *buf, u32 len)
289 {
290 	struct dma_async_tx_descriptor *tx;
291 	struct completion *dma_completion;
292 	dma_async_tx_callback callback;
293 	struct dma_chan *chan;
294 	dma_cookie_t cookie;
295 	unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
296 	dma_addr_t buf_dma;
297 	int ret;
298 	u32 timeout;
299 
300 	if (dir == DMA_DEV_TO_MEM) {
301 		chan = ebu_host->dma_rx;
302 		dma_completion = &ebu_host->dma_access_complete;
303 		callback = ebu_dma_rx_callback;
304 	} else {
305 		chan = ebu_host->dma_tx;
306 		dma_completion = &ebu_host->dma_access_complete;
307 		callback = ebu_dma_tx_callback;
308 	}
309 
310 	buf_dma = dma_map_single(chan->device->dev, (void *)buf, len, dir);
311 	if (dma_mapping_error(chan->device->dev, buf_dma)) {
312 		dev_err(ebu_host->dev, "Failed to map DMA buffer\n");
313 		ret = -EIO;
314 		goto err_unmap;
315 	}
316 
317 	tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags);
318 	if (!tx) {
319 		ret = -ENXIO;
320 		goto err_unmap;
321 	}
322 
323 	tx->callback = callback;
324 	tx->callback_param = ebu_host;
325 	cookie = tx->tx_submit(tx);
326 
327 	ret = dma_submit_error(cookie);
328 	if (ret) {
329 		dev_err(ebu_host->dev, "dma_submit_error %d\n", cookie);
330 		ret = -EIO;
331 		goto err_unmap;
332 	}
333 
334 	init_completion(dma_completion);
335 	dma_async_issue_pending(chan);
336 
337 	/* Wait DMA to finish the data transfer.*/
338 	timeout = wait_for_completion_timeout(dma_completion, msecs_to_jiffies(1000));
339 	if (!timeout) {
340 		dev_err(ebu_host->dev, "I/O Error in DMA RX (status %d)\n",
341 			dmaengine_tx_status(chan, cookie, NULL));
342 		dmaengine_terminate_sync(chan);
343 		ret = -ETIMEDOUT;
344 		goto err_unmap;
345 	}
346 
347 	return 0;
348 
349 err_unmap:
350 	dma_unmap_single(ebu_host->dev, buf_dma, len, dir);
351 
352 	return ret;
353 }
354 
355 static void ebu_nand_trigger(struct ebu_nand_controller *ebu_host,
356 			     int page, u32 cmd)
357 {
358 	unsigned int val;
359 
360 	val = cmd | (page & 0xFF) << HSNAND_CTL1_ADDR_SHIFT;
361 	writel(val, ebu_host->hsnand + HSNAND_CTL1);
362 	val = (page & 0xFFFF00) >> 8 | HSNAND_CTL2_CYC_N_V5;
363 	writel(val, ebu_host->hsnand + HSNAND_CTL2);
364 
365 	writel(ebu_host->nd_para0, ebu_host->hsnand + HSNAND_PARA0);
366 
367 	/* clear first, will update later */
368 	writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_0);
369 	writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_1);
370 
371 	writel(HSNAND_INT_MSK_CTL_WR_C,
372 	       ebu_host->hsnand + HSNAND_INT_MSK_CTL);
373 
374 	if (!cmd)
375 		val = HSNAND_CTL_RW_READ;
376 	else
377 		val = HSNAND_CTL_RW_WRITE;
378 
379 	writel(HSNAND_CTL_MSG_EN | HSNAND_CTL_CKFF_EN |
380 	       HSNAND_CTL_ECC_OFF_V8TH | HSNAND_CTL_CE_SEL_CS(ebu_host->cs_num) |
381 	       HSNAND_CTL_ENABLE_ECC | HSNAND_CTL_GO | val,
382 	       ebu_host->hsnand + HSNAND_CTL);
383 }
384 
385 static int ebu_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf,
386 				    int oob_required, int page)
387 {
388 	struct mtd_info *mtd = nand_to_mtd(chip);
389 	struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
390 	int ret, reg_data;
391 
392 	ebu_nand_trigger(ebu_host, page, NAND_CMD_READ0);
393 
394 	ret = ebu_dma_start(ebu_host, DMA_DEV_TO_MEM, buf, mtd->writesize);
395 	if (ret)
396 		return ret;
397 
398 	if (oob_required)
399 		chip->ecc.read_oob(chip, page);
400 
401 	reg_data = readl(ebu_host->hsnand + HSNAND_CTL);
402 	reg_data &= ~HSNAND_CTL_GO;
403 	writel(reg_data, ebu_host->hsnand + HSNAND_CTL);
404 
405 	return 0;
406 }
407 
408 static int ebu_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
409 				     int oob_required, int page)
410 {
411 	struct mtd_info *mtd = nand_to_mtd(chip);
412 	struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
413 	void __iomem *int_sta = ebu_host->hsnand + HSNAND_INT_STA;
414 	int reg_data, ret, val;
415 	u32 reg;
416 
417 	ebu_nand_trigger(ebu_host, page, NAND_CMD_SEQIN);
418 
419 	ret = ebu_dma_start(ebu_host, DMA_MEM_TO_DEV, buf, mtd->writesize);
420 	if (ret)
421 		return ret;
422 
423 	if (oob_required) {
424 		reg = get_unaligned_le32(chip->oob_poi);
425 		writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
426 
427 		reg = get_unaligned_le32(chip->oob_poi + 4);
428 		writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
429 	}
430 
431 	ret = readl_poll_timeout_atomic(int_sta, val, !(val & HSNAND_INT_STA_WR_C),
432 					10, 1000);
433 	if (ret)
434 		return ret;
435 
436 	reg_data = readl(ebu_host->hsnand + HSNAND_CTL);
437 	reg_data &= ~HSNAND_CTL_GO;
438 	writel(reg_data, ebu_host->hsnand + HSNAND_CTL);
439 
440 	return 0;
441 }
442 
443 static const u8 ecc_strength[] = { 1, 1, 4, 8, 24, 32, 40, 60, };
444 
445 static int ebu_nand_attach_chip(struct nand_chip *chip)
446 {
447 	struct mtd_info *mtd = nand_to_mtd(chip);
448 	struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
449 	u32 ecc_steps, ecc_bytes, ecc_total, pagesize, pg_per_blk;
450 	u32 ecc_strength_ds = chip->ecc.strength;
451 	u32 ecc_size = chip->ecc.size;
452 	u32 writesize = mtd->writesize;
453 	u32 blocksize = mtd->erasesize;
454 	int bch_algo, start, val;
455 
456 	/* Default to an ECC size of 512 */
457 	if (!chip->ecc.size)
458 		chip->ecc.size = 512;
459 
460 	switch (ecc_size) {
461 	case 512:
462 		start = 1;
463 		if (!ecc_strength_ds)
464 			ecc_strength_ds = 4;
465 		break;
466 	case 1024:
467 		start = 4;
468 		if (!ecc_strength_ds)
469 			ecc_strength_ds = 32;
470 		break;
471 	default:
472 		return -EINVAL;
473 	}
474 
475 	/* BCH ECC algorithm Settings for number of bits per 512B/1024B */
476 	bch_algo = round_up(start + 1, 4);
477 	for (val = start; val < bch_algo; val++) {
478 		if (ecc_strength_ds == ecc_strength[val])
479 			break;
480 	}
481 	if (val == bch_algo)
482 		return -EINVAL;
483 
484 	if (ecc_strength_ds == 8)
485 		ecc_bytes = 14;
486 	else
487 		ecc_bytes = DIV_ROUND_UP(ecc_strength_ds * fls(8 * ecc_size), 8);
488 
489 	ecc_steps = writesize / ecc_size;
490 	ecc_total = ecc_steps * ecc_bytes;
491 	if ((ecc_total + 8) > mtd->oobsize)
492 		return -ERANGE;
493 
494 	chip->ecc.total = ecc_total;
495 	pagesize = fls(writesize >> 11);
496 	if (pagesize > HSNAND_PARA0_PAGE_V8192)
497 		return -ERANGE;
498 
499 	pg_per_blk = fls((blocksize / writesize) >> 6) / 8;
500 	if (pg_per_blk > HSNAND_PARA0_PIB_V256)
501 		return -ERANGE;
502 
503 	ebu_host->nd_para0 = pagesize | pg_per_blk | HSNAND_PARA0_BYP_EN_NP |
504 			     HSNAND_PARA0_BYP_DEC_NP | HSNAND_PARA0_ADEP_EN |
505 			     HSNAND_PARA0_TYPE_ONFI | (val << 29);
506 
507 	mtd_set_ooblayout(mtd, &ebu_nand_ooblayout_ops);
508 	chip->ecc.read_page = ebu_nand_read_page_hwecc;
509 	chip->ecc.write_page = ebu_nand_write_page_hwecc;
510 
511 	return 0;
512 }
513 
514 static int ebu_nand_exec_op(struct nand_chip *chip,
515 			    const struct nand_operation *op, bool check_only)
516 {
517 	const struct nand_op_instr *instr = NULL;
518 	unsigned int op_id;
519 	int i, timeout_ms, ret = 0;
520 
521 	if (check_only)
522 		return 0;
523 
524 	ebu_select_chip(chip);
525 	for (op_id = 0; op_id < op->ninstrs; op_id++) {
526 		instr = &op->instrs[op_id];
527 
528 		switch (instr->type) {
529 		case NAND_OP_CMD_INSTR:
530 			ebu_nand_writeb(chip, HSNAND_CLE_OFFS | HSNAND_CS_OFFS,
531 					instr->ctx.cmd.opcode);
532 			break;
533 
534 		case NAND_OP_ADDR_INSTR:
535 			for (i = 0; i < instr->ctx.addr.naddrs; i++)
536 				ebu_nand_writeb(chip,
537 						HSNAND_ALE_OFFS | HSNAND_CS_OFFS,
538 						instr->ctx.addr.addrs[i]);
539 			break;
540 
541 		case NAND_OP_DATA_IN_INSTR:
542 			ebu_read_buf(chip, instr->ctx.data.buf.in,
543 				     instr->ctx.data.len);
544 			break;
545 
546 		case NAND_OP_DATA_OUT_INSTR:
547 			ebu_write_buf(chip, instr->ctx.data.buf.out,
548 				      instr->ctx.data.len);
549 			break;
550 
551 		case NAND_OP_WAITRDY_INSTR:
552 			timeout_ms = instr->ctx.waitrdy.timeout_ms * 1000;
553 			ret = ebu_nand_waitrdy(chip, timeout_ms);
554 			break;
555 		}
556 	}
557 
558 	return ret;
559 }
560 
561 static const struct nand_controller_ops ebu_nand_controller_ops = {
562 	.attach_chip = ebu_nand_attach_chip,
563 	.setup_interface = ebu_nand_set_timings,
564 	.exec_op = ebu_nand_exec_op,
565 };
566 
567 static void ebu_dma_cleanup(struct ebu_nand_controller *ebu_host)
568 {
569 	if (ebu_host->dma_rx)
570 		dma_release_channel(ebu_host->dma_rx);
571 
572 	if (ebu_host->dma_tx)
573 		dma_release_channel(ebu_host->dma_tx);
574 }
575 
576 static int ebu_nand_probe(struct platform_device *pdev)
577 {
578 	struct device *dev = &pdev->dev;
579 	struct ebu_nand_controller *ebu_host;
580 	struct device_node *chip_np;
581 	struct nand_chip *nand;
582 	struct mtd_info *mtd;
583 	struct resource *res;
584 	char *resname;
585 	int ret;
586 	u32 cs;
587 
588 	ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL);
589 	if (!ebu_host)
590 		return -ENOMEM;
591 
592 	ebu_host->dev = dev;
593 	nand_controller_init(&ebu_host->controller);
594 
595 	ebu_host->ebu = devm_platform_ioremap_resource_byname(pdev, "ebunand");
596 	if (IS_ERR(ebu_host->ebu))
597 		return PTR_ERR(ebu_host->ebu);
598 
599 	ebu_host->hsnand = devm_platform_ioremap_resource_byname(pdev, "hsnand");
600 	if (IS_ERR(ebu_host->hsnand))
601 		return PTR_ERR(ebu_host->hsnand);
602 
603 	chip_np = of_get_next_child(dev->of_node, NULL);
604 	if (!chip_np)
605 		return dev_err_probe(dev, -EINVAL,
606 				     "Could not find child node for the NAND chip\n");
607 
608 	ret = of_property_read_u32(chip_np, "reg", &cs);
609 	if (ret) {
610 		dev_err(dev, "failed to get chip select: %d\n", ret);
611 		goto err_of_node_put;
612 	}
613 	if (cs >= MAX_CS) {
614 		dev_err(dev, "got invalid chip select: %d\n", cs);
615 		ret = -EINVAL;
616 		goto err_of_node_put;
617 	}
618 
619 	ebu_host->cs_num = cs;
620 
621 	resname = devm_kasprintf(dev, GFP_KERNEL, "nand_cs%d", cs);
622 	if (!resname) {
623 		ret = -ENOMEM;
624 		goto err_of_node_put;
625 	}
626 
627 	ebu_host->cs[cs].chipaddr = devm_platform_ioremap_resource_byname(pdev,
628 									  resname);
629 	if (IS_ERR(ebu_host->cs[cs].chipaddr)) {
630 		ret = PTR_ERR(ebu_host->cs[cs].chipaddr);
631 		goto err_of_node_put;
632 	}
633 
634 	ebu_host->clk = devm_clk_get_enabled(dev, NULL);
635 	if (IS_ERR(ebu_host->clk)) {
636 		ret = dev_err_probe(dev, PTR_ERR(ebu_host->clk),
637 				    "failed to get and enable clock\n");
638 		goto err_of_node_put;
639 	}
640 
641 	ebu_host->dma_tx = dma_request_chan(dev, "tx");
642 	if (IS_ERR(ebu_host->dma_tx)) {
643 		ret = dev_err_probe(dev, PTR_ERR(ebu_host->dma_tx),
644 				    "failed to request DMA tx chan!.\n");
645 		goto err_of_node_put;
646 	}
647 
648 	ebu_host->dma_rx = dma_request_chan(dev, "rx");
649 	if (IS_ERR(ebu_host->dma_rx)) {
650 		ret = dev_err_probe(dev, PTR_ERR(ebu_host->dma_rx),
651 				    "failed to request DMA rx chan!.\n");
652 		ebu_host->dma_rx = NULL;
653 		goto err_cleanup_dma;
654 	}
655 
656 	resname = devm_kasprintf(dev, GFP_KERNEL, "addr_sel%d", cs);
657 	if (!resname) {
658 		ret = -ENOMEM;
659 		goto err_cleanup_dma;
660 	}
661 
662 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resname);
663 	if (!res) {
664 		ret = -EINVAL;
665 		goto err_cleanup_dma;
666 	}
667 	ebu_host->cs[cs].addr_sel = res->start;
668 	writel(ebu_host->cs[cs].addr_sel | EBU_ADDR_MASK(5) | EBU_ADDR_SEL_REGEN,
669 	       ebu_host->ebu + EBU_ADDR_SEL(cs));
670 
671 	nand_set_flash_node(&ebu_host->chip, chip_np);
672 
673 	mtd = nand_to_mtd(&ebu_host->chip);
674 	if (!mtd->name) {
675 		dev_err(ebu_host->dev, "NAND label property is mandatory\n");
676 		ret = -EINVAL;
677 		goto err_cleanup_dma;
678 	}
679 
680 	mtd->dev.parent = dev;
681 	ebu_host->dev = dev;
682 
683 	platform_set_drvdata(pdev, ebu_host);
684 	nand_set_controller_data(&ebu_host->chip, ebu_host);
685 
686 	nand = &ebu_host->chip;
687 	nand->controller = &ebu_host->controller;
688 	nand->controller->ops = &ebu_nand_controller_ops;
689 
690 	/* Scan to find existence of the device */
691 	ret = nand_scan(&ebu_host->chip, 1);
692 	if (ret)
693 		goto err_cleanup_dma;
694 
695 	ret = mtd_device_register(mtd, NULL, 0);
696 	if (ret)
697 		goto err_clean_nand;
698 
699 	return 0;
700 
701 err_clean_nand:
702 	nand_cleanup(&ebu_host->chip);
703 err_cleanup_dma:
704 	ebu_dma_cleanup(ebu_host);
705 err_of_node_put:
706 	of_node_put(chip_np);
707 
708 	return ret;
709 }
710 
711 static void ebu_nand_remove(struct platform_device *pdev)
712 {
713 	struct ebu_nand_controller *ebu_host = platform_get_drvdata(pdev);
714 	int ret;
715 
716 	ret = mtd_device_unregister(nand_to_mtd(&ebu_host->chip));
717 	WARN_ON(ret);
718 	nand_cleanup(&ebu_host->chip);
719 	ebu_nand_disable(&ebu_host->chip);
720 	ebu_dma_cleanup(ebu_host);
721 }
722 
723 static const struct of_device_id ebu_nand_match[] = {
724 	{ .compatible = "intel,lgm-ebunand" },
725 	{}
726 };
727 MODULE_DEVICE_TABLE(of, ebu_nand_match);
728 
729 static struct platform_driver ebu_nand_driver = {
730 	.probe = ebu_nand_probe,
731 	.remove_new = ebu_nand_remove,
732 	.driver = {
733 		.name = "intel-nand-controller",
734 		.of_match_table = ebu_nand_match,
735 	},
736 
737 };
738 module_platform_driver(ebu_nand_driver);
739 
740 MODULE_LICENSE("GPL v2");
741 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
742 MODULE_DESCRIPTION("Intel's LGM External Bus NAND Controller driver");
743