1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Ingenic JZ47xx NAND driver
4  *
5  * Copyright (c) 2015 Imagination Technologies
6  * Author: Alex Smith <alex.smith@imgtec.com>
7  */
8 
9 #include <linux/delay.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/rawnand.h>
22 #include <linux/mtd/partitions.h>
23 
24 #include <linux/jz4780-nemc.h>
25 
26 #include "ingenic_ecc.h"
27 
28 #define DRV_NAME	"ingenic-nand"
29 
30 struct jz_soc_info {
31 	unsigned long data_offset;
32 	unsigned long addr_offset;
33 	unsigned long cmd_offset;
34 	const struct mtd_ooblayout_ops *oob_layout;
35 };
36 
37 struct ingenic_nand_cs {
38 	unsigned int bank;
39 	void __iomem *base;
40 };
41 
42 struct ingenic_nfc {
43 	struct device *dev;
44 	struct ingenic_ecc *ecc;
45 	const struct jz_soc_info *soc_info;
46 	struct nand_controller controller;
47 	unsigned int num_banks;
48 	struct list_head chips;
49 	struct ingenic_nand_cs cs[];
50 };
51 
52 struct ingenic_nand {
53 	struct nand_chip chip;
54 	struct list_head chip_list;
55 
56 	struct gpio_desc *busy_gpio;
57 	struct gpio_desc *wp_gpio;
58 	unsigned int reading: 1;
59 };
60 
61 static inline struct ingenic_nand *to_ingenic_nand(struct mtd_info *mtd)
62 {
63 	return container_of(mtd_to_nand(mtd), struct ingenic_nand, chip);
64 }
65 
66 static inline struct ingenic_nfc *to_ingenic_nfc(struct nand_controller *ctrl)
67 {
68 	return container_of(ctrl, struct ingenic_nfc, controller);
69 }
70 
71 static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section,
72 				 struct mtd_oob_region *oobregion)
73 {
74 	struct nand_chip *chip = mtd_to_nand(mtd);
75 	struct nand_ecc_ctrl *ecc = &chip->ecc;
76 
77 	if (section || !ecc->total)
78 		return -ERANGE;
79 
80 	oobregion->length = ecc->total;
81 	oobregion->offset = 12;
82 
83 	return 0;
84 }
85 
86 static int qi_lb60_ooblayout_free(struct mtd_info *mtd, int section,
87 				  struct mtd_oob_region *oobregion)
88 {
89 	struct nand_chip *chip = mtd_to_nand(mtd);
90 	struct nand_ecc_ctrl *ecc = &chip->ecc;
91 
92 	if (section)
93 		return -ERANGE;
94 
95 	oobregion->length = mtd->oobsize - ecc->total - 12;
96 	oobregion->offset = 12 + ecc->total;
97 
98 	return 0;
99 }
100 
101 static const struct mtd_ooblayout_ops qi_lb60_ooblayout_ops = {
102 	.ecc = qi_lb60_ooblayout_ecc,
103 	.free = qi_lb60_ooblayout_free,
104 };
105 
106 static int jz4725b_ooblayout_ecc(struct mtd_info *mtd, int section,
107 				 struct mtd_oob_region *oobregion)
108 {
109 	struct nand_chip *chip = mtd_to_nand(mtd);
110 	struct nand_ecc_ctrl *ecc = &chip->ecc;
111 
112 	if (section || !ecc->total)
113 		return -ERANGE;
114 
115 	oobregion->length = ecc->total;
116 	oobregion->offset = 3;
117 
118 	return 0;
119 }
120 
121 static int jz4725b_ooblayout_free(struct mtd_info *mtd, int section,
122 				  struct mtd_oob_region *oobregion)
123 {
124 	struct nand_chip *chip = mtd_to_nand(mtd);
125 	struct nand_ecc_ctrl *ecc = &chip->ecc;
126 
127 	if (section)
128 		return -ERANGE;
129 
130 	oobregion->length = mtd->oobsize - ecc->total - 3;
131 	oobregion->offset = 3 + ecc->total;
132 
133 	return 0;
134 }
135 
136 static const struct mtd_ooblayout_ops jz4725b_ooblayout_ops = {
137 	.ecc = jz4725b_ooblayout_ecc,
138 	.free = jz4725b_ooblayout_free,
139 };
140 
141 static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
142 {
143 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
144 
145 	nand->reading = (mode == NAND_ECC_READ);
146 }
147 
148 static int ingenic_nand_ecc_calculate(struct nand_chip *chip, const u8 *dat,
149 				      u8 *ecc_code)
150 {
151 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
152 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
153 	struct ingenic_ecc_params params;
154 
155 	/*
156 	 * Don't need to generate the ECC when reading, the ECC engine does it
157 	 * for us as part of decoding/correction.
158 	 */
159 	if (nand->reading)
160 		return 0;
161 
162 	params.size = nand->chip.ecc.size;
163 	params.bytes = nand->chip.ecc.bytes;
164 	params.strength = nand->chip.ecc.strength;
165 
166 	return ingenic_ecc_calculate(nfc->ecc, &params, dat, ecc_code);
167 }
168 
169 static int ingenic_nand_ecc_correct(struct nand_chip *chip, u8 *dat,
170 				    u8 *read_ecc, u8 *calc_ecc)
171 {
172 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
173 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
174 	struct ingenic_ecc_params params;
175 
176 	params.size = nand->chip.ecc.size;
177 	params.bytes = nand->chip.ecc.bytes;
178 	params.strength = nand->chip.ecc.strength;
179 
180 	return ingenic_ecc_correct(nfc->ecc, &params, dat, read_ecc);
181 }
182 
183 static int ingenic_nand_attach_chip(struct nand_chip *chip)
184 {
185 	struct mtd_info *mtd = nand_to_mtd(chip);
186 	struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
187 	int eccbytes;
188 
189 	if (chip->ecc.strength == 4) {
190 		/* JZ4740 uses 9 bytes of ECC to correct maximum 4 errors */
191 		chip->ecc.bytes = 9;
192 	} else {
193 		chip->ecc.bytes = fls((1 + 8) * chip->ecc.size)	*
194 				  (chip->ecc.strength / 8);
195 	}
196 
197 	switch (chip->ecc.engine_type) {
198 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
199 		if (!nfc->ecc) {
200 			dev_err(nfc->dev, "HW ECC selected, but ECC controller not found\n");
201 			return -ENODEV;
202 		}
203 
204 		chip->ecc.hwctl = ingenic_nand_ecc_hwctl;
205 		chip->ecc.calculate = ingenic_nand_ecc_calculate;
206 		chip->ecc.correct = ingenic_nand_ecc_correct;
207 		fallthrough;
208 	case NAND_ECC_ENGINE_TYPE_SOFT:
209 		dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
210 			 (nfc->ecc) ? "hardware ECC" : "software ECC",
211 			 chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
212 		break;
213 	case NAND_ECC_ENGINE_TYPE_NONE:
214 		dev_info(nfc->dev, "not using ECC\n");
215 		break;
216 	default:
217 		dev_err(nfc->dev, "ECC mode %d not supported\n",
218 			chip->ecc.engine_type);
219 		return -EINVAL;
220 	}
221 
222 	/* The NAND core will generate the ECC layout for SW ECC */
223 	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
224 		return 0;
225 
226 	/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
227 	eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
228 
229 	if (eccbytes > mtd->oobsize - 2) {
230 		dev_err(nfc->dev,
231 			"invalid ECC config: required %d ECC bytes, but only %d are available",
232 			eccbytes, mtd->oobsize - 2);
233 		return -EINVAL;
234 	}
235 
236 	/*
237 	 * The generic layout for BBT markers will most likely overlap with our
238 	 * ECC bytes in the OOB, so move the BBT markers outside the OOB area.
239 	 */
240 	if (chip->bbt_options & NAND_BBT_USE_FLASH)
241 		chip->bbt_options |= NAND_BBT_NO_OOB;
242 
243 	/* For legacy reasons we use a different layout on the qi,lb60 board. */
244 	if (of_machine_is_compatible("qi,lb60"))
245 		mtd_set_ooblayout(mtd, &qi_lb60_ooblayout_ops);
246 	else if (nfc->soc_info->oob_layout)
247 		mtd_set_ooblayout(mtd, nfc->soc_info->oob_layout);
248 	else
249 		mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
250 
251 	return 0;
252 }
253 
254 static int ingenic_nand_exec_instr(struct nand_chip *chip,
255 				   struct ingenic_nand_cs *cs,
256 				   const struct nand_op_instr *instr)
257 {
258 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
259 	struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
260 	unsigned int i;
261 
262 	switch (instr->type) {
263 	case NAND_OP_CMD_INSTR:
264 		writeb(instr->ctx.cmd.opcode,
265 		       cs->base + nfc->soc_info->cmd_offset);
266 		return 0;
267 	case NAND_OP_ADDR_INSTR:
268 		for (i = 0; i < instr->ctx.addr.naddrs; i++)
269 			writeb(instr->ctx.addr.addrs[i],
270 			       cs->base + nfc->soc_info->addr_offset);
271 		return 0;
272 	case NAND_OP_DATA_IN_INSTR:
273 		if (instr->ctx.data.force_8bit ||
274 		    !(chip->options & NAND_BUSWIDTH_16))
275 			ioread8_rep(cs->base + nfc->soc_info->data_offset,
276 				    instr->ctx.data.buf.in,
277 				    instr->ctx.data.len);
278 		else
279 			ioread16_rep(cs->base + nfc->soc_info->data_offset,
280 				     instr->ctx.data.buf.in,
281 				     instr->ctx.data.len);
282 		return 0;
283 	case NAND_OP_DATA_OUT_INSTR:
284 		if (instr->ctx.data.force_8bit ||
285 		    !(chip->options & NAND_BUSWIDTH_16))
286 			iowrite8_rep(cs->base + nfc->soc_info->data_offset,
287 				     instr->ctx.data.buf.out,
288 				     instr->ctx.data.len);
289 		else
290 			iowrite16_rep(cs->base + nfc->soc_info->data_offset,
291 				      instr->ctx.data.buf.out,
292 				      instr->ctx.data.len);
293 		return 0;
294 	case NAND_OP_WAITRDY_INSTR:
295 		if (!nand->busy_gpio)
296 			return nand_soft_waitrdy(chip,
297 						 instr->ctx.waitrdy.timeout_ms);
298 
299 		return nand_gpio_waitrdy(chip, nand->busy_gpio,
300 					 instr->ctx.waitrdy.timeout_ms);
301 	default:
302 		break;
303 	}
304 
305 	return -EINVAL;
306 }
307 
308 static int ingenic_nand_exec_op(struct nand_chip *chip,
309 				const struct nand_operation *op,
310 				bool check_only)
311 {
312 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
313 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
314 	struct ingenic_nand_cs *cs;
315 	unsigned int i;
316 	int ret = 0;
317 
318 	if (check_only)
319 		return 0;
320 
321 	cs = &nfc->cs[op->cs];
322 	jz4780_nemc_assert(nfc->dev, cs->bank, true);
323 	for (i = 0; i < op->ninstrs; i++) {
324 		ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]);
325 		if (ret)
326 			break;
327 
328 		if (op->instrs[i].delay_ns)
329 			ndelay(op->instrs[i].delay_ns);
330 	}
331 	jz4780_nemc_assert(nfc->dev, cs->bank, false);
332 
333 	return ret;
334 }
335 
336 static const struct nand_controller_ops ingenic_nand_controller_ops = {
337 	.attach_chip = ingenic_nand_attach_chip,
338 	.exec_op = ingenic_nand_exec_op,
339 };
340 
341 static int ingenic_nand_init_chip(struct platform_device *pdev,
342 				  struct ingenic_nfc *nfc,
343 				  struct device_node *np,
344 				  unsigned int chipnr)
345 {
346 	struct device *dev = &pdev->dev;
347 	struct ingenic_nand *nand;
348 	struct ingenic_nand_cs *cs;
349 	struct nand_chip *chip;
350 	struct mtd_info *mtd;
351 	const __be32 *reg;
352 	int ret = 0;
353 
354 	cs = &nfc->cs[chipnr];
355 
356 	reg = of_get_property(np, "reg", NULL);
357 	if (!reg)
358 		return -EINVAL;
359 
360 	cs->bank = be32_to_cpu(*reg);
361 
362 	jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
363 
364 	cs->base = devm_platform_ioremap_resource(pdev, chipnr);
365 	if (IS_ERR(cs->base))
366 		return PTR_ERR(cs->base);
367 
368 	nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
369 	if (!nand)
370 		return -ENOMEM;
371 
372 	nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
373 
374 	if (IS_ERR(nand->busy_gpio)) {
375 		ret = PTR_ERR(nand->busy_gpio);
376 		dev_err(dev, "failed to request busy GPIO: %d\n", ret);
377 		return ret;
378 	}
379 
380 	/*
381 	 * The rb-gpios semantics was undocumented and qi,lb60 (along with
382 	 * the ingenic driver) got it wrong. The active state encodes the
383 	 * NAND ready state, which is high level. Since there's no signal
384 	 * inverter on this board, it should be active-high. Let's fix that
385 	 * here for older DTs so we can re-use the generic nand_gpio_waitrdy()
386 	 * helper, and be consistent with what other drivers do.
387 	 */
388 	if (of_machine_is_compatible("qi,lb60") &&
389 	    gpiod_is_active_low(nand->busy_gpio))
390 		gpiod_toggle_active_low(nand->busy_gpio);
391 
392 	nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
393 
394 	if (IS_ERR(nand->wp_gpio)) {
395 		ret = PTR_ERR(nand->wp_gpio);
396 		dev_err(dev, "failed to request WP GPIO: %d\n", ret);
397 		return ret;
398 	}
399 
400 	chip = &nand->chip;
401 	mtd = nand_to_mtd(chip);
402 	mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
403 				   cs->bank);
404 	if (!mtd->name)
405 		return -ENOMEM;
406 	mtd->dev.parent = dev;
407 
408 	chip->options = NAND_NO_SUBPAGE_WRITE;
409 	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
410 	chip->controller = &nfc->controller;
411 	nand_set_flash_node(chip, np);
412 
413 	chip->controller->ops = &ingenic_nand_controller_ops;
414 	ret = nand_scan(chip, 1);
415 	if (ret)
416 		return ret;
417 
418 	ret = mtd_device_register(mtd, NULL, 0);
419 	if (ret) {
420 		nand_cleanup(chip);
421 		return ret;
422 	}
423 
424 	list_add_tail(&nand->chip_list, &nfc->chips);
425 
426 	return 0;
427 }
428 
429 static void ingenic_nand_cleanup_chips(struct ingenic_nfc *nfc)
430 {
431 	struct ingenic_nand *ingenic_chip;
432 	struct nand_chip *chip;
433 	int ret;
434 
435 	while (!list_empty(&nfc->chips)) {
436 		ingenic_chip = list_first_entry(&nfc->chips,
437 						struct ingenic_nand, chip_list);
438 		chip = &ingenic_chip->chip;
439 		ret = mtd_device_unregister(nand_to_mtd(chip));
440 		WARN_ON(ret);
441 		nand_cleanup(chip);
442 		list_del(&ingenic_chip->chip_list);
443 	}
444 }
445 
446 static int ingenic_nand_init_chips(struct ingenic_nfc *nfc,
447 				   struct platform_device *pdev)
448 {
449 	struct device *dev = &pdev->dev;
450 	struct device_node *np;
451 	int i = 0;
452 	int ret;
453 	int num_chips = of_get_child_count(dev->of_node);
454 
455 	if (num_chips > nfc->num_banks) {
456 		dev_err(dev, "found %d chips but only %d banks\n",
457 			num_chips, nfc->num_banks);
458 		return -EINVAL;
459 	}
460 
461 	for_each_child_of_node(dev->of_node, np) {
462 		ret = ingenic_nand_init_chip(pdev, nfc, np, i);
463 		if (ret) {
464 			ingenic_nand_cleanup_chips(nfc);
465 			of_node_put(np);
466 			return ret;
467 		}
468 
469 		i++;
470 	}
471 
472 	return 0;
473 }
474 
475 static int ingenic_nand_probe(struct platform_device *pdev)
476 {
477 	struct device *dev = &pdev->dev;
478 	unsigned int num_banks;
479 	struct ingenic_nfc *nfc;
480 	int ret;
481 
482 	num_banks = jz4780_nemc_num_banks(dev);
483 	if (num_banks == 0) {
484 		dev_err(dev, "no banks found\n");
485 		return -ENODEV;
486 	}
487 
488 	nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL);
489 	if (!nfc)
490 		return -ENOMEM;
491 
492 	nfc->soc_info = device_get_match_data(dev);
493 	if (!nfc->soc_info)
494 		return -EINVAL;
495 
496 	/*
497 	 * Check for ECC HW before we call nand_scan_ident, to prevent us from
498 	 * having to call it again if the ECC driver returns -EPROBE_DEFER.
499 	 */
500 	nfc->ecc = of_ingenic_ecc_get(dev->of_node);
501 	if (IS_ERR(nfc->ecc))
502 		return PTR_ERR(nfc->ecc);
503 
504 	nfc->dev = dev;
505 	nfc->num_banks = num_banks;
506 
507 	nand_controller_init(&nfc->controller);
508 	INIT_LIST_HEAD(&nfc->chips);
509 
510 	ret = ingenic_nand_init_chips(nfc, pdev);
511 	if (ret) {
512 		if (nfc->ecc)
513 			ingenic_ecc_release(nfc->ecc);
514 		return ret;
515 	}
516 
517 	platform_set_drvdata(pdev, nfc);
518 	return 0;
519 }
520 
521 static int ingenic_nand_remove(struct platform_device *pdev)
522 {
523 	struct ingenic_nfc *nfc = platform_get_drvdata(pdev);
524 
525 	if (nfc->ecc)
526 		ingenic_ecc_release(nfc->ecc);
527 
528 	ingenic_nand_cleanup_chips(nfc);
529 
530 	return 0;
531 }
532 
533 static const struct jz_soc_info jz4740_soc_info = {
534 	.data_offset = 0x00000000,
535 	.cmd_offset = 0x00008000,
536 	.addr_offset = 0x00010000,
537 };
538 
539 static const struct jz_soc_info jz4725b_soc_info = {
540 	.data_offset = 0x00000000,
541 	.cmd_offset = 0x00008000,
542 	.addr_offset = 0x00010000,
543 	.oob_layout = &jz4725b_ooblayout_ops,
544 };
545 
546 static const struct jz_soc_info jz4780_soc_info = {
547 	.data_offset = 0x00000000,
548 	.cmd_offset = 0x00400000,
549 	.addr_offset = 0x00800000,
550 };
551 
552 static const struct of_device_id ingenic_nand_dt_match[] = {
553 	{ .compatible = "ingenic,jz4740-nand", .data = &jz4740_soc_info },
554 	{ .compatible = "ingenic,jz4725b-nand", .data = &jz4725b_soc_info },
555 	{ .compatible = "ingenic,jz4780-nand", .data = &jz4780_soc_info },
556 	{},
557 };
558 MODULE_DEVICE_TABLE(of, ingenic_nand_dt_match);
559 
560 static struct platform_driver ingenic_nand_driver = {
561 	.probe		= ingenic_nand_probe,
562 	.remove		= ingenic_nand_remove,
563 	.driver	= {
564 		.name	= DRV_NAME,
565 		.of_match_table = of_match_ptr(ingenic_nand_dt_match),
566 	},
567 };
568 module_platform_driver(ingenic_nand_driver);
569 
570 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
571 MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
572 MODULE_DESCRIPTION("Ingenic JZ47xx NAND driver");
573 MODULE_LICENSE("GPL v2");
574