1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Ingenic JZ47xx NAND driver
4  *
5  * Copyright (c) 2015 Imagination Technologies
6  * Author: Alex Smith <alex.smith@imgtec.com>
7  */
8 
9 #include <linux/delay.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/rawnand.h>
22 #include <linux/mtd/partitions.h>
23 
24 #include <linux/jz4780-nemc.h>
25 
26 #include "ingenic_ecc.h"
27 
28 #define DRV_NAME	"ingenic-nand"
29 
30 /* Command delay when there is no R/B pin. */
31 #define RB_DELAY_US	100
32 
33 struct jz_soc_info {
34 	unsigned long data_offset;
35 	unsigned long addr_offset;
36 	unsigned long cmd_offset;
37 	const struct mtd_ooblayout_ops *oob_layout;
38 };
39 
40 struct ingenic_nand_cs {
41 	unsigned int bank;
42 	void __iomem *base;
43 };
44 
45 struct ingenic_nfc {
46 	struct device *dev;
47 	struct ingenic_ecc *ecc;
48 	const struct jz_soc_info *soc_info;
49 	struct nand_controller controller;
50 	unsigned int num_banks;
51 	struct list_head chips;
52 	int selected;
53 	struct ingenic_nand_cs cs[];
54 };
55 
56 struct ingenic_nand {
57 	struct nand_chip chip;
58 	struct list_head chip_list;
59 
60 	struct gpio_desc *busy_gpio;
61 	struct gpio_desc *wp_gpio;
62 	unsigned int reading: 1;
63 };
64 
65 static inline struct ingenic_nand *to_ingenic_nand(struct mtd_info *mtd)
66 {
67 	return container_of(mtd_to_nand(mtd), struct ingenic_nand, chip);
68 }
69 
70 static inline struct ingenic_nfc *to_ingenic_nfc(struct nand_controller *ctrl)
71 {
72 	return container_of(ctrl, struct ingenic_nfc, controller);
73 }
74 
75 static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section,
76 				 struct mtd_oob_region *oobregion)
77 {
78 	struct nand_chip *chip = mtd_to_nand(mtd);
79 	struct nand_ecc_ctrl *ecc = &chip->ecc;
80 
81 	if (section || !ecc->total)
82 		return -ERANGE;
83 
84 	oobregion->length = ecc->total;
85 	oobregion->offset = 12;
86 
87 	return 0;
88 }
89 
90 static int qi_lb60_ooblayout_free(struct mtd_info *mtd, int section,
91 				  struct mtd_oob_region *oobregion)
92 {
93 	struct nand_chip *chip = mtd_to_nand(mtd);
94 	struct nand_ecc_ctrl *ecc = &chip->ecc;
95 
96 	if (section)
97 		return -ERANGE;
98 
99 	oobregion->length = mtd->oobsize - ecc->total - 12;
100 	oobregion->offset = 12 + ecc->total;
101 
102 	return 0;
103 }
104 
105 const struct mtd_ooblayout_ops qi_lb60_ooblayout_ops = {
106 	.ecc = qi_lb60_ooblayout_ecc,
107 	.free = qi_lb60_ooblayout_free,
108 };
109 
110 static int jz4725b_ooblayout_ecc(struct mtd_info *mtd, int section,
111 				 struct mtd_oob_region *oobregion)
112 {
113 	struct nand_chip *chip = mtd_to_nand(mtd);
114 	struct nand_ecc_ctrl *ecc = &chip->ecc;
115 
116 	if (section || !ecc->total)
117 		return -ERANGE;
118 
119 	oobregion->length = ecc->total;
120 	oobregion->offset = 3;
121 
122 	return 0;
123 }
124 
125 static int jz4725b_ooblayout_free(struct mtd_info *mtd, int section,
126 				  struct mtd_oob_region *oobregion)
127 {
128 	struct nand_chip *chip = mtd_to_nand(mtd);
129 	struct nand_ecc_ctrl *ecc = &chip->ecc;
130 
131 	if (section)
132 		return -ERANGE;
133 
134 	oobregion->length = mtd->oobsize - ecc->total - 3;
135 	oobregion->offset = 3 + ecc->total;
136 
137 	return 0;
138 }
139 
140 static const struct mtd_ooblayout_ops jz4725b_ooblayout_ops = {
141 	.ecc = jz4725b_ooblayout_ecc,
142 	.free = jz4725b_ooblayout_free,
143 };
144 
145 static void ingenic_nand_select_chip(struct nand_chip *chip, int chipnr)
146 {
147 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
148 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
149 	struct ingenic_nand_cs *cs;
150 
151 	/* Ensure the currently selected chip is deasserted. */
152 	if (chipnr == -1 && nfc->selected >= 0) {
153 		cs = &nfc->cs[nfc->selected];
154 		jz4780_nemc_assert(nfc->dev, cs->bank, false);
155 	}
156 
157 	nfc->selected = chipnr;
158 }
159 
160 static void ingenic_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
161 				  unsigned int ctrl)
162 {
163 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
164 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
165 	struct ingenic_nand_cs *cs;
166 
167 	if (WARN_ON(nfc->selected < 0))
168 		return;
169 
170 	cs = &nfc->cs[nfc->selected];
171 
172 	jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
173 
174 	if (cmd == NAND_CMD_NONE)
175 		return;
176 
177 	if (ctrl & NAND_ALE)
178 		writeb(cmd, cs->base + nfc->soc_info->addr_offset);
179 	else if (ctrl & NAND_CLE)
180 		writeb(cmd, cs->base + nfc->soc_info->cmd_offset);
181 }
182 
183 static int ingenic_nand_dev_ready(struct nand_chip *chip)
184 {
185 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
186 
187 	return !gpiod_get_value_cansleep(nand->busy_gpio);
188 }
189 
190 static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
191 {
192 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
193 
194 	nand->reading = (mode == NAND_ECC_READ);
195 }
196 
197 static int ingenic_nand_ecc_calculate(struct nand_chip *chip, const u8 *dat,
198 				      u8 *ecc_code)
199 {
200 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
201 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
202 	struct ingenic_ecc_params params;
203 
204 	/*
205 	 * Don't need to generate the ECC when reading, the ECC engine does it
206 	 * for us as part of decoding/correction.
207 	 */
208 	if (nand->reading)
209 		return 0;
210 
211 	params.size = nand->chip.ecc.size;
212 	params.bytes = nand->chip.ecc.bytes;
213 	params.strength = nand->chip.ecc.strength;
214 
215 	return ingenic_ecc_calculate(nfc->ecc, &params, dat, ecc_code);
216 }
217 
218 static int ingenic_nand_ecc_correct(struct nand_chip *chip, u8 *dat,
219 				    u8 *read_ecc, u8 *calc_ecc)
220 {
221 	struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
222 	struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
223 	struct ingenic_ecc_params params;
224 
225 	params.size = nand->chip.ecc.size;
226 	params.bytes = nand->chip.ecc.bytes;
227 	params.strength = nand->chip.ecc.strength;
228 
229 	return ingenic_ecc_correct(nfc->ecc, &params, dat, read_ecc);
230 }
231 
232 static int ingenic_nand_attach_chip(struct nand_chip *chip)
233 {
234 	struct mtd_info *mtd = nand_to_mtd(chip);
235 	struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
236 	int eccbytes;
237 
238 	if (chip->ecc.strength == 4) {
239 		/* JZ4740 uses 9 bytes of ECC to correct maximum 4 errors */
240 		chip->ecc.bytes = 9;
241 	} else {
242 		chip->ecc.bytes = fls((1 + 8) * chip->ecc.size)	*
243 				  (chip->ecc.strength / 8);
244 	}
245 
246 	switch (chip->ecc.mode) {
247 	case NAND_ECC_HW:
248 		if (!nfc->ecc) {
249 			dev_err(nfc->dev, "HW ECC selected, but ECC controller not found\n");
250 			return -ENODEV;
251 		}
252 
253 		chip->ecc.hwctl = ingenic_nand_ecc_hwctl;
254 		chip->ecc.calculate = ingenic_nand_ecc_calculate;
255 		chip->ecc.correct = ingenic_nand_ecc_correct;
256 		/* fall through */
257 	case NAND_ECC_SOFT:
258 		dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n",
259 			 (nfc->ecc) ? "hardware ECC" : "software ECC",
260 			 chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
261 		break;
262 	case NAND_ECC_NONE:
263 		dev_info(nfc->dev, "not using ECC\n");
264 		break;
265 	default:
266 		dev_err(nfc->dev, "ECC mode %d not supported\n",
267 			chip->ecc.mode);
268 		return -EINVAL;
269 	}
270 
271 	/* The NAND core will generate the ECC layout for SW ECC */
272 	if (chip->ecc.mode != NAND_ECC_HW)
273 		return 0;
274 
275 	/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
276 	eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
277 
278 	if (eccbytes > mtd->oobsize - 2) {
279 		dev_err(nfc->dev,
280 			"invalid ECC config: required %d ECC bytes, but only %d are available",
281 			eccbytes, mtd->oobsize - 2);
282 		return -EINVAL;
283 	}
284 
285 	/*
286 	 * The generic layout for BBT markers will most likely overlap with our
287 	 * ECC bytes in the OOB, so move the BBT markers outside the OOB area.
288 	 */
289 	if (chip->bbt_options & NAND_BBT_USE_FLASH)
290 		chip->bbt_options |= NAND_BBT_NO_OOB;
291 
292 	/* For legacy reasons we use a different layout on the qi,lb60 board. */
293 	if (of_machine_is_compatible("qi,lb60"))
294 		mtd_set_ooblayout(mtd, &qi_lb60_ooblayout_ops);
295 	else
296 		mtd_set_ooblayout(mtd, nfc->soc_info->oob_layout);
297 
298 	return 0;
299 }
300 
301 static const struct nand_controller_ops ingenic_nand_controller_ops = {
302 	.attach_chip = ingenic_nand_attach_chip,
303 };
304 
305 static int ingenic_nand_init_chip(struct platform_device *pdev,
306 				  struct ingenic_nfc *nfc,
307 				  struct device_node *np,
308 				  unsigned int chipnr)
309 {
310 	struct device *dev = &pdev->dev;
311 	struct ingenic_nand *nand;
312 	struct ingenic_nand_cs *cs;
313 	struct nand_chip *chip;
314 	struct mtd_info *mtd;
315 	const __be32 *reg;
316 	int ret = 0;
317 
318 	cs = &nfc->cs[chipnr];
319 
320 	reg = of_get_property(np, "reg", NULL);
321 	if (!reg)
322 		return -EINVAL;
323 
324 	cs->bank = be32_to_cpu(*reg);
325 
326 	jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
327 
328 	cs->base = devm_platform_ioremap_resource(pdev, chipnr);
329 	if (IS_ERR(cs->base))
330 		return PTR_ERR(cs->base);
331 
332 	nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
333 	if (!nand)
334 		return -ENOMEM;
335 
336 	nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
337 
338 	if (IS_ERR(nand->busy_gpio)) {
339 		ret = PTR_ERR(nand->busy_gpio);
340 		dev_err(dev, "failed to request busy GPIO: %d\n", ret);
341 		return ret;
342 	} else if (nand->busy_gpio) {
343 		nand->chip.legacy.dev_ready = ingenic_nand_dev_ready;
344 	}
345 
346 	nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
347 
348 	if (IS_ERR(nand->wp_gpio)) {
349 		ret = PTR_ERR(nand->wp_gpio);
350 		dev_err(dev, "failed to request WP GPIO: %d\n", ret);
351 		return ret;
352 	}
353 
354 	chip = &nand->chip;
355 	mtd = nand_to_mtd(chip);
356 	mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
357 				   cs->bank);
358 	if (!mtd->name)
359 		return -ENOMEM;
360 	mtd->dev.parent = dev;
361 
362 	chip->legacy.IO_ADDR_R = cs->base + nfc->soc_info->data_offset;
363 	chip->legacy.IO_ADDR_W = cs->base + nfc->soc_info->data_offset;
364 	chip->legacy.chip_delay = RB_DELAY_US;
365 	chip->options = NAND_NO_SUBPAGE_WRITE;
366 	chip->legacy.select_chip = ingenic_nand_select_chip;
367 	chip->legacy.cmd_ctrl = ingenic_nand_cmd_ctrl;
368 	chip->ecc.mode = NAND_ECC_HW;
369 	chip->controller = &nfc->controller;
370 	nand_set_flash_node(chip, np);
371 
372 	chip->controller->ops = &ingenic_nand_controller_ops;
373 	ret = nand_scan(chip, 1);
374 	if (ret)
375 		return ret;
376 
377 	ret = mtd_device_register(mtd, NULL, 0);
378 	if (ret) {
379 		nand_release(chip);
380 		return ret;
381 	}
382 
383 	list_add_tail(&nand->chip_list, &nfc->chips);
384 
385 	return 0;
386 }
387 
388 static void ingenic_nand_cleanup_chips(struct ingenic_nfc *nfc)
389 {
390 	struct ingenic_nand *chip;
391 
392 	while (!list_empty(&nfc->chips)) {
393 		chip = list_first_entry(&nfc->chips,
394 					struct ingenic_nand, chip_list);
395 		nand_release(&chip->chip);
396 		list_del(&chip->chip_list);
397 	}
398 }
399 
400 static int ingenic_nand_init_chips(struct ingenic_nfc *nfc,
401 				   struct platform_device *pdev)
402 {
403 	struct device *dev = &pdev->dev;
404 	struct device_node *np;
405 	int i = 0;
406 	int ret;
407 	int num_chips = of_get_child_count(dev->of_node);
408 
409 	if (num_chips > nfc->num_banks) {
410 		dev_err(dev, "found %d chips but only %d banks\n",
411 			num_chips, nfc->num_banks);
412 		return -EINVAL;
413 	}
414 
415 	for_each_child_of_node(dev->of_node, np) {
416 		ret = ingenic_nand_init_chip(pdev, nfc, np, i);
417 		if (ret) {
418 			ingenic_nand_cleanup_chips(nfc);
419 			of_node_put(np);
420 			return ret;
421 		}
422 
423 		i++;
424 	}
425 
426 	return 0;
427 }
428 
429 static int ingenic_nand_probe(struct platform_device *pdev)
430 {
431 	struct device *dev = &pdev->dev;
432 	unsigned int num_banks;
433 	struct ingenic_nfc *nfc;
434 	int ret;
435 
436 	num_banks = jz4780_nemc_num_banks(dev);
437 	if (num_banks == 0) {
438 		dev_err(dev, "no banks found\n");
439 		return -ENODEV;
440 	}
441 
442 	nfc = devm_kzalloc(dev, struct_size(nfc, cs, num_banks), GFP_KERNEL);
443 	if (!nfc)
444 		return -ENOMEM;
445 
446 	nfc->soc_info = device_get_match_data(dev);
447 	if (!nfc->soc_info)
448 		return -EINVAL;
449 
450 	/*
451 	 * Check for ECC HW before we call nand_scan_ident, to prevent us from
452 	 * having to call it again if the ECC driver returns -EPROBE_DEFER.
453 	 */
454 	nfc->ecc = of_ingenic_ecc_get(dev->of_node);
455 	if (IS_ERR(nfc->ecc))
456 		return PTR_ERR(nfc->ecc);
457 
458 	nfc->dev = dev;
459 	nfc->num_banks = num_banks;
460 
461 	nand_controller_init(&nfc->controller);
462 	INIT_LIST_HEAD(&nfc->chips);
463 
464 	ret = ingenic_nand_init_chips(nfc, pdev);
465 	if (ret) {
466 		if (nfc->ecc)
467 			ingenic_ecc_release(nfc->ecc);
468 		return ret;
469 	}
470 
471 	platform_set_drvdata(pdev, nfc);
472 	return 0;
473 }
474 
475 static int ingenic_nand_remove(struct platform_device *pdev)
476 {
477 	struct ingenic_nfc *nfc = platform_get_drvdata(pdev);
478 
479 	if (nfc->ecc)
480 		ingenic_ecc_release(nfc->ecc);
481 
482 	ingenic_nand_cleanup_chips(nfc);
483 
484 	return 0;
485 }
486 
487 static const struct jz_soc_info jz4740_soc_info = {
488 	.data_offset = 0x00000000,
489 	.cmd_offset = 0x00008000,
490 	.addr_offset = 0x00010000,
491 	.oob_layout = &nand_ooblayout_lp_ops,
492 };
493 
494 static const struct jz_soc_info jz4725b_soc_info = {
495 	.data_offset = 0x00000000,
496 	.cmd_offset = 0x00008000,
497 	.addr_offset = 0x00010000,
498 	.oob_layout = &jz4725b_ooblayout_ops,
499 };
500 
501 static const struct jz_soc_info jz4780_soc_info = {
502 	.data_offset = 0x00000000,
503 	.cmd_offset = 0x00400000,
504 	.addr_offset = 0x00800000,
505 	.oob_layout = &nand_ooblayout_lp_ops,
506 };
507 
508 static const struct of_device_id ingenic_nand_dt_match[] = {
509 	{ .compatible = "ingenic,jz4740-nand", .data = &jz4740_soc_info },
510 	{ .compatible = "ingenic,jz4725b-nand", .data = &jz4725b_soc_info },
511 	{ .compatible = "ingenic,jz4780-nand", .data = &jz4780_soc_info },
512 	{},
513 };
514 MODULE_DEVICE_TABLE(of, ingenic_nand_dt_match);
515 
516 static struct platform_driver ingenic_nand_driver = {
517 	.probe		= ingenic_nand_probe,
518 	.remove		= ingenic_nand_remove,
519 	.driver	= {
520 		.name	= DRV_NAME,
521 		.of_match_table = of_match_ptr(ingenic_nand_dt_match),
522 	},
523 };
524 module_platform_driver(ingenic_nand_driver);
525 
526 MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
527 MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
528 MODULE_DESCRIPTION("Ingenic JZ47xx NAND driver");
529 MODULE_LICENSE("GPL v2");
530