1 /* 2 * Freescale GPMI NAND Flash Driver 3 * 4 * Copyright 2008-2011 Freescale Semiconductor, Inc. 5 * Copyright 2008 Embedded Alley Solutions, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 #ifndef __GPMI_NAND_GPMI_REGS_H 22 #define __GPMI_NAND_GPMI_REGS_H 23 24 #define HW_GPMI_CTRL0 0x00000000 25 #define HW_GPMI_CTRL0_SET 0x00000004 26 #define HW_GPMI_CTRL0_CLR 0x00000008 27 #define HW_GPMI_CTRL0_TOG 0x0000000c 28 29 #define BP_GPMI_CTRL0_COMMAND_MODE 24 30 #define BM_GPMI_CTRL0_COMMAND_MODE (3 << BP_GPMI_CTRL0_COMMAND_MODE) 31 #define BF_GPMI_CTRL0_COMMAND_MODE(v) \ 32 (((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE) 33 #define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 34 #define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 35 #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 36 #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 37 38 #define BM_GPMI_CTRL0_WORD_LENGTH (1 << 23) 39 #define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 40 #define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 41 42 /* 43 * Difference in LOCK_CS between imx23 and imx28 : 44 * This bit may impact the _POWER_ consumption. So some chips 45 * do not set it. 46 */ 47 #define MX23_BP_GPMI_CTRL0_LOCK_CS 22 48 #define MX28_BP_GPMI_CTRL0_LOCK_CS 27 49 #define LOCK_CS_ENABLE 0x1 50 #define BF_GPMI_CTRL0_LOCK_CS(v, x) 0x0 51 52 /* Difference in CS between imx23 and imx28 */ 53 #define BP_GPMI_CTRL0_CS 20 54 #define MX23_BM_GPMI_CTRL0_CS (3 << BP_GPMI_CTRL0_CS) 55 #define MX28_BM_GPMI_CTRL0_CS (7 << BP_GPMI_CTRL0_CS) 56 #define BF_GPMI_CTRL0_CS(v, x) (((v) << BP_GPMI_CTRL0_CS) & \ 57 (GPMI_IS_MX23((x)) \ 58 ? MX23_BM_GPMI_CTRL0_CS \ 59 : MX28_BM_GPMI_CTRL0_CS)) 60 61 #define BP_GPMI_CTRL0_ADDRESS 17 62 #define BM_GPMI_CTRL0_ADDRESS (3 << BP_GPMI_CTRL0_ADDRESS) 63 #define BF_GPMI_CTRL0_ADDRESS(v) \ 64 (((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS) 65 #define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 66 #define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 67 #define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 68 69 #define BM_GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) 70 #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 71 #define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 72 73 #define BP_GPMI_CTRL0_XFER_COUNT 0 74 #define BM_GPMI_CTRL0_XFER_COUNT (0xffff << BP_GPMI_CTRL0_XFER_COUNT) 75 #define BF_GPMI_CTRL0_XFER_COUNT(v) \ 76 (((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT) 77 78 #define HW_GPMI_COMPARE 0x00000010 79 80 #define HW_GPMI_ECCCTRL 0x00000020 81 #define HW_GPMI_ECCCTRL_SET 0x00000024 82 #define HW_GPMI_ECCCTRL_CLR 0x00000028 83 #define HW_GPMI_ECCCTRL_TOG 0x0000002c 84 85 #define BP_GPMI_ECCCTRL_ECC_CMD 13 86 #define BM_GPMI_ECCCTRL_ECC_CMD (3 << BP_GPMI_ECCCTRL_ECC_CMD) 87 #define BF_GPMI_ECCCTRL_ECC_CMD(v) \ 88 (((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD) 89 #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0 90 #define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1 91 92 #define BM_GPMI_ECCCTRL_ENABLE_ECC (1 << 12) 93 #define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 94 #define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 95 96 #define BP_GPMI_ECCCTRL_BUFFER_MASK 0 97 #define BM_GPMI_ECCCTRL_BUFFER_MASK (0x1ff << BP_GPMI_ECCCTRL_BUFFER_MASK) 98 #define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \ 99 (((v) << BP_GPMI_ECCCTRL_BUFFER_MASK) & BM_GPMI_ECCCTRL_BUFFER_MASK) 100 #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 101 #define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF 102 103 #define HW_GPMI_ECCCOUNT 0x00000030 104 #define HW_GPMI_PAYLOAD 0x00000040 105 #define HW_GPMI_AUXILIARY 0x00000050 106 #define HW_GPMI_CTRL1 0x00000060 107 #define HW_GPMI_CTRL1_SET 0x00000064 108 #define HW_GPMI_CTRL1_CLR 0x00000068 109 #define HW_GPMI_CTRL1_TOG 0x0000006c 110 111 #define BP_GPMI_CTRL1_DECOUPLE_CS 24 112 #define BM_GPMI_CTRL1_DECOUPLE_CS (1 << BP_GPMI_CTRL1_DECOUPLE_CS) 113 114 #define BP_GPMI_CTRL1_WRN_DLY_SEL 22 115 #define BM_GPMI_CTRL1_WRN_DLY_SEL (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL) 116 #define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \ 117 (((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL) 118 #define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0 119 #define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1 120 #define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2 121 #define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3 122 123 #define BM_GPMI_CTRL1_BCH_MODE (1 << 18) 124 125 #define BP_GPMI_CTRL1_DLL_ENABLE 17 126 #define BM_GPMI_CTRL1_DLL_ENABLE (1 << BP_GPMI_CTRL1_DLL_ENABLE) 127 128 #define BP_GPMI_CTRL1_HALF_PERIOD 16 129 #define BM_GPMI_CTRL1_HALF_PERIOD (1 << BP_GPMI_CTRL1_HALF_PERIOD) 130 131 #define BP_GPMI_CTRL1_RDN_DELAY 12 132 #define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY) 133 #define BF_GPMI_CTRL1_RDN_DELAY(v) \ 134 (((v) << BP_GPMI_CTRL1_RDN_DELAY) & BM_GPMI_CTRL1_RDN_DELAY) 135 136 #define BM_GPMI_CTRL1_DEV_RESET (1 << 3) 137 #define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 138 #define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 139 140 #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) 141 #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 142 #define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 143 144 #define BM_GPMI_CTRL1_CAMERA_MODE (1 << 1) 145 #define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 146 #define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 147 148 #define BM_GPMI_CTRL1_GPMI_MODE (1 << 0) 149 150 #define BM_GPMI_CTRL1_CLEAR_MASK (BM_GPMI_CTRL1_WRN_DLY_SEL | \ 151 BM_GPMI_CTRL1_DLL_ENABLE | \ 152 BM_GPMI_CTRL1_RDN_DELAY | \ 153 BM_GPMI_CTRL1_HALF_PERIOD) 154 155 #define HW_GPMI_TIMING0 0x00000070 156 157 #define BP_GPMI_TIMING0_ADDRESS_SETUP 16 158 #define BM_GPMI_TIMING0_ADDRESS_SETUP (0xff << BP_GPMI_TIMING0_ADDRESS_SETUP) 159 #define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ 160 (((v) << BP_GPMI_TIMING0_ADDRESS_SETUP) & BM_GPMI_TIMING0_ADDRESS_SETUP) 161 162 #define BP_GPMI_TIMING0_DATA_HOLD 8 163 #define BM_GPMI_TIMING0_DATA_HOLD (0xff << BP_GPMI_TIMING0_DATA_HOLD) 164 #define BF_GPMI_TIMING0_DATA_HOLD(v) \ 165 (((v) << BP_GPMI_TIMING0_DATA_HOLD) & BM_GPMI_TIMING0_DATA_HOLD) 166 167 #define BP_GPMI_TIMING0_DATA_SETUP 0 168 #define BM_GPMI_TIMING0_DATA_SETUP (0xff << BP_GPMI_TIMING0_DATA_SETUP) 169 #define BF_GPMI_TIMING0_DATA_SETUP(v) \ 170 (((v) << BP_GPMI_TIMING0_DATA_SETUP) & BM_GPMI_TIMING0_DATA_SETUP) 171 172 #define HW_GPMI_TIMING1 0x00000080 173 #define BP_GPMI_TIMING1_BUSY_TIMEOUT 16 174 #define BM_GPMI_TIMING1_BUSY_TIMEOUT (0xffff << BP_GPMI_TIMING1_BUSY_TIMEOUT) 175 #define BF_GPMI_TIMING1_BUSY_TIMEOUT(v) \ 176 (((v) << BP_GPMI_TIMING1_BUSY_TIMEOUT) & BM_GPMI_TIMING1_BUSY_TIMEOUT) 177 178 #define HW_GPMI_TIMING2 0x00000090 179 #define HW_GPMI_DATA 0x000000a0 180 181 /* MX28 uses this to detect READY. */ 182 #define HW_GPMI_STAT 0x000000b0 183 #define MX28_BP_GPMI_STAT_READY_BUSY 24 184 #define MX28_BM_GPMI_STAT_READY_BUSY (0xff << MX28_BP_GPMI_STAT_READY_BUSY) 185 #define MX28_BF_GPMI_STAT_READY_BUSY(v) \ 186 (((v) << MX28_BP_GPMI_STAT_READY_BUSY) & MX28_BM_GPMI_STAT_READY_BUSY) 187 188 /* MX23 uses this to detect READY. */ 189 #define HW_GPMI_DEBUG 0x000000c0 190 #define MX23_BP_GPMI_DEBUG_READY0 28 191 #define MX23_BM_GPMI_DEBUG_READY0 (1 << MX23_BP_GPMI_DEBUG_READY0) 192 #endif 193