1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Updated, and converted to generic GPIO based driver by Russell King. 4 * 5 * Written by Ben Dooks <ben@simtec.co.uk> 6 * Based on 2.4 version by Mark Whittaker 7 * 8 * © 2004 Simtec Electronics 9 * 10 * Device driver for NAND flash that uses a memory mapped interface to 11 * read/write the NAND commands and data, and GPIO pins for control signals 12 * (the DT binding refers to this as "GPIO assisted NAND flash") 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/err.h> 17 #include <linux/slab.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/io.h> 22 #include <linux/mtd/mtd.h> 23 #include <linux/mtd/rawnand.h> 24 #include <linux/mtd/partitions.h> 25 #include <linux/mtd/nand-gpio.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/delay.h> 29 30 struct gpiomtd { 31 struct nand_controller base; 32 void __iomem *io; 33 void __iomem *io_sync; 34 struct nand_chip nand_chip; 35 struct gpio_nand_platdata plat; 36 struct gpio_desc *nce; /* Optional chip enable */ 37 struct gpio_desc *cle; 38 struct gpio_desc *ale; 39 struct gpio_desc *rdy; 40 struct gpio_desc *nwp; /* Optional write protection */ 41 }; 42 43 static inline struct gpiomtd *gpio_nand_getpriv(struct mtd_info *mtd) 44 { 45 return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip); 46 } 47 48 49 #ifdef CONFIG_ARM 50 /* gpio_nand_dosync() 51 * 52 * Make sure the GPIO state changes occur in-order with writes to NAND 53 * memory region. 54 * Needed on PXA due to bus-reordering within the SoC itself (see section on 55 * I/O ordering in PXA manual (section 2.3, p35) 56 */ 57 static void gpio_nand_dosync(struct gpiomtd *gpiomtd) 58 { 59 unsigned long tmp; 60 61 if (gpiomtd->io_sync) { 62 /* 63 * Linux memory barriers don't cater for what's required here. 64 * What's required is what's here - a read from a separate 65 * region with a dependency on that read. 66 */ 67 tmp = readl(gpiomtd->io_sync); 68 asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp)); 69 } 70 } 71 #else 72 static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {} 73 #endif 74 75 static int gpio_nand_exec_instr(struct nand_chip *chip, 76 const struct nand_op_instr *instr) 77 { 78 struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip)); 79 unsigned int i; 80 81 switch (instr->type) { 82 case NAND_OP_CMD_INSTR: 83 gpio_nand_dosync(gpiomtd); 84 gpiod_set_value(gpiomtd->cle, 1); 85 gpio_nand_dosync(gpiomtd); 86 writeb(instr->ctx.cmd.opcode, gpiomtd->io); 87 gpio_nand_dosync(gpiomtd); 88 gpiod_set_value(gpiomtd->cle, 0); 89 return 0; 90 91 case NAND_OP_ADDR_INSTR: 92 gpio_nand_dosync(gpiomtd); 93 gpiod_set_value(gpiomtd->ale, 1); 94 gpio_nand_dosync(gpiomtd); 95 for (i = 0; i < instr->ctx.addr.naddrs; i++) 96 writeb(instr->ctx.addr.addrs[i], gpiomtd->io); 97 gpio_nand_dosync(gpiomtd); 98 gpiod_set_value(gpiomtd->ale, 0); 99 return 0; 100 101 case NAND_OP_DATA_IN_INSTR: 102 gpio_nand_dosync(gpiomtd); 103 if ((chip->options & NAND_BUSWIDTH_16) && 104 !instr->ctx.data.force_8bit) 105 ioread16_rep(gpiomtd->io, instr->ctx.data.buf.in, 106 instr->ctx.data.len / 2); 107 else 108 ioread8_rep(gpiomtd->io, instr->ctx.data.buf.in, 109 instr->ctx.data.len); 110 return 0; 111 112 case NAND_OP_DATA_OUT_INSTR: 113 gpio_nand_dosync(gpiomtd); 114 if ((chip->options & NAND_BUSWIDTH_16) && 115 !instr->ctx.data.force_8bit) 116 iowrite16_rep(gpiomtd->io, instr->ctx.data.buf.out, 117 instr->ctx.data.len / 2); 118 else 119 iowrite8_rep(gpiomtd->io, instr->ctx.data.buf.out, 120 instr->ctx.data.len); 121 return 0; 122 123 case NAND_OP_WAITRDY_INSTR: 124 if (!gpiomtd->rdy) 125 return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms); 126 127 return nand_gpio_waitrdy(chip, gpiomtd->rdy, 128 instr->ctx.waitrdy.timeout_ms); 129 130 default: 131 return -EINVAL; 132 } 133 134 return 0; 135 } 136 137 static int gpio_nand_exec_op(struct nand_chip *chip, 138 const struct nand_operation *op, 139 bool check_only) 140 { 141 struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip)); 142 unsigned int i; 143 int ret = 0; 144 145 if (check_only) 146 return 0; 147 148 gpio_nand_dosync(gpiomtd); 149 gpiod_set_value(gpiomtd->nce, 0); 150 for (i = 0; i < op->ninstrs; i++) { 151 ret = gpio_nand_exec_instr(chip, &op->instrs[i]); 152 if (ret) 153 break; 154 155 if (op->instrs[i].delay_ns) 156 ndelay(op->instrs[i].delay_ns); 157 } 158 gpio_nand_dosync(gpiomtd); 159 gpiod_set_value(gpiomtd->nce, 1); 160 161 return ret; 162 } 163 164 static const struct nand_controller_ops gpio_nand_ops = { 165 .exec_op = gpio_nand_exec_op, 166 }; 167 168 #ifdef CONFIG_OF 169 static const struct of_device_id gpio_nand_id_table[] = { 170 { .compatible = "gpio-control-nand" }, 171 {} 172 }; 173 MODULE_DEVICE_TABLE(of, gpio_nand_id_table); 174 175 static int gpio_nand_get_config_of(const struct device *dev, 176 struct gpio_nand_platdata *plat) 177 { 178 u32 val; 179 180 if (!dev->of_node) 181 return -ENODEV; 182 183 if (!of_property_read_u32(dev->of_node, "bank-width", &val)) { 184 if (val == 2) { 185 plat->options |= NAND_BUSWIDTH_16; 186 } else if (val != 1) { 187 dev_err(dev, "invalid bank-width %u\n", val); 188 return -EINVAL; 189 } 190 } 191 192 if (!of_property_read_u32(dev->of_node, "chip-delay", &val)) 193 plat->chip_delay = val; 194 195 return 0; 196 } 197 198 static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev) 199 { 200 struct resource *r; 201 u64 addr; 202 203 if (of_property_read_u64(pdev->dev.of_node, 204 "gpio-control-nand,io-sync-reg", &addr)) 205 return NULL; 206 207 r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL); 208 if (!r) 209 return NULL; 210 211 r->start = addr; 212 r->end = r->start + 0x3; 213 r->flags = IORESOURCE_MEM; 214 215 return r; 216 } 217 #else /* CONFIG_OF */ 218 static inline int gpio_nand_get_config_of(const struct device *dev, 219 struct gpio_nand_platdata *plat) 220 { 221 return -ENOSYS; 222 } 223 224 static inline struct resource * 225 gpio_nand_get_io_sync_of(struct platform_device *pdev) 226 { 227 return NULL; 228 } 229 #endif /* CONFIG_OF */ 230 231 static inline int gpio_nand_get_config(const struct device *dev, 232 struct gpio_nand_platdata *plat) 233 { 234 int ret = gpio_nand_get_config_of(dev, plat); 235 236 if (!ret) 237 return ret; 238 239 if (dev_get_platdata(dev)) { 240 memcpy(plat, dev_get_platdata(dev), sizeof(*plat)); 241 return 0; 242 } 243 244 return -EINVAL; 245 } 246 247 static inline struct resource * 248 gpio_nand_get_io_sync(struct platform_device *pdev) 249 { 250 struct resource *r = gpio_nand_get_io_sync_of(pdev); 251 252 if (r) 253 return r; 254 255 return platform_get_resource(pdev, IORESOURCE_MEM, 1); 256 } 257 258 static int gpio_nand_remove(struct platform_device *pdev) 259 { 260 struct gpiomtd *gpiomtd = platform_get_drvdata(pdev); 261 struct nand_chip *chip = &gpiomtd->nand_chip; 262 int ret; 263 264 ret = mtd_device_unregister(nand_to_mtd(chip)); 265 WARN_ON(ret); 266 nand_cleanup(chip); 267 268 /* Enable write protection and disable the chip */ 269 if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) 270 gpiod_set_value(gpiomtd->nwp, 0); 271 if (gpiomtd->nce && !IS_ERR(gpiomtd->nce)) 272 gpiod_set_value(gpiomtd->nce, 0); 273 274 return 0; 275 } 276 277 static int gpio_nand_probe(struct platform_device *pdev) 278 { 279 struct gpiomtd *gpiomtd; 280 struct nand_chip *chip; 281 struct mtd_info *mtd; 282 struct resource *res; 283 struct device *dev = &pdev->dev; 284 int ret = 0; 285 286 if (!dev->of_node && !dev_get_platdata(dev)) 287 return -EINVAL; 288 289 gpiomtd = devm_kzalloc(dev, sizeof(*gpiomtd), GFP_KERNEL); 290 if (!gpiomtd) 291 return -ENOMEM; 292 293 chip = &gpiomtd->nand_chip; 294 295 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 296 gpiomtd->io = devm_ioremap_resource(dev, res); 297 if (IS_ERR(gpiomtd->io)) 298 return PTR_ERR(gpiomtd->io); 299 300 res = gpio_nand_get_io_sync(pdev); 301 if (res) { 302 gpiomtd->io_sync = devm_ioremap_resource(dev, res); 303 if (IS_ERR(gpiomtd->io_sync)) 304 return PTR_ERR(gpiomtd->io_sync); 305 } 306 307 ret = gpio_nand_get_config(dev, &gpiomtd->plat); 308 if (ret) 309 return ret; 310 311 /* Just enable the chip */ 312 gpiomtd->nce = devm_gpiod_get_optional(dev, "nce", GPIOD_OUT_HIGH); 313 if (IS_ERR(gpiomtd->nce)) 314 return PTR_ERR(gpiomtd->nce); 315 316 /* We disable write protection once we know probe() will succeed */ 317 gpiomtd->nwp = devm_gpiod_get_optional(dev, "nwp", GPIOD_OUT_LOW); 318 if (IS_ERR(gpiomtd->nwp)) { 319 ret = PTR_ERR(gpiomtd->nwp); 320 goto out_ce; 321 } 322 323 gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW); 324 if (IS_ERR(gpiomtd->ale)) { 325 ret = PTR_ERR(gpiomtd->ale); 326 goto out_ce; 327 } 328 329 gpiomtd->cle = devm_gpiod_get(dev, "cle", GPIOD_OUT_LOW); 330 if (IS_ERR(gpiomtd->cle)) { 331 ret = PTR_ERR(gpiomtd->cle); 332 goto out_ce; 333 } 334 335 gpiomtd->rdy = devm_gpiod_get_optional(dev, "rdy", GPIOD_IN); 336 if (IS_ERR(gpiomtd->rdy)) { 337 ret = PTR_ERR(gpiomtd->rdy); 338 goto out_ce; 339 } 340 341 nand_controller_init(&gpiomtd->base); 342 gpiomtd->base.ops = &gpio_nand_ops; 343 344 nand_set_flash_node(chip, pdev->dev.of_node); 345 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 346 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 347 chip->options = gpiomtd->plat.options; 348 chip->controller = &gpiomtd->base; 349 350 mtd = nand_to_mtd(chip); 351 mtd->dev.parent = dev; 352 353 platform_set_drvdata(pdev, gpiomtd); 354 355 /* Disable write protection, if wired up */ 356 if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) 357 gpiod_direction_output(gpiomtd->nwp, 1); 358 359 ret = nand_scan(chip, 1); 360 if (ret) 361 goto err_wp; 362 363 if (gpiomtd->plat.adjust_parts) 364 gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size); 365 366 ret = mtd_device_register(mtd, gpiomtd->plat.parts, 367 gpiomtd->plat.num_parts); 368 if (!ret) 369 return 0; 370 371 err_wp: 372 if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) 373 gpiod_set_value(gpiomtd->nwp, 0); 374 out_ce: 375 if (gpiomtd->nce && !IS_ERR(gpiomtd->nce)) 376 gpiod_set_value(gpiomtd->nce, 0); 377 378 return ret; 379 } 380 381 static struct platform_driver gpio_nand_driver = { 382 .probe = gpio_nand_probe, 383 .remove = gpio_nand_remove, 384 .driver = { 385 .name = "gpio-nand", 386 .of_match_table = of_match_ptr(gpio_nand_id_table), 387 }, 388 }; 389 390 module_platform_driver(gpio_nand_driver); 391 392 MODULE_LICENSE("GPL"); 393 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 394 MODULE_DESCRIPTION("GPIO NAND Driver"); 395