1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Updated, and converted to generic GPIO based driver by Russell King. 4 * 5 * Written by Ben Dooks <ben@simtec.co.uk> 6 * Based on 2.4 version by Mark Whittaker 7 * 8 * © 2004 Simtec Electronics 9 * 10 * Device driver for NAND flash that uses a memory mapped interface to 11 * read/write the NAND commands and data, and GPIO pins for control signals 12 * (the DT binding refers to this as "GPIO assisted NAND flash") 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/err.h> 17 #include <linux/slab.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/io.h> 22 #include <linux/mtd/mtd.h> 23 #include <linux/mtd/rawnand.h> 24 #include <linux/mtd/partitions.h> 25 #include <linux/mtd/nand-gpio.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/delay.h> 29 30 struct gpiomtd { 31 struct nand_controller base; 32 void __iomem *io; 33 void __iomem *io_sync; 34 struct nand_chip nand_chip; 35 struct gpio_nand_platdata plat; 36 struct gpio_desc *nce; /* Optional chip enable */ 37 struct gpio_desc *cle; 38 struct gpio_desc *ale; 39 struct gpio_desc *rdy; 40 struct gpio_desc *nwp; /* Optional write protection */ 41 }; 42 43 static inline struct gpiomtd *gpio_nand_getpriv(struct mtd_info *mtd) 44 { 45 return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip); 46 } 47 48 49 #ifdef CONFIG_ARM 50 /* gpio_nand_dosync() 51 * 52 * Make sure the GPIO state changes occur in-order with writes to NAND 53 * memory region. 54 * Needed on PXA due to bus-reordering within the SoC itself (see section on 55 * I/O ordering in PXA manual (section 2.3, p35) 56 */ 57 static void gpio_nand_dosync(struct gpiomtd *gpiomtd) 58 { 59 unsigned long tmp; 60 61 if (gpiomtd->io_sync) { 62 /* 63 * Linux memory barriers don't cater for what's required here. 64 * What's required is what's here - a read from a separate 65 * region with a dependency on that read. 66 */ 67 tmp = readl(gpiomtd->io_sync); 68 asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp)); 69 } 70 } 71 #else 72 static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {} 73 #endif 74 75 static int gpio_nand_exec_instr(struct nand_chip *chip, 76 const struct nand_op_instr *instr) 77 { 78 struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip)); 79 unsigned int i; 80 81 switch (instr->type) { 82 case NAND_OP_CMD_INSTR: 83 gpio_nand_dosync(gpiomtd); 84 gpiod_set_value(gpiomtd->cle, 1); 85 gpio_nand_dosync(gpiomtd); 86 writeb(instr->ctx.cmd.opcode, gpiomtd->io); 87 gpio_nand_dosync(gpiomtd); 88 gpiod_set_value(gpiomtd->cle, 0); 89 return 0; 90 91 case NAND_OP_ADDR_INSTR: 92 gpio_nand_dosync(gpiomtd); 93 gpiod_set_value(gpiomtd->ale, 1); 94 gpio_nand_dosync(gpiomtd); 95 for (i = 0; i < instr->ctx.addr.naddrs; i++) 96 writeb(instr->ctx.addr.addrs[i], gpiomtd->io); 97 gpio_nand_dosync(gpiomtd); 98 gpiod_set_value(gpiomtd->ale, 0); 99 return 0; 100 101 case NAND_OP_DATA_IN_INSTR: 102 gpio_nand_dosync(gpiomtd); 103 if ((chip->options & NAND_BUSWIDTH_16) && 104 !instr->ctx.data.force_8bit) 105 ioread16_rep(gpiomtd->io, instr->ctx.data.buf.in, 106 instr->ctx.data.len / 2); 107 else 108 ioread8_rep(gpiomtd->io, instr->ctx.data.buf.in, 109 instr->ctx.data.len); 110 return 0; 111 112 case NAND_OP_DATA_OUT_INSTR: 113 gpio_nand_dosync(gpiomtd); 114 if ((chip->options & NAND_BUSWIDTH_16) && 115 !instr->ctx.data.force_8bit) 116 iowrite16_rep(gpiomtd->io, instr->ctx.data.buf.out, 117 instr->ctx.data.len / 2); 118 else 119 iowrite8_rep(gpiomtd->io, instr->ctx.data.buf.out, 120 instr->ctx.data.len); 121 return 0; 122 123 case NAND_OP_WAITRDY_INSTR: 124 if (!gpiomtd->rdy) 125 return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms); 126 127 return nand_gpio_waitrdy(chip, gpiomtd->rdy, 128 instr->ctx.waitrdy.timeout_ms); 129 130 default: 131 return -EINVAL; 132 } 133 134 return 0; 135 } 136 137 static int gpio_nand_exec_op(struct nand_chip *chip, 138 const struct nand_operation *op, 139 bool check_only) 140 { 141 struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip)); 142 unsigned int i; 143 int ret = 0; 144 145 if (check_only) 146 return 0; 147 148 gpio_nand_dosync(gpiomtd); 149 gpiod_set_value(gpiomtd->nce, 0); 150 for (i = 0; i < op->ninstrs; i++) { 151 ret = gpio_nand_exec_instr(chip, &op->instrs[i]); 152 if (ret) 153 break; 154 155 if (op->instrs[i].delay_ns) 156 ndelay(op->instrs[i].delay_ns); 157 } 158 gpio_nand_dosync(gpiomtd); 159 gpiod_set_value(gpiomtd->nce, 1); 160 161 return ret; 162 } 163 164 static int gpio_nand_attach_chip(struct nand_chip *chip) 165 { 166 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 167 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 168 169 return 0; 170 } 171 172 static const struct nand_controller_ops gpio_nand_ops = { 173 .exec_op = gpio_nand_exec_op, 174 .attach_chip = gpio_nand_attach_chip, 175 }; 176 177 #ifdef CONFIG_OF 178 static const struct of_device_id gpio_nand_id_table[] = { 179 { .compatible = "gpio-control-nand" }, 180 {} 181 }; 182 MODULE_DEVICE_TABLE(of, gpio_nand_id_table); 183 184 static int gpio_nand_get_config_of(const struct device *dev, 185 struct gpio_nand_platdata *plat) 186 { 187 u32 val; 188 189 if (!dev->of_node) 190 return -ENODEV; 191 192 if (!of_property_read_u32(dev->of_node, "bank-width", &val)) { 193 if (val == 2) { 194 plat->options |= NAND_BUSWIDTH_16; 195 } else if (val != 1) { 196 dev_err(dev, "invalid bank-width %u\n", val); 197 return -EINVAL; 198 } 199 } 200 201 if (!of_property_read_u32(dev->of_node, "chip-delay", &val)) 202 plat->chip_delay = val; 203 204 return 0; 205 } 206 207 static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev) 208 { 209 struct resource *r; 210 u64 addr; 211 212 if (of_property_read_u64(pdev->dev.of_node, 213 "gpio-control-nand,io-sync-reg", &addr)) 214 return NULL; 215 216 r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL); 217 if (!r) 218 return NULL; 219 220 r->start = addr; 221 r->end = r->start + 0x3; 222 r->flags = IORESOURCE_MEM; 223 224 return r; 225 } 226 #else /* CONFIG_OF */ 227 static inline int gpio_nand_get_config_of(const struct device *dev, 228 struct gpio_nand_platdata *plat) 229 { 230 return -ENOSYS; 231 } 232 233 static inline struct resource * 234 gpio_nand_get_io_sync_of(struct platform_device *pdev) 235 { 236 return NULL; 237 } 238 #endif /* CONFIG_OF */ 239 240 static inline int gpio_nand_get_config(const struct device *dev, 241 struct gpio_nand_platdata *plat) 242 { 243 int ret = gpio_nand_get_config_of(dev, plat); 244 245 if (!ret) 246 return ret; 247 248 if (dev_get_platdata(dev)) { 249 memcpy(plat, dev_get_platdata(dev), sizeof(*plat)); 250 return 0; 251 } 252 253 return -EINVAL; 254 } 255 256 static inline struct resource * 257 gpio_nand_get_io_sync(struct platform_device *pdev) 258 { 259 struct resource *r = gpio_nand_get_io_sync_of(pdev); 260 261 if (r) 262 return r; 263 264 return platform_get_resource(pdev, IORESOURCE_MEM, 1); 265 } 266 267 static int gpio_nand_remove(struct platform_device *pdev) 268 { 269 struct gpiomtd *gpiomtd = platform_get_drvdata(pdev); 270 struct nand_chip *chip = &gpiomtd->nand_chip; 271 int ret; 272 273 ret = mtd_device_unregister(nand_to_mtd(chip)); 274 WARN_ON(ret); 275 nand_cleanup(chip); 276 277 /* Enable write protection and disable the chip */ 278 if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) 279 gpiod_set_value(gpiomtd->nwp, 0); 280 if (gpiomtd->nce && !IS_ERR(gpiomtd->nce)) 281 gpiod_set_value(gpiomtd->nce, 0); 282 283 return 0; 284 } 285 286 static int gpio_nand_probe(struct platform_device *pdev) 287 { 288 struct gpiomtd *gpiomtd; 289 struct nand_chip *chip; 290 struct mtd_info *mtd; 291 struct resource *res; 292 struct device *dev = &pdev->dev; 293 int ret = 0; 294 295 if (!dev->of_node && !dev_get_platdata(dev)) 296 return -EINVAL; 297 298 gpiomtd = devm_kzalloc(dev, sizeof(*gpiomtd), GFP_KERNEL); 299 if (!gpiomtd) 300 return -ENOMEM; 301 302 chip = &gpiomtd->nand_chip; 303 304 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 305 gpiomtd->io = devm_ioremap_resource(dev, res); 306 if (IS_ERR(gpiomtd->io)) 307 return PTR_ERR(gpiomtd->io); 308 309 res = gpio_nand_get_io_sync(pdev); 310 if (res) { 311 gpiomtd->io_sync = devm_ioremap_resource(dev, res); 312 if (IS_ERR(gpiomtd->io_sync)) 313 return PTR_ERR(gpiomtd->io_sync); 314 } 315 316 ret = gpio_nand_get_config(dev, &gpiomtd->plat); 317 if (ret) 318 return ret; 319 320 /* Just enable the chip */ 321 gpiomtd->nce = devm_gpiod_get_optional(dev, "nce", GPIOD_OUT_HIGH); 322 if (IS_ERR(gpiomtd->nce)) 323 return PTR_ERR(gpiomtd->nce); 324 325 /* We disable write protection once we know probe() will succeed */ 326 gpiomtd->nwp = devm_gpiod_get_optional(dev, "nwp", GPIOD_OUT_LOW); 327 if (IS_ERR(gpiomtd->nwp)) { 328 ret = PTR_ERR(gpiomtd->nwp); 329 goto out_ce; 330 } 331 332 gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW); 333 if (IS_ERR(gpiomtd->ale)) { 334 ret = PTR_ERR(gpiomtd->ale); 335 goto out_ce; 336 } 337 338 gpiomtd->cle = devm_gpiod_get(dev, "cle", GPIOD_OUT_LOW); 339 if (IS_ERR(gpiomtd->cle)) { 340 ret = PTR_ERR(gpiomtd->cle); 341 goto out_ce; 342 } 343 344 gpiomtd->rdy = devm_gpiod_get_optional(dev, "rdy", GPIOD_IN); 345 if (IS_ERR(gpiomtd->rdy)) { 346 ret = PTR_ERR(gpiomtd->rdy); 347 goto out_ce; 348 } 349 350 nand_controller_init(&gpiomtd->base); 351 gpiomtd->base.ops = &gpio_nand_ops; 352 353 nand_set_flash_node(chip, pdev->dev.of_node); 354 chip->options = gpiomtd->plat.options; 355 chip->controller = &gpiomtd->base; 356 357 mtd = nand_to_mtd(chip); 358 mtd->dev.parent = dev; 359 360 platform_set_drvdata(pdev, gpiomtd); 361 362 /* Disable write protection, if wired up */ 363 if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) 364 gpiod_direction_output(gpiomtd->nwp, 1); 365 366 ret = nand_scan(chip, 1); 367 if (ret) 368 goto err_wp; 369 370 if (gpiomtd->plat.adjust_parts) 371 gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size); 372 373 ret = mtd_device_register(mtd, gpiomtd->plat.parts, 374 gpiomtd->plat.num_parts); 375 if (!ret) 376 return 0; 377 378 err_wp: 379 if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) 380 gpiod_set_value(gpiomtd->nwp, 0); 381 out_ce: 382 if (gpiomtd->nce && !IS_ERR(gpiomtd->nce)) 383 gpiod_set_value(gpiomtd->nce, 0); 384 385 return ret; 386 } 387 388 static struct platform_driver gpio_nand_driver = { 389 .probe = gpio_nand_probe, 390 .remove = gpio_nand_remove, 391 .driver = { 392 .name = "gpio-nand", 393 .of_match_table = of_match_ptr(gpio_nand_id_table), 394 }, 395 }; 396 397 module_platform_driver(gpio_nand_driver); 398 399 MODULE_LICENSE("GPL"); 400 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 401 MODULE_DESCRIPTION("GPIO NAND Driver"); 402