1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ST Microelectronics 4 * Flexible Static Memory Controller (FSMC) 5 * Driver for NAND portions 6 * 7 * Copyright © 2010 ST Microelectronics 8 * Vipin Kumar <vipin.kumar@st.com> 9 * Ashish Priyadarshi 10 * 11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8) 12 * Copyright © 2007 STMicroelectronics Pvt. Ltd. 13 * Copyright © 2009 Alessandro Rubini 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/completion.h> 18 #include <linux/dmaengine.h> 19 #include <linux/dma-direction.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/err.h> 22 #include <linux/init.h> 23 #include <linux/module.h> 24 #include <linux/resource.h> 25 #include <linux/sched.h> 26 #include <linux/types.h> 27 #include <linux/mtd/mtd.h> 28 #include <linux/mtd/nand-ecc-sw-hamming.h> 29 #include <linux/mtd/rawnand.h> 30 #include <linux/platform_device.h> 31 #include <linux/of.h> 32 #include <linux/mtd/partitions.h> 33 #include <linux/io.h> 34 #include <linux/slab.h> 35 #include <linux/amba/bus.h> 36 #include <mtd/mtd-abi.h> 37 38 /* fsmc controller registers for NOR flash */ 39 #define CTRL 0x0 40 /* ctrl register definitions */ 41 #define BANK_ENABLE BIT(0) 42 #define MUXED BIT(1) 43 #define NOR_DEV (2 << 2) 44 #define WIDTH_16 BIT(4) 45 #define RSTPWRDWN BIT(6) 46 #define WPROT BIT(7) 47 #define WRT_ENABLE BIT(12) 48 #define WAIT_ENB BIT(13) 49 50 #define CTRL_TIM 0x4 51 /* ctrl_tim register definitions */ 52 53 #define FSMC_NOR_BANK_SZ 0x8 54 #define FSMC_NOR_REG_SIZE 0x40 55 56 #define FSMC_NOR_REG(base, bank, reg) ((base) + \ 57 (FSMC_NOR_BANK_SZ * (bank)) + \ 58 (reg)) 59 60 /* fsmc controller registers for NAND flash */ 61 #define FSMC_PC 0x00 62 /* pc register definitions */ 63 #define FSMC_RESET BIT(0) 64 #define FSMC_WAITON BIT(1) 65 #define FSMC_ENABLE BIT(2) 66 #define FSMC_DEVTYPE_NAND BIT(3) 67 #define FSMC_DEVWID_16 BIT(4) 68 #define FSMC_ECCEN BIT(6) 69 #define FSMC_ECCPLEN_256 BIT(7) 70 #define FSMC_TCLR_SHIFT (9) 71 #define FSMC_TCLR_MASK (0xF) 72 #define FSMC_TAR_SHIFT (13) 73 #define FSMC_TAR_MASK (0xF) 74 #define STS 0x04 75 /* sts register definitions */ 76 #define FSMC_CODE_RDY BIT(15) 77 #define COMM 0x08 78 /* comm register definitions */ 79 #define FSMC_TSET_SHIFT 0 80 #define FSMC_TSET_MASK 0xFF 81 #define FSMC_TWAIT_SHIFT 8 82 #define FSMC_TWAIT_MASK 0xFF 83 #define FSMC_THOLD_SHIFT 16 84 #define FSMC_THOLD_MASK 0xFF 85 #define FSMC_THIZ_SHIFT 24 86 #define FSMC_THIZ_MASK 0xFF 87 #define ATTRIB 0x0C 88 #define IOATA 0x10 89 #define ECC1 0x14 90 #define ECC2 0x18 91 #define ECC3 0x1C 92 #define FSMC_NAND_BANK_SZ 0x20 93 94 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) 95 96 struct fsmc_nand_timings { 97 u8 tclr; 98 u8 tar; 99 u8 thiz; 100 u8 thold; 101 u8 twait; 102 u8 tset; 103 }; 104 105 enum access_mode { 106 USE_DMA_ACCESS = 1, 107 USE_WORD_ACCESS, 108 }; 109 110 /** 111 * struct fsmc_nand_data - structure for FSMC NAND device state 112 * 113 * @base: Inherit from the nand_controller struct 114 * @pid: Part ID on the AMBA PrimeCell format 115 * @nand: Chip related info for a NAND flash. 116 * 117 * @bank: Bank number for probed device. 118 * @dev: Parent device 119 * @mode: Access mode 120 * @clk: Clock structure for FSMC. 121 * 122 * @read_dma_chan: DMA channel for read access 123 * @write_dma_chan: DMA channel for write access to NAND 124 * @dma_access_complete: Completion structure 125 * 126 * @dev_timings: NAND timings 127 * 128 * @data_pa: NAND Physical port for Data. 129 * @data_va: NAND port for Data. 130 * @cmd_va: NAND port for Command. 131 * @addr_va: NAND port for Address. 132 * @regs_va: Registers base address for a given bank. 133 */ 134 struct fsmc_nand_data { 135 struct nand_controller base; 136 u32 pid; 137 struct nand_chip nand; 138 139 unsigned int bank; 140 struct device *dev; 141 enum access_mode mode; 142 struct clk *clk; 143 144 /* DMA related objects */ 145 struct dma_chan *read_dma_chan; 146 struct dma_chan *write_dma_chan; 147 struct completion dma_access_complete; 148 149 struct fsmc_nand_timings *dev_timings; 150 151 dma_addr_t data_pa; 152 void __iomem *data_va; 153 void __iomem *cmd_va; 154 void __iomem *addr_va; 155 void __iomem *regs_va; 156 }; 157 158 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section, 159 struct mtd_oob_region *oobregion) 160 { 161 struct nand_chip *chip = mtd_to_nand(mtd); 162 163 if (section >= chip->ecc.steps) 164 return -ERANGE; 165 166 oobregion->offset = (section * 16) + 2; 167 oobregion->length = 3; 168 169 return 0; 170 } 171 172 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section, 173 struct mtd_oob_region *oobregion) 174 { 175 struct nand_chip *chip = mtd_to_nand(mtd); 176 177 if (section >= chip->ecc.steps) 178 return -ERANGE; 179 180 oobregion->offset = (section * 16) + 8; 181 182 if (section < chip->ecc.steps - 1) 183 oobregion->length = 8; 184 else 185 oobregion->length = mtd->oobsize - oobregion->offset; 186 187 return 0; 188 } 189 190 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = { 191 .ecc = fsmc_ecc1_ooblayout_ecc, 192 .free = fsmc_ecc1_ooblayout_free, 193 }; 194 195 /* 196 * ECC placement definitions in oobfree type format. 197 * There are 13 bytes of ecc for every 512 byte block and it has to be read 198 * consecutively and immediately after the 512 byte data block for hardware to 199 * generate the error bit offsets in 512 byte data. 200 */ 201 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section, 202 struct mtd_oob_region *oobregion) 203 { 204 struct nand_chip *chip = mtd_to_nand(mtd); 205 206 if (section >= chip->ecc.steps) 207 return -ERANGE; 208 209 oobregion->length = chip->ecc.bytes; 210 211 if (!section && mtd->writesize <= 512) 212 oobregion->offset = 0; 213 else 214 oobregion->offset = (section * 16) + 2; 215 216 return 0; 217 } 218 219 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section, 220 struct mtd_oob_region *oobregion) 221 { 222 struct nand_chip *chip = mtd_to_nand(mtd); 223 224 if (section >= chip->ecc.steps) 225 return -ERANGE; 226 227 oobregion->offset = (section * 16) + 15; 228 229 if (section < chip->ecc.steps - 1) 230 oobregion->length = 3; 231 else 232 oobregion->length = mtd->oobsize - oobregion->offset; 233 234 return 0; 235 } 236 237 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = { 238 .ecc = fsmc_ecc4_ooblayout_ecc, 239 .free = fsmc_ecc4_ooblayout_free, 240 }; 241 242 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip) 243 { 244 return container_of(chip, struct fsmc_nand_data, nand); 245 } 246 247 /* 248 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine 249 * 250 * This routine initializes timing parameters related to NAND memory access in 251 * FSMC registers 252 */ 253 static void fsmc_nand_setup(struct fsmc_nand_data *host, 254 struct fsmc_nand_timings *tims) 255 { 256 u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; 257 u32 tclr, tar, thiz, thold, twait, tset; 258 259 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT; 260 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT; 261 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT; 262 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT; 263 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; 264 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; 265 266 if (host->nand.options & NAND_BUSWIDTH_16) 267 value |= FSMC_DEVWID_16; 268 269 writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC); 270 writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM); 271 writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB); 272 } 273 274 static int fsmc_calc_timings(struct fsmc_nand_data *host, 275 const struct nand_sdr_timings *sdrt, 276 struct fsmc_nand_timings *tims) 277 { 278 unsigned long hclk = clk_get_rate(host->clk); 279 unsigned long hclkn = NSEC_PER_SEC / hclk; 280 u32 thiz, thold, twait, tset; 281 282 if (sdrt->tRC_min < 30000) 283 return -EOPNOTSUPP; 284 285 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1; 286 if (tims->tar > FSMC_TAR_MASK) 287 tims->tar = FSMC_TAR_MASK; 288 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1; 289 if (tims->tclr > FSMC_TCLR_MASK) 290 tims->tclr = FSMC_TCLR_MASK; 291 292 thiz = sdrt->tCS_min - sdrt->tWP_min; 293 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn); 294 295 thold = sdrt->tDH_min; 296 if (thold < sdrt->tCH_min) 297 thold = sdrt->tCH_min; 298 if (thold < sdrt->tCLH_min) 299 thold = sdrt->tCLH_min; 300 if (thold < sdrt->tWH_min) 301 thold = sdrt->tWH_min; 302 if (thold < sdrt->tALH_min) 303 thold = sdrt->tALH_min; 304 if (thold < sdrt->tREH_min) 305 thold = sdrt->tREH_min; 306 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn); 307 if (tims->thold == 0) 308 tims->thold = 1; 309 else if (tims->thold > FSMC_THOLD_MASK) 310 tims->thold = FSMC_THOLD_MASK; 311 312 twait = max(sdrt->tRP_min, sdrt->tWP_min); 313 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1; 314 if (tims->twait == 0) 315 tims->twait = 1; 316 else if (tims->twait > FSMC_TWAIT_MASK) 317 tims->twait = FSMC_TWAIT_MASK; 318 319 tset = max(sdrt->tCS_min - sdrt->tWP_min, 320 sdrt->tCEA_max - sdrt->tREA_max); 321 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1; 322 if (tims->tset == 0) 323 tims->tset = 1; 324 else if (tims->tset > FSMC_TSET_MASK) 325 tims->tset = FSMC_TSET_MASK; 326 327 return 0; 328 } 329 330 static int fsmc_setup_interface(struct nand_chip *nand, int csline, 331 const struct nand_interface_config *conf) 332 { 333 struct fsmc_nand_data *host = nand_to_fsmc(nand); 334 struct fsmc_nand_timings tims; 335 const struct nand_sdr_timings *sdrt; 336 int ret; 337 338 sdrt = nand_get_sdr_timings(conf); 339 if (IS_ERR(sdrt)) 340 return PTR_ERR(sdrt); 341 342 ret = fsmc_calc_timings(host, sdrt, &tims); 343 if (ret) 344 return ret; 345 346 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 347 return 0; 348 349 fsmc_nand_setup(host, &tims); 350 351 return 0; 352 } 353 354 /* 355 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers 356 */ 357 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode) 358 { 359 struct fsmc_nand_data *host = nand_to_fsmc(chip); 360 361 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256, 362 host->regs_va + FSMC_PC); 363 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN, 364 host->regs_va + FSMC_PC); 365 writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN, 366 host->regs_va + FSMC_PC); 367 } 368 369 /* 370 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by 371 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to 372 * max of 8-bits) 373 */ 374 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data, 375 u8 *ecc) 376 { 377 struct fsmc_nand_data *host = nand_to_fsmc(chip); 378 u32 ecc_tmp; 379 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; 380 381 do { 382 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY) 383 break; 384 385 cond_resched(); 386 } while (!time_after_eq(jiffies, deadline)); 387 388 if (time_after_eq(jiffies, deadline)) { 389 dev_err(host->dev, "calculate ecc timed out\n"); 390 return -ETIMEDOUT; 391 } 392 393 ecc_tmp = readl_relaxed(host->regs_va + ECC1); 394 ecc[0] = ecc_tmp; 395 ecc[1] = ecc_tmp >> 8; 396 ecc[2] = ecc_tmp >> 16; 397 ecc[3] = ecc_tmp >> 24; 398 399 ecc_tmp = readl_relaxed(host->regs_va + ECC2); 400 ecc[4] = ecc_tmp; 401 ecc[5] = ecc_tmp >> 8; 402 ecc[6] = ecc_tmp >> 16; 403 ecc[7] = ecc_tmp >> 24; 404 405 ecc_tmp = readl_relaxed(host->regs_va + ECC3); 406 ecc[8] = ecc_tmp; 407 ecc[9] = ecc_tmp >> 8; 408 ecc[10] = ecc_tmp >> 16; 409 ecc[11] = ecc_tmp >> 24; 410 411 ecc_tmp = readl_relaxed(host->regs_va + STS); 412 ecc[12] = ecc_tmp >> 16; 413 414 return 0; 415 } 416 417 /* 418 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by 419 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to 420 * max of 1-bit) 421 */ 422 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data, 423 u8 *ecc) 424 { 425 struct fsmc_nand_data *host = nand_to_fsmc(chip); 426 u32 ecc_tmp; 427 428 ecc_tmp = readl_relaxed(host->regs_va + ECC1); 429 ecc[0] = ecc_tmp; 430 ecc[1] = ecc_tmp >> 8; 431 ecc[2] = ecc_tmp >> 16; 432 433 return 0; 434 } 435 436 static int fsmc_correct_ecc1(struct nand_chip *chip, 437 unsigned char *buf, 438 unsigned char *read_ecc, 439 unsigned char *calc_ecc) 440 { 441 bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER; 442 443 return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc, 444 chip->ecc.size, sm_order); 445 } 446 447 /* Count the number of 0's in buff upto a max of max_bits */ 448 static int count_written_bits(u8 *buff, int size, int max_bits) 449 { 450 int k, written_bits = 0; 451 452 for (k = 0; k < size; k++) { 453 written_bits += hweight8(~buff[k]); 454 if (written_bits > max_bits) 455 break; 456 } 457 458 return written_bits; 459 } 460 461 static void dma_complete(void *param) 462 { 463 struct fsmc_nand_data *host = param; 464 465 complete(&host->dma_access_complete); 466 } 467 468 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len, 469 enum dma_data_direction direction) 470 { 471 struct dma_chan *chan; 472 struct dma_device *dma_dev; 473 struct dma_async_tx_descriptor *tx; 474 dma_addr_t dma_dst, dma_src, dma_addr; 475 dma_cookie_t cookie; 476 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 477 int ret; 478 unsigned long time_left; 479 480 if (direction == DMA_TO_DEVICE) 481 chan = host->write_dma_chan; 482 else if (direction == DMA_FROM_DEVICE) 483 chan = host->read_dma_chan; 484 else 485 return -EINVAL; 486 487 dma_dev = chan->device; 488 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction); 489 490 if (direction == DMA_TO_DEVICE) { 491 dma_src = dma_addr; 492 dma_dst = host->data_pa; 493 } else { 494 dma_src = host->data_pa; 495 dma_dst = dma_addr; 496 } 497 498 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, 499 len, flags); 500 if (!tx) { 501 dev_err(host->dev, "device_prep_dma_memcpy error\n"); 502 ret = -EIO; 503 goto unmap_dma; 504 } 505 506 tx->callback = dma_complete; 507 tx->callback_param = host; 508 cookie = tx->tx_submit(tx); 509 510 ret = dma_submit_error(cookie); 511 if (ret) { 512 dev_err(host->dev, "dma_submit_error %d\n", cookie); 513 goto unmap_dma; 514 } 515 516 dma_async_issue_pending(chan); 517 518 time_left = 519 wait_for_completion_timeout(&host->dma_access_complete, 520 msecs_to_jiffies(3000)); 521 if (time_left == 0) { 522 dmaengine_terminate_all(chan); 523 dev_err(host->dev, "wait_for_completion_timeout\n"); 524 ret = -ETIMEDOUT; 525 goto unmap_dma; 526 } 527 528 ret = 0; 529 530 unmap_dma: 531 dma_unmap_single(dma_dev->dev, dma_addr, len, direction); 532 533 return ret; 534 } 535 536 /* 537 * fsmc_write_buf - write buffer to chip 538 * @host: FSMC NAND controller 539 * @buf: data buffer 540 * @len: number of bytes to write 541 */ 542 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf, 543 int len) 544 { 545 int i; 546 547 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && 548 IS_ALIGNED(len, sizeof(u32))) { 549 u32 *p = (u32 *)buf; 550 551 len = len >> 2; 552 for (i = 0; i < len; i++) 553 writel_relaxed(p[i], host->data_va); 554 } else { 555 for (i = 0; i < len; i++) 556 writeb_relaxed(buf[i], host->data_va); 557 } 558 } 559 560 /* 561 * fsmc_read_buf - read chip data into buffer 562 * @host: FSMC NAND controller 563 * @buf: buffer to store date 564 * @len: number of bytes to read 565 */ 566 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len) 567 { 568 int i; 569 570 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && 571 IS_ALIGNED(len, sizeof(u32))) { 572 u32 *p = (u32 *)buf; 573 574 len = len >> 2; 575 for (i = 0; i < len; i++) 576 p[i] = readl_relaxed(host->data_va); 577 } else { 578 for (i = 0; i < len; i++) 579 buf[i] = readb_relaxed(host->data_va); 580 } 581 } 582 583 /* 584 * fsmc_read_buf_dma - read chip data into buffer 585 * @host: FSMC NAND controller 586 * @buf: buffer to store date 587 * @len: number of bytes to read 588 */ 589 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf, 590 int len) 591 { 592 dma_xfer(host, buf, len, DMA_FROM_DEVICE); 593 } 594 595 /* 596 * fsmc_write_buf_dma - write buffer to chip 597 * @host: FSMC NAND controller 598 * @buf: data buffer 599 * @len: number of bytes to write 600 */ 601 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf, 602 int len) 603 { 604 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE); 605 } 606 607 /* 608 * fsmc_exec_op - hook called by the core to execute NAND operations 609 * 610 * This controller is simple enough and thus does not need to use the parser 611 * provided by the core, instead, handle every situation here. 612 */ 613 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op, 614 bool check_only) 615 { 616 struct fsmc_nand_data *host = nand_to_fsmc(chip); 617 const struct nand_op_instr *instr = NULL; 618 int ret = 0; 619 unsigned int op_id; 620 int i; 621 622 if (check_only) 623 return 0; 624 625 pr_debug("Executing operation [%d instructions]:\n", op->ninstrs); 626 627 for (op_id = 0; op_id < op->ninstrs; op_id++) { 628 instr = &op->instrs[op_id]; 629 630 nand_op_trace(" ", instr); 631 632 switch (instr->type) { 633 case NAND_OP_CMD_INSTR: 634 writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va); 635 break; 636 637 case NAND_OP_ADDR_INSTR: 638 for (i = 0; i < instr->ctx.addr.naddrs; i++) 639 writeb_relaxed(instr->ctx.addr.addrs[i], 640 host->addr_va); 641 break; 642 643 case NAND_OP_DATA_IN_INSTR: 644 if (host->mode == USE_DMA_ACCESS) 645 fsmc_read_buf_dma(host, instr->ctx.data.buf.in, 646 instr->ctx.data.len); 647 else 648 fsmc_read_buf(host, instr->ctx.data.buf.in, 649 instr->ctx.data.len); 650 break; 651 652 case NAND_OP_DATA_OUT_INSTR: 653 if (host->mode == USE_DMA_ACCESS) 654 fsmc_write_buf_dma(host, 655 instr->ctx.data.buf.out, 656 instr->ctx.data.len); 657 else 658 fsmc_write_buf(host, instr->ctx.data.buf.out, 659 instr->ctx.data.len); 660 break; 661 662 case NAND_OP_WAITRDY_INSTR: 663 ret = nand_soft_waitrdy(chip, 664 instr->ctx.waitrdy.timeout_ms); 665 break; 666 } 667 } 668 669 return ret; 670 } 671 672 /* 673 * fsmc_read_page_hwecc 674 * @chip: nand chip info structure 675 * @buf: buffer to store read data 676 * @oob_required: caller expects OOB data read to chip->oob_poi 677 * @page: page number to read 678 * 679 * This routine is needed for fsmc version 8 as reading from NAND chip has to be 680 * performed in a strict sequence as follows: 681 * data(512 byte) -> ecc(13 byte) 682 * After this read, fsmc hardware generates and reports error data bits(up to a 683 * max of 8 bits) 684 */ 685 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf, 686 int oob_required, int page) 687 { 688 struct mtd_info *mtd = nand_to_mtd(chip); 689 int i, j, s, stat, eccsize = chip->ecc.size; 690 int eccbytes = chip->ecc.bytes; 691 int eccsteps = chip->ecc.steps; 692 u8 *p = buf; 693 u8 *ecc_calc = chip->ecc.calc_buf; 694 u8 *ecc_code = chip->ecc.code_buf; 695 int off, len, ret, group = 0; 696 /* 697 * ecc_oob is intentionally taken as u16. In 16bit devices, we 698 * end up reading 14 bytes (7 words) from oob. The local array is 699 * to maintain word alignment 700 */ 701 u16 ecc_oob[7]; 702 u8 *oob = (u8 *)&ecc_oob[0]; 703 unsigned int max_bitflips = 0; 704 705 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { 706 nand_read_page_op(chip, page, s * eccsize, NULL, 0); 707 chip->ecc.hwctl(chip, NAND_ECC_READ); 708 ret = nand_read_data_op(chip, p, eccsize, false, false); 709 if (ret) 710 return ret; 711 712 for (j = 0; j < eccbytes;) { 713 struct mtd_oob_region oobregion; 714 715 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion); 716 if (ret) 717 return ret; 718 719 off = oobregion.offset; 720 len = oobregion.length; 721 722 /* 723 * length is intentionally kept a higher multiple of 2 724 * to read at least 13 bytes even in case of 16 bit NAND 725 * devices 726 */ 727 if (chip->options & NAND_BUSWIDTH_16) 728 len = roundup(len, 2); 729 730 nand_read_oob_op(chip, page, off, oob + j, len); 731 j += len; 732 } 733 734 memcpy(&ecc_code[i], oob, chip->ecc.bytes); 735 chip->ecc.calculate(chip, p, &ecc_calc[i]); 736 737 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); 738 if (stat < 0) { 739 mtd->ecc_stats.failed++; 740 } else { 741 mtd->ecc_stats.corrected += stat; 742 max_bitflips = max_t(unsigned int, max_bitflips, stat); 743 } 744 } 745 746 return max_bitflips; 747 } 748 749 /* 750 * fsmc_bch8_correct_data 751 * @mtd: mtd info structure 752 * @dat: buffer of read data 753 * @read_ecc: ecc read from device spare area 754 * @calc_ecc: ecc calculated from read data 755 * 756 * calc_ecc is a 104 bit information containing maximum of 8 error 757 * offset information of 13 bits each in 512 bytes of read data. 758 */ 759 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat, 760 u8 *read_ecc, u8 *calc_ecc) 761 { 762 struct fsmc_nand_data *host = nand_to_fsmc(chip); 763 u32 err_idx[8]; 764 u32 num_err, i; 765 u32 ecc1, ecc2, ecc3, ecc4; 766 767 num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF; 768 769 /* no bit flipping */ 770 if (likely(num_err == 0)) 771 return 0; 772 773 /* too many errors */ 774 if (unlikely(num_err > 8)) { 775 /* 776 * This is a temporary erase check. A newly erased page read 777 * would result in an ecc error because the oob data is also 778 * erased to FF and the calculated ecc for an FF data is not 779 * FF..FF. 780 * This is a workaround to skip performing correction in case 781 * data is FF..FF 782 * 783 * Logic: 784 * For every page, each bit written as 0 is counted until these 785 * number of bits are greater than 8 (the maximum correction 786 * capability of FSMC for each 512 + 13 bytes) 787 */ 788 789 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); 790 int bits_data = count_written_bits(dat, chip->ecc.size, 8); 791 792 if ((bits_ecc + bits_data) <= 8) { 793 if (bits_data) 794 memset(dat, 0xff, chip->ecc.size); 795 return bits_data; 796 } 797 798 return -EBADMSG; 799 } 800 801 /* 802 * ------------------- calc_ecc[] bit wise -----------|--13 bits--| 803 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| 804 * 805 * calc_ecc is a 104 bit information containing maximum of 8 error 806 * offset information of 13 bits each. calc_ecc is copied into a 807 * u64 array and error offset indexes are populated in err_idx 808 * array 809 */ 810 ecc1 = readl_relaxed(host->regs_va + ECC1); 811 ecc2 = readl_relaxed(host->regs_va + ECC2); 812 ecc3 = readl_relaxed(host->regs_va + ECC3); 813 ecc4 = readl_relaxed(host->regs_va + STS); 814 815 err_idx[0] = (ecc1 >> 0) & 0x1FFF; 816 err_idx[1] = (ecc1 >> 13) & 0x1FFF; 817 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); 818 err_idx[3] = (ecc2 >> 7) & 0x1FFF; 819 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); 820 err_idx[5] = (ecc3 >> 1) & 0x1FFF; 821 err_idx[6] = (ecc3 >> 14) & 0x1FFF; 822 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); 823 824 i = 0; 825 while (num_err--) { 826 err_idx[i] ^= 3; 827 828 if (err_idx[i] < chip->ecc.size * 8) { 829 int err = err_idx[i]; 830 831 dat[err >> 3] ^= BIT(err & 7); 832 i++; 833 } 834 } 835 return i; 836 } 837 838 static bool filter(struct dma_chan *chan, void *slave) 839 { 840 chan->private = slave; 841 return true; 842 } 843 844 static int fsmc_nand_probe_config_dt(struct platform_device *pdev, 845 struct fsmc_nand_data *host, 846 struct nand_chip *nand) 847 { 848 struct device_node *np = pdev->dev.of_node; 849 u32 val; 850 int ret; 851 852 nand->options = 0; 853 854 if (!of_property_read_u32(np, "bank-width", &val)) { 855 if (val == 2) { 856 nand->options |= NAND_BUSWIDTH_16; 857 } else if (val != 1) { 858 dev_err(&pdev->dev, "invalid bank-width %u\n", val); 859 return -EINVAL; 860 } 861 } 862 863 if (of_get_property(np, "nand-skip-bbtscan", NULL)) 864 nand->options |= NAND_SKIP_BBTSCAN; 865 866 host->dev_timings = devm_kzalloc(&pdev->dev, 867 sizeof(*host->dev_timings), 868 GFP_KERNEL); 869 if (!host->dev_timings) 870 return -ENOMEM; 871 872 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings, 873 sizeof(*host->dev_timings)); 874 if (ret) 875 host->dev_timings = NULL; 876 877 /* Set default NAND bank to 0 */ 878 host->bank = 0; 879 if (!of_property_read_u32(np, "bank", &val)) { 880 if (val > 3) { 881 dev_err(&pdev->dev, "invalid bank %u\n", val); 882 return -EINVAL; 883 } 884 host->bank = val; 885 } 886 return 0; 887 } 888 889 static int fsmc_nand_attach_chip(struct nand_chip *nand) 890 { 891 struct mtd_info *mtd = nand_to_mtd(nand); 892 struct fsmc_nand_data *host = nand_to_fsmc(nand); 893 894 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) 895 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 896 897 if (!nand->ecc.size) 898 nand->ecc.size = 512; 899 900 if (AMBA_REV_BITS(host->pid) >= 8) { 901 nand->ecc.read_page = fsmc_read_page_hwecc; 902 nand->ecc.calculate = fsmc_read_hwecc_ecc4; 903 nand->ecc.correct = fsmc_bch8_correct_data; 904 nand->ecc.bytes = 13; 905 nand->ecc.strength = 8; 906 } 907 908 if (AMBA_REV_BITS(host->pid) >= 8) { 909 switch (mtd->oobsize) { 910 case 16: 911 case 64: 912 case 128: 913 case 224: 914 case 256: 915 break; 916 default: 917 dev_warn(host->dev, 918 "No oob scheme defined for oobsize %d\n", 919 mtd->oobsize); 920 return -EINVAL; 921 } 922 923 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops); 924 925 return 0; 926 } 927 928 switch (nand->ecc.engine_type) { 929 case NAND_ECC_ENGINE_TYPE_ON_HOST: 930 dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); 931 nand->ecc.calculate = fsmc_read_hwecc_ecc1; 932 nand->ecc.correct = fsmc_correct_ecc1; 933 nand->ecc.hwctl = fsmc_enable_hwecc; 934 nand->ecc.bytes = 3; 935 nand->ecc.strength = 1; 936 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; 937 break; 938 939 case NAND_ECC_ENGINE_TYPE_SOFT: 940 if (nand->ecc.algo == NAND_ECC_ALGO_BCH) { 941 dev_info(host->dev, 942 "Using 4-bit SW BCH ECC scheme\n"); 943 break; 944 } 945 break; 946 947 case NAND_ECC_ENGINE_TYPE_ON_DIE: 948 break; 949 950 default: 951 dev_err(host->dev, "Unsupported ECC mode!\n"); 952 return -ENOTSUPP; 953 } 954 955 /* 956 * Don't set layout for BCH4 SW ECC. This will be 957 * generated later during BCH initialization. 958 */ 959 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 960 switch (mtd->oobsize) { 961 case 16: 962 case 64: 963 case 128: 964 mtd_set_ooblayout(mtd, 965 &fsmc_ecc1_ooblayout_ops); 966 break; 967 default: 968 dev_warn(host->dev, 969 "No oob scheme defined for oobsize %d\n", 970 mtd->oobsize); 971 return -EINVAL; 972 } 973 } 974 975 return 0; 976 } 977 978 static const struct nand_controller_ops fsmc_nand_controller_ops = { 979 .attach_chip = fsmc_nand_attach_chip, 980 .exec_op = fsmc_exec_op, 981 .setup_interface = fsmc_setup_interface, 982 }; 983 984 /** 985 * fsmc_nand_disable() - Disables the NAND bank 986 * @host: The instance to disable 987 */ 988 static void fsmc_nand_disable(struct fsmc_nand_data *host) 989 { 990 u32 val; 991 992 val = readl(host->regs_va + FSMC_PC); 993 val &= ~FSMC_ENABLE; 994 writel(val, host->regs_va + FSMC_PC); 995 } 996 997 /* 998 * fsmc_nand_probe - Probe function 999 * @pdev: platform device structure 1000 */ 1001 static int __init fsmc_nand_probe(struct platform_device *pdev) 1002 { 1003 struct fsmc_nand_data *host; 1004 struct mtd_info *mtd; 1005 struct nand_chip *nand; 1006 struct resource *res; 1007 void __iomem *base; 1008 dma_cap_mask_t mask; 1009 int ret = 0; 1010 u32 pid; 1011 int i; 1012 1013 /* Allocate memory for the device structure (and zero it) */ 1014 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 1015 if (!host) 1016 return -ENOMEM; 1017 1018 nand = &host->nand; 1019 1020 ret = fsmc_nand_probe_config_dt(pdev, host, nand); 1021 if (ret) 1022 return ret; 1023 1024 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); 1025 host->data_va = devm_ioremap_resource(&pdev->dev, res); 1026 if (IS_ERR(host->data_va)) 1027 return PTR_ERR(host->data_va); 1028 1029 host->data_pa = (dma_addr_t)res->start; 1030 1031 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); 1032 host->addr_va = devm_ioremap_resource(&pdev->dev, res); 1033 if (IS_ERR(host->addr_va)) 1034 return PTR_ERR(host->addr_va); 1035 1036 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); 1037 host->cmd_va = devm_ioremap_resource(&pdev->dev, res); 1038 if (IS_ERR(host->cmd_va)) 1039 return PTR_ERR(host->cmd_va); 1040 1041 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); 1042 base = devm_ioremap_resource(&pdev->dev, res); 1043 if (IS_ERR(base)) 1044 return PTR_ERR(base); 1045 1046 host->regs_va = base + FSMC_NOR_REG_SIZE + 1047 (host->bank * FSMC_NAND_BANK_SZ); 1048 1049 host->clk = devm_clk_get(&pdev->dev, NULL); 1050 if (IS_ERR(host->clk)) { 1051 dev_err(&pdev->dev, "failed to fetch block clock\n"); 1052 return PTR_ERR(host->clk); 1053 } 1054 1055 ret = clk_prepare_enable(host->clk); 1056 if (ret) 1057 return ret; 1058 1059 /* 1060 * This device ID is actually a common AMBA ID as used on the 1061 * AMBA PrimeCell bus. However it is not a PrimeCell. 1062 */ 1063 for (pid = 0, i = 0; i < 4; i++) 1064 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & 1065 255) << (i * 8); 1066 1067 host->pid = pid; 1068 1069 dev_info(&pdev->dev, 1070 "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n", 1071 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid), 1072 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid)); 1073 1074 host->dev = &pdev->dev; 1075 1076 if (host->mode == USE_DMA_ACCESS) 1077 init_completion(&host->dma_access_complete); 1078 1079 /* Link all private pointers */ 1080 mtd = nand_to_mtd(&host->nand); 1081 nand_set_flash_node(nand, pdev->dev.of_node); 1082 1083 mtd->dev.parent = &pdev->dev; 1084 1085 nand->badblockbits = 7; 1086 1087 if (host->mode == USE_DMA_ACCESS) { 1088 dma_cap_zero(mask); 1089 dma_cap_set(DMA_MEMCPY, mask); 1090 host->read_dma_chan = dma_request_channel(mask, filter, NULL); 1091 if (!host->read_dma_chan) { 1092 dev_err(&pdev->dev, "Unable to get read dma channel\n"); 1093 ret = -ENODEV; 1094 goto disable_clk; 1095 } 1096 host->write_dma_chan = dma_request_channel(mask, filter, NULL); 1097 if (!host->write_dma_chan) { 1098 dev_err(&pdev->dev, "Unable to get write dma channel\n"); 1099 ret = -ENODEV; 1100 goto release_dma_read_chan; 1101 } 1102 } 1103 1104 if (host->dev_timings) { 1105 fsmc_nand_setup(host, host->dev_timings); 1106 nand->options |= NAND_KEEP_TIMINGS; 1107 } 1108 1109 nand_controller_init(&host->base); 1110 host->base.ops = &fsmc_nand_controller_ops; 1111 nand->controller = &host->base; 1112 1113 /* 1114 * Scan to find existence of the device 1115 */ 1116 ret = nand_scan(nand, 1); 1117 if (ret) 1118 goto release_dma_write_chan; 1119 1120 mtd->name = "nand"; 1121 ret = mtd_device_register(mtd, NULL, 0); 1122 if (ret) 1123 goto cleanup_nand; 1124 1125 platform_set_drvdata(pdev, host); 1126 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); 1127 1128 return 0; 1129 1130 cleanup_nand: 1131 nand_cleanup(nand); 1132 release_dma_write_chan: 1133 if (host->mode == USE_DMA_ACCESS) 1134 dma_release_channel(host->write_dma_chan); 1135 release_dma_read_chan: 1136 if (host->mode == USE_DMA_ACCESS) 1137 dma_release_channel(host->read_dma_chan); 1138 disable_clk: 1139 fsmc_nand_disable(host); 1140 clk_disable_unprepare(host->clk); 1141 1142 return ret; 1143 } 1144 1145 /* 1146 * Clean up routine 1147 */ 1148 static int fsmc_nand_remove(struct platform_device *pdev) 1149 { 1150 struct fsmc_nand_data *host = platform_get_drvdata(pdev); 1151 1152 if (host) { 1153 struct nand_chip *chip = &host->nand; 1154 int ret; 1155 1156 ret = mtd_device_unregister(nand_to_mtd(chip)); 1157 WARN_ON(ret); 1158 nand_cleanup(chip); 1159 fsmc_nand_disable(host); 1160 1161 if (host->mode == USE_DMA_ACCESS) { 1162 dma_release_channel(host->write_dma_chan); 1163 dma_release_channel(host->read_dma_chan); 1164 } 1165 clk_disable_unprepare(host->clk); 1166 } 1167 1168 return 0; 1169 } 1170 1171 #ifdef CONFIG_PM_SLEEP 1172 static int fsmc_nand_suspend(struct device *dev) 1173 { 1174 struct fsmc_nand_data *host = dev_get_drvdata(dev); 1175 1176 if (host) 1177 clk_disable_unprepare(host->clk); 1178 1179 return 0; 1180 } 1181 1182 static int fsmc_nand_resume(struct device *dev) 1183 { 1184 struct fsmc_nand_data *host = dev_get_drvdata(dev); 1185 1186 if (host) { 1187 clk_prepare_enable(host->clk); 1188 if (host->dev_timings) 1189 fsmc_nand_setup(host, host->dev_timings); 1190 nand_reset(&host->nand, 0); 1191 } 1192 1193 return 0; 1194 } 1195 #endif 1196 1197 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume); 1198 1199 static const struct of_device_id fsmc_nand_id_table[] = { 1200 { .compatible = "st,spear600-fsmc-nand" }, 1201 { .compatible = "stericsson,fsmc-nand" }, 1202 {} 1203 }; 1204 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table); 1205 1206 static struct platform_driver fsmc_nand_driver = { 1207 .remove = fsmc_nand_remove, 1208 .driver = { 1209 .name = "fsmc-nand", 1210 .of_match_table = fsmc_nand_id_table, 1211 .pm = &fsmc_nand_pm_ops, 1212 }, 1213 }; 1214 1215 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe); 1216 1217 MODULE_LICENSE("GPL v2"); 1218 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi"); 1219 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms"); 1220