1 /* 2 * ST Microelectronics 3 * Flexible Static Memory Controller (FSMC) 4 * Driver for NAND portions 5 * 6 * Copyright © 2010 ST Microelectronics 7 * Vipin Kumar <vipin.kumar@st.com> 8 * Ashish Priyadarshi 9 * 10 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8) 11 * Copyright © 2007 STMicroelectronics Pvt. Ltd. 12 * Copyright © 2009 Alessandro Rubini 13 * 14 * This file is licensed under the terms of the GNU General Public 15 * License version 2. This program is licensed "as is" without any 16 * warranty of any kind, whether express or implied. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/completion.h> 21 #include <linux/dmaengine.h> 22 #include <linux/dma-direction.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/err.h> 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/resource.h> 28 #include <linux/sched.h> 29 #include <linux/types.h> 30 #include <linux/mtd/mtd.h> 31 #include <linux/mtd/rawnand.h> 32 #include <linux/mtd/nand_ecc.h> 33 #include <linux/platform_device.h> 34 #include <linux/of.h> 35 #include <linux/mtd/partitions.h> 36 #include <linux/io.h> 37 #include <linux/slab.h> 38 #include <linux/amba/bus.h> 39 #include <mtd/mtd-abi.h> 40 41 /* fsmc controller registers for NOR flash */ 42 #define CTRL 0x0 43 /* ctrl register definitions */ 44 #define BANK_ENABLE (1 << 0) 45 #define MUXED (1 << 1) 46 #define NOR_DEV (2 << 2) 47 #define WIDTH_8 (0 << 4) 48 #define WIDTH_16 (1 << 4) 49 #define RSTPWRDWN (1 << 6) 50 #define WPROT (1 << 7) 51 #define WRT_ENABLE (1 << 12) 52 #define WAIT_ENB (1 << 13) 53 54 #define CTRL_TIM 0x4 55 /* ctrl_tim register definitions */ 56 57 #define FSMC_NOR_BANK_SZ 0x8 58 #define FSMC_NOR_REG_SIZE 0x40 59 60 #define FSMC_NOR_REG(base, bank, reg) (base + \ 61 FSMC_NOR_BANK_SZ * (bank) + \ 62 reg) 63 64 /* fsmc controller registers for NAND flash */ 65 #define FSMC_PC 0x00 66 /* pc register definitions */ 67 #define FSMC_RESET (1 << 0) 68 #define FSMC_WAITON (1 << 1) 69 #define FSMC_ENABLE (1 << 2) 70 #define FSMC_DEVTYPE_NAND (1 << 3) 71 #define FSMC_DEVWID_8 (0 << 4) 72 #define FSMC_DEVWID_16 (1 << 4) 73 #define FSMC_ECCEN (1 << 6) 74 #define FSMC_ECCPLEN_512 (0 << 7) 75 #define FSMC_ECCPLEN_256 (1 << 7) 76 #define FSMC_TCLR_1 (1) 77 #define FSMC_TCLR_SHIFT (9) 78 #define FSMC_TCLR_MASK (0xF) 79 #define FSMC_TAR_1 (1) 80 #define FSMC_TAR_SHIFT (13) 81 #define FSMC_TAR_MASK (0xF) 82 #define STS 0x04 83 /* sts register definitions */ 84 #define FSMC_CODE_RDY (1 << 15) 85 #define COMM 0x08 86 /* comm register definitions */ 87 #define FSMC_TSET_0 0 88 #define FSMC_TSET_SHIFT 0 89 #define FSMC_TSET_MASK 0xFF 90 #define FSMC_TWAIT_6 6 91 #define FSMC_TWAIT_SHIFT 8 92 #define FSMC_TWAIT_MASK 0xFF 93 #define FSMC_THOLD_4 4 94 #define FSMC_THOLD_SHIFT 16 95 #define FSMC_THOLD_MASK 0xFF 96 #define FSMC_THIZ_1 1 97 #define FSMC_THIZ_SHIFT 24 98 #define FSMC_THIZ_MASK 0xFF 99 #define ATTRIB 0x0C 100 #define IOATA 0x10 101 #define ECC1 0x14 102 #define ECC2 0x18 103 #define ECC3 0x1C 104 #define FSMC_NAND_BANK_SZ 0x20 105 106 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) 107 108 struct fsmc_nand_timings { 109 uint8_t tclr; 110 uint8_t tar; 111 uint8_t thiz; 112 uint8_t thold; 113 uint8_t twait; 114 uint8_t tset; 115 }; 116 117 enum access_mode { 118 USE_DMA_ACCESS = 1, 119 USE_WORD_ACCESS, 120 }; 121 122 /** 123 * struct fsmc_nand_data - structure for FSMC NAND device state 124 * 125 * @pid: Part ID on the AMBA PrimeCell format 126 * @mtd: MTD info for a NAND flash. 127 * @nand: Chip related info for a NAND flash. 128 * @partitions: Partition info for a NAND Flash. 129 * @nr_partitions: Total number of partition of a NAND flash. 130 * 131 * @bank: Bank number for probed device. 132 * @clk: Clock structure for FSMC. 133 * 134 * @read_dma_chan: DMA channel for read access 135 * @write_dma_chan: DMA channel for write access to NAND 136 * @dma_access_complete: Completion structure 137 * 138 * @data_pa: NAND Physical port for Data. 139 * @data_va: NAND port for Data. 140 * @cmd_va: NAND port for Command. 141 * @addr_va: NAND port for Address. 142 * @regs_va: Registers base address for a given bank. 143 */ 144 struct fsmc_nand_data { 145 u32 pid; 146 struct nand_chip nand; 147 148 unsigned int bank; 149 struct device *dev; 150 enum access_mode mode; 151 struct clk *clk; 152 153 /* DMA related objects */ 154 struct dma_chan *read_dma_chan; 155 struct dma_chan *write_dma_chan; 156 struct completion dma_access_complete; 157 158 struct fsmc_nand_timings *dev_timings; 159 160 dma_addr_t data_pa; 161 void __iomem *data_va; 162 void __iomem *cmd_va; 163 void __iomem *addr_va; 164 void __iomem *regs_va; 165 }; 166 167 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section, 168 struct mtd_oob_region *oobregion) 169 { 170 struct nand_chip *chip = mtd_to_nand(mtd); 171 172 if (section >= chip->ecc.steps) 173 return -ERANGE; 174 175 oobregion->offset = (section * 16) + 2; 176 oobregion->length = 3; 177 178 return 0; 179 } 180 181 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section, 182 struct mtd_oob_region *oobregion) 183 { 184 struct nand_chip *chip = mtd_to_nand(mtd); 185 186 if (section >= chip->ecc.steps) 187 return -ERANGE; 188 189 oobregion->offset = (section * 16) + 8; 190 191 if (section < chip->ecc.steps - 1) 192 oobregion->length = 8; 193 else 194 oobregion->length = mtd->oobsize - oobregion->offset; 195 196 return 0; 197 } 198 199 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = { 200 .ecc = fsmc_ecc1_ooblayout_ecc, 201 .free = fsmc_ecc1_ooblayout_free, 202 }; 203 204 /* 205 * ECC placement definitions in oobfree type format. 206 * There are 13 bytes of ecc for every 512 byte block and it has to be read 207 * consecutively and immediately after the 512 byte data block for hardware to 208 * generate the error bit offsets in 512 byte data. 209 */ 210 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section, 211 struct mtd_oob_region *oobregion) 212 { 213 struct nand_chip *chip = mtd_to_nand(mtd); 214 215 if (section >= chip->ecc.steps) 216 return -ERANGE; 217 218 oobregion->length = chip->ecc.bytes; 219 220 if (!section && mtd->writesize <= 512) 221 oobregion->offset = 0; 222 else 223 oobregion->offset = (section * 16) + 2; 224 225 return 0; 226 } 227 228 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section, 229 struct mtd_oob_region *oobregion) 230 { 231 struct nand_chip *chip = mtd_to_nand(mtd); 232 233 if (section >= chip->ecc.steps) 234 return -ERANGE; 235 236 oobregion->offset = (section * 16) + 15; 237 238 if (section < chip->ecc.steps - 1) 239 oobregion->length = 3; 240 else 241 oobregion->length = mtd->oobsize - oobregion->offset; 242 243 return 0; 244 } 245 246 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = { 247 .ecc = fsmc_ecc4_ooblayout_ecc, 248 .free = fsmc_ecc4_ooblayout_free, 249 }; 250 251 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd) 252 { 253 return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand); 254 } 255 256 /* 257 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine 258 * 259 * This routine initializes timing parameters related to NAND memory access in 260 * FSMC registers 261 */ 262 static void fsmc_nand_setup(struct fsmc_nand_data *host, 263 struct fsmc_nand_timings *tims) 264 { 265 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; 266 uint32_t tclr, tar, thiz, thold, twait, tset; 267 268 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT; 269 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT; 270 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT; 271 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT; 272 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; 273 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; 274 275 if (host->nand.options & NAND_BUSWIDTH_16) 276 writel_relaxed(value | FSMC_DEVWID_16, 277 host->regs_va + FSMC_PC); 278 else 279 writel_relaxed(value | FSMC_DEVWID_8, host->regs_va + FSMC_PC); 280 281 writel_relaxed(readl(host->regs_va + FSMC_PC) | tclr | tar, 282 host->regs_va + FSMC_PC); 283 writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM); 284 writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB); 285 } 286 287 static int fsmc_calc_timings(struct fsmc_nand_data *host, 288 const struct nand_sdr_timings *sdrt, 289 struct fsmc_nand_timings *tims) 290 { 291 unsigned long hclk = clk_get_rate(host->clk); 292 unsigned long hclkn = NSEC_PER_SEC / hclk; 293 uint32_t thiz, thold, twait, tset; 294 295 if (sdrt->tRC_min < 30000) 296 return -EOPNOTSUPP; 297 298 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1; 299 if (tims->tar > FSMC_TAR_MASK) 300 tims->tar = FSMC_TAR_MASK; 301 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1; 302 if (tims->tclr > FSMC_TCLR_MASK) 303 tims->tclr = FSMC_TCLR_MASK; 304 305 thiz = sdrt->tCS_min - sdrt->tWP_min; 306 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn); 307 308 thold = sdrt->tDH_min; 309 if (thold < sdrt->tCH_min) 310 thold = sdrt->tCH_min; 311 if (thold < sdrt->tCLH_min) 312 thold = sdrt->tCLH_min; 313 if (thold < sdrt->tWH_min) 314 thold = sdrt->tWH_min; 315 if (thold < sdrt->tALH_min) 316 thold = sdrt->tALH_min; 317 if (thold < sdrt->tREH_min) 318 thold = sdrt->tREH_min; 319 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn); 320 if (tims->thold == 0) 321 tims->thold = 1; 322 else if (tims->thold > FSMC_THOLD_MASK) 323 tims->thold = FSMC_THOLD_MASK; 324 325 twait = max(sdrt->tRP_min, sdrt->tWP_min); 326 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1; 327 if (tims->twait == 0) 328 tims->twait = 1; 329 else if (tims->twait > FSMC_TWAIT_MASK) 330 tims->twait = FSMC_TWAIT_MASK; 331 332 tset = max(sdrt->tCS_min - sdrt->tWP_min, 333 sdrt->tCEA_max - sdrt->tREA_max); 334 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1; 335 if (tims->tset == 0) 336 tims->tset = 1; 337 else if (tims->tset > FSMC_TSET_MASK) 338 tims->tset = FSMC_TSET_MASK; 339 340 return 0; 341 } 342 343 static int fsmc_setup_data_interface(struct mtd_info *mtd, int csline, 344 const struct nand_data_interface *conf) 345 { 346 struct nand_chip *nand = mtd_to_nand(mtd); 347 struct fsmc_nand_data *host = nand_get_controller_data(nand); 348 struct fsmc_nand_timings tims; 349 const struct nand_sdr_timings *sdrt; 350 int ret; 351 352 sdrt = nand_get_sdr_timings(conf); 353 if (IS_ERR(sdrt)) 354 return PTR_ERR(sdrt); 355 356 ret = fsmc_calc_timings(host, sdrt, &tims); 357 if (ret) 358 return ret; 359 360 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 361 return 0; 362 363 fsmc_nand_setup(host, &tims); 364 365 return 0; 366 } 367 368 /* 369 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers 370 */ 371 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) 372 { 373 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 374 375 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256, 376 host->regs_va + FSMC_PC); 377 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN, 378 host->regs_va + FSMC_PC); 379 writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN, 380 host->regs_va + FSMC_PC); 381 } 382 383 /* 384 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by 385 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to 386 * max of 8-bits) 387 */ 388 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data, 389 uint8_t *ecc) 390 { 391 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 392 uint32_t ecc_tmp; 393 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; 394 395 do { 396 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY) 397 break; 398 else 399 cond_resched(); 400 } while (!time_after_eq(jiffies, deadline)); 401 402 if (time_after_eq(jiffies, deadline)) { 403 dev_err(host->dev, "calculate ecc timed out\n"); 404 return -ETIMEDOUT; 405 } 406 407 ecc_tmp = readl_relaxed(host->regs_va + ECC1); 408 ecc[0] = (uint8_t) (ecc_tmp >> 0); 409 ecc[1] = (uint8_t) (ecc_tmp >> 8); 410 ecc[2] = (uint8_t) (ecc_tmp >> 16); 411 ecc[3] = (uint8_t) (ecc_tmp >> 24); 412 413 ecc_tmp = readl_relaxed(host->regs_va + ECC2); 414 ecc[4] = (uint8_t) (ecc_tmp >> 0); 415 ecc[5] = (uint8_t) (ecc_tmp >> 8); 416 ecc[6] = (uint8_t) (ecc_tmp >> 16); 417 ecc[7] = (uint8_t) (ecc_tmp >> 24); 418 419 ecc_tmp = readl_relaxed(host->regs_va + ECC3); 420 ecc[8] = (uint8_t) (ecc_tmp >> 0); 421 ecc[9] = (uint8_t) (ecc_tmp >> 8); 422 ecc[10] = (uint8_t) (ecc_tmp >> 16); 423 ecc[11] = (uint8_t) (ecc_tmp >> 24); 424 425 ecc_tmp = readl_relaxed(host->regs_va + STS); 426 ecc[12] = (uint8_t) (ecc_tmp >> 16); 427 428 return 0; 429 } 430 431 /* 432 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by 433 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to 434 * max of 1-bit) 435 */ 436 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data, 437 uint8_t *ecc) 438 { 439 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 440 uint32_t ecc_tmp; 441 442 ecc_tmp = readl_relaxed(host->regs_va + ECC1); 443 ecc[0] = (uint8_t) (ecc_tmp >> 0); 444 ecc[1] = (uint8_t) (ecc_tmp >> 8); 445 ecc[2] = (uint8_t) (ecc_tmp >> 16); 446 447 return 0; 448 } 449 450 /* Count the number of 0's in buff upto a max of max_bits */ 451 static int count_written_bits(uint8_t *buff, int size, int max_bits) 452 { 453 int k, written_bits = 0; 454 455 for (k = 0; k < size; k++) { 456 written_bits += hweight8(~buff[k]); 457 if (written_bits > max_bits) 458 break; 459 } 460 461 return written_bits; 462 } 463 464 static void dma_complete(void *param) 465 { 466 struct fsmc_nand_data *host = param; 467 468 complete(&host->dma_access_complete); 469 } 470 471 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len, 472 enum dma_data_direction direction) 473 { 474 struct dma_chan *chan; 475 struct dma_device *dma_dev; 476 struct dma_async_tx_descriptor *tx; 477 dma_addr_t dma_dst, dma_src, dma_addr; 478 dma_cookie_t cookie; 479 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 480 int ret; 481 unsigned long time_left; 482 483 if (direction == DMA_TO_DEVICE) 484 chan = host->write_dma_chan; 485 else if (direction == DMA_FROM_DEVICE) 486 chan = host->read_dma_chan; 487 else 488 return -EINVAL; 489 490 dma_dev = chan->device; 491 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction); 492 493 if (direction == DMA_TO_DEVICE) { 494 dma_src = dma_addr; 495 dma_dst = host->data_pa; 496 } else { 497 dma_src = host->data_pa; 498 dma_dst = dma_addr; 499 } 500 501 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, 502 len, flags); 503 if (!tx) { 504 dev_err(host->dev, "device_prep_dma_memcpy error\n"); 505 ret = -EIO; 506 goto unmap_dma; 507 } 508 509 tx->callback = dma_complete; 510 tx->callback_param = host; 511 cookie = tx->tx_submit(tx); 512 513 ret = dma_submit_error(cookie); 514 if (ret) { 515 dev_err(host->dev, "dma_submit_error %d\n", cookie); 516 goto unmap_dma; 517 } 518 519 dma_async_issue_pending(chan); 520 521 time_left = 522 wait_for_completion_timeout(&host->dma_access_complete, 523 msecs_to_jiffies(3000)); 524 if (time_left == 0) { 525 dmaengine_terminate_all(chan); 526 dev_err(host->dev, "wait_for_completion_timeout\n"); 527 ret = -ETIMEDOUT; 528 goto unmap_dma; 529 } 530 531 ret = 0; 532 533 unmap_dma: 534 dma_unmap_single(dma_dev->dev, dma_addr, len, direction); 535 536 return ret; 537 } 538 539 /* 540 * fsmc_write_buf - write buffer to chip 541 * @mtd: MTD device structure 542 * @buf: data buffer 543 * @len: number of bytes to write 544 */ 545 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 546 { 547 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 548 int i; 549 550 if (IS_ALIGNED((uintptr_t)buf, sizeof(uint32_t)) && 551 IS_ALIGNED(len, sizeof(uint32_t))) { 552 uint32_t *p = (uint32_t *)buf; 553 len = len >> 2; 554 for (i = 0; i < len; i++) 555 writel_relaxed(p[i], host->data_va); 556 } else { 557 for (i = 0; i < len; i++) 558 writeb_relaxed(buf[i], host->data_va); 559 } 560 } 561 562 /* 563 * fsmc_read_buf - read chip data into buffer 564 * @mtd: MTD device structure 565 * @buf: buffer to store date 566 * @len: number of bytes to read 567 */ 568 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 569 { 570 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 571 int i; 572 573 if (IS_ALIGNED((uintptr_t)buf, sizeof(uint32_t)) && 574 IS_ALIGNED(len, sizeof(uint32_t))) { 575 uint32_t *p = (uint32_t *)buf; 576 len = len >> 2; 577 for (i = 0; i < len; i++) 578 p[i] = readl_relaxed(host->data_va); 579 } else { 580 for (i = 0; i < len; i++) 581 buf[i] = readb_relaxed(host->data_va); 582 } 583 } 584 585 /* 586 * fsmc_read_buf_dma - read chip data into buffer 587 * @mtd: MTD device structure 588 * @buf: buffer to store date 589 * @len: number of bytes to read 590 */ 591 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len) 592 { 593 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 594 595 dma_xfer(host, buf, len, DMA_FROM_DEVICE); 596 } 597 598 /* 599 * fsmc_write_buf_dma - write buffer to chip 600 * @mtd: MTD device structure 601 * @buf: data buffer 602 * @len: number of bytes to write 603 */ 604 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf, 605 int len) 606 { 607 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 608 609 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE); 610 } 611 612 /* fsmc_select_chip - assert or deassert nCE */ 613 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr) 614 { 615 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 616 u32 pc; 617 618 /* Support only one CS */ 619 if (chipnr > 0) 620 return; 621 622 pc = readl(host->regs_va + FSMC_PC); 623 if (chipnr < 0) 624 writel_relaxed(pc & ~FSMC_ENABLE, host->regs_va + FSMC_PC); 625 else 626 writel_relaxed(pc | FSMC_ENABLE, host->regs_va + FSMC_PC); 627 628 /* nCE line must be asserted before starting any operation */ 629 mb(); 630 } 631 632 /* 633 * fsmc_exec_op - hook called by the core to execute NAND operations 634 * 635 * This controller is simple enough and thus does not need to use the parser 636 * provided by the core, instead, handle every situation here. 637 */ 638 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op, 639 bool check_only) 640 { 641 struct mtd_info *mtd = nand_to_mtd(chip); 642 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 643 const struct nand_op_instr *instr = NULL; 644 int ret = 0; 645 unsigned int op_id; 646 int i; 647 648 pr_debug("Executing operation [%d instructions]:\n", op->ninstrs); 649 for (op_id = 0; op_id < op->ninstrs; op_id++) { 650 instr = &op->instrs[op_id]; 651 652 switch (instr->type) { 653 case NAND_OP_CMD_INSTR: 654 pr_debug(" ->CMD [0x%02x]\n", 655 instr->ctx.cmd.opcode); 656 657 writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va); 658 break; 659 660 case NAND_OP_ADDR_INSTR: 661 pr_debug(" ->ADDR [%d cyc]", 662 instr->ctx.addr.naddrs); 663 664 for (i = 0; i < instr->ctx.addr.naddrs; i++) 665 writeb_relaxed(instr->ctx.addr.addrs[i], 666 host->addr_va); 667 break; 668 669 case NAND_OP_DATA_IN_INSTR: 670 pr_debug(" ->DATA_IN [%d B%s]\n", instr->ctx.data.len, 671 instr->ctx.data.force_8bit ? 672 ", force 8-bit" : ""); 673 674 if (host->mode == USE_DMA_ACCESS) 675 fsmc_read_buf_dma(mtd, instr->ctx.data.buf.in, 676 instr->ctx.data.len); 677 else 678 fsmc_read_buf(mtd, instr->ctx.data.buf.in, 679 instr->ctx.data.len); 680 break; 681 682 case NAND_OP_DATA_OUT_INSTR: 683 pr_debug(" ->DATA_OUT [%d B%s]\n", instr->ctx.data.len, 684 instr->ctx.data.force_8bit ? 685 ", force 8-bit" : ""); 686 687 if (host->mode == USE_DMA_ACCESS) 688 fsmc_write_buf_dma(mtd, instr->ctx.data.buf.out, 689 instr->ctx.data.len); 690 else 691 fsmc_write_buf(mtd, instr->ctx.data.buf.out, 692 instr->ctx.data.len); 693 break; 694 695 case NAND_OP_WAITRDY_INSTR: 696 pr_debug(" ->WAITRDY [max %d ms]\n", 697 instr->ctx.waitrdy.timeout_ms); 698 699 ret = nand_soft_waitrdy(chip, 700 instr->ctx.waitrdy.timeout_ms); 701 break; 702 } 703 } 704 705 return ret; 706 } 707 708 /* 709 * fsmc_read_page_hwecc 710 * @mtd: mtd info structure 711 * @chip: nand chip info structure 712 * @buf: buffer to store read data 713 * @oob_required: caller expects OOB data read to chip->oob_poi 714 * @page: page number to read 715 * 716 * This routine is needed for fsmc version 8 as reading from NAND chip has to be 717 * performed in a strict sequence as follows: 718 * data(512 byte) -> ecc(13 byte) 719 * After this read, fsmc hardware generates and reports error data bits(up to a 720 * max of 8 bits) 721 */ 722 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 723 uint8_t *buf, int oob_required, int page) 724 { 725 int i, j, s, stat, eccsize = chip->ecc.size; 726 int eccbytes = chip->ecc.bytes; 727 int eccsteps = chip->ecc.steps; 728 uint8_t *p = buf; 729 uint8_t *ecc_calc = chip->ecc.calc_buf; 730 uint8_t *ecc_code = chip->ecc.code_buf; 731 int off, len, group = 0; 732 /* 733 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we 734 * end up reading 14 bytes (7 words) from oob. The local array is 735 * to maintain word alignment 736 */ 737 uint16_t ecc_oob[7]; 738 uint8_t *oob = (uint8_t *)&ecc_oob[0]; 739 unsigned int max_bitflips = 0; 740 741 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { 742 nand_read_page_op(chip, page, s * eccsize, NULL, 0); 743 chip->ecc.hwctl(mtd, NAND_ECC_READ); 744 nand_read_data_op(chip, p, eccsize, false); 745 746 for (j = 0; j < eccbytes;) { 747 struct mtd_oob_region oobregion; 748 int ret; 749 750 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion); 751 if (ret) 752 return ret; 753 754 off = oobregion.offset; 755 len = oobregion.length; 756 757 /* 758 * length is intentionally kept a higher multiple of 2 759 * to read at least 13 bytes even in case of 16 bit NAND 760 * devices 761 */ 762 if (chip->options & NAND_BUSWIDTH_16) 763 len = roundup(len, 2); 764 765 nand_read_oob_op(chip, page, off, oob + j, len); 766 j += len; 767 } 768 769 memcpy(&ecc_code[i], oob, chip->ecc.bytes); 770 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 771 772 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 773 if (stat < 0) { 774 mtd->ecc_stats.failed++; 775 } else { 776 mtd->ecc_stats.corrected += stat; 777 max_bitflips = max_t(unsigned int, max_bitflips, stat); 778 } 779 } 780 781 return max_bitflips; 782 } 783 784 /* 785 * fsmc_bch8_correct_data 786 * @mtd: mtd info structure 787 * @dat: buffer of read data 788 * @read_ecc: ecc read from device spare area 789 * @calc_ecc: ecc calculated from read data 790 * 791 * calc_ecc is a 104 bit information containing maximum of 8 error 792 * offset informations of 13 bits each in 512 bytes of read data. 793 */ 794 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat, 795 uint8_t *read_ecc, uint8_t *calc_ecc) 796 { 797 struct nand_chip *chip = mtd_to_nand(mtd); 798 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 799 uint32_t err_idx[8]; 800 uint32_t num_err, i; 801 uint32_t ecc1, ecc2, ecc3, ecc4; 802 803 num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF; 804 805 /* no bit flipping */ 806 if (likely(num_err == 0)) 807 return 0; 808 809 /* too many errors */ 810 if (unlikely(num_err > 8)) { 811 /* 812 * This is a temporary erase check. A newly erased page read 813 * would result in an ecc error because the oob data is also 814 * erased to FF and the calculated ecc for an FF data is not 815 * FF..FF. 816 * This is a workaround to skip performing correction in case 817 * data is FF..FF 818 * 819 * Logic: 820 * For every page, each bit written as 0 is counted until these 821 * number of bits are greater than 8 (the maximum correction 822 * capability of FSMC for each 512 + 13 bytes) 823 */ 824 825 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); 826 int bits_data = count_written_bits(dat, chip->ecc.size, 8); 827 828 if ((bits_ecc + bits_data) <= 8) { 829 if (bits_data) 830 memset(dat, 0xff, chip->ecc.size); 831 return bits_data; 832 } 833 834 return -EBADMSG; 835 } 836 837 /* 838 * ------------------- calc_ecc[] bit wise -----------|--13 bits--| 839 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| 840 * 841 * calc_ecc is a 104 bit information containing maximum of 8 error 842 * offset informations of 13 bits each. calc_ecc is copied into a 843 * uint64_t array and error offset indexes are populated in err_idx 844 * array 845 */ 846 ecc1 = readl_relaxed(host->regs_va + ECC1); 847 ecc2 = readl_relaxed(host->regs_va + ECC2); 848 ecc3 = readl_relaxed(host->regs_va + ECC3); 849 ecc4 = readl_relaxed(host->regs_va + STS); 850 851 err_idx[0] = (ecc1 >> 0) & 0x1FFF; 852 err_idx[1] = (ecc1 >> 13) & 0x1FFF; 853 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); 854 err_idx[3] = (ecc2 >> 7) & 0x1FFF; 855 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); 856 err_idx[5] = (ecc3 >> 1) & 0x1FFF; 857 err_idx[6] = (ecc3 >> 14) & 0x1FFF; 858 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); 859 860 i = 0; 861 while (num_err--) { 862 change_bit(0, (unsigned long *)&err_idx[i]); 863 change_bit(1, (unsigned long *)&err_idx[i]); 864 865 if (err_idx[i] < chip->ecc.size * 8) { 866 change_bit(err_idx[i], (unsigned long *)dat); 867 i++; 868 } 869 } 870 return i; 871 } 872 873 static bool filter(struct dma_chan *chan, void *slave) 874 { 875 chan->private = slave; 876 return true; 877 } 878 879 static int fsmc_nand_probe_config_dt(struct platform_device *pdev, 880 struct fsmc_nand_data *host, 881 struct nand_chip *nand) 882 { 883 struct device_node *np = pdev->dev.of_node; 884 u32 val; 885 int ret; 886 887 nand->options = 0; 888 889 if (!of_property_read_u32(np, "bank-width", &val)) { 890 if (val == 2) { 891 nand->options |= NAND_BUSWIDTH_16; 892 } else if (val != 1) { 893 dev_err(&pdev->dev, "invalid bank-width %u\n", val); 894 return -EINVAL; 895 } 896 } 897 898 if (of_get_property(np, "nand-skip-bbtscan", NULL)) 899 nand->options |= NAND_SKIP_BBTSCAN; 900 901 host->dev_timings = devm_kzalloc(&pdev->dev, 902 sizeof(*host->dev_timings), GFP_KERNEL); 903 if (!host->dev_timings) 904 return -ENOMEM; 905 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings, 906 sizeof(*host->dev_timings)); 907 if (ret) 908 host->dev_timings = NULL; 909 910 /* Set default NAND bank to 0 */ 911 host->bank = 0; 912 if (!of_property_read_u32(np, "bank", &val)) { 913 if (val > 3) { 914 dev_err(&pdev->dev, "invalid bank %u\n", val); 915 return -EINVAL; 916 } 917 host->bank = val; 918 } 919 return 0; 920 } 921 922 static int fsmc_nand_attach_chip(struct nand_chip *nand) 923 { 924 struct mtd_info *mtd = nand_to_mtd(nand); 925 struct fsmc_nand_data *host = mtd_to_fsmc(mtd); 926 927 if (AMBA_REV_BITS(host->pid) >= 8) { 928 switch (mtd->oobsize) { 929 case 16: 930 case 64: 931 case 128: 932 case 224: 933 case 256: 934 break; 935 default: 936 dev_warn(host->dev, 937 "No oob scheme defined for oobsize %d\n", 938 mtd->oobsize); 939 return -EINVAL; 940 } 941 942 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops); 943 944 return 0; 945 } 946 947 switch (nand->ecc.mode) { 948 case NAND_ECC_HW: 949 dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); 950 nand->ecc.calculate = fsmc_read_hwecc_ecc1; 951 nand->ecc.correct = nand_correct_data; 952 nand->ecc.bytes = 3; 953 nand->ecc.strength = 1; 954 break; 955 956 case NAND_ECC_SOFT: 957 if (nand->ecc.algo == NAND_ECC_BCH) { 958 dev_info(host->dev, 959 "Using 4-bit SW BCH ECC scheme\n"); 960 break; 961 } 962 963 case NAND_ECC_ON_DIE: 964 break; 965 966 default: 967 dev_err(host->dev, "Unsupported ECC mode!\n"); 968 return -ENOTSUPP; 969 } 970 971 /* 972 * Don't set layout for BCH4 SW ECC. This will be 973 * generated later in nand_bch_init() later. 974 */ 975 if (nand->ecc.mode == NAND_ECC_HW) { 976 switch (mtd->oobsize) { 977 case 16: 978 case 64: 979 case 128: 980 mtd_set_ooblayout(mtd, 981 &fsmc_ecc1_ooblayout_ops); 982 break; 983 default: 984 dev_warn(host->dev, 985 "No oob scheme defined for oobsize %d\n", 986 mtd->oobsize); 987 return -EINVAL; 988 } 989 } 990 991 return 0; 992 } 993 994 static const struct nand_controller_ops fsmc_nand_controller_ops = { 995 .attach_chip = fsmc_nand_attach_chip, 996 }; 997 998 /* 999 * fsmc_nand_probe - Probe function 1000 * @pdev: platform device structure 1001 */ 1002 static int __init fsmc_nand_probe(struct platform_device *pdev) 1003 { 1004 struct fsmc_nand_data *host; 1005 struct mtd_info *mtd; 1006 struct nand_chip *nand; 1007 struct resource *res; 1008 void __iomem *base; 1009 dma_cap_mask_t mask; 1010 int ret = 0; 1011 u32 pid; 1012 int i; 1013 1014 /* Allocate memory for the device structure (and zero it) */ 1015 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 1016 if (!host) 1017 return -ENOMEM; 1018 1019 nand = &host->nand; 1020 1021 ret = fsmc_nand_probe_config_dt(pdev, host, nand); 1022 if (ret) 1023 return ret; 1024 1025 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); 1026 host->data_va = devm_ioremap_resource(&pdev->dev, res); 1027 if (IS_ERR(host->data_va)) 1028 return PTR_ERR(host->data_va); 1029 1030 host->data_pa = (dma_addr_t)res->start; 1031 1032 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); 1033 host->addr_va = devm_ioremap_resource(&pdev->dev, res); 1034 if (IS_ERR(host->addr_va)) 1035 return PTR_ERR(host->addr_va); 1036 1037 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); 1038 host->cmd_va = devm_ioremap_resource(&pdev->dev, res); 1039 if (IS_ERR(host->cmd_va)) 1040 return PTR_ERR(host->cmd_va); 1041 1042 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); 1043 base = devm_ioremap_resource(&pdev->dev, res); 1044 if (IS_ERR(base)) 1045 return PTR_ERR(base); 1046 1047 host->regs_va = base + FSMC_NOR_REG_SIZE + 1048 (host->bank * FSMC_NAND_BANK_SZ); 1049 1050 host->clk = devm_clk_get(&pdev->dev, NULL); 1051 if (IS_ERR(host->clk)) { 1052 dev_err(&pdev->dev, "failed to fetch block clock\n"); 1053 return PTR_ERR(host->clk); 1054 } 1055 1056 ret = clk_prepare_enable(host->clk); 1057 if (ret) 1058 return ret; 1059 1060 /* 1061 * This device ID is actually a common AMBA ID as used on the 1062 * AMBA PrimeCell bus. However it is not a PrimeCell. 1063 */ 1064 for (pid = 0, i = 0; i < 4; i++) 1065 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8); 1066 host->pid = pid; 1067 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, " 1068 "revision %02x, config %02x\n", 1069 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid), 1070 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid)); 1071 1072 host->dev = &pdev->dev; 1073 1074 if (host->mode == USE_DMA_ACCESS) 1075 init_completion(&host->dma_access_complete); 1076 1077 /* Link all private pointers */ 1078 mtd = nand_to_mtd(&host->nand); 1079 nand_set_controller_data(nand, host); 1080 nand_set_flash_node(nand, pdev->dev.of_node); 1081 1082 mtd->dev.parent = &pdev->dev; 1083 nand->exec_op = fsmc_exec_op; 1084 nand->select_chip = fsmc_select_chip; 1085 nand->chip_delay = 30; 1086 1087 /* 1088 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident() 1089 * can overwrite this value if the DT provides a different value. 1090 */ 1091 nand->ecc.mode = NAND_ECC_HW; 1092 nand->ecc.hwctl = fsmc_enable_hwecc; 1093 nand->ecc.size = 512; 1094 nand->badblockbits = 7; 1095 1096 if (host->mode == USE_DMA_ACCESS) { 1097 dma_cap_zero(mask); 1098 dma_cap_set(DMA_MEMCPY, mask); 1099 host->read_dma_chan = dma_request_channel(mask, filter, NULL); 1100 if (!host->read_dma_chan) { 1101 dev_err(&pdev->dev, "Unable to get read dma channel\n"); 1102 goto disable_clk; 1103 } 1104 host->write_dma_chan = dma_request_channel(mask, filter, NULL); 1105 if (!host->write_dma_chan) { 1106 dev_err(&pdev->dev, "Unable to get write dma channel\n"); 1107 goto release_dma_read_chan; 1108 } 1109 } 1110 1111 if (host->dev_timings) 1112 fsmc_nand_setup(host, host->dev_timings); 1113 else 1114 nand->setup_data_interface = fsmc_setup_data_interface; 1115 1116 if (AMBA_REV_BITS(host->pid) >= 8) { 1117 nand->ecc.read_page = fsmc_read_page_hwecc; 1118 nand->ecc.calculate = fsmc_read_hwecc_ecc4; 1119 nand->ecc.correct = fsmc_bch8_correct_data; 1120 nand->ecc.bytes = 13; 1121 nand->ecc.strength = 8; 1122 } 1123 1124 /* 1125 * Scan to find existence of the device 1126 */ 1127 nand->dummy_controller.ops = &fsmc_nand_controller_ops; 1128 ret = nand_scan(mtd, 1); 1129 if (ret) 1130 goto release_dma_write_chan; 1131 1132 mtd->name = "nand"; 1133 ret = mtd_device_register(mtd, NULL, 0); 1134 if (ret) 1135 goto cleanup_nand; 1136 1137 platform_set_drvdata(pdev, host); 1138 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); 1139 1140 return 0; 1141 1142 cleanup_nand: 1143 nand_cleanup(nand); 1144 release_dma_write_chan: 1145 if (host->mode == USE_DMA_ACCESS) 1146 dma_release_channel(host->write_dma_chan); 1147 release_dma_read_chan: 1148 if (host->mode == USE_DMA_ACCESS) 1149 dma_release_channel(host->read_dma_chan); 1150 disable_clk: 1151 clk_disable_unprepare(host->clk); 1152 1153 return ret; 1154 } 1155 1156 /* 1157 * Clean up routine 1158 */ 1159 static int fsmc_nand_remove(struct platform_device *pdev) 1160 { 1161 struct fsmc_nand_data *host = platform_get_drvdata(pdev); 1162 1163 if (host) { 1164 nand_release(nand_to_mtd(&host->nand)); 1165 1166 if (host->mode == USE_DMA_ACCESS) { 1167 dma_release_channel(host->write_dma_chan); 1168 dma_release_channel(host->read_dma_chan); 1169 } 1170 clk_disable_unprepare(host->clk); 1171 } 1172 1173 return 0; 1174 } 1175 1176 #ifdef CONFIG_PM_SLEEP 1177 static int fsmc_nand_suspend(struct device *dev) 1178 { 1179 struct fsmc_nand_data *host = dev_get_drvdata(dev); 1180 if (host) 1181 clk_disable_unprepare(host->clk); 1182 return 0; 1183 } 1184 1185 static int fsmc_nand_resume(struct device *dev) 1186 { 1187 struct fsmc_nand_data *host = dev_get_drvdata(dev); 1188 if (host) { 1189 clk_prepare_enable(host->clk); 1190 if (host->dev_timings) 1191 fsmc_nand_setup(host, host->dev_timings); 1192 } 1193 return 0; 1194 } 1195 #endif 1196 1197 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume); 1198 1199 static const struct of_device_id fsmc_nand_id_table[] = { 1200 { .compatible = "st,spear600-fsmc-nand" }, 1201 { .compatible = "stericsson,fsmc-nand" }, 1202 {} 1203 }; 1204 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table); 1205 1206 static struct platform_driver fsmc_nand_driver = { 1207 .remove = fsmc_nand_remove, 1208 .driver = { 1209 .name = "fsmc-nand", 1210 .of_match_table = fsmc_nand_id_table, 1211 .pm = &fsmc_nand_pm_ops, 1212 }, 1213 }; 1214 1215 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe); 1216 1217 MODULE_LICENSE("GPL"); 1218 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi"); 1219 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms"); 1220