1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ST Microelectronics 4 * Flexible Static Memory Controller (FSMC) 5 * Driver for NAND portions 6 * 7 * Copyright © 2010 ST Microelectronics 8 * Vipin Kumar <vipin.kumar@st.com> 9 * Ashish Priyadarshi 10 * 11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8) 12 * Copyright © 2007 STMicroelectronics Pvt. Ltd. 13 * Copyright © 2009 Alessandro Rubini 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/completion.h> 18 #include <linux/dmaengine.h> 19 #include <linux/dma-direction.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/err.h> 22 #include <linux/init.h> 23 #include <linux/module.h> 24 #include <linux/resource.h> 25 #include <linux/sched.h> 26 #include <linux/types.h> 27 #include <linux/mtd/mtd.h> 28 #include <linux/mtd/rawnand.h> 29 #include <linux/mtd/nand_ecc.h> 30 #include <linux/platform_device.h> 31 #include <linux/of.h> 32 #include <linux/mtd/partitions.h> 33 #include <linux/io.h> 34 #include <linux/slab.h> 35 #include <linux/amba/bus.h> 36 #include <mtd/mtd-abi.h> 37 38 /* fsmc controller registers for NOR flash */ 39 #define CTRL 0x0 40 /* ctrl register definitions */ 41 #define BANK_ENABLE BIT(0) 42 #define MUXED BIT(1) 43 #define NOR_DEV (2 << 2) 44 #define WIDTH_16 BIT(4) 45 #define RSTPWRDWN BIT(6) 46 #define WPROT BIT(7) 47 #define WRT_ENABLE BIT(12) 48 #define WAIT_ENB BIT(13) 49 50 #define CTRL_TIM 0x4 51 /* ctrl_tim register definitions */ 52 53 #define FSMC_NOR_BANK_SZ 0x8 54 #define FSMC_NOR_REG_SIZE 0x40 55 56 #define FSMC_NOR_REG(base, bank, reg) ((base) + \ 57 (FSMC_NOR_BANK_SZ * (bank)) + \ 58 (reg)) 59 60 /* fsmc controller registers for NAND flash */ 61 #define FSMC_PC 0x00 62 /* pc register definitions */ 63 #define FSMC_RESET BIT(0) 64 #define FSMC_WAITON BIT(1) 65 #define FSMC_ENABLE BIT(2) 66 #define FSMC_DEVTYPE_NAND BIT(3) 67 #define FSMC_DEVWID_16 BIT(4) 68 #define FSMC_ECCEN BIT(6) 69 #define FSMC_ECCPLEN_256 BIT(7) 70 #define FSMC_TCLR_SHIFT (9) 71 #define FSMC_TCLR_MASK (0xF) 72 #define FSMC_TAR_SHIFT (13) 73 #define FSMC_TAR_MASK (0xF) 74 #define STS 0x04 75 /* sts register definitions */ 76 #define FSMC_CODE_RDY BIT(15) 77 #define COMM 0x08 78 /* comm register definitions */ 79 #define FSMC_TSET_SHIFT 0 80 #define FSMC_TSET_MASK 0xFF 81 #define FSMC_TWAIT_SHIFT 8 82 #define FSMC_TWAIT_MASK 0xFF 83 #define FSMC_THOLD_SHIFT 16 84 #define FSMC_THOLD_MASK 0xFF 85 #define FSMC_THIZ_SHIFT 24 86 #define FSMC_THIZ_MASK 0xFF 87 #define ATTRIB 0x0C 88 #define IOATA 0x10 89 #define ECC1 0x14 90 #define ECC2 0x18 91 #define ECC3 0x1C 92 #define FSMC_NAND_BANK_SZ 0x20 93 94 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) 95 96 struct fsmc_nand_timings { 97 u8 tclr; 98 u8 tar; 99 u8 thiz; 100 u8 thold; 101 u8 twait; 102 u8 tset; 103 }; 104 105 enum access_mode { 106 USE_DMA_ACCESS = 1, 107 USE_WORD_ACCESS, 108 }; 109 110 /** 111 * struct fsmc_nand_data - structure for FSMC NAND device state 112 * 113 * @base: Inherit from the nand_controller struct 114 * @pid: Part ID on the AMBA PrimeCell format 115 * @nand: Chip related info for a NAND flash. 116 * 117 * @bank: Bank number for probed device. 118 * @dev: Parent device 119 * @mode: Access mode 120 * @clk: Clock structure for FSMC. 121 * 122 * @read_dma_chan: DMA channel for read access 123 * @write_dma_chan: DMA channel for write access to NAND 124 * @dma_access_complete: Completion structure 125 * 126 * @dev_timings: NAND timings 127 * 128 * @data_pa: NAND Physical port for Data. 129 * @data_va: NAND port for Data. 130 * @cmd_va: NAND port for Command. 131 * @addr_va: NAND port for Address. 132 * @regs_va: Registers base address for a given bank. 133 */ 134 struct fsmc_nand_data { 135 struct nand_controller base; 136 u32 pid; 137 struct nand_chip nand; 138 139 unsigned int bank; 140 struct device *dev; 141 enum access_mode mode; 142 struct clk *clk; 143 144 /* DMA related objects */ 145 struct dma_chan *read_dma_chan; 146 struct dma_chan *write_dma_chan; 147 struct completion dma_access_complete; 148 149 struct fsmc_nand_timings *dev_timings; 150 151 dma_addr_t data_pa; 152 void __iomem *data_va; 153 void __iomem *cmd_va; 154 void __iomem *addr_va; 155 void __iomem *regs_va; 156 }; 157 158 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section, 159 struct mtd_oob_region *oobregion) 160 { 161 struct nand_chip *chip = mtd_to_nand(mtd); 162 163 if (section >= chip->ecc.steps) 164 return -ERANGE; 165 166 oobregion->offset = (section * 16) + 2; 167 oobregion->length = 3; 168 169 return 0; 170 } 171 172 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section, 173 struct mtd_oob_region *oobregion) 174 { 175 struct nand_chip *chip = mtd_to_nand(mtd); 176 177 if (section >= chip->ecc.steps) 178 return -ERANGE; 179 180 oobregion->offset = (section * 16) + 8; 181 182 if (section < chip->ecc.steps - 1) 183 oobregion->length = 8; 184 else 185 oobregion->length = mtd->oobsize - oobregion->offset; 186 187 return 0; 188 } 189 190 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = { 191 .ecc = fsmc_ecc1_ooblayout_ecc, 192 .free = fsmc_ecc1_ooblayout_free, 193 }; 194 195 /* 196 * ECC placement definitions in oobfree type format. 197 * There are 13 bytes of ecc for every 512 byte block and it has to be read 198 * consecutively and immediately after the 512 byte data block for hardware to 199 * generate the error bit offsets in 512 byte data. 200 */ 201 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section, 202 struct mtd_oob_region *oobregion) 203 { 204 struct nand_chip *chip = mtd_to_nand(mtd); 205 206 if (section >= chip->ecc.steps) 207 return -ERANGE; 208 209 oobregion->length = chip->ecc.bytes; 210 211 if (!section && mtd->writesize <= 512) 212 oobregion->offset = 0; 213 else 214 oobregion->offset = (section * 16) + 2; 215 216 return 0; 217 } 218 219 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section, 220 struct mtd_oob_region *oobregion) 221 { 222 struct nand_chip *chip = mtd_to_nand(mtd); 223 224 if (section >= chip->ecc.steps) 225 return -ERANGE; 226 227 oobregion->offset = (section * 16) + 15; 228 229 if (section < chip->ecc.steps - 1) 230 oobregion->length = 3; 231 else 232 oobregion->length = mtd->oobsize - oobregion->offset; 233 234 return 0; 235 } 236 237 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = { 238 .ecc = fsmc_ecc4_ooblayout_ecc, 239 .free = fsmc_ecc4_ooblayout_free, 240 }; 241 242 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip) 243 { 244 return container_of(chip, struct fsmc_nand_data, nand); 245 } 246 247 /* 248 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine 249 * 250 * This routine initializes timing parameters related to NAND memory access in 251 * FSMC registers 252 */ 253 static void fsmc_nand_setup(struct fsmc_nand_data *host, 254 struct fsmc_nand_timings *tims) 255 { 256 u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; 257 u32 tclr, tar, thiz, thold, twait, tset; 258 259 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT; 260 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT; 261 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT; 262 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT; 263 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; 264 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; 265 266 if (host->nand.options & NAND_BUSWIDTH_16) 267 value |= FSMC_DEVWID_16; 268 269 writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC); 270 writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM); 271 writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB); 272 } 273 274 static int fsmc_calc_timings(struct fsmc_nand_data *host, 275 const struct nand_sdr_timings *sdrt, 276 struct fsmc_nand_timings *tims) 277 { 278 unsigned long hclk = clk_get_rate(host->clk); 279 unsigned long hclkn = NSEC_PER_SEC / hclk; 280 u32 thiz, thold, twait, tset; 281 282 if (sdrt->tRC_min < 30000) 283 return -EOPNOTSUPP; 284 285 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1; 286 if (tims->tar > FSMC_TAR_MASK) 287 tims->tar = FSMC_TAR_MASK; 288 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1; 289 if (tims->tclr > FSMC_TCLR_MASK) 290 tims->tclr = FSMC_TCLR_MASK; 291 292 thiz = sdrt->tCS_min - sdrt->tWP_min; 293 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn); 294 295 thold = sdrt->tDH_min; 296 if (thold < sdrt->tCH_min) 297 thold = sdrt->tCH_min; 298 if (thold < sdrt->tCLH_min) 299 thold = sdrt->tCLH_min; 300 if (thold < sdrt->tWH_min) 301 thold = sdrt->tWH_min; 302 if (thold < sdrt->tALH_min) 303 thold = sdrt->tALH_min; 304 if (thold < sdrt->tREH_min) 305 thold = sdrt->tREH_min; 306 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn); 307 if (tims->thold == 0) 308 tims->thold = 1; 309 else if (tims->thold > FSMC_THOLD_MASK) 310 tims->thold = FSMC_THOLD_MASK; 311 312 twait = max(sdrt->tRP_min, sdrt->tWP_min); 313 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1; 314 if (tims->twait == 0) 315 tims->twait = 1; 316 else if (tims->twait > FSMC_TWAIT_MASK) 317 tims->twait = FSMC_TWAIT_MASK; 318 319 tset = max(sdrt->tCS_min - sdrt->tWP_min, 320 sdrt->tCEA_max - sdrt->tREA_max); 321 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1; 322 if (tims->tset == 0) 323 tims->tset = 1; 324 else if (tims->tset > FSMC_TSET_MASK) 325 tims->tset = FSMC_TSET_MASK; 326 327 return 0; 328 } 329 330 static int fsmc_setup_interface(struct nand_chip *nand, int csline, 331 const struct nand_interface_config *conf) 332 { 333 struct fsmc_nand_data *host = nand_to_fsmc(nand); 334 struct fsmc_nand_timings tims; 335 const struct nand_sdr_timings *sdrt; 336 int ret; 337 338 sdrt = nand_get_sdr_timings(conf); 339 if (IS_ERR(sdrt)) 340 return PTR_ERR(sdrt); 341 342 ret = fsmc_calc_timings(host, sdrt, &tims); 343 if (ret) 344 return ret; 345 346 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 347 return 0; 348 349 fsmc_nand_setup(host, &tims); 350 351 return 0; 352 } 353 354 /* 355 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers 356 */ 357 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode) 358 { 359 struct fsmc_nand_data *host = nand_to_fsmc(chip); 360 361 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256, 362 host->regs_va + FSMC_PC); 363 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN, 364 host->regs_va + FSMC_PC); 365 writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN, 366 host->regs_va + FSMC_PC); 367 } 368 369 /* 370 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by 371 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to 372 * max of 8-bits) 373 */ 374 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data, 375 u8 *ecc) 376 { 377 struct fsmc_nand_data *host = nand_to_fsmc(chip); 378 u32 ecc_tmp; 379 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; 380 381 do { 382 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY) 383 break; 384 385 cond_resched(); 386 } while (!time_after_eq(jiffies, deadline)); 387 388 if (time_after_eq(jiffies, deadline)) { 389 dev_err(host->dev, "calculate ecc timed out\n"); 390 return -ETIMEDOUT; 391 } 392 393 ecc_tmp = readl_relaxed(host->regs_va + ECC1); 394 ecc[0] = ecc_tmp; 395 ecc[1] = ecc_tmp >> 8; 396 ecc[2] = ecc_tmp >> 16; 397 ecc[3] = ecc_tmp >> 24; 398 399 ecc_tmp = readl_relaxed(host->regs_va + ECC2); 400 ecc[4] = ecc_tmp; 401 ecc[5] = ecc_tmp >> 8; 402 ecc[6] = ecc_tmp >> 16; 403 ecc[7] = ecc_tmp >> 24; 404 405 ecc_tmp = readl_relaxed(host->regs_va + ECC3); 406 ecc[8] = ecc_tmp; 407 ecc[9] = ecc_tmp >> 8; 408 ecc[10] = ecc_tmp >> 16; 409 ecc[11] = ecc_tmp >> 24; 410 411 ecc_tmp = readl_relaxed(host->regs_va + STS); 412 ecc[12] = ecc_tmp >> 16; 413 414 return 0; 415 } 416 417 /* 418 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by 419 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to 420 * max of 1-bit) 421 */ 422 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data, 423 u8 *ecc) 424 { 425 struct fsmc_nand_data *host = nand_to_fsmc(chip); 426 u32 ecc_tmp; 427 428 ecc_tmp = readl_relaxed(host->regs_va + ECC1); 429 ecc[0] = ecc_tmp; 430 ecc[1] = ecc_tmp >> 8; 431 ecc[2] = ecc_tmp >> 16; 432 433 return 0; 434 } 435 436 /* Count the number of 0's in buff upto a max of max_bits */ 437 static int count_written_bits(u8 *buff, int size, int max_bits) 438 { 439 int k, written_bits = 0; 440 441 for (k = 0; k < size; k++) { 442 written_bits += hweight8(~buff[k]); 443 if (written_bits > max_bits) 444 break; 445 } 446 447 return written_bits; 448 } 449 450 static void dma_complete(void *param) 451 { 452 struct fsmc_nand_data *host = param; 453 454 complete(&host->dma_access_complete); 455 } 456 457 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len, 458 enum dma_data_direction direction) 459 { 460 struct dma_chan *chan; 461 struct dma_device *dma_dev; 462 struct dma_async_tx_descriptor *tx; 463 dma_addr_t dma_dst, dma_src, dma_addr; 464 dma_cookie_t cookie; 465 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 466 int ret; 467 unsigned long time_left; 468 469 if (direction == DMA_TO_DEVICE) 470 chan = host->write_dma_chan; 471 else if (direction == DMA_FROM_DEVICE) 472 chan = host->read_dma_chan; 473 else 474 return -EINVAL; 475 476 dma_dev = chan->device; 477 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction); 478 479 if (direction == DMA_TO_DEVICE) { 480 dma_src = dma_addr; 481 dma_dst = host->data_pa; 482 } else { 483 dma_src = host->data_pa; 484 dma_dst = dma_addr; 485 } 486 487 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, 488 len, flags); 489 if (!tx) { 490 dev_err(host->dev, "device_prep_dma_memcpy error\n"); 491 ret = -EIO; 492 goto unmap_dma; 493 } 494 495 tx->callback = dma_complete; 496 tx->callback_param = host; 497 cookie = tx->tx_submit(tx); 498 499 ret = dma_submit_error(cookie); 500 if (ret) { 501 dev_err(host->dev, "dma_submit_error %d\n", cookie); 502 goto unmap_dma; 503 } 504 505 dma_async_issue_pending(chan); 506 507 time_left = 508 wait_for_completion_timeout(&host->dma_access_complete, 509 msecs_to_jiffies(3000)); 510 if (time_left == 0) { 511 dmaengine_terminate_all(chan); 512 dev_err(host->dev, "wait_for_completion_timeout\n"); 513 ret = -ETIMEDOUT; 514 goto unmap_dma; 515 } 516 517 ret = 0; 518 519 unmap_dma: 520 dma_unmap_single(dma_dev->dev, dma_addr, len, direction); 521 522 return ret; 523 } 524 525 /* 526 * fsmc_write_buf - write buffer to chip 527 * @host: FSMC NAND controller 528 * @buf: data buffer 529 * @len: number of bytes to write 530 */ 531 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf, 532 int len) 533 { 534 int i; 535 536 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && 537 IS_ALIGNED(len, sizeof(u32))) { 538 u32 *p = (u32 *)buf; 539 540 len = len >> 2; 541 for (i = 0; i < len; i++) 542 writel_relaxed(p[i], host->data_va); 543 } else { 544 for (i = 0; i < len; i++) 545 writeb_relaxed(buf[i], host->data_va); 546 } 547 } 548 549 /* 550 * fsmc_read_buf - read chip data into buffer 551 * @host: FSMC NAND controller 552 * @buf: buffer to store date 553 * @len: number of bytes to read 554 */ 555 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len) 556 { 557 int i; 558 559 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && 560 IS_ALIGNED(len, sizeof(u32))) { 561 u32 *p = (u32 *)buf; 562 563 len = len >> 2; 564 for (i = 0; i < len; i++) 565 p[i] = readl_relaxed(host->data_va); 566 } else { 567 for (i = 0; i < len; i++) 568 buf[i] = readb_relaxed(host->data_va); 569 } 570 } 571 572 /* 573 * fsmc_read_buf_dma - read chip data into buffer 574 * @host: FSMC NAND controller 575 * @buf: buffer to store date 576 * @len: number of bytes to read 577 */ 578 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf, 579 int len) 580 { 581 dma_xfer(host, buf, len, DMA_FROM_DEVICE); 582 } 583 584 /* 585 * fsmc_write_buf_dma - write buffer to chip 586 * @host: FSMC NAND controller 587 * @buf: data buffer 588 * @len: number of bytes to write 589 */ 590 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf, 591 int len) 592 { 593 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE); 594 } 595 596 /* 597 * fsmc_exec_op - hook called by the core to execute NAND operations 598 * 599 * This controller is simple enough and thus does not need to use the parser 600 * provided by the core, instead, handle every situation here. 601 */ 602 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op, 603 bool check_only) 604 { 605 struct fsmc_nand_data *host = nand_to_fsmc(chip); 606 const struct nand_op_instr *instr = NULL; 607 int ret = 0; 608 unsigned int op_id; 609 int i; 610 611 if (check_only) 612 return 0; 613 614 pr_debug("Executing operation [%d instructions]:\n", op->ninstrs); 615 616 for (op_id = 0; op_id < op->ninstrs; op_id++) { 617 instr = &op->instrs[op_id]; 618 619 nand_op_trace(" ", instr); 620 621 switch (instr->type) { 622 case NAND_OP_CMD_INSTR: 623 writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va); 624 break; 625 626 case NAND_OP_ADDR_INSTR: 627 for (i = 0; i < instr->ctx.addr.naddrs; i++) 628 writeb_relaxed(instr->ctx.addr.addrs[i], 629 host->addr_va); 630 break; 631 632 case NAND_OP_DATA_IN_INSTR: 633 if (host->mode == USE_DMA_ACCESS) 634 fsmc_read_buf_dma(host, instr->ctx.data.buf.in, 635 instr->ctx.data.len); 636 else 637 fsmc_read_buf(host, instr->ctx.data.buf.in, 638 instr->ctx.data.len); 639 break; 640 641 case NAND_OP_DATA_OUT_INSTR: 642 if (host->mode == USE_DMA_ACCESS) 643 fsmc_write_buf_dma(host, 644 instr->ctx.data.buf.out, 645 instr->ctx.data.len); 646 else 647 fsmc_write_buf(host, instr->ctx.data.buf.out, 648 instr->ctx.data.len); 649 break; 650 651 case NAND_OP_WAITRDY_INSTR: 652 ret = nand_soft_waitrdy(chip, 653 instr->ctx.waitrdy.timeout_ms); 654 break; 655 } 656 } 657 658 return ret; 659 } 660 661 /* 662 * fsmc_read_page_hwecc 663 * @chip: nand chip info structure 664 * @buf: buffer to store read data 665 * @oob_required: caller expects OOB data read to chip->oob_poi 666 * @page: page number to read 667 * 668 * This routine is needed for fsmc version 8 as reading from NAND chip has to be 669 * performed in a strict sequence as follows: 670 * data(512 byte) -> ecc(13 byte) 671 * After this read, fsmc hardware generates and reports error data bits(up to a 672 * max of 8 bits) 673 */ 674 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf, 675 int oob_required, int page) 676 { 677 struct mtd_info *mtd = nand_to_mtd(chip); 678 int i, j, s, stat, eccsize = chip->ecc.size; 679 int eccbytes = chip->ecc.bytes; 680 int eccsteps = chip->ecc.steps; 681 u8 *p = buf; 682 u8 *ecc_calc = chip->ecc.calc_buf; 683 u8 *ecc_code = chip->ecc.code_buf; 684 int off, len, ret, group = 0; 685 /* 686 * ecc_oob is intentionally taken as u16. In 16bit devices, we 687 * end up reading 14 bytes (7 words) from oob. The local array is 688 * to maintain word alignment 689 */ 690 u16 ecc_oob[7]; 691 u8 *oob = (u8 *)&ecc_oob[0]; 692 unsigned int max_bitflips = 0; 693 694 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { 695 nand_read_page_op(chip, page, s * eccsize, NULL, 0); 696 chip->ecc.hwctl(chip, NAND_ECC_READ); 697 ret = nand_read_data_op(chip, p, eccsize, false, false); 698 if (ret) 699 return ret; 700 701 for (j = 0; j < eccbytes;) { 702 struct mtd_oob_region oobregion; 703 704 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion); 705 if (ret) 706 return ret; 707 708 off = oobregion.offset; 709 len = oobregion.length; 710 711 /* 712 * length is intentionally kept a higher multiple of 2 713 * to read at least 13 bytes even in case of 16 bit NAND 714 * devices 715 */ 716 if (chip->options & NAND_BUSWIDTH_16) 717 len = roundup(len, 2); 718 719 nand_read_oob_op(chip, page, off, oob + j, len); 720 j += len; 721 } 722 723 memcpy(&ecc_code[i], oob, chip->ecc.bytes); 724 chip->ecc.calculate(chip, p, &ecc_calc[i]); 725 726 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); 727 if (stat < 0) { 728 mtd->ecc_stats.failed++; 729 } else { 730 mtd->ecc_stats.corrected += stat; 731 max_bitflips = max_t(unsigned int, max_bitflips, stat); 732 } 733 } 734 735 return max_bitflips; 736 } 737 738 /* 739 * fsmc_bch8_correct_data 740 * @mtd: mtd info structure 741 * @dat: buffer of read data 742 * @read_ecc: ecc read from device spare area 743 * @calc_ecc: ecc calculated from read data 744 * 745 * calc_ecc is a 104 bit information containing maximum of 8 error 746 * offset information of 13 bits each in 512 bytes of read data. 747 */ 748 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat, 749 u8 *read_ecc, u8 *calc_ecc) 750 { 751 struct fsmc_nand_data *host = nand_to_fsmc(chip); 752 u32 err_idx[8]; 753 u32 num_err, i; 754 u32 ecc1, ecc2, ecc3, ecc4; 755 756 num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF; 757 758 /* no bit flipping */ 759 if (likely(num_err == 0)) 760 return 0; 761 762 /* too many errors */ 763 if (unlikely(num_err > 8)) { 764 /* 765 * This is a temporary erase check. A newly erased page read 766 * would result in an ecc error because the oob data is also 767 * erased to FF and the calculated ecc for an FF data is not 768 * FF..FF. 769 * This is a workaround to skip performing correction in case 770 * data is FF..FF 771 * 772 * Logic: 773 * For every page, each bit written as 0 is counted until these 774 * number of bits are greater than 8 (the maximum correction 775 * capability of FSMC for each 512 + 13 bytes) 776 */ 777 778 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); 779 int bits_data = count_written_bits(dat, chip->ecc.size, 8); 780 781 if ((bits_ecc + bits_data) <= 8) { 782 if (bits_data) 783 memset(dat, 0xff, chip->ecc.size); 784 return bits_data; 785 } 786 787 return -EBADMSG; 788 } 789 790 /* 791 * ------------------- calc_ecc[] bit wise -----------|--13 bits--| 792 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| 793 * 794 * calc_ecc is a 104 bit information containing maximum of 8 error 795 * offset information of 13 bits each. calc_ecc is copied into a 796 * u64 array and error offset indexes are populated in err_idx 797 * array 798 */ 799 ecc1 = readl_relaxed(host->regs_va + ECC1); 800 ecc2 = readl_relaxed(host->regs_va + ECC2); 801 ecc3 = readl_relaxed(host->regs_va + ECC3); 802 ecc4 = readl_relaxed(host->regs_va + STS); 803 804 err_idx[0] = (ecc1 >> 0) & 0x1FFF; 805 err_idx[1] = (ecc1 >> 13) & 0x1FFF; 806 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); 807 err_idx[3] = (ecc2 >> 7) & 0x1FFF; 808 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); 809 err_idx[5] = (ecc3 >> 1) & 0x1FFF; 810 err_idx[6] = (ecc3 >> 14) & 0x1FFF; 811 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); 812 813 i = 0; 814 while (num_err--) { 815 err_idx[i] ^= 3; 816 817 if (err_idx[i] < chip->ecc.size * 8) { 818 int err = err_idx[i]; 819 820 dat[err >> 3] ^= BIT(err & 7); 821 i++; 822 } 823 } 824 return i; 825 } 826 827 static bool filter(struct dma_chan *chan, void *slave) 828 { 829 chan->private = slave; 830 return true; 831 } 832 833 static int fsmc_nand_probe_config_dt(struct platform_device *pdev, 834 struct fsmc_nand_data *host, 835 struct nand_chip *nand) 836 { 837 struct device_node *np = pdev->dev.of_node; 838 u32 val; 839 int ret; 840 841 nand->options = 0; 842 843 if (!of_property_read_u32(np, "bank-width", &val)) { 844 if (val == 2) { 845 nand->options |= NAND_BUSWIDTH_16; 846 } else if (val != 1) { 847 dev_err(&pdev->dev, "invalid bank-width %u\n", val); 848 return -EINVAL; 849 } 850 } 851 852 if (of_get_property(np, "nand-skip-bbtscan", NULL)) 853 nand->options |= NAND_SKIP_BBTSCAN; 854 855 host->dev_timings = devm_kzalloc(&pdev->dev, 856 sizeof(*host->dev_timings), 857 GFP_KERNEL); 858 if (!host->dev_timings) 859 return -ENOMEM; 860 861 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings, 862 sizeof(*host->dev_timings)); 863 if (ret) 864 host->dev_timings = NULL; 865 866 /* Set default NAND bank to 0 */ 867 host->bank = 0; 868 if (!of_property_read_u32(np, "bank", &val)) { 869 if (val > 3) { 870 dev_err(&pdev->dev, "invalid bank %u\n", val); 871 return -EINVAL; 872 } 873 host->bank = val; 874 } 875 return 0; 876 } 877 878 static int fsmc_nand_attach_chip(struct nand_chip *nand) 879 { 880 struct mtd_info *mtd = nand_to_mtd(nand); 881 struct fsmc_nand_data *host = nand_to_fsmc(nand); 882 883 if (AMBA_REV_BITS(host->pid) >= 8) { 884 switch (mtd->oobsize) { 885 case 16: 886 case 64: 887 case 128: 888 case 224: 889 case 256: 890 break; 891 default: 892 dev_warn(host->dev, 893 "No oob scheme defined for oobsize %d\n", 894 mtd->oobsize); 895 return -EINVAL; 896 } 897 898 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops); 899 900 return 0; 901 } 902 903 switch (nand->ecc.engine_type) { 904 case NAND_ECC_ENGINE_TYPE_ON_HOST: 905 dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); 906 nand->ecc.calculate = fsmc_read_hwecc_ecc1; 907 nand->ecc.correct = nand_correct_data; 908 nand->ecc.bytes = 3; 909 nand->ecc.strength = 1; 910 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; 911 break; 912 913 case NAND_ECC_ENGINE_TYPE_SOFT: 914 if (nand->ecc.algo == NAND_ECC_ALGO_BCH) { 915 dev_info(host->dev, 916 "Using 4-bit SW BCH ECC scheme\n"); 917 break; 918 } 919 920 case NAND_ECC_ENGINE_TYPE_ON_DIE: 921 break; 922 923 default: 924 dev_err(host->dev, "Unsupported ECC mode!\n"); 925 return -ENOTSUPP; 926 } 927 928 /* 929 * Don't set layout for BCH4 SW ECC. This will be 930 * generated later in nand_bch_init() later. 931 */ 932 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 933 switch (mtd->oobsize) { 934 case 16: 935 case 64: 936 case 128: 937 mtd_set_ooblayout(mtd, 938 &fsmc_ecc1_ooblayout_ops); 939 break; 940 default: 941 dev_warn(host->dev, 942 "No oob scheme defined for oobsize %d\n", 943 mtd->oobsize); 944 return -EINVAL; 945 } 946 } 947 948 return 0; 949 } 950 951 static const struct nand_controller_ops fsmc_nand_controller_ops = { 952 .attach_chip = fsmc_nand_attach_chip, 953 .exec_op = fsmc_exec_op, 954 .setup_interface = fsmc_setup_interface, 955 }; 956 957 /** 958 * fsmc_nand_disable() - Disables the NAND bank 959 * @host: The instance to disable 960 */ 961 static void fsmc_nand_disable(struct fsmc_nand_data *host) 962 { 963 u32 val; 964 965 val = readl(host->regs_va + FSMC_PC); 966 val &= ~FSMC_ENABLE; 967 writel(val, host->regs_va + FSMC_PC); 968 } 969 970 /* 971 * fsmc_nand_probe - Probe function 972 * @pdev: platform device structure 973 */ 974 static int __init fsmc_nand_probe(struct platform_device *pdev) 975 { 976 struct fsmc_nand_data *host; 977 struct mtd_info *mtd; 978 struct nand_chip *nand; 979 struct resource *res; 980 void __iomem *base; 981 dma_cap_mask_t mask; 982 int ret = 0; 983 u32 pid; 984 int i; 985 986 /* Allocate memory for the device structure (and zero it) */ 987 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 988 if (!host) 989 return -ENOMEM; 990 991 nand = &host->nand; 992 993 ret = fsmc_nand_probe_config_dt(pdev, host, nand); 994 if (ret) 995 return ret; 996 997 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); 998 host->data_va = devm_ioremap_resource(&pdev->dev, res); 999 if (IS_ERR(host->data_va)) 1000 return PTR_ERR(host->data_va); 1001 1002 host->data_pa = (dma_addr_t)res->start; 1003 1004 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); 1005 host->addr_va = devm_ioremap_resource(&pdev->dev, res); 1006 if (IS_ERR(host->addr_va)) 1007 return PTR_ERR(host->addr_va); 1008 1009 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); 1010 host->cmd_va = devm_ioremap_resource(&pdev->dev, res); 1011 if (IS_ERR(host->cmd_va)) 1012 return PTR_ERR(host->cmd_va); 1013 1014 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); 1015 base = devm_ioremap_resource(&pdev->dev, res); 1016 if (IS_ERR(base)) 1017 return PTR_ERR(base); 1018 1019 host->regs_va = base + FSMC_NOR_REG_SIZE + 1020 (host->bank * FSMC_NAND_BANK_SZ); 1021 1022 host->clk = devm_clk_get(&pdev->dev, NULL); 1023 if (IS_ERR(host->clk)) { 1024 dev_err(&pdev->dev, "failed to fetch block clock\n"); 1025 return PTR_ERR(host->clk); 1026 } 1027 1028 ret = clk_prepare_enable(host->clk); 1029 if (ret) 1030 return ret; 1031 1032 /* 1033 * This device ID is actually a common AMBA ID as used on the 1034 * AMBA PrimeCell bus. However it is not a PrimeCell. 1035 */ 1036 for (pid = 0, i = 0; i < 4; i++) 1037 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & 1038 255) << (i * 8); 1039 1040 host->pid = pid; 1041 1042 dev_info(&pdev->dev, 1043 "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n", 1044 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid), 1045 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid)); 1046 1047 host->dev = &pdev->dev; 1048 1049 if (host->mode == USE_DMA_ACCESS) 1050 init_completion(&host->dma_access_complete); 1051 1052 /* Link all private pointers */ 1053 mtd = nand_to_mtd(&host->nand); 1054 nand_set_flash_node(nand, pdev->dev.of_node); 1055 1056 mtd->dev.parent = &pdev->dev; 1057 1058 /* 1059 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident() 1060 * can overwrite this value if the DT provides a different value. 1061 */ 1062 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1063 nand->ecc.hwctl = fsmc_enable_hwecc; 1064 nand->ecc.size = 512; 1065 nand->badblockbits = 7; 1066 1067 if (host->mode == USE_DMA_ACCESS) { 1068 dma_cap_zero(mask); 1069 dma_cap_set(DMA_MEMCPY, mask); 1070 host->read_dma_chan = dma_request_channel(mask, filter, NULL); 1071 if (!host->read_dma_chan) { 1072 dev_err(&pdev->dev, "Unable to get read dma channel\n"); 1073 goto disable_clk; 1074 } 1075 host->write_dma_chan = dma_request_channel(mask, filter, NULL); 1076 if (!host->write_dma_chan) { 1077 dev_err(&pdev->dev, "Unable to get write dma channel\n"); 1078 goto release_dma_read_chan; 1079 } 1080 } 1081 1082 if (host->dev_timings) { 1083 fsmc_nand_setup(host, host->dev_timings); 1084 nand->options |= NAND_KEEP_TIMINGS; 1085 } 1086 1087 if (AMBA_REV_BITS(host->pid) >= 8) { 1088 nand->ecc.read_page = fsmc_read_page_hwecc; 1089 nand->ecc.calculate = fsmc_read_hwecc_ecc4; 1090 nand->ecc.correct = fsmc_bch8_correct_data; 1091 nand->ecc.bytes = 13; 1092 nand->ecc.strength = 8; 1093 } 1094 1095 nand_controller_init(&host->base); 1096 host->base.ops = &fsmc_nand_controller_ops; 1097 nand->controller = &host->base; 1098 1099 /* 1100 * Scan to find existence of the device 1101 */ 1102 ret = nand_scan(nand, 1); 1103 if (ret) 1104 goto release_dma_write_chan; 1105 1106 mtd->name = "nand"; 1107 ret = mtd_device_register(mtd, NULL, 0); 1108 if (ret) 1109 goto cleanup_nand; 1110 1111 platform_set_drvdata(pdev, host); 1112 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); 1113 1114 return 0; 1115 1116 cleanup_nand: 1117 nand_cleanup(nand); 1118 release_dma_write_chan: 1119 if (host->mode == USE_DMA_ACCESS) 1120 dma_release_channel(host->write_dma_chan); 1121 release_dma_read_chan: 1122 if (host->mode == USE_DMA_ACCESS) 1123 dma_release_channel(host->read_dma_chan); 1124 disable_clk: 1125 fsmc_nand_disable(host); 1126 clk_disable_unprepare(host->clk); 1127 1128 return ret; 1129 } 1130 1131 /* 1132 * Clean up routine 1133 */ 1134 static int fsmc_nand_remove(struct platform_device *pdev) 1135 { 1136 struct fsmc_nand_data *host = platform_get_drvdata(pdev); 1137 1138 if (host) { 1139 struct nand_chip *chip = &host->nand; 1140 int ret; 1141 1142 ret = mtd_device_unregister(nand_to_mtd(chip)); 1143 WARN_ON(ret); 1144 nand_cleanup(chip); 1145 fsmc_nand_disable(host); 1146 1147 if (host->mode == USE_DMA_ACCESS) { 1148 dma_release_channel(host->write_dma_chan); 1149 dma_release_channel(host->read_dma_chan); 1150 } 1151 clk_disable_unprepare(host->clk); 1152 } 1153 1154 return 0; 1155 } 1156 1157 #ifdef CONFIG_PM_SLEEP 1158 static int fsmc_nand_suspend(struct device *dev) 1159 { 1160 struct fsmc_nand_data *host = dev_get_drvdata(dev); 1161 1162 if (host) 1163 clk_disable_unprepare(host->clk); 1164 1165 return 0; 1166 } 1167 1168 static int fsmc_nand_resume(struct device *dev) 1169 { 1170 struct fsmc_nand_data *host = dev_get_drvdata(dev); 1171 1172 if (host) { 1173 clk_prepare_enable(host->clk); 1174 if (host->dev_timings) 1175 fsmc_nand_setup(host, host->dev_timings); 1176 nand_reset(&host->nand, 0); 1177 } 1178 1179 return 0; 1180 } 1181 #endif 1182 1183 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume); 1184 1185 static const struct of_device_id fsmc_nand_id_table[] = { 1186 { .compatible = "st,spear600-fsmc-nand" }, 1187 { .compatible = "stericsson,fsmc-nand" }, 1188 {} 1189 }; 1190 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table); 1191 1192 static struct platform_driver fsmc_nand_driver = { 1193 .remove = fsmc_nand_remove, 1194 .driver = { 1195 .name = "fsmc-nand", 1196 .of_match_table = fsmc_nand_id_table, 1197 .pm = &fsmc_nand_pm_ops, 1198 }, 1199 }; 1200 1201 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe); 1202 1203 MODULE_LICENSE("GPL v2"); 1204 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi"); 1205 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms"); 1206