1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ST Microelectronics
4 * Flexible Static Memory Controller (FSMC)
5 * Driver for NAND portions
6 *
7 * Copyright © 2010 ST Microelectronics
8 * Vipin Kumar <vipin.kumar@st.com>
9 * Ashish Priyadarshi
10 *
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
12 * Copyright © 2007 STMicroelectronics Pvt. Ltd.
13 * Copyright © 2009 Alessandro Rubini
14 */
15
16 #include <linux/clk.h>
17 #include <linux/completion.h>
18 #include <linux/delay.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-direction.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/err.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/resource.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand-ecc-sw-hamming.h>
30 #include <linux/mtd/rawnand.h>
31 #include <linux/platform_device.h>
32 #include <linux/of.h>
33 #include <linux/mtd/partitions.h>
34 #include <linux/io.h>
35 #include <linux/slab.h>
36 #include <linux/amba/bus.h>
37 #include <mtd/mtd-abi.h>
38
39 /* fsmc controller registers for NOR flash */
40 #define CTRL 0x0
41 /* ctrl register definitions */
42 #define BANK_ENABLE BIT(0)
43 #define MUXED BIT(1)
44 #define NOR_DEV (2 << 2)
45 #define WIDTH_16 BIT(4)
46 #define RSTPWRDWN BIT(6)
47 #define WPROT BIT(7)
48 #define WRT_ENABLE BIT(12)
49 #define WAIT_ENB BIT(13)
50
51 #define CTRL_TIM 0x4
52 /* ctrl_tim register definitions */
53
54 #define FSMC_NOR_BANK_SZ 0x8
55 #define FSMC_NOR_REG_SIZE 0x40
56
57 #define FSMC_NOR_REG(base, bank, reg) ((base) + \
58 (FSMC_NOR_BANK_SZ * (bank)) + \
59 (reg))
60
61 /* fsmc controller registers for NAND flash */
62 #define FSMC_PC 0x00
63 /* pc register definitions */
64 #define FSMC_RESET BIT(0)
65 #define FSMC_WAITON BIT(1)
66 #define FSMC_ENABLE BIT(2)
67 #define FSMC_DEVTYPE_NAND BIT(3)
68 #define FSMC_DEVWID_16 BIT(4)
69 #define FSMC_ECCEN BIT(6)
70 #define FSMC_ECCPLEN_256 BIT(7)
71 #define FSMC_TCLR_SHIFT (9)
72 #define FSMC_TCLR_MASK (0xF)
73 #define FSMC_TAR_SHIFT (13)
74 #define FSMC_TAR_MASK (0xF)
75 #define STS 0x04
76 /* sts register definitions */
77 #define FSMC_CODE_RDY BIT(15)
78 #define COMM 0x08
79 /* comm register definitions */
80 #define FSMC_TSET_SHIFT 0
81 #define FSMC_TSET_MASK 0xFF
82 #define FSMC_TWAIT_SHIFT 8
83 #define FSMC_TWAIT_MASK 0xFF
84 #define FSMC_THOLD_SHIFT 16
85 #define FSMC_THOLD_MASK 0xFF
86 #define FSMC_THIZ_SHIFT 24
87 #define FSMC_THIZ_MASK 0xFF
88 #define ATTRIB 0x0C
89 #define IOATA 0x10
90 #define ECC1 0x14
91 #define ECC2 0x18
92 #define ECC3 0x1C
93 #define FSMC_NAND_BANK_SZ 0x20
94
95 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
96
97 /*
98 * According to SPEAr300 Reference Manual (RM0082)
99 * TOUDEL = 7ns (Output delay from the flip-flops to the board)
100 * TINDEL = 5ns (Input delay from the board to the flipflop)
101 */
102 #define TOUTDEL 7000
103 #define TINDEL 5000
104
105 struct fsmc_nand_timings {
106 u8 tclr;
107 u8 tar;
108 u8 thiz;
109 u8 thold;
110 u8 twait;
111 u8 tset;
112 };
113
114 enum access_mode {
115 USE_DMA_ACCESS = 1,
116 USE_WORD_ACCESS,
117 };
118
119 /**
120 * struct fsmc_nand_data - structure for FSMC NAND device state
121 *
122 * @base: Inherit from the nand_controller struct
123 * @pid: Part ID on the AMBA PrimeCell format
124 * @nand: Chip related info for a NAND flash.
125 *
126 * @bank: Bank number for probed device.
127 * @dev: Parent device
128 * @mode: Access mode
129 * @clk: Clock structure for FSMC.
130 *
131 * @read_dma_chan: DMA channel for read access
132 * @write_dma_chan: DMA channel for write access to NAND
133 * @dma_access_complete: Completion structure
134 *
135 * @dev_timings: NAND timings
136 *
137 * @data_pa: NAND Physical port for Data.
138 * @data_va: NAND port for Data.
139 * @cmd_va: NAND port for Command.
140 * @addr_va: NAND port for Address.
141 * @regs_va: Registers base address for a given bank.
142 */
143 struct fsmc_nand_data {
144 struct nand_controller base;
145 u32 pid;
146 struct nand_chip nand;
147
148 unsigned int bank;
149 struct device *dev;
150 enum access_mode mode;
151 struct clk *clk;
152
153 /* DMA related objects */
154 struct dma_chan *read_dma_chan;
155 struct dma_chan *write_dma_chan;
156 struct completion dma_access_complete;
157
158 struct fsmc_nand_timings *dev_timings;
159
160 dma_addr_t data_pa;
161 void __iomem *data_va;
162 void __iomem *cmd_va;
163 void __iomem *addr_va;
164 void __iomem *regs_va;
165 };
166
fsmc_ecc1_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)167 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
168 struct mtd_oob_region *oobregion)
169 {
170 struct nand_chip *chip = mtd_to_nand(mtd);
171
172 if (section >= chip->ecc.steps)
173 return -ERANGE;
174
175 oobregion->offset = (section * 16) + 2;
176 oobregion->length = 3;
177
178 return 0;
179 }
180
fsmc_ecc1_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)181 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
182 struct mtd_oob_region *oobregion)
183 {
184 struct nand_chip *chip = mtd_to_nand(mtd);
185
186 if (section >= chip->ecc.steps)
187 return -ERANGE;
188
189 oobregion->offset = (section * 16) + 8;
190
191 if (section < chip->ecc.steps - 1)
192 oobregion->length = 8;
193 else
194 oobregion->length = mtd->oobsize - oobregion->offset;
195
196 return 0;
197 }
198
199 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
200 .ecc = fsmc_ecc1_ooblayout_ecc,
201 .free = fsmc_ecc1_ooblayout_free,
202 };
203
204 /*
205 * ECC placement definitions in oobfree type format.
206 * There are 13 bytes of ecc for every 512 byte block and it has to be read
207 * consecutively and immediately after the 512 byte data block for hardware to
208 * generate the error bit offsets in 512 byte data.
209 */
fsmc_ecc4_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)210 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
211 struct mtd_oob_region *oobregion)
212 {
213 struct nand_chip *chip = mtd_to_nand(mtd);
214
215 if (section >= chip->ecc.steps)
216 return -ERANGE;
217
218 oobregion->length = chip->ecc.bytes;
219
220 if (!section && mtd->writesize <= 512)
221 oobregion->offset = 0;
222 else
223 oobregion->offset = (section * 16) + 2;
224
225 return 0;
226 }
227
fsmc_ecc4_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)228 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
229 struct mtd_oob_region *oobregion)
230 {
231 struct nand_chip *chip = mtd_to_nand(mtd);
232
233 if (section >= chip->ecc.steps)
234 return -ERANGE;
235
236 oobregion->offset = (section * 16) + 15;
237
238 if (section < chip->ecc.steps - 1)
239 oobregion->length = 3;
240 else
241 oobregion->length = mtd->oobsize - oobregion->offset;
242
243 return 0;
244 }
245
246 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
247 .ecc = fsmc_ecc4_ooblayout_ecc,
248 .free = fsmc_ecc4_ooblayout_free,
249 };
250
nand_to_fsmc(struct nand_chip * chip)251 static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
252 {
253 return container_of(chip, struct fsmc_nand_data, nand);
254 }
255
256 /*
257 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
258 *
259 * This routine initializes timing parameters related to NAND memory access in
260 * FSMC registers
261 */
fsmc_nand_setup(struct fsmc_nand_data * host,struct fsmc_nand_timings * tims)262 static void fsmc_nand_setup(struct fsmc_nand_data *host,
263 struct fsmc_nand_timings *tims)
264 {
265 u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
266 u32 tclr, tar, thiz, thold, twait, tset;
267
268 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
269 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
270 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
271 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
272 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
273 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
274
275 if (host->nand.options & NAND_BUSWIDTH_16)
276 value |= FSMC_DEVWID_16;
277
278 writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
279 writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
280 writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
281 }
282
fsmc_calc_timings(struct fsmc_nand_data * host,const struct nand_sdr_timings * sdrt,struct fsmc_nand_timings * tims)283 static int fsmc_calc_timings(struct fsmc_nand_data *host,
284 const struct nand_sdr_timings *sdrt,
285 struct fsmc_nand_timings *tims)
286 {
287 unsigned long hclk = clk_get_rate(host->clk);
288 unsigned long hclkn = NSEC_PER_SEC / hclk;
289 u32 thiz, thold, twait, tset, twait_min;
290
291 if (sdrt->tRC_min < 30000)
292 return -EOPNOTSUPP;
293
294 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
295 if (tims->tar > FSMC_TAR_MASK)
296 tims->tar = FSMC_TAR_MASK;
297 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
298 if (tims->tclr > FSMC_TCLR_MASK)
299 tims->tclr = FSMC_TCLR_MASK;
300
301 thiz = sdrt->tCS_min - sdrt->tWP_min;
302 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
303
304 thold = sdrt->tDH_min;
305 if (thold < sdrt->tCH_min)
306 thold = sdrt->tCH_min;
307 if (thold < sdrt->tCLH_min)
308 thold = sdrt->tCLH_min;
309 if (thold < sdrt->tWH_min)
310 thold = sdrt->tWH_min;
311 if (thold < sdrt->tALH_min)
312 thold = sdrt->tALH_min;
313 if (thold < sdrt->tREH_min)
314 thold = sdrt->tREH_min;
315 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
316 if (tims->thold == 0)
317 tims->thold = 1;
318 else if (tims->thold > FSMC_THOLD_MASK)
319 tims->thold = FSMC_THOLD_MASK;
320
321 tset = max(sdrt->tCS_min - sdrt->tWP_min,
322 sdrt->tCEA_max - sdrt->tREA_max);
323 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
324 if (tims->tset == 0)
325 tims->tset = 1;
326 else if (tims->tset > FSMC_TSET_MASK)
327 tims->tset = FSMC_TSET_MASK;
328
329 /*
330 * According to SPEAr300 Reference Manual (RM0082) which gives more
331 * information related to FSMSC timings than the SPEAr600 one (RM0305),
332 * twait >= tCEA - (tset * TCLK) + TOUTDEL + TINDEL
333 */
334 twait_min = sdrt->tCEA_max - ((tims->tset + 1) * hclkn * 1000)
335 + TOUTDEL + TINDEL;
336 twait = max3(sdrt->tRP_min, sdrt->tWP_min, twait_min);
337
338 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
339 if (tims->twait == 0)
340 tims->twait = 1;
341 else if (tims->twait > FSMC_TWAIT_MASK)
342 tims->twait = FSMC_TWAIT_MASK;
343
344 return 0;
345 }
346
fsmc_setup_interface(struct nand_chip * nand,int csline,const struct nand_interface_config * conf)347 static int fsmc_setup_interface(struct nand_chip *nand, int csline,
348 const struct nand_interface_config *conf)
349 {
350 struct fsmc_nand_data *host = nand_to_fsmc(nand);
351 struct fsmc_nand_timings tims;
352 const struct nand_sdr_timings *sdrt;
353 int ret;
354
355 sdrt = nand_get_sdr_timings(conf);
356 if (IS_ERR(sdrt))
357 return PTR_ERR(sdrt);
358
359 ret = fsmc_calc_timings(host, sdrt, &tims);
360 if (ret)
361 return ret;
362
363 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
364 return 0;
365
366 fsmc_nand_setup(host, &tims);
367
368 return 0;
369 }
370
371 /*
372 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
373 */
fsmc_enable_hwecc(struct nand_chip * chip,int mode)374 static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
375 {
376 struct fsmc_nand_data *host = nand_to_fsmc(chip);
377
378 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
379 host->regs_va + FSMC_PC);
380 writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN,
381 host->regs_va + FSMC_PC);
382 writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN,
383 host->regs_va + FSMC_PC);
384 }
385
386 /*
387 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
388 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
389 * max of 8-bits)
390 */
fsmc_read_hwecc_ecc4(struct nand_chip * chip,const u8 * data,u8 * ecc)391 static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
392 u8 *ecc)
393 {
394 struct fsmc_nand_data *host = nand_to_fsmc(chip);
395 u32 ecc_tmp;
396 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
397
398 do {
399 if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
400 break;
401
402 cond_resched();
403 } while (!time_after_eq(jiffies, deadline));
404
405 if (time_after_eq(jiffies, deadline)) {
406 dev_err(host->dev, "calculate ecc timed out\n");
407 return -ETIMEDOUT;
408 }
409
410 ecc_tmp = readl_relaxed(host->regs_va + ECC1);
411 ecc[0] = ecc_tmp;
412 ecc[1] = ecc_tmp >> 8;
413 ecc[2] = ecc_tmp >> 16;
414 ecc[3] = ecc_tmp >> 24;
415
416 ecc_tmp = readl_relaxed(host->regs_va + ECC2);
417 ecc[4] = ecc_tmp;
418 ecc[5] = ecc_tmp >> 8;
419 ecc[6] = ecc_tmp >> 16;
420 ecc[7] = ecc_tmp >> 24;
421
422 ecc_tmp = readl_relaxed(host->regs_va + ECC3);
423 ecc[8] = ecc_tmp;
424 ecc[9] = ecc_tmp >> 8;
425 ecc[10] = ecc_tmp >> 16;
426 ecc[11] = ecc_tmp >> 24;
427
428 ecc_tmp = readl_relaxed(host->regs_va + STS);
429 ecc[12] = ecc_tmp >> 16;
430
431 return 0;
432 }
433
434 /*
435 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
436 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
437 * max of 1-bit)
438 */
fsmc_read_hwecc_ecc1(struct nand_chip * chip,const u8 * data,u8 * ecc)439 static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
440 u8 *ecc)
441 {
442 struct fsmc_nand_data *host = nand_to_fsmc(chip);
443 u32 ecc_tmp;
444
445 ecc_tmp = readl_relaxed(host->regs_va + ECC1);
446 ecc[0] = ecc_tmp;
447 ecc[1] = ecc_tmp >> 8;
448 ecc[2] = ecc_tmp >> 16;
449
450 return 0;
451 }
452
fsmc_correct_ecc1(struct nand_chip * chip,unsigned char * buf,unsigned char * read_ecc,unsigned char * calc_ecc)453 static int fsmc_correct_ecc1(struct nand_chip *chip,
454 unsigned char *buf,
455 unsigned char *read_ecc,
456 unsigned char *calc_ecc)
457 {
458 bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER;
459
460 return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
461 chip->ecc.size, sm_order);
462 }
463
464 /* Count the number of 0's in buff upto a max of max_bits */
count_written_bits(u8 * buff,int size,int max_bits)465 static int count_written_bits(u8 *buff, int size, int max_bits)
466 {
467 int k, written_bits = 0;
468
469 for (k = 0; k < size; k++) {
470 written_bits += hweight8(~buff[k]);
471 if (written_bits > max_bits)
472 break;
473 }
474
475 return written_bits;
476 }
477
dma_complete(void * param)478 static void dma_complete(void *param)
479 {
480 struct fsmc_nand_data *host = param;
481
482 complete(&host->dma_access_complete);
483 }
484
dma_xfer(struct fsmc_nand_data * host,void * buffer,int len,enum dma_data_direction direction)485 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
486 enum dma_data_direction direction)
487 {
488 struct dma_chan *chan;
489 struct dma_device *dma_dev;
490 struct dma_async_tx_descriptor *tx;
491 dma_addr_t dma_dst, dma_src, dma_addr;
492 dma_cookie_t cookie;
493 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
494 int ret;
495 unsigned long time_left;
496
497 if (direction == DMA_TO_DEVICE)
498 chan = host->write_dma_chan;
499 else if (direction == DMA_FROM_DEVICE)
500 chan = host->read_dma_chan;
501 else
502 return -EINVAL;
503
504 dma_dev = chan->device;
505 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
506
507 if (direction == DMA_TO_DEVICE) {
508 dma_src = dma_addr;
509 dma_dst = host->data_pa;
510 } else {
511 dma_src = host->data_pa;
512 dma_dst = dma_addr;
513 }
514
515 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
516 len, flags);
517 if (!tx) {
518 dev_err(host->dev, "device_prep_dma_memcpy error\n");
519 ret = -EIO;
520 goto unmap_dma;
521 }
522
523 tx->callback = dma_complete;
524 tx->callback_param = host;
525 cookie = tx->tx_submit(tx);
526
527 ret = dma_submit_error(cookie);
528 if (ret) {
529 dev_err(host->dev, "dma_submit_error %d\n", cookie);
530 goto unmap_dma;
531 }
532
533 dma_async_issue_pending(chan);
534
535 time_left =
536 wait_for_completion_timeout(&host->dma_access_complete,
537 msecs_to_jiffies(3000));
538 if (time_left == 0) {
539 dmaengine_terminate_all(chan);
540 dev_err(host->dev, "wait_for_completion_timeout\n");
541 ret = -ETIMEDOUT;
542 goto unmap_dma;
543 }
544
545 ret = 0;
546
547 unmap_dma:
548 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
549
550 return ret;
551 }
552
553 /*
554 * fsmc_write_buf - write buffer to chip
555 * @host: FSMC NAND controller
556 * @buf: data buffer
557 * @len: number of bytes to write
558 */
fsmc_write_buf(struct fsmc_nand_data * host,const u8 * buf,int len)559 static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
560 int len)
561 {
562 int i;
563
564 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
565 IS_ALIGNED(len, sizeof(u32))) {
566 u32 *p = (u32 *)buf;
567
568 len = len >> 2;
569 for (i = 0; i < len; i++)
570 writel_relaxed(p[i], host->data_va);
571 } else {
572 for (i = 0; i < len; i++)
573 writeb_relaxed(buf[i], host->data_va);
574 }
575 }
576
577 /*
578 * fsmc_read_buf - read chip data into buffer
579 * @host: FSMC NAND controller
580 * @buf: buffer to store date
581 * @len: number of bytes to read
582 */
fsmc_read_buf(struct fsmc_nand_data * host,u8 * buf,int len)583 static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
584 {
585 int i;
586
587 if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
588 IS_ALIGNED(len, sizeof(u32))) {
589 u32 *p = (u32 *)buf;
590
591 len = len >> 2;
592 for (i = 0; i < len; i++)
593 p[i] = readl_relaxed(host->data_va);
594 } else {
595 for (i = 0; i < len; i++)
596 buf[i] = readb_relaxed(host->data_va);
597 }
598 }
599
600 /*
601 * fsmc_read_buf_dma - read chip data into buffer
602 * @host: FSMC NAND controller
603 * @buf: buffer to store date
604 * @len: number of bytes to read
605 */
fsmc_read_buf_dma(struct fsmc_nand_data * host,u8 * buf,int len)606 static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
607 int len)
608 {
609 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
610 }
611
612 /*
613 * fsmc_write_buf_dma - write buffer to chip
614 * @host: FSMC NAND controller
615 * @buf: data buffer
616 * @len: number of bytes to write
617 */
fsmc_write_buf_dma(struct fsmc_nand_data * host,const u8 * buf,int len)618 static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
619 int len)
620 {
621 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
622 }
623
624 /*
625 * fsmc_exec_op - hook called by the core to execute NAND operations
626 *
627 * This controller is simple enough and thus does not need to use the parser
628 * provided by the core, instead, handle every situation here.
629 */
fsmc_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)630 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
631 bool check_only)
632 {
633 struct fsmc_nand_data *host = nand_to_fsmc(chip);
634 const struct nand_op_instr *instr = NULL;
635 int ret = 0;
636 unsigned int op_id;
637 int i;
638
639 if (check_only)
640 return 0;
641
642 pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
643
644 for (op_id = 0; op_id < op->ninstrs; op_id++) {
645 instr = &op->instrs[op_id];
646
647 nand_op_trace(" ", instr);
648
649 switch (instr->type) {
650 case NAND_OP_CMD_INSTR:
651 writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
652 break;
653
654 case NAND_OP_ADDR_INSTR:
655 for (i = 0; i < instr->ctx.addr.naddrs; i++)
656 writeb_relaxed(instr->ctx.addr.addrs[i],
657 host->addr_va);
658 break;
659
660 case NAND_OP_DATA_IN_INSTR:
661 if (host->mode == USE_DMA_ACCESS)
662 fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
663 instr->ctx.data.len);
664 else
665 fsmc_read_buf(host, instr->ctx.data.buf.in,
666 instr->ctx.data.len);
667 break;
668
669 case NAND_OP_DATA_OUT_INSTR:
670 if (host->mode == USE_DMA_ACCESS)
671 fsmc_write_buf_dma(host,
672 instr->ctx.data.buf.out,
673 instr->ctx.data.len);
674 else
675 fsmc_write_buf(host, instr->ctx.data.buf.out,
676 instr->ctx.data.len);
677 break;
678
679 case NAND_OP_WAITRDY_INSTR:
680 ret = nand_soft_waitrdy(chip,
681 instr->ctx.waitrdy.timeout_ms);
682 break;
683 }
684
685 if (instr->delay_ns)
686 ndelay(instr->delay_ns);
687 }
688
689 return ret;
690 }
691
692 /*
693 * fsmc_read_page_hwecc
694 * @chip: nand chip info structure
695 * @buf: buffer to store read data
696 * @oob_required: caller expects OOB data read to chip->oob_poi
697 * @page: page number to read
698 *
699 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
700 * performed in a strict sequence as follows:
701 * data(512 byte) -> ecc(13 byte)
702 * After this read, fsmc hardware generates and reports error data bits(up to a
703 * max of 8 bits)
704 */
fsmc_read_page_hwecc(struct nand_chip * chip,u8 * buf,int oob_required,int page)705 static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
706 int oob_required, int page)
707 {
708 struct mtd_info *mtd = nand_to_mtd(chip);
709 int i, j, s, stat, eccsize = chip->ecc.size;
710 int eccbytes = chip->ecc.bytes;
711 int eccsteps = chip->ecc.steps;
712 u8 *p = buf;
713 u8 *ecc_calc = chip->ecc.calc_buf;
714 u8 *ecc_code = chip->ecc.code_buf;
715 int off, len, ret, group = 0;
716 /*
717 * ecc_oob is intentionally taken as u16. In 16bit devices, we
718 * end up reading 14 bytes (7 words) from oob. The local array is
719 * to maintain word alignment
720 */
721 u16 ecc_oob[7];
722 u8 *oob = (u8 *)&ecc_oob[0];
723 unsigned int max_bitflips = 0;
724
725 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
726 nand_read_page_op(chip, page, s * eccsize, NULL, 0);
727 chip->ecc.hwctl(chip, NAND_ECC_READ);
728 ret = nand_read_data_op(chip, p, eccsize, false, false);
729 if (ret)
730 return ret;
731
732 for (j = 0; j < eccbytes;) {
733 struct mtd_oob_region oobregion;
734
735 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
736 if (ret)
737 return ret;
738
739 off = oobregion.offset;
740 len = oobregion.length;
741
742 /*
743 * length is intentionally kept a higher multiple of 2
744 * to read at least 13 bytes even in case of 16 bit NAND
745 * devices
746 */
747 if (chip->options & NAND_BUSWIDTH_16)
748 len = roundup(len, 2);
749
750 nand_read_oob_op(chip, page, off, oob + j, len);
751 j += len;
752 }
753
754 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
755 chip->ecc.calculate(chip, p, &ecc_calc[i]);
756
757 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
758 if (stat < 0) {
759 mtd->ecc_stats.failed++;
760 } else {
761 mtd->ecc_stats.corrected += stat;
762 max_bitflips = max_t(unsigned int, max_bitflips, stat);
763 }
764 }
765
766 return max_bitflips;
767 }
768
769 /*
770 * fsmc_bch8_correct_data
771 * @mtd: mtd info structure
772 * @dat: buffer of read data
773 * @read_ecc: ecc read from device spare area
774 * @calc_ecc: ecc calculated from read data
775 *
776 * calc_ecc is a 104 bit information containing maximum of 8 error
777 * offset information of 13 bits each in 512 bytes of read data.
778 */
fsmc_bch8_correct_data(struct nand_chip * chip,u8 * dat,u8 * read_ecc,u8 * calc_ecc)779 static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
780 u8 *read_ecc, u8 *calc_ecc)
781 {
782 struct fsmc_nand_data *host = nand_to_fsmc(chip);
783 u32 err_idx[8];
784 u32 num_err, i;
785 u32 ecc1, ecc2, ecc3, ecc4;
786
787 num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
788
789 /* no bit flipping */
790 if (likely(num_err == 0))
791 return 0;
792
793 /* too many errors */
794 if (unlikely(num_err > 8)) {
795 /*
796 * This is a temporary erase check. A newly erased page read
797 * would result in an ecc error because the oob data is also
798 * erased to FF and the calculated ecc for an FF data is not
799 * FF..FF.
800 * This is a workaround to skip performing correction in case
801 * data is FF..FF
802 *
803 * Logic:
804 * For every page, each bit written as 0 is counted until these
805 * number of bits are greater than 8 (the maximum correction
806 * capability of FSMC for each 512 + 13 bytes)
807 */
808
809 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
810 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
811
812 if ((bits_ecc + bits_data) <= 8) {
813 if (bits_data)
814 memset(dat, 0xff, chip->ecc.size);
815 return bits_data;
816 }
817
818 return -EBADMSG;
819 }
820
821 /*
822 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
823 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
824 *
825 * calc_ecc is a 104 bit information containing maximum of 8 error
826 * offset information of 13 bits each. calc_ecc is copied into a
827 * u64 array and error offset indexes are populated in err_idx
828 * array
829 */
830 ecc1 = readl_relaxed(host->regs_va + ECC1);
831 ecc2 = readl_relaxed(host->regs_va + ECC2);
832 ecc3 = readl_relaxed(host->regs_va + ECC3);
833 ecc4 = readl_relaxed(host->regs_va + STS);
834
835 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
836 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
837 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
838 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
839 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
840 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
841 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
842 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
843
844 i = 0;
845 while (num_err--) {
846 err_idx[i] ^= 3;
847
848 if (err_idx[i] < chip->ecc.size * 8) {
849 int err = err_idx[i];
850
851 dat[err >> 3] ^= BIT(err & 7);
852 i++;
853 }
854 }
855 return i;
856 }
857
filter(struct dma_chan * chan,void * slave)858 static bool filter(struct dma_chan *chan, void *slave)
859 {
860 chan->private = slave;
861 return true;
862 }
863
fsmc_nand_probe_config_dt(struct platform_device * pdev,struct fsmc_nand_data * host,struct nand_chip * nand)864 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
865 struct fsmc_nand_data *host,
866 struct nand_chip *nand)
867 {
868 struct device_node *np = pdev->dev.of_node;
869 u32 val;
870 int ret;
871
872 nand->options = 0;
873
874 if (!of_property_read_u32(np, "bank-width", &val)) {
875 if (val == 2) {
876 nand->options |= NAND_BUSWIDTH_16;
877 } else if (val != 1) {
878 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
879 return -EINVAL;
880 }
881 }
882
883 if (of_property_read_bool(np, "nand-skip-bbtscan"))
884 nand->options |= NAND_SKIP_BBTSCAN;
885
886 host->dev_timings = devm_kzalloc(&pdev->dev,
887 sizeof(*host->dev_timings),
888 GFP_KERNEL);
889 if (!host->dev_timings)
890 return -ENOMEM;
891
892 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
893 sizeof(*host->dev_timings));
894 if (ret)
895 host->dev_timings = NULL;
896
897 /* Set default NAND bank to 0 */
898 host->bank = 0;
899 if (!of_property_read_u32(np, "bank", &val)) {
900 if (val > 3) {
901 dev_err(&pdev->dev, "invalid bank %u\n", val);
902 return -EINVAL;
903 }
904 host->bank = val;
905 }
906 return 0;
907 }
908
fsmc_nand_attach_chip(struct nand_chip * nand)909 static int fsmc_nand_attach_chip(struct nand_chip *nand)
910 {
911 struct mtd_info *mtd = nand_to_mtd(nand);
912 struct fsmc_nand_data *host = nand_to_fsmc(nand);
913
914 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
915 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
916
917 if (!nand->ecc.size)
918 nand->ecc.size = 512;
919
920 if (AMBA_REV_BITS(host->pid) >= 8) {
921 nand->ecc.read_page = fsmc_read_page_hwecc;
922 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
923 nand->ecc.correct = fsmc_bch8_correct_data;
924 nand->ecc.bytes = 13;
925 nand->ecc.strength = 8;
926 }
927
928 if (AMBA_REV_BITS(host->pid) >= 8) {
929 switch (mtd->oobsize) {
930 case 16:
931 case 64:
932 case 128:
933 case 224:
934 case 256:
935 break;
936 default:
937 dev_warn(host->dev,
938 "No oob scheme defined for oobsize %d\n",
939 mtd->oobsize);
940 return -EINVAL;
941 }
942
943 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
944
945 return 0;
946 }
947
948 switch (nand->ecc.engine_type) {
949 case NAND_ECC_ENGINE_TYPE_ON_HOST:
950 dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
951 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
952 nand->ecc.correct = fsmc_correct_ecc1;
953 nand->ecc.hwctl = fsmc_enable_hwecc;
954 nand->ecc.bytes = 3;
955 nand->ecc.strength = 1;
956 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
957 break;
958
959 case NAND_ECC_ENGINE_TYPE_SOFT:
960 if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
961 dev_info(host->dev,
962 "Using 4-bit SW BCH ECC scheme\n");
963 break;
964 }
965 break;
966
967 case NAND_ECC_ENGINE_TYPE_ON_DIE:
968 break;
969
970 default:
971 dev_err(host->dev, "Unsupported ECC mode!\n");
972 return -ENOTSUPP;
973 }
974
975 /*
976 * Don't set layout for BCH4 SW ECC. This will be
977 * generated later during BCH initialization.
978 */
979 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
980 switch (mtd->oobsize) {
981 case 16:
982 case 64:
983 case 128:
984 mtd_set_ooblayout(mtd,
985 &fsmc_ecc1_ooblayout_ops);
986 break;
987 default:
988 dev_warn(host->dev,
989 "No oob scheme defined for oobsize %d\n",
990 mtd->oobsize);
991 return -EINVAL;
992 }
993 }
994
995 return 0;
996 }
997
998 static const struct nand_controller_ops fsmc_nand_controller_ops = {
999 .attach_chip = fsmc_nand_attach_chip,
1000 .exec_op = fsmc_exec_op,
1001 .setup_interface = fsmc_setup_interface,
1002 };
1003
1004 /**
1005 * fsmc_nand_disable() - Disables the NAND bank
1006 * @host: The instance to disable
1007 */
fsmc_nand_disable(struct fsmc_nand_data * host)1008 static void fsmc_nand_disable(struct fsmc_nand_data *host)
1009 {
1010 u32 val;
1011
1012 val = readl(host->regs_va + FSMC_PC);
1013 val &= ~FSMC_ENABLE;
1014 writel(val, host->regs_va + FSMC_PC);
1015 }
1016
1017 /*
1018 * fsmc_nand_probe - Probe function
1019 * @pdev: platform device structure
1020 */
fsmc_nand_probe(struct platform_device * pdev)1021 static int __init fsmc_nand_probe(struct platform_device *pdev)
1022 {
1023 struct fsmc_nand_data *host;
1024 struct mtd_info *mtd;
1025 struct nand_chip *nand;
1026 struct resource *res;
1027 void __iomem *base;
1028 dma_cap_mask_t mask;
1029 int ret = 0;
1030 u32 pid;
1031 int i;
1032
1033 /* Allocate memory for the device structure (and zero it) */
1034 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1035 if (!host)
1036 return -ENOMEM;
1037
1038 nand = &host->nand;
1039
1040 ret = fsmc_nand_probe_config_dt(pdev, host, nand);
1041 if (ret)
1042 return ret;
1043
1044 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
1045 host->data_va = devm_ioremap_resource(&pdev->dev, res);
1046 if (IS_ERR(host->data_va))
1047 return PTR_ERR(host->data_va);
1048
1049 host->data_pa = (dma_addr_t)res->start;
1050
1051 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
1052 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
1053 if (IS_ERR(host->addr_va))
1054 return PTR_ERR(host->addr_va);
1055
1056 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
1057 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
1058 if (IS_ERR(host->cmd_va))
1059 return PTR_ERR(host->cmd_va);
1060
1061 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
1062 base = devm_ioremap_resource(&pdev->dev, res);
1063 if (IS_ERR(base))
1064 return PTR_ERR(base);
1065
1066 host->regs_va = base + FSMC_NOR_REG_SIZE +
1067 (host->bank * FSMC_NAND_BANK_SZ);
1068
1069 host->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1070 if (IS_ERR(host->clk)) {
1071 dev_err(&pdev->dev, "failed to fetch block clock\n");
1072 return PTR_ERR(host->clk);
1073 }
1074
1075 /*
1076 * This device ID is actually a common AMBA ID as used on the
1077 * AMBA PrimeCell bus. However it is not a PrimeCell.
1078 */
1079 for (pid = 0, i = 0; i < 4; i++)
1080 pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1081 255) << (i * 8);
1082
1083 host->pid = pid;
1084
1085 dev_info(&pdev->dev,
1086 "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
1087 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1088 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1089
1090 host->dev = &pdev->dev;
1091
1092 if (host->mode == USE_DMA_ACCESS)
1093 init_completion(&host->dma_access_complete);
1094
1095 /* Link all private pointers */
1096 mtd = nand_to_mtd(&host->nand);
1097 nand_set_flash_node(nand, pdev->dev.of_node);
1098
1099 mtd->dev.parent = &pdev->dev;
1100
1101 nand->badblockbits = 7;
1102
1103 if (host->mode == USE_DMA_ACCESS) {
1104 dma_cap_zero(mask);
1105 dma_cap_set(DMA_MEMCPY, mask);
1106 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
1107 if (!host->read_dma_chan) {
1108 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1109 ret = -ENODEV;
1110 goto disable_fsmc;
1111 }
1112 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
1113 if (!host->write_dma_chan) {
1114 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1115 ret = -ENODEV;
1116 goto release_dma_read_chan;
1117 }
1118 }
1119
1120 if (host->dev_timings) {
1121 fsmc_nand_setup(host, host->dev_timings);
1122 nand->options |= NAND_KEEP_TIMINGS;
1123 }
1124
1125 nand_controller_init(&host->base);
1126 host->base.ops = &fsmc_nand_controller_ops;
1127 nand->controller = &host->base;
1128
1129 /*
1130 * Scan to find existence of the device
1131 */
1132 ret = nand_scan(nand, 1);
1133 if (ret)
1134 goto release_dma_write_chan;
1135
1136 mtd->name = "nand";
1137 ret = mtd_device_register(mtd, NULL, 0);
1138 if (ret)
1139 goto cleanup_nand;
1140
1141 platform_set_drvdata(pdev, host);
1142 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1143
1144 return 0;
1145
1146 cleanup_nand:
1147 nand_cleanup(nand);
1148 release_dma_write_chan:
1149 if (host->mode == USE_DMA_ACCESS)
1150 dma_release_channel(host->write_dma_chan);
1151 release_dma_read_chan:
1152 if (host->mode == USE_DMA_ACCESS)
1153 dma_release_channel(host->read_dma_chan);
1154 disable_fsmc:
1155 fsmc_nand_disable(host);
1156
1157 return ret;
1158 }
1159
1160 /*
1161 * Clean up routine
1162 */
fsmc_nand_remove(struct platform_device * pdev)1163 static void fsmc_nand_remove(struct platform_device *pdev)
1164 {
1165 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1166
1167 if (host) {
1168 struct nand_chip *chip = &host->nand;
1169 int ret;
1170
1171 ret = mtd_device_unregister(nand_to_mtd(chip));
1172 WARN_ON(ret);
1173 nand_cleanup(chip);
1174 fsmc_nand_disable(host);
1175
1176 if (host->mode == USE_DMA_ACCESS) {
1177 dma_release_channel(host->write_dma_chan);
1178 dma_release_channel(host->read_dma_chan);
1179 }
1180 }
1181 }
1182
1183 #ifdef CONFIG_PM_SLEEP
fsmc_nand_suspend(struct device * dev)1184 static int fsmc_nand_suspend(struct device *dev)
1185 {
1186 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1187
1188 if (host)
1189 clk_disable_unprepare(host->clk);
1190
1191 return 0;
1192 }
1193
fsmc_nand_resume(struct device * dev)1194 static int fsmc_nand_resume(struct device *dev)
1195 {
1196 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1197 int ret;
1198
1199 if (host) {
1200 ret = clk_prepare_enable(host->clk);
1201 if (ret) {
1202 dev_err(dev, "failed to enable clk\n");
1203 return ret;
1204 }
1205 if (host->dev_timings)
1206 fsmc_nand_setup(host, host->dev_timings);
1207 nand_reset(&host->nand, 0);
1208 }
1209
1210 return 0;
1211 }
1212 #endif
1213
1214 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1215
1216 static const struct of_device_id fsmc_nand_id_table[] = {
1217 { .compatible = "st,spear600-fsmc-nand" },
1218 { .compatible = "stericsson,fsmc-nand" },
1219 {}
1220 };
1221 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1222
1223 static struct platform_driver fsmc_nand_driver = {
1224 .remove_new = fsmc_nand_remove,
1225 .driver = {
1226 .name = "fsmc-nand",
1227 .of_match_table = fsmc_nand_id_table,
1228 .pm = &fsmc_nand_pm_ops,
1229 },
1230 };
1231
1232 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1233
1234 MODULE_LICENSE("GPL v2");
1235 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1236 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
1237