1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale UPM NAND driver. 4 * 5 * Copyright © 2007-2008 MontaVista Software, Inc. 6 * 7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/mtd/rawnand.h> 14 #include <linux/mtd/nand_ecc.h> 15 #include <linux/mtd/partitions.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_gpio.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 #include <asm/fsl_lbc.h> 23 24 #define FSL_UPM_WAIT_RUN_PATTERN 0x1 25 #define FSL_UPM_WAIT_WRITE_BYTE 0x2 26 #define FSL_UPM_WAIT_WRITE_BUFFER 0x4 27 28 struct fsl_upm_nand { 29 struct device *dev; 30 struct nand_chip chip; 31 int last_ctrl; 32 struct mtd_partition *parts; 33 struct fsl_upm upm; 34 uint8_t upm_addr_offset; 35 uint8_t upm_cmd_offset; 36 void __iomem *io_base; 37 int rnb_gpio[NAND_MAX_CHIPS]; 38 uint32_t mchip_offsets[NAND_MAX_CHIPS]; 39 uint32_t mchip_count; 40 uint32_t mchip_number; 41 int chip_delay; 42 uint32_t wait_flags; 43 }; 44 45 static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo) 46 { 47 return container_of(mtd_to_nand(mtdinfo), struct fsl_upm_nand, 48 chip); 49 } 50 51 static int fun_chip_ready(struct nand_chip *chip) 52 { 53 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip)); 54 55 if (gpio_get_value(fun->rnb_gpio[fun->mchip_number])) 56 return 1; 57 58 dev_vdbg(fun->dev, "busy\n"); 59 return 0; 60 } 61 62 static void fun_wait_rnb(struct fsl_upm_nand *fun) 63 { 64 if (fun->rnb_gpio[fun->mchip_number] >= 0) { 65 struct mtd_info *mtd = nand_to_mtd(&fun->chip); 66 int cnt = 1000000; 67 68 while (--cnt && !fun_chip_ready(&fun->chip)) 69 cpu_relax(); 70 if (!cnt) 71 dev_err(fun->dev, "tired waiting for RNB\n"); 72 } else { 73 ndelay(100); 74 } 75 } 76 77 static void fun_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl) 78 { 79 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip)); 80 u32 mar; 81 82 if (!(ctrl & fun->last_ctrl)) { 83 fsl_upm_end_pattern(&fun->upm); 84 85 if (cmd == NAND_CMD_NONE) 86 return; 87 88 fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE); 89 } 90 91 if (ctrl & NAND_CTRL_CHANGE) { 92 if (ctrl & NAND_ALE) 93 fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); 94 else if (ctrl & NAND_CLE) 95 fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); 96 } 97 98 mar = (cmd << (32 - fun->upm.width)) | 99 fun->mchip_offsets[fun->mchip_number]; 100 fsl_upm_run_pattern(&fun->upm, chip->legacy.IO_ADDR_R, mar); 101 102 if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN) 103 fun_wait_rnb(fun); 104 } 105 106 static void fun_select_chip(struct nand_chip *chip, int mchip_nr) 107 { 108 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip)); 109 110 if (mchip_nr == -1) { 111 chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); 112 } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) { 113 fun->mchip_number = mchip_nr; 114 chip->legacy.IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr]; 115 chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R; 116 } else { 117 BUG(); 118 } 119 } 120 121 static uint8_t fun_read_byte(struct nand_chip *chip) 122 { 123 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip)); 124 125 return in_8(fun->chip.legacy.IO_ADDR_R); 126 } 127 128 static void fun_read_buf(struct nand_chip *chip, uint8_t *buf, int len) 129 { 130 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip)); 131 int i; 132 133 for (i = 0; i < len; i++) 134 buf[i] = in_8(fun->chip.legacy.IO_ADDR_R); 135 } 136 137 static void fun_write_buf(struct nand_chip *chip, const uint8_t *buf, int len) 138 { 139 struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip)); 140 int i; 141 142 for (i = 0; i < len; i++) { 143 out_8(fun->chip.legacy.IO_ADDR_W, buf[i]); 144 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE) 145 fun_wait_rnb(fun); 146 } 147 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER) 148 fun_wait_rnb(fun); 149 } 150 151 static int fun_chip_init(struct fsl_upm_nand *fun, 152 const struct device_node *upm_np, 153 const struct resource *io_res) 154 { 155 struct mtd_info *mtd = nand_to_mtd(&fun->chip); 156 int ret; 157 struct device_node *flash_np; 158 159 fun->chip.legacy.IO_ADDR_R = fun->io_base; 160 fun->chip.legacy.IO_ADDR_W = fun->io_base; 161 fun->chip.legacy.cmd_ctrl = fun_cmd_ctrl; 162 fun->chip.legacy.chip_delay = fun->chip_delay; 163 fun->chip.legacy.read_byte = fun_read_byte; 164 fun->chip.legacy.read_buf = fun_read_buf; 165 fun->chip.legacy.write_buf = fun_write_buf; 166 fun->chip.ecc.mode = NAND_ECC_SOFT; 167 fun->chip.ecc.algo = NAND_ECC_HAMMING; 168 if (fun->mchip_count > 1) 169 fun->chip.legacy.select_chip = fun_select_chip; 170 171 if (fun->rnb_gpio[0] >= 0) 172 fun->chip.legacy.dev_ready = fun_chip_ready; 173 174 mtd->dev.parent = fun->dev; 175 176 flash_np = of_get_next_child(upm_np, NULL); 177 if (!flash_np) 178 return -ENODEV; 179 180 nand_set_flash_node(&fun->chip, flash_np); 181 mtd->name = kasprintf(GFP_KERNEL, "0x%llx.%pOFn", (u64)io_res->start, 182 flash_np); 183 if (!mtd->name) { 184 ret = -ENOMEM; 185 goto err; 186 } 187 188 ret = nand_scan(&fun->chip, fun->mchip_count); 189 if (ret) 190 goto err; 191 192 ret = mtd_device_register(mtd, NULL, 0); 193 err: 194 of_node_put(flash_np); 195 if (ret) 196 kfree(mtd->name); 197 return ret; 198 } 199 200 static int fun_probe(struct platform_device *ofdev) 201 { 202 struct fsl_upm_nand *fun; 203 struct resource io_res; 204 const __be32 *prop; 205 int rnb_gpio; 206 int ret; 207 int size; 208 int i; 209 210 fun = kzalloc(sizeof(*fun), GFP_KERNEL); 211 if (!fun) 212 return -ENOMEM; 213 214 ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res); 215 if (ret) { 216 dev_err(&ofdev->dev, "can't get IO base\n"); 217 goto err1; 218 } 219 220 ret = fsl_upm_find(io_res.start, &fun->upm); 221 if (ret) { 222 dev_err(&ofdev->dev, "can't find UPM\n"); 223 goto err1; 224 } 225 226 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset", 227 &size); 228 if (!prop || size != sizeof(uint32_t)) { 229 dev_err(&ofdev->dev, "can't get UPM address offset\n"); 230 ret = -EINVAL; 231 goto err1; 232 } 233 fun->upm_addr_offset = *prop; 234 235 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size); 236 if (!prop || size != sizeof(uint32_t)) { 237 dev_err(&ofdev->dev, "can't get UPM command offset\n"); 238 ret = -EINVAL; 239 goto err1; 240 } 241 fun->upm_cmd_offset = *prop; 242 243 prop = of_get_property(ofdev->dev.of_node, 244 "fsl,upm-addr-line-cs-offsets", &size); 245 if (prop && (size / sizeof(uint32_t)) > 0) { 246 fun->mchip_count = size / sizeof(uint32_t); 247 if (fun->mchip_count >= NAND_MAX_CHIPS) { 248 dev_err(&ofdev->dev, "too much multiple chips\n"); 249 goto err1; 250 } 251 for (i = 0; i < fun->mchip_count; i++) 252 fun->mchip_offsets[i] = be32_to_cpu(prop[i]); 253 } else { 254 fun->mchip_count = 1; 255 } 256 257 for (i = 0; i < fun->mchip_count; i++) { 258 fun->rnb_gpio[i] = -1; 259 rnb_gpio = of_get_gpio(ofdev->dev.of_node, i); 260 if (rnb_gpio >= 0) { 261 ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev)); 262 if (ret) { 263 dev_err(&ofdev->dev, 264 "can't request RNB gpio #%d\n", i); 265 goto err2; 266 } 267 gpio_direction_input(rnb_gpio); 268 fun->rnb_gpio[i] = rnb_gpio; 269 } else if (rnb_gpio == -EINVAL) { 270 dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i); 271 goto err2; 272 } 273 } 274 275 prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL); 276 if (prop) 277 fun->chip_delay = be32_to_cpup(prop); 278 else 279 fun->chip_delay = 50; 280 281 prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size); 282 if (prop && size == sizeof(uint32_t)) 283 fun->wait_flags = be32_to_cpup(prop); 284 else 285 fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN | 286 FSL_UPM_WAIT_WRITE_BYTE; 287 288 fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start, 289 resource_size(&io_res)); 290 if (!fun->io_base) { 291 ret = -ENOMEM; 292 goto err2; 293 } 294 295 fun->dev = &ofdev->dev; 296 fun->last_ctrl = NAND_CLE; 297 298 ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res); 299 if (ret) 300 goto err2; 301 302 dev_set_drvdata(&ofdev->dev, fun); 303 304 return 0; 305 err2: 306 for (i = 0; i < fun->mchip_count; i++) { 307 if (fun->rnb_gpio[i] < 0) 308 break; 309 gpio_free(fun->rnb_gpio[i]); 310 } 311 err1: 312 kfree(fun); 313 314 return ret; 315 } 316 317 static int fun_remove(struct platform_device *ofdev) 318 { 319 struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev); 320 struct mtd_info *mtd = nand_to_mtd(&fun->chip); 321 int i; 322 323 nand_release(&fun->chip); 324 kfree(mtd->name); 325 326 for (i = 0; i < fun->mchip_count; i++) { 327 if (fun->rnb_gpio[i] < 0) 328 break; 329 gpio_free(fun->rnb_gpio[i]); 330 } 331 332 kfree(fun); 333 334 return 0; 335 } 336 337 static const struct of_device_id of_fun_match[] = { 338 { .compatible = "fsl,upm-nand" }, 339 {}, 340 }; 341 MODULE_DEVICE_TABLE(of, of_fun_match); 342 343 static struct platform_driver of_fun_driver = { 344 .driver = { 345 .name = "fsl,upm-nand", 346 .of_match_table = of_fun_match, 347 }, 348 .probe = fun_probe, 349 .remove = fun_remove, 350 }; 351 352 module_platform_driver(of_fun_driver); 353 354 MODULE_LICENSE("GPL"); 355 MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>"); 356 MODULE_DESCRIPTION("Driver for NAND chips working through Freescale " 357 "LocalBus User-Programmable Machine"); 358