1 /* 2 * Freescale Integrated Flash Controller NAND driver 3 * 4 * Copyright 2011-2012 Freescale Semiconductor, Inc 5 * 6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/module.h> 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/of_address.h> 27 #include <linux/slab.h> 28 #include <linux/mtd/mtd.h> 29 #include <linux/mtd/rawnand.h> 30 #include <linux/mtd/partitions.h> 31 #include <linux/mtd/nand_ecc.h> 32 #include <linux/fsl_ifc.h> 33 34 #define ERR_BYTE 0xFF /* Value returned for read 35 bytes when read failed */ 36 #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait 37 for IFC NAND Machine */ 38 39 struct fsl_ifc_ctrl; 40 41 /* mtd information per set */ 42 struct fsl_ifc_mtd { 43 struct nand_chip chip; 44 struct fsl_ifc_ctrl *ctrl; 45 46 struct device *dev; 47 int bank; /* Chip select bank number */ 48 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */ 49 u8 __iomem *vbase; /* Chip select base virtual address */ 50 }; 51 52 /* overview of the fsl ifc controller */ 53 struct fsl_ifc_nand_ctrl { 54 struct nand_hw_control controller; 55 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT]; 56 57 void __iomem *addr; /* Address of assigned IFC buffer */ 58 unsigned int page; /* Last page written to / read from */ 59 unsigned int read_bytes;/* Number of bytes read during command */ 60 unsigned int column; /* Saved column from SEQIN */ 61 unsigned int index; /* Pointer to next byte to 'read' */ 62 unsigned int oob; /* Non zero if operating on OOB data */ 63 unsigned int eccread; /* Non zero for a full-page ECC read */ 64 unsigned int counter; /* counter for the initializations */ 65 unsigned int max_bitflips; /* Saved during READ0 cmd */ 66 }; 67 68 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl; 69 70 /* 71 * Generic flash bbt descriptors 72 */ 73 static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 74 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 75 76 static struct nand_bbt_descr bbt_main_descr = { 77 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 78 NAND_BBT_2BIT | NAND_BBT_VERSION, 79 .offs = 2, /* 0 on 8-bit small page */ 80 .len = 4, 81 .veroffs = 6, 82 .maxblocks = 4, 83 .pattern = bbt_pattern, 84 }; 85 86 static struct nand_bbt_descr bbt_mirror_descr = { 87 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 88 NAND_BBT_2BIT | NAND_BBT_VERSION, 89 .offs = 2, /* 0 on 8-bit small page */ 90 .len = 4, 91 .veroffs = 6, 92 .maxblocks = 4, 93 .pattern = mirror_pattern, 94 }; 95 96 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section, 97 struct mtd_oob_region *oobregion) 98 { 99 struct nand_chip *chip = mtd_to_nand(mtd); 100 101 if (section) 102 return -ERANGE; 103 104 oobregion->offset = 8; 105 oobregion->length = chip->ecc.total; 106 107 return 0; 108 } 109 110 static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section, 111 struct mtd_oob_region *oobregion) 112 { 113 struct nand_chip *chip = mtd_to_nand(mtd); 114 115 if (section > 1) 116 return -ERANGE; 117 118 if (mtd->writesize == 512 && 119 !(chip->options & NAND_BUSWIDTH_16)) { 120 if (!section) { 121 oobregion->offset = 0; 122 oobregion->length = 5; 123 } else { 124 oobregion->offset = 6; 125 oobregion->length = 2; 126 } 127 128 return 0; 129 } 130 131 if (!section) { 132 oobregion->offset = 2; 133 oobregion->length = 6; 134 } else { 135 oobregion->offset = chip->ecc.total + 8; 136 oobregion->length = mtd->oobsize - oobregion->offset; 137 } 138 139 return 0; 140 } 141 142 static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = { 143 .ecc = fsl_ifc_ooblayout_ecc, 144 .free = fsl_ifc_ooblayout_free, 145 }; 146 147 /* 148 * Set up the IFC hardware block and page address fields, and the ifc nand 149 * structure addr field to point to the correct IFC buffer in memory 150 */ 151 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) 152 { 153 struct nand_chip *chip = mtd_to_nand(mtd); 154 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 155 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 156 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; 157 int buf_num; 158 159 ifc_nand_ctrl->page = page_addr; 160 /* Program ROW0/COL0 */ 161 ifc_out32(page_addr, &ifc->ifc_nand.row0); 162 ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0); 163 164 buf_num = page_addr & priv->bufnum_mask; 165 166 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2); 167 ifc_nand_ctrl->index = column; 168 169 /* for OOB data point to the second half of the buffer */ 170 if (oob) 171 ifc_nand_ctrl->index += mtd->writesize; 172 } 173 174 /* returns nonzero if entire page is blank */ 175 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, 176 u32 eccstat, unsigned int bufnum) 177 { 178 return (eccstat >> ((3 - bufnum % 4) * 8)) & 15; 179 } 180 181 /* 182 * execute IFC NAND command and wait for it to complete 183 */ 184 static void fsl_ifc_run_command(struct mtd_info *mtd) 185 { 186 struct nand_chip *chip = mtd_to_nand(mtd); 187 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 188 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 189 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; 190 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; 191 u32 eccstat; 192 int i; 193 194 /* set the chip select for NAND Transaction */ 195 ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT, 196 &ifc->ifc_nand.nand_csel); 197 198 dev_vdbg(priv->dev, 199 "%s: fir0=%08x fcr0=%08x\n", 200 __func__, 201 ifc_in32(&ifc->ifc_nand.nand_fir0), 202 ifc_in32(&ifc->ifc_nand.nand_fcr0)); 203 204 ctrl->nand_stat = 0; 205 206 /* start read/write seq */ 207 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); 208 209 /* wait for command complete flag or timeout */ 210 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, 211 msecs_to_jiffies(IFC_TIMEOUT_MSECS)); 212 213 /* ctrl->nand_stat will be updated from IRQ context */ 214 if (!ctrl->nand_stat) 215 dev_err(priv->dev, "Controller is not responding\n"); 216 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER) 217 dev_err(priv->dev, "NAND Flash Timeout Error\n"); 218 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER) 219 dev_err(priv->dev, "NAND Flash Write Protect Error\n"); 220 221 nctrl->max_bitflips = 0; 222 223 if (nctrl->eccread) { 224 int errors; 225 int bufnum = nctrl->page & priv->bufnum_mask; 226 int sector_start = bufnum * chip->ecc.steps; 227 int sector_end = sector_start + chip->ecc.steps - 1; 228 __be32 *eccstat_regs; 229 230 eccstat_regs = ifc->ifc_nand.nand_eccstat; 231 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]); 232 233 for (i = sector_start; i <= sector_end; i++) { 234 if (i != sector_start && !(i % 4)) 235 eccstat = ifc_in32(&eccstat_regs[i / 4]); 236 237 errors = check_read_ecc(mtd, ctrl, eccstat, i); 238 239 if (errors == 15) { 240 /* 241 * Uncorrectable error. 242 * We'll check for blank pages later. 243 * 244 * We disable ECCER reporting due to... 245 * erratum IFC-A002770 -- so report it now if we 246 * see an uncorrectable error in ECCSTAT. 247 */ 248 ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER; 249 continue; 250 } 251 252 mtd->ecc_stats.corrected += errors; 253 nctrl->max_bitflips = max_t(unsigned int, 254 nctrl->max_bitflips, 255 errors); 256 } 257 258 nctrl->eccread = 0; 259 } 260 } 261 262 static void fsl_ifc_do_read(struct nand_chip *chip, 263 int oob, 264 struct mtd_info *mtd) 265 { 266 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 267 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 268 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; 269 270 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ 271 if (mtd->writesize > 512) { 272 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 273 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 274 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 275 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | 276 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT), 277 &ifc->ifc_nand.nand_fir0); 278 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); 279 280 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | 281 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT), 282 &ifc->ifc_nand.nand_fcr0); 283 } else { 284 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 285 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 286 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 287 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT), 288 &ifc->ifc_nand.nand_fir0); 289 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); 290 291 if (oob) 292 ifc_out32(NAND_CMD_READOOB << 293 IFC_NAND_FCR0_CMD0_SHIFT, 294 &ifc->ifc_nand.nand_fcr0); 295 else 296 ifc_out32(NAND_CMD_READ0 << 297 IFC_NAND_FCR0_CMD0_SHIFT, 298 &ifc->ifc_nand.nand_fcr0); 299 } 300 } 301 302 /* cmdfunc send commands to the IFC NAND Machine */ 303 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, 304 int column, int page_addr) { 305 struct nand_chip *chip = mtd_to_nand(mtd); 306 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 307 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 308 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; 309 310 /* clear the read buffer */ 311 ifc_nand_ctrl->read_bytes = 0; 312 if (command != NAND_CMD_PAGEPROG) 313 ifc_nand_ctrl->index = 0; 314 315 switch (command) { 316 /* READ0 read the entire buffer to use hardware ECC. */ 317 case NAND_CMD_READ0: 318 ifc_out32(0, &ifc->ifc_nand.nand_fbcr); 319 set_addr(mtd, 0, page_addr, 0); 320 321 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; 322 ifc_nand_ctrl->index += column; 323 324 if (chip->ecc.mode == NAND_ECC_HW) 325 ifc_nand_ctrl->eccread = 1; 326 327 fsl_ifc_do_read(chip, 0, mtd); 328 fsl_ifc_run_command(mtd); 329 return; 330 331 /* READOOB reads only the OOB because no ECC is performed. */ 332 case NAND_CMD_READOOB: 333 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr); 334 set_addr(mtd, column, page_addr, 1); 335 336 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; 337 338 fsl_ifc_do_read(chip, 1, mtd); 339 fsl_ifc_run_command(mtd); 340 341 return; 342 343 case NAND_CMD_READID: 344 case NAND_CMD_PARAM: { 345 /* 346 * For READID, read 8 bytes that are currently used. 347 * For PARAM, read all 3 copies of 256-bytes pages. 348 */ 349 int len = 8; 350 int timing = IFC_FIR_OP_RB; 351 if (command == NAND_CMD_PARAM) { 352 timing = IFC_FIR_OP_RBCD; 353 len = 256 * 3; 354 } 355 356 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 357 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | 358 (timing << IFC_NAND_FIR0_OP2_SHIFT), 359 &ifc->ifc_nand.nand_fir0); 360 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT, 361 &ifc->ifc_nand.nand_fcr0); 362 ifc_out32(column, &ifc->ifc_nand.row3); 363 364 ifc_out32(len, &ifc->ifc_nand.nand_fbcr); 365 ifc_nand_ctrl->read_bytes = len; 366 367 set_addr(mtd, 0, 0, 0); 368 fsl_ifc_run_command(mtd); 369 return; 370 } 371 372 /* ERASE1 stores the block and page address */ 373 case NAND_CMD_ERASE1: 374 set_addr(mtd, 0, page_addr, 0); 375 return; 376 377 /* ERASE2 uses the block and page address from ERASE1 */ 378 case NAND_CMD_ERASE2: 379 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 380 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | 381 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT), 382 &ifc->ifc_nand.nand_fir0); 383 384 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | 385 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT), 386 &ifc->ifc_nand.nand_fcr0); 387 388 ifc_out32(0, &ifc->ifc_nand.nand_fbcr); 389 ifc_nand_ctrl->read_bytes = 0; 390 fsl_ifc_run_command(mtd); 391 return; 392 393 /* SEQIN sets up the addr buffer and all registers except the length */ 394 case NAND_CMD_SEQIN: { 395 u32 nand_fcr0; 396 ifc_nand_ctrl->column = column; 397 ifc_nand_ctrl->oob = 0; 398 399 if (mtd->writesize > 512) { 400 nand_fcr0 = 401 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | 402 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | 403 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); 404 405 ifc_out32( 406 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 407 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 408 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 409 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | 410 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT), 411 &ifc->ifc_nand.nand_fir0); 412 ifc_out32( 413 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | 414 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) | 415 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT), 416 &ifc->ifc_nand.nand_fir1); 417 } else { 418 nand_fcr0 = ((NAND_CMD_PAGEPROG << 419 IFC_NAND_FCR0_CMD1_SHIFT) | 420 (NAND_CMD_SEQIN << 421 IFC_NAND_FCR0_CMD2_SHIFT) | 422 (NAND_CMD_STATUS << 423 IFC_NAND_FCR0_CMD3_SHIFT)); 424 425 ifc_out32( 426 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 427 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | 428 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | 429 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | 430 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT), 431 &ifc->ifc_nand.nand_fir0); 432 ifc_out32( 433 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | 434 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | 435 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) | 436 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT), 437 &ifc->ifc_nand.nand_fir1); 438 439 if (column >= mtd->writesize) 440 nand_fcr0 |= 441 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT; 442 else 443 nand_fcr0 |= 444 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT; 445 } 446 447 if (column >= mtd->writesize) { 448 /* OOB area --> READOOB */ 449 column -= mtd->writesize; 450 ifc_nand_ctrl->oob = 1; 451 } 452 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0); 453 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob); 454 return; 455 } 456 457 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ 458 case NAND_CMD_PAGEPROG: { 459 if (ifc_nand_ctrl->oob) { 460 ifc_out32(ifc_nand_ctrl->index - 461 ifc_nand_ctrl->column, 462 &ifc->ifc_nand.nand_fbcr); 463 } else { 464 ifc_out32(0, &ifc->ifc_nand.nand_fbcr); 465 } 466 467 fsl_ifc_run_command(mtd); 468 return; 469 } 470 471 case NAND_CMD_STATUS: { 472 void __iomem *addr; 473 474 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 475 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT), 476 &ifc->ifc_nand.nand_fir0); 477 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, 478 &ifc->ifc_nand.nand_fcr0); 479 ifc_out32(1, &ifc->ifc_nand.nand_fbcr); 480 set_addr(mtd, 0, 0, 0); 481 ifc_nand_ctrl->read_bytes = 1; 482 483 fsl_ifc_run_command(mtd); 484 485 /* 486 * The chip always seems to report that it is 487 * write-protected, even when it is not. 488 */ 489 addr = ifc_nand_ctrl->addr; 490 if (chip->options & NAND_BUSWIDTH_16) 491 ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr); 492 else 493 ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr); 494 return; 495 } 496 497 case NAND_CMD_RESET: 498 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT, 499 &ifc->ifc_nand.nand_fir0); 500 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT, 501 &ifc->ifc_nand.nand_fcr0); 502 fsl_ifc_run_command(mtd); 503 return; 504 505 default: 506 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n", 507 __func__, command); 508 } 509 } 510 511 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) 512 { 513 /* The hardware does not seem to support multiple 514 * chips per bank. 515 */ 516 } 517 518 /* 519 * Write buf to the IFC NAND Controller Data Buffer 520 */ 521 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) 522 { 523 struct nand_chip *chip = mtd_to_nand(mtd); 524 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 525 unsigned int bufsize = mtd->writesize + mtd->oobsize; 526 527 if (len <= 0) { 528 dev_err(priv->dev, "%s: len %d bytes", __func__, len); 529 return; 530 } 531 532 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) { 533 dev_err(priv->dev, 534 "%s: beyond end of buffer (%d requested, %u available)\n", 535 __func__, len, bufsize - ifc_nand_ctrl->index); 536 len = bufsize - ifc_nand_ctrl->index; 537 } 538 539 memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len); 540 ifc_nand_ctrl->index += len; 541 } 542 543 /* 544 * Read a byte from either the IFC hardware buffer 545 * read function for 8-bit buswidth 546 */ 547 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd) 548 { 549 struct nand_chip *chip = mtd_to_nand(mtd); 550 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 551 unsigned int offset; 552 553 /* 554 * If there are still bytes in the IFC buffer, then use the 555 * next byte. 556 */ 557 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { 558 offset = ifc_nand_ctrl->index++; 559 return ifc_in8(ifc_nand_ctrl->addr + offset); 560 } 561 562 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); 563 return ERR_BYTE; 564 } 565 566 /* 567 * Read two bytes from the IFC hardware buffer 568 * read function for 16-bit buswith 569 */ 570 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) 571 { 572 struct nand_chip *chip = mtd_to_nand(mtd); 573 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 574 uint16_t data; 575 576 /* 577 * If there are still bytes in the IFC buffer, then use the 578 * next byte. 579 */ 580 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { 581 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index); 582 ifc_nand_ctrl->index += 2; 583 return (uint8_t) data; 584 } 585 586 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); 587 return ERR_BYTE; 588 } 589 590 /* 591 * Read from the IFC Controller Data Buffer 592 */ 593 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) 594 { 595 struct nand_chip *chip = mtd_to_nand(mtd); 596 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 597 int avail; 598 599 if (len < 0) { 600 dev_err(priv->dev, "%s: len %d bytes", __func__, len); 601 return; 602 } 603 604 avail = min((unsigned int)len, 605 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index); 606 memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail); 607 ifc_nand_ctrl->index += avail; 608 609 if (len > avail) 610 dev_err(priv->dev, 611 "%s: beyond end of buffer (%d requested, %d available)\n", 612 __func__, len, avail); 613 } 614 615 /* 616 * This function is called after Program and Erase Operations to 617 * check for success or failure. 618 */ 619 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) 620 { 621 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 622 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 623 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; 624 u32 nand_fsr; 625 int status; 626 627 /* Use READ_STATUS command, but wait for the device to be ready */ 628 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 629 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT), 630 &ifc->ifc_nand.nand_fir0); 631 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, 632 &ifc->ifc_nand.nand_fcr0); 633 ifc_out32(1, &ifc->ifc_nand.nand_fbcr); 634 set_addr(mtd, 0, 0, 0); 635 ifc_nand_ctrl->read_bytes = 1; 636 637 fsl_ifc_run_command(mtd); 638 639 nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); 640 status = nand_fsr >> 24; 641 /* 642 * The chip always seems to report that it is 643 * write-protected, even when it is not. 644 */ 645 return status | NAND_STATUS_WP; 646 } 647 648 /* 649 * The controller does not check for bitflips in erased pages, 650 * therefore software must check instead. 651 */ 652 static int check_erased_page(struct nand_chip *chip, u8 *buf) 653 { 654 struct mtd_info *mtd = nand_to_mtd(chip); 655 u8 *ecc = chip->oob_poi; 656 const int ecc_size = chip->ecc.bytes; 657 const int pkt_size = chip->ecc.size; 658 int i, res, bitflips = 0; 659 struct mtd_oob_region oobregion = { }; 660 661 mtd_ooblayout_ecc(mtd, 0, &oobregion); 662 ecc += oobregion.offset; 663 664 for (i = 0; i < chip->ecc.steps; ++i) { 665 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, 666 NULL, 0, 667 chip->ecc.strength); 668 if (res < 0) 669 mtd->ecc_stats.failed++; 670 else 671 mtd->ecc_stats.corrected += res; 672 673 bitflips = max(res, bitflips); 674 buf += pkt_size; 675 ecc += ecc_size; 676 } 677 678 return bitflips; 679 } 680 681 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, 682 uint8_t *buf, int oob_required, int page) 683 { 684 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 685 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 686 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; 687 688 nand_read_page_op(chip, page, 0, buf, mtd->writesize); 689 if (oob_required) 690 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); 691 692 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) { 693 if (!oob_required) 694 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); 695 696 return check_erased_page(chip, buf); 697 } 698 699 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) 700 mtd->ecc_stats.failed++; 701 702 return nctrl->max_bitflips; 703 } 704 705 /* ECC will be calculated automatically, and errors will be detected in 706 * waitfunc. 707 */ 708 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip, 709 const uint8_t *buf, int oob_required, int page) 710 { 711 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); 712 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize); 713 714 return nand_prog_page_end_op(chip); 715 } 716 717 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd) 718 { 719 struct nand_chip *chip = mtd_to_nand(mtd); 720 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); 721 722 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__, 723 chip->numchips); 724 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__, 725 chip->chipsize); 726 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__, 727 chip->pagemask); 728 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__, 729 chip->chip_delay); 730 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__, 731 chip->badblockpos); 732 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__, 733 chip->chip_shift); 734 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__, 735 chip->page_shift); 736 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__, 737 chip->phys_erase_shift); 738 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__, 739 chip->ecc.mode); 740 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__, 741 chip->ecc.steps); 742 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__, 743 chip->ecc.bytes); 744 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__, 745 chip->ecc.total); 746 dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__, 747 mtd->ooblayout); 748 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags); 749 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size); 750 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__, 751 mtd->erasesize); 752 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__, 753 mtd->writesize); 754 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__, 755 mtd->oobsize); 756 757 return 0; 758 } 759 760 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) 761 { 762 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 763 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; 764 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs; 765 uint32_t csor = 0, csor_8k = 0, csor_ext = 0; 766 uint32_t cs = priv->bank; 767 768 /* Save CSOR and CSOR_ext */ 769 csor = ifc_in32(&ifc_global->csor_cs[cs].csor); 770 csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext); 771 772 /* chage PageSize 8K and SpareSize 1K*/ 773 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; 774 ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor); 775 ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext); 776 777 /* READID */ 778 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 779 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | 780 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT), 781 &ifc_runtime->ifc_nand.nand_fir0); 782 ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT, 783 &ifc_runtime->ifc_nand.nand_fcr0); 784 ifc_out32(0x0, &ifc_runtime->ifc_nand.row3); 785 786 ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr); 787 788 /* Program ROW0/COL0 */ 789 ifc_out32(0x0, &ifc_runtime->ifc_nand.row0); 790 ifc_out32(0x0, &ifc_runtime->ifc_nand.col0); 791 792 /* set the chip select for NAND Transaction */ 793 ifc_out32(cs << IFC_NAND_CSEL_SHIFT, 794 &ifc_runtime->ifc_nand.nand_csel); 795 796 /* start read seq */ 797 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, 798 &ifc_runtime->ifc_nand.nandseq_strt); 799 800 /* wait for command complete flag or timeout */ 801 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, 802 msecs_to_jiffies(IFC_TIMEOUT_MSECS)); 803 804 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) 805 pr_err("fsl-ifc: Failed to Initialise SRAM\n"); 806 807 /* Restore CSOR and CSOR_ext */ 808 ifc_out32(csor, &ifc_global->csor_cs[cs].csor); 809 ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext); 810 } 811 812 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) 813 { 814 struct fsl_ifc_ctrl *ctrl = priv->ctrl; 815 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs; 816 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; 817 struct nand_chip *chip = &priv->chip; 818 struct mtd_info *mtd = nand_to_mtd(&priv->chip); 819 u32 csor; 820 821 /* Fill in fsl_ifc_mtd structure */ 822 mtd->dev.parent = priv->dev; 823 nand_set_flash_node(chip, priv->dev->of_node); 824 825 /* fill in nand_chip structure */ 826 /* set up function call table */ 827 if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)) 828 & CSPR_PORT_SIZE_16) 829 chip->read_byte = fsl_ifc_read_byte16; 830 else 831 chip->read_byte = fsl_ifc_read_byte; 832 833 chip->write_buf = fsl_ifc_write_buf; 834 chip->read_buf = fsl_ifc_read_buf; 835 chip->select_chip = fsl_ifc_select_chip; 836 chip->cmdfunc = fsl_ifc_cmdfunc; 837 chip->waitfunc = fsl_ifc_wait; 838 chip->set_features = nand_get_set_features_notsupp; 839 chip->get_features = nand_get_set_features_notsupp; 840 841 chip->bbt_td = &bbt_main_descr; 842 chip->bbt_md = &bbt_mirror_descr; 843 844 ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr); 845 846 /* set up nand options */ 847 chip->bbt_options = NAND_BBT_USE_FLASH; 848 chip->options = NAND_NO_SUBPAGE_WRITE; 849 850 if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr) 851 & CSPR_PORT_SIZE_16) { 852 chip->read_byte = fsl_ifc_read_byte16; 853 chip->options |= NAND_BUSWIDTH_16; 854 } else { 855 chip->read_byte = fsl_ifc_read_byte; 856 } 857 858 chip->controller = &ifc_nand_ctrl->controller; 859 nand_set_controller_data(chip, priv); 860 861 chip->ecc.read_page = fsl_ifc_read_page; 862 chip->ecc.write_page = fsl_ifc_write_page; 863 864 csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor); 865 866 switch (csor & CSOR_NAND_PGS_MASK) { 867 case CSOR_NAND_PGS_512: 868 if (!(chip->options & NAND_BUSWIDTH_16)) { 869 /* Avoid conflict with bad block marker */ 870 bbt_main_descr.offs = 0; 871 bbt_mirror_descr.offs = 0; 872 } 873 874 priv->bufnum_mask = 15; 875 break; 876 877 case CSOR_NAND_PGS_2K: 878 priv->bufnum_mask = 3; 879 break; 880 881 case CSOR_NAND_PGS_4K: 882 priv->bufnum_mask = 1; 883 break; 884 885 case CSOR_NAND_PGS_8K: 886 priv->bufnum_mask = 0; 887 break; 888 889 default: 890 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor); 891 return -ENODEV; 892 } 893 894 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */ 895 if (csor & CSOR_NAND_ECC_DEC_EN) { 896 chip->ecc.mode = NAND_ECC_HW; 897 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops); 898 899 /* Hardware generates ECC per 512 Bytes */ 900 chip->ecc.size = 512; 901 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) { 902 chip->ecc.bytes = 8; 903 chip->ecc.strength = 4; 904 } else { 905 chip->ecc.bytes = 16; 906 chip->ecc.strength = 8; 907 } 908 } else { 909 chip->ecc.mode = NAND_ECC_SOFT; 910 chip->ecc.algo = NAND_ECC_HAMMING; 911 } 912 913 if (ctrl->version >= FSL_IFC_VERSION_1_1_0) 914 fsl_ifc_sram_init(priv); 915 916 /* 917 * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older 918 * versions which had 8KB. Hence bufnum mask needs to be updated. 919 */ 920 if (ctrl->version >= FSL_IFC_VERSION_2_0_0) 921 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1; 922 923 return 0; 924 } 925 926 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv) 927 { 928 struct mtd_info *mtd = nand_to_mtd(&priv->chip); 929 930 kfree(mtd->name); 931 932 if (priv->vbase) 933 iounmap(priv->vbase); 934 935 ifc_nand_ctrl->chips[priv->bank] = NULL; 936 937 return 0; 938 } 939 940 static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank, 941 phys_addr_t addr) 942 { 943 u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr); 944 945 if (!(cspr & CSPR_V)) 946 return 0; 947 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND) 948 return 0; 949 950 return (cspr & CSPR_BA) == convert_ifc_address(addr); 951 } 952 953 static DEFINE_MUTEX(fsl_ifc_nand_mutex); 954 955 static int fsl_ifc_nand_probe(struct platform_device *dev) 956 { 957 struct fsl_ifc_runtime __iomem *ifc; 958 struct fsl_ifc_mtd *priv; 959 struct resource res; 960 static const char *part_probe_types[] 961 = { "cmdlinepart", "RedBoot", "ofpart", NULL }; 962 int ret; 963 int bank; 964 struct device_node *node = dev->dev.of_node; 965 struct mtd_info *mtd; 966 967 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs) 968 return -ENODEV; 969 ifc = fsl_ifc_ctrl_dev->rregs; 970 971 /* get, allocate and map the memory resource */ 972 ret = of_address_to_resource(node, 0, &res); 973 if (ret) { 974 dev_err(&dev->dev, "%s: failed to get resource\n", __func__); 975 return ret; 976 } 977 978 /* find which chip select it is connected to */ 979 for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) { 980 if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start)) 981 break; 982 } 983 984 if (bank >= fsl_ifc_ctrl_dev->banks) { 985 dev_err(&dev->dev, "%s: address did not match any chip selects\n", 986 __func__); 987 return -ENODEV; 988 } 989 990 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 991 if (!priv) 992 return -ENOMEM; 993 994 mutex_lock(&fsl_ifc_nand_mutex); 995 if (!fsl_ifc_ctrl_dev->nand) { 996 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL); 997 if (!ifc_nand_ctrl) { 998 mutex_unlock(&fsl_ifc_nand_mutex); 999 return -ENOMEM; 1000 } 1001 1002 ifc_nand_ctrl->read_bytes = 0; 1003 ifc_nand_ctrl->index = 0; 1004 ifc_nand_ctrl->addr = NULL; 1005 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl; 1006 1007 nand_hw_control_init(&ifc_nand_ctrl->controller); 1008 } else { 1009 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand; 1010 } 1011 mutex_unlock(&fsl_ifc_nand_mutex); 1012 1013 ifc_nand_ctrl->chips[bank] = priv; 1014 priv->bank = bank; 1015 priv->ctrl = fsl_ifc_ctrl_dev; 1016 priv->dev = &dev->dev; 1017 1018 priv->vbase = ioremap(res.start, resource_size(&res)); 1019 if (!priv->vbase) { 1020 dev_err(priv->dev, "%s: failed to map chip region\n", __func__); 1021 ret = -ENOMEM; 1022 goto err; 1023 } 1024 1025 dev_set_drvdata(priv->dev, priv); 1026 1027 ifc_out32(IFC_NAND_EVTER_EN_OPC_EN | 1028 IFC_NAND_EVTER_EN_FTOER_EN | 1029 IFC_NAND_EVTER_EN_WPER_EN, 1030 &ifc->ifc_nand.nand_evter_en); 1031 1032 /* enable NAND Machine Interrupts */ 1033 ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN | 1034 IFC_NAND_EVTER_INTR_FTOERIR_EN | 1035 IFC_NAND_EVTER_INTR_WPERIR_EN, 1036 &ifc->ifc_nand.nand_evter_intr_en); 1037 1038 mtd = nand_to_mtd(&priv->chip); 1039 mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start); 1040 if (!mtd->name) { 1041 ret = -ENOMEM; 1042 goto err; 1043 } 1044 1045 ret = fsl_ifc_chip_init(priv); 1046 if (ret) 1047 goto err; 1048 1049 ret = nand_scan_ident(mtd, 1, NULL); 1050 if (ret) 1051 goto err; 1052 1053 ret = fsl_ifc_chip_init_tail(mtd); 1054 if (ret) 1055 goto err; 1056 1057 ret = nand_scan_tail(mtd); 1058 if (ret) 1059 goto err; 1060 1061 /* First look for RedBoot table or partitions on the command 1062 * line, these take precedence over device tree information */ 1063 ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0); 1064 if (ret) 1065 goto cleanup_nand; 1066 1067 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n", 1068 (unsigned long long)res.start, priv->bank); 1069 1070 return 0; 1071 1072 cleanup_nand: 1073 nand_cleanup(&priv->chip); 1074 err: 1075 fsl_ifc_chip_remove(priv); 1076 1077 return ret; 1078 } 1079 1080 static int fsl_ifc_nand_remove(struct platform_device *dev) 1081 { 1082 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev); 1083 struct mtd_info *mtd = nand_to_mtd(&priv->chip); 1084 1085 nand_release(mtd); 1086 fsl_ifc_chip_remove(priv); 1087 1088 mutex_lock(&fsl_ifc_nand_mutex); 1089 ifc_nand_ctrl->counter--; 1090 if (!ifc_nand_ctrl->counter) { 1091 fsl_ifc_ctrl_dev->nand = NULL; 1092 kfree(ifc_nand_ctrl); 1093 } 1094 mutex_unlock(&fsl_ifc_nand_mutex); 1095 1096 return 0; 1097 } 1098 1099 static const struct of_device_id fsl_ifc_nand_match[] = { 1100 { 1101 .compatible = "fsl,ifc-nand", 1102 }, 1103 {} 1104 }; 1105 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match); 1106 1107 static struct platform_driver fsl_ifc_nand_driver = { 1108 .driver = { 1109 .name = "fsl,ifc-nand", 1110 .of_match_table = fsl_ifc_nand_match, 1111 }, 1112 .probe = fsl_ifc_nand_probe, 1113 .remove = fsl_ifc_nand_remove, 1114 }; 1115 1116 module_platform_driver(fsl_ifc_nand_driver); 1117 1118 MODULE_LICENSE("GPL"); 1119 MODULE_AUTHOR("Freescale"); 1120 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver"); 1121