1 /* Freescale Enhanced Local Bus Controller NAND driver
2  *
3  * Copyright © 2006-2007, 2010 Freescale Semiconductor
4  *
5  * Authors: Nick Spence <nick.spence@freescale.com>,
6  *          Scott Wood <scottwood@freescale.com>
7  *          Jack Lan <jack.lan@freescale.com>
8  *          Roy Zang <tie-fei.zang@freescale.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
23  */
24 
25 #include <linux/module.h>
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/string.h>
29 #include <linux/ioport.h>
30 #include <linux/of_address.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/rawnand.h>
38 #include <linux/mtd/nand_ecc.h>
39 #include <linux/mtd/partitions.h>
40 
41 #include <asm/io.h>
42 #include <asm/fsl_lbc.h>
43 
44 #define MAX_BANKS 8
45 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
46 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
47 
48 /* mtd information per set */
49 
50 struct fsl_elbc_mtd {
51 	struct nand_chip chip;
52 	struct fsl_lbc_ctrl *ctrl;
53 
54 	struct device *dev;
55 	int bank;               /* Chip select bank number           */
56 	u8 __iomem *vbase;      /* Chip select base virtual address  */
57 	int page_size;          /* NAND page size (0=512, 1=2048)    */
58 	unsigned int fmr;       /* FCM Flash Mode Register value     */
59 };
60 
61 /* Freescale eLBC FCM controller information */
62 
63 struct fsl_elbc_fcm_ctrl {
64 	struct nand_controller controller;
65 	struct fsl_elbc_mtd *chips[MAX_BANKS];
66 
67 	u8 __iomem *addr;        /* Address of assigned FCM buffer        */
68 	unsigned int page;       /* Last page written to / read from      */
69 	unsigned int read_bytes; /* Number of bytes read during command   */
70 	unsigned int column;     /* Saved column from SEQIN               */
71 	unsigned int index;      /* Pointer to next byte to 'read'        */
72 	unsigned int status;     /* status read from LTESR after last op  */
73 	unsigned int mdr;        /* UPM/FCM Data Register value           */
74 	unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
75 	unsigned int oob;        /* Non zero if operating on OOB data     */
76 	unsigned int counter;	 /* counter for the initializations	  */
77 	unsigned int max_bitflips;  /* Saved during READ0 cmd		  */
78 };
79 
80 /* These map to the positions used by the FCM hardware ECC generator */
81 
82 static int fsl_elbc_ooblayout_ecc(struct mtd_info *mtd, int section,
83 				  struct mtd_oob_region *oobregion)
84 {
85 	struct nand_chip *chip = mtd_to_nand(mtd);
86 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
87 
88 	if (section >= chip->ecc.steps)
89 		return -ERANGE;
90 
91 	oobregion->offset = (16 * section) + 6;
92 	if (priv->fmr & FMR_ECCM)
93 		oobregion->offset += 2;
94 
95 	oobregion->length = chip->ecc.bytes;
96 
97 	return 0;
98 }
99 
100 static int fsl_elbc_ooblayout_free(struct mtd_info *mtd, int section,
101 				   struct mtd_oob_region *oobregion)
102 {
103 	struct nand_chip *chip = mtd_to_nand(mtd);
104 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
105 
106 	if (section > chip->ecc.steps)
107 		return -ERANGE;
108 
109 	if (!section) {
110 		oobregion->offset = 0;
111 		if (mtd->writesize > 512)
112 			oobregion->offset++;
113 		oobregion->length = (priv->fmr & FMR_ECCM) ? 7 : 5;
114 	} else {
115 		oobregion->offset = (16 * section) -
116 				    ((priv->fmr & FMR_ECCM) ? 5 : 7);
117 		if (section < chip->ecc.steps)
118 			oobregion->length = 13;
119 		else
120 			oobregion->length = mtd->oobsize - oobregion->offset;
121 	}
122 
123 	return 0;
124 }
125 
126 static const struct mtd_ooblayout_ops fsl_elbc_ooblayout_ops = {
127 	.ecc = fsl_elbc_ooblayout_ecc,
128 	.free = fsl_elbc_ooblayout_free,
129 };
130 
131 /*
132  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
133  * interfere with ECC positions, that's why we implement our own descriptors.
134  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
135  */
136 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
137 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
138 
139 static struct nand_bbt_descr bbt_main_descr = {
140 	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
141 		   NAND_BBT_2BIT | NAND_BBT_VERSION,
142 	.offs =	11,
143 	.len = 4,
144 	.veroffs = 15,
145 	.maxblocks = 4,
146 	.pattern = bbt_pattern,
147 };
148 
149 static struct nand_bbt_descr bbt_mirror_descr = {
150 	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
151 		   NAND_BBT_2BIT | NAND_BBT_VERSION,
152 	.offs =	11,
153 	.len = 4,
154 	.veroffs = 15,
155 	.maxblocks = 4,
156 	.pattern = mirror_pattern,
157 };
158 
159 /*=================================*/
160 
161 /*
162  * Set up the FCM hardware block and page address fields, and the fcm
163  * structure addr field to point to the correct FCM buffer in memory
164  */
165 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
166 {
167 	struct nand_chip *chip = mtd_to_nand(mtd);
168 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
169 	struct fsl_lbc_ctrl *ctrl = priv->ctrl;
170 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
171 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
172 	int buf_num;
173 
174 	elbc_fcm_ctrl->page = page_addr;
175 
176 	if (priv->page_size) {
177 		/*
178 		 * large page size chip : FPAR[PI] save the lowest 6 bits,
179 		 *                        FBAR[BLK] save the other bits.
180 		 */
181 		out_be32(&lbc->fbar, page_addr >> 6);
182 		out_be32(&lbc->fpar,
183 		         ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
184 		         (oob ? FPAR_LP_MS : 0) | column);
185 		buf_num = (page_addr & 1) << 2;
186 	} else {
187 		/*
188 		 * small page size chip : FPAR[PI] save the lowest 5 bits,
189 		 *                        FBAR[BLK] save the other bits.
190 		 */
191 		out_be32(&lbc->fbar, page_addr >> 5);
192 		out_be32(&lbc->fpar,
193 		         ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
194 		         (oob ? FPAR_SP_MS : 0) | column);
195 		buf_num = page_addr & 7;
196 	}
197 
198 	elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
199 	elbc_fcm_ctrl->index = column;
200 
201 	/* for OOB data point to the second half of the buffer */
202 	if (oob)
203 		elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
204 
205 	dev_vdbg(priv->dev, "set_addr: bank=%d, "
206 			    "elbc_fcm_ctrl->addr=0x%p (0x%p), "
207 	                    "index %x, pes %d ps %d\n",
208 		 buf_num, elbc_fcm_ctrl->addr, priv->vbase,
209 		 elbc_fcm_ctrl->index,
210 	         chip->phys_erase_shift, chip->page_shift);
211 }
212 
213 /*
214  * execute FCM command and wait for it to complete
215  */
216 static int fsl_elbc_run_command(struct mtd_info *mtd)
217 {
218 	struct nand_chip *chip = mtd_to_nand(mtd);
219 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
220 	struct fsl_lbc_ctrl *ctrl = priv->ctrl;
221 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
222 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
223 
224 	/* Setup the FMR[OP] to execute without write protection */
225 	out_be32(&lbc->fmr, priv->fmr | 3);
226 	if (elbc_fcm_ctrl->use_mdr)
227 		out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
228 
229 	dev_vdbg(priv->dev,
230 	         "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
231 	         in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
232 	dev_vdbg(priv->dev,
233 	         "fsl_elbc_run_command: fbar=%08x fpar=%08x "
234 	         "fbcr=%08x bank=%d\n",
235 	         in_be32(&lbc->fbar), in_be32(&lbc->fpar),
236 	         in_be32(&lbc->fbcr), priv->bank);
237 
238 	ctrl->irq_status = 0;
239 	/* execute special operation */
240 	out_be32(&lbc->lsor, priv->bank);
241 
242 	/* wait for FCM complete flag or timeout */
243 	wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
244 	                   FCM_TIMEOUT_MSECS * HZ/1000);
245 	elbc_fcm_ctrl->status = ctrl->irq_status;
246 	/* store mdr value in case it was needed */
247 	if (elbc_fcm_ctrl->use_mdr)
248 		elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
249 
250 	elbc_fcm_ctrl->use_mdr = 0;
251 
252 	if (elbc_fcm_ctrl->status != LTESR_CC) {
253 		dev_info(priv->dev,
254 		         "command failed: fir %x fcr %x status %x mdr %x\n",
255 		         in_be32(&lbc->fir), in_be32(&lbc->fcr),
256 			 elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
257 		return -EIO;
258 	}
259 
260 	if (chip->ecc.mode != NAND_ECC_HW)
261 		return 0;
262 
263 	elbc_fcm_ctrl->max_bitflips = 0;
264 
265 	if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
266 		uint32_t lteccr = in_be32(&lbc->lteccr);
267 		/*
268 		 * if command was a full page read and the ELBC
269 		 * has the LTECCR register, then bits 12-15 (ppc order) of
270 		 * LTECCR indicates which 512 byte sub-pages had fixed errors.
271 		 * bits 28-31 are uncorrectable errors, marked elsewhere.
272 		 * for small page nand only 1 bit is used.
273 		 * if the ELBC doesn't have the lteccr register it reads 0
274 		 * FIXME: 4 bits can be corrected on NANDs with 2k pages, so
275 		 * count the number of sub-pages with bitflips and update
276 		 * ecc_stats.corrected accordingly.
277 		 */
278 		if (lteccr & 0x000F000F)
279 			out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
280 		if (lteccr & 0x000F0000) {
281 			mtd->ecc_stats.corrected++;
282 			elbc_fcm_ctrl->max_bitflips = 1;
283 		}
284 	}
285 
286 	return 0;
287 }
288 
289 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
290 {
291 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
292 	struct fsl_lbc_ctrl *ctrl = priv->ctrl;
293 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
294 
295 	if (priv->page_size) {
296 		out_be32(&lbc->fir,
297 		         (FIR_OP_CM0 << FIR_OP0_SHIFT) |
298 		         (FIR_OP_CA  << FIR_OP1_SHIFT) |
299 		         (FIR_OP_PA  << FIR_OP2_SHIFT) |
300 		         (FIR_OP_CM1 << FIR_OP3_SHIFT) |
301 		         (FIR_OP_RBW << FIR_OP4_SHIFT));
302 
303 		out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
304 		                    (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
305 	} else {
306 		out_be32(&lbc->fir,
307 		         (FIR_OP_CM0 << FIR_OP0_SHIFT) |
308 		         (FIR_OP_CA  << FIR_OP1_SHIFT) |
309 		         (FIR_OP_PA  << FIR_OP2_SHIFT) |
310 		         (FIR_OP_RBW << FIR_OP3_SHIFT));
311 
312 		if (oob)
313 			out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
314 		else
315 			out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
316 	}
317 }
318 
319 /* cmdfunc send commands to the FCM */
320 static void fsl_elbc_cmdfunc(struct nand_chip *chip, unsigned int command,
321                              int column, int page_addr)
322 {
323 	struct mtd_info *mtd = nand_to_mtd(chip);
324 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
325 	struct fsl_lbc_ctrl *ctrl = priv->ctrl;
326 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
327 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
328 
329 	elbc_fcm_ctrl->use_mdr = 0;
330 
331 	/* clear the read buffer */
332 	elbc_fcm_ctrl->read_bytes = 0;
333 	if (command != NAND_CMD_PAGEPROG)
334 		elbc_fcm_ctrl->index = 0;
335 
336 	switch (command) {
337 	/* READ0 and READ1 read the entire buffer to use hardware ECC. */
338 	case NAND_CMD_READ1:
339 		column += 256;
340 
341 	/* fall-through */
342 	case NAND_CMD_READ0:
343 		dev_dbg(priv->dev,
344 		        "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
345 		        " 0x%x, column: 0x%x.\n", page_addr, column);
346 
347 
348 		out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
349 		set_addr(mtd, 0, page_addr, 0);
350 
351 		elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
352 		elbc_fcm_ctrl->index += column;
353 
354 		fsl_elbc_do_read(chip, 0);
355 		fsl_elbc_run_command(mtd);
356 		return;
357 
358 	/* RNDOUT moves the pointer inside the page */
359 	case NAND_CMD_RNDOUT:
360 		dev_dbg(priv->dev,
361 			"fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n",
362 			column);
363 
364 		elbc_fcm_ctrl->index = column;
365 		return;
366 
367 	/* READOOB reads only the OOB because no ECC is performed. */
368 	case NAND_CMD_READOOB:
369 		dev_vdbg(priv->dev,
370 		         "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
371 			 " 0x%x, column: 0x%x.\n", page_addr, column);
372 
373 		out_be32(&lbc->fbcr, mtd->oobsize - column);
374 		set_addr(mtd, column, page_addr, 1);
375 
376 		elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
377 
378 		fsl_elbc_do_read(chip, 1);
379 		fsl_elbc_run_command(mtd);
380 		return;
381 
382 	case NAND_CMD_READID:
383 	case NAND_CMD_PARAM:
384 		dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
385 
386 		out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
387 		                    (FIR_OP_UA  << FIR_OP1_SHIFT) |
388 		                    (FIR_OP_RBW << FIR_OP2_SHIFT));
389 		out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
390 		/*
391 		 * although currently it's 8 bytes for READID, we always read
392 		 * the maximum 256 bytes(for PARAM)
393 		 */
394 		out_be32(&lbc->fbcr, 256);
395 		elbc_fcm_ctrl->read_bytes = 256;
396 		elbc_fcm_ctrl->use_mdr = 1;
397 		elbc_fcm_ctrl->mdr = column;
398 		set_addr(mtd, 0, 0, 0);
399 		fsl_elbc_run_command(mtd);
400 		return;
401 
402 	/* ERASE1 stores the block and page address */
403 	case NAND_CMD_ERASE1:
404 		dev_vdbg(priv->dev,
405 		         "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
406 		         "page_addr: 0x%x.\n", page_addr);
407 		set_addr(mtd, 0, page_addr, 0);
408 		return;
409 
410 	/* ERASE2 uses the block and page address from ERASE1 */
411 	case NAND_CMD_ERASE2:
412 		dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
413 
414 		out_be32(&lbc->fir,
415 		         (FIR_OP_CM0 << FIR_OP0_SHIFT) |
416 		         (FIR_OP_PA  << FIR_OP1_SHIFT) |
417 		         (FIR_OP_CM2 << FIR_OP2_SHIFT) |
418 		         (FIR_OP_CW1 << FIR_OP3_SHIFT) |
419 		         (FIR_OP_RS  << FIR_OP4_SHIFT));
420 
421 		out_be32(&lbc->fcr,
422 		         (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
423 		         (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
424 		         (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
425 
426 		out_be32(&lbc->fbcr, 0);
427 		elbc_fcm_ctrl->read_bytes = 0;
428 		elbc_fcm_ctrl->use_mdr = 1;
429 
430 		fsl_elbc_run_command(mtd);
431 		return;
432 
433 	/* SEQIN sets up the addr buffer and all registers except the length */
434 	case NAND_CMD_SEQIN: {
435 		__be32 fcr;
436 		dev_vdbg(priv->dev,
437 			 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
438 		         "page_addr: 0x%x, column: 0x%x.\n",
439 		         page_addr, column);
440 
441 		elbc_fcm_ctrl->column = column;
442 		elbc_fcm_ctrl->use_mdr = 1;
443 
444 		if (column >= mtd->writesize) {
445 			/* OOB area */
446 			column -= mtd->writesize;
447 			elbc_fcm_ctrl->oob = 1;
448 		} else {
449 			WARN_ON(column != 0);
450 			elbc_fcm_ctrl->oob = 0;
451 		}
452 
453 		fcr = (NAND_CMD_STATUS   << FCR_CMD1_SHIFT) |
454 		      (NAND_CMD_SEQIN    << FCR_CMD2_SHIFT) |
455 		      (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
456 
457 		if (priv->page_size) {
458 			out_be32(&lbc->fir,
459 			         (FIR_OP_CM2 << FIR_OP0_SHIFT) |
460 			         (FIR_OP_CA  << FIR_OP1_SHIFT) |
461 			         (FIR_OP_PA  << FIR_OP2_SHIFT) |
462 			         (FIR_OP_WB  << FIR_OP3_SHIFT) |
463 			         (FIR_OP_CM3 << FIR_OP4_SHIFT) |
464 			         (FIR_OP_CW1 << FIR_OP5_SHIFT) |
465 			         (FIR_OP_RS  << FIR_OP6_SHIFT));
466 		} else {
467 			out_be32(&lbc->fir,
468 			         (FIR_OP_CM0 << FIR_OP0_SHIFT) |
469 			         (FIR_OP_CM2 << FIR_OP1_SHIFT) |
470 			         (FIR_OP_CA  << FIR_OP2_SHIFT) |
471 			         (FIR_OP_PA  << FIR_OP3_SHIFT) |
472 			         (FIR_OP_WB  << FIR_OP4_SHIFT) |
473 			         (FIR_OP_CM3 << FIR_OP5_SHIFT) |
474 			         (FIR_OP_CW1 << FIR_OP6_SHIFT) |
475 			         (FIR_OP_RS  << FIR_OP7_SHIFT));
476 
477 			if (elbc_fcm_ctrl->oob)
478 				/* OOB area --> READOOB */
479 				fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
480 			else
481 				/* First 256 bytes --> READ0 */
482 				fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
483 		}
484 
485 		out_be32(&lbc->fcr, fcr);
486 		set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
487 		return;
488 	}
489 
490 	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
491 	case NAND_CMD_PAGEPROG: {
492 		dev_vdbg(priv->dev,
493 		         "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
494 			 "writing %d bytes.\n", elbc_fcm_ctrl->index);
495 
496 		/* if the write did not start at 0 or is not a full page
497 		 * then set the exact length, otherwise use a full page
498 		 * write so the HW generates the ECC.
499 		 */
500 		if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
501 		    elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
502 			out_be32(&lbc->fbcr,
503 				elbc_fcm_ctrl->index - elbc_fcm_ctrl->column);
504 		else
505 			out_be32(&lbc->fbcr, 0);
506 
507 		fsl_elbc_run_command(mtd);
508 		return;
509 	}
510 
511 	/* CMD_STATUS must read the status byte while CEB is active */
512 	/* Note - it does not wait for the ready line */
513 	case NAND_CMD_STATUS:
514 		out_be32(&lbc->fir,
515 		         (FIR_OP_CM0 << FIR_OP0_SHIFT) |
516 		         (FIR_OP_RBW << FIR_OP1_SHIFT));
517 		out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
518 		out_be32(&lbc->fbcr, 1);
519 		set_addr(mtd, 0, 0, 0);
520 		elbc_fcm_ctrl->read_bytes = 1;
521 
522 		fsl_elbc_run_command(mtd);
523 
524 		/* The chip always seems to report that it is
525 		 * write-protected, even when it is not.
526 		 */
527 		setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
528 		return;
529 
530 	/* RESET without waiting for the ready line */
531 	case NAND_CMD_RESET:
532 		dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
533 		out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
534 		out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
535 		fsl_elbc_run_command(mtd);
536 		return;
537 
538 	default:
539 		dev_err(priv->dev,
540 		        "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
541 		        command);
542 	}
543 }
544 
545 static void fsl_elbc_select_chip(struct nand_chip *chip, int cs)
546 {
547 	/* The hardware does not seem to support multiple
548 	 * chips per bank.
549 	 */
550 }
551 
552 /*
553  * Write buf to the FCM Controller Data Buffer
554  */
555 static void fsl_elbc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
556 {
557 	struct mtd_info *mtd = nand_to_mtd(chip);
558 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
559 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
560 	unsigned int bufsize = mtd->writesize + mtd->oobsize;
561 
562 	if (len <= 0) {
563 		dev_err(priv->dev, "write_buf of %d bytes", len);
564 		elbc_fcm_ctrl->status = 0;
565 		return;
566 	}
567 
568 	if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
569 		dev_err(priv->dev,
570 		        "write_buf beyond end of buffer "
571 		        "(%d requested, %u available)\n",
572 			len, bufsize - elbc_fcm_ctrl->index);
573 		len = bufsize - elbc_fcm_ctrl->index;
574 	}
575 
576 	memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
577 	/*
578 	 * This is workaround for the weird elbc hangs during nand write,
579 	 * Scott Wood says: "...perhaps difference in how long it takes a
580 	 * write to make it through the localbus compared to a write to IMMR
581 	 * is causing problems, and sync isn't helping for some reason."
582 	 * Reading back the last byte helps though.
583 	 */
584 	in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
585 
586 	elbc_fcm_ctrl->index += len;
587 }
588 
589 /*
590  * read a byte from either the FCM hardware buffer if it has any data left
591  * otherwise issue a command to read a single byte.
592  */
593 static u8 fsl_elbc_read_byte(struct nand_chip *chip)
594 {
595 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
596 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
597 
598 	/* If there are still bytes in the FCM, then use the next byte. */
599 	if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
600 		return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
601 
602 	dev_err(priv->dev, "read_byte beyond end of buffer\n");
603 	return ERR_BYTE;
604 }
605 
606 /*
607  * Read from the FCM Controller Data Buffer
608  */
609 static void fsl_elbc_read_buf(struct nand_chip *chip, u8 *buf, int len)
610 {
611 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
612 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
613 	int avail;
614 
615 	if (len < 0)
616 		return;
617 
618 	avail = min((unsigned int)len,
619 			elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
620 	memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
621 	elbc_fcm_ctrl->index += avail;
622 
623 	if (len > avail)
624 		dev_err(priv->dev,
625 		        "read_buf beyond end of buffer "
626 		        "(%d requested, %d available)\n",
627 		        len, avail);
628 }
629 
630 /* This function is called after Program and Erase Operations to
631  * check for success or failure.
632  */
633 static int fsl_elbc_wait(struct nand_chip *chip)
634 {
635 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
636 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
637 
638 	if (elbc_fcm_ctrl->status != LTESR_CC)
639 		return NAND_STATUS_FAIL;
640 
641 	/* The chip always seems to report that it is
642 	 * write-protected, even when it is not.
643 	 */
644 	return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
645 }
646 
647 static int fsl_elbc_read_page(struct nand_chip *chip, uint8_t *buf,
648 			      int oob_required, int page)
649 {
650 	struct mtd_info *mtd = nand_to_mtd(chip);
651 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
652 	struct fsl_lbc_ctrl *ctrl = priv->ctrl;
653 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
654 
655 	nand_read_page_op(chip, page, 0, buf, mtd->writesize);
656 	if (oob_required)
657 		fsl_elbc_read_buf(chip, chip->oob_poi, mtd->oobsize);
658 
659 	if (fsl_elbc_wait(chip) & NAND_STATUS_FAIL)
660 		mtd->ecc_stats.failed++;
661 
662 	return elbc_fcm_ctrl->max_bitflips;
663 }
664 
665 /* ECC will be calculated automatically, and errors will be detected in
666  * waitfunc.
667  */
668 static int fsl_elbc_write_page(struct nand_chip *chip, const uint8_t *buf,
669 			       int oob_required, int page)
670 {
671 	struct mtd_info *mtd = nand_to_mtd(chip);
672 
673 	nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
674 	fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize);
675 
676 	return nand_prog_page_end_op(chip);
677 }
678 
679 /* ECC will be calculated automatically, and errors will be detected in
680  * waitfunc.
681  */
682 static int fsl_elbc_write_subpage(struct nand_chip *chip, uint32_t offset,
683 				  uint32_t data_len, const uint8_t *buf,
684 				  int oob_required, int page)
685 {
686 	struct mtd_info *mtd = nand_to_mtd(chip);
687 
688 	nand_prog_page_begin_op(chip, page, 0, NULL, 0);
689 	fsl_elbc_write_buf(chip, buf, mtd->writesize);
690 	fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize);
691 	return nand_prog_page_end_op(chip);
692 }
693 
694 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
695 {
696 	struct fsl_lbc_ctrl *ctrl = priv->ctrl;
697 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
698 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
699 	struct nand_chip *chip = &priv->chip;
700 	struct mtd_info *mtd = nand_to_mtd(chip);
701 
702 	dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
703 
704 	/* Fill in fsl_elbc_mtd structure */
705 	mtd->dev.parent = priv->dev;
706 	nand_set_flash_node(chip, priv->dev->of_node);
707 
708 	/* set timeout to maximum */
709 	priv->fmr = 15 << FMR_CWTO_SHIFT;
710 	if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
711 		priv->fmr |= FMR_ECCM;
712 
713 	/* fill in nand_chip structure */
714 	/* set up function call table */
715 	chip->legacy.read_byte = fsl_elbc_read_byte;
716 	chip->legacy.write_buf = fsl_elbc_write_buf;
717 	chip->legacy.read_buf = fsl_elbc_read_buf;
718 	chip->legacy.select_chip = fsl_elbc_select_chip;
719 	chip->legacy.cmdfunc = fsl_elbc_cmdfunc;
720 	chip->legacy.waitfunc = fsl_elbc_wait;
721 	chip->legacy.set_features = nand_get_set_features_notsupp;
722 	chip->legacy.get_features = nand_get_set_features_notsupp;
723 
724 	chip->bbt_td = &bbt_main_descr;
725 	chip->bbt_md = &bbt_mirror_descr;
726 
727 	/* set up nand options */
728 	chip->bbt_options = NAND_BBT_USE_FLASH;
729 
730 	chip->controller = &elbc_fcm_ctrl->controller;
731 	nand_set_controller_data(chip, priv);
732 
733 	return 0;
734 }
735 
736 static int fsl_elbc_attach_chip(struct nand_chip *chip)
737 {
738 	struct mtd_info *mtd = nand_to_mtd(chip);
739 	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
740 	struct fsl_lbc_ctrl *ctrl = priv->ctrl;
741 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
742 	unsigned int al;
743 
744 	switch (chip->ecc.mode) {
745 	/*
746 	 * if ECC was not chosen in DT, decide whether to use HW or SW ECC from
747 	 * CS Base Register
748 	 */
749 	case NAND_ECC_NONE:
750 		/* If CS Base Register selects full hardware ECC then use it */
751 		if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
752 		    BR_DECC_CHK_GEN) {
753 			chip->ecc.read_page = fsl_elbc_read_page;
754 			chip->ecc.write_page = fsl_elbc_write_page;
755 			chip->ecc.write_subpage = fsl_elbc_write_subpage;
756 
757 			chip->ecc.mode = NAND_ECC_HW;
758 			mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops);
759 			chip->ecc.size = 512;
760 			chip->ecc.bytes = 3;
761 			chip->ecc.strength = 1;
762 		} else {
763 			/* otherwise fall back to default software ECC */
764 			chip->ecc.mode = NAND_ECC_SOFT;
765 			chip->ecc.algo = NAND_ECC_HAMMING;
766 		}
767 		break;
768 
769 	/* if SW ECC was chosen in DT, we do not need to set anything here */
770 	case NAND_ECC_SOFT:
771 		break;
772 
773 	/* should we also implement NAND_ECC_HW to do as the code above? */
774 	default:
775 		return -EINVAL;
776 	}
777 
778 	/* calculate FMR Address Length field */
779 	al = 0;
780 	if (chip->pagemask & 0xffff0000)
781 		al++;
782 	if (chip->pagemask & 0xff000000)
783 		al++;
784 
785 	priv->fmr |= al << FMR_AL_SHIFT;
786 
787 	dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
788 	        nanddev_ntargets(&chip->base));
789 	dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
790 	        nanddev_target_size(&chip->base));
791 	dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
792 	        chip->pagemask);
793 	dev_dbg(priv->dev, "fsl_elbc_init: nand->legacy.chip_delay = %d\n",
794 	        chip->legacy.chip_delay);
795 	dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
796 	        chip->badblockpos);
797 	dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
798 	        chip->chip_shift);
799 	dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
800 	        chip->page_shift);
801 	dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
802 	        chip->phys_erase_shift);
803 	dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
804 	        chip->ecc.mode);
805 	dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
806 	        chip->ecc.steps);
807 	dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
808 	        chip->ecc.bytes);
809 	dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
810 	        chip->ecc.total);
811 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->ooblayout = %p\n",
812 		mtd->ooblayout);
813 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
814 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
815 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
816 	        mtd->erasesize);
817 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
818 	        mtd->writesize);
819 	dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
820 	        mtd->oobsize);
821 
822 	/* adjust Option Register and ECC to match Flash page size */
823 	if (mtd->writesize == 512) {
824 		priv->page_size = 0;
825 		clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
826 	} else if (mtd->writesize == 2048) {
827 		priv->page_size = 1;
828 		setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
829 	} else {
830 		dev_err(priv->dev,
831 		        "fsl_elbc_init: page size %d is not supported\n",
832 		        mtd->writesize);
833 		return -ENOTSUPP;
834 	}
835 
836 	return 0;
837 }
838 
839 static const struct nand_controller_ops fsl_elbc_controller_ops = {
840 	.attach_chip = fsl_elbc_attach_chip,
841 };
842 
843 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
844 {
845 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
846 	struct mtd_info *mtd = nand_to_mtd(&priv->chip);
847 
848 	kfree(mtd->name);
849 
850 	if (priv->vbase)
851 		iounmap(priv->vbase);
852 
853 	elbc_fcm_ctrl->chips[priv->bank] = NULL;
854 	kfree(priv);
855 	return 0;
856 }
857 
858 static DEFINE_MUTEX(fsl_elbc_nand_mutex);
859 
860 static int fsl_elbc_nand_probe(struct platform_device *pdev)
861 {
862 	struct fsl_lbc_regs __iomem *lbc;
863 	struct fsl_elbc_mtd *priv;
864 	struct resource res;
865 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
866 	static const char *part_probe_types[]
867 		= { "cmdlinepart", "RedBoot", "ofpart", NULL };
868 	int ret;
869 	int bank;
870 	struct device *dev;
871 	struct device_node *node = pdev->dev.of_node;
872 	struct mtd_info *mtd;
873 
874 	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
875 		return -ENODEV;
876 	lbc = fsl_lbc_ctrl_dev->regs;
877 	dev = fsl_lbc_ctrl_dev->dev;
878 
879 	/* get, allocate and map the memory resource */
880 	ret = of_address_to_resource(node, 0, &res);
881 	if (ret) {
882 		dev_err(dev, "failed to get resource\n");
883 		return ret;
884 	}
885 
886 	/* find which chip select it is connected to */
887 	for (bank = 0; bank < MAX_BANKS; bank++)
888 		if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
889 		    (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
890 		    (in_be32(&lbc->bank[bank].br) &
891 		     in_be32(&lbc->bank[bank].or) & BR_BA)
892 		     == fsl_lbc_addr(res.start))
893 			break;
894 
895 	if (bank >= MAX_BANKS) {
896 		dev_err(dev, "address did not match any chip selects\n");
897 		return -ENODEV;
898 	}
899 
900 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
901 	if (!priv)
902 		return -ENOMEM;
903 
904 	mutex_lock(&fsl_elbc_nand_mutex);
905 	if (!fsl_lbc_ctrl_dev->nand) {
906 		elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
907 		if (!elbc_fcm_ctrl) {
908 			mutex_unlock(&fsl_elbc_nand_mutex);
909 			ret = -ENOMEM;
910 			goto err;
911 		}
912 		elbc_fcm_ctrl->counter++;
913 
914 		nand_controller_init(&elbc_fcm_ctrl->controller);
915 		fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
916 	} else {
917 		elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
918 	}
919 	mutex_unlock(&fsl_elbc_nand_mutex);
920 
921 	elbc_fcm_ctrl->chips[bank] = priv;
922 	priv->bank = bank;
923 	priv->ctrl = fsl_lbc_ctrl_dev;
924 	priv->dev = &pdev->dev;
925 	dev_set_drvdata(priv->dev, priv);
926 
927 	priv->vbase = ioremap(res.start, resource_size(&res));
928 	if (!priv->vbase) {
929 		dev_err(dev, "failed to map chip region\n");
930 		ret = -ENOMEM;
931 		goto err;
932 	}
933 
934 	mtd = nand_to_mtd(&priv->chip);
935 	mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
936 	if (!nand_to_mtd(&priv->chip)->name) {
937 		ret = -ENOMEM;
938 		goto err;
939 	}
940 
941 	ret = fsl_elbc_chip_init(priv);
942 	if (ret)
943 		goto err;
944 
945 	priv->chip.controller->ops = &fsl_elbc_controller_ops;
946 	ret = nand_scan(&priv->chip, 1);
947 	if (ret)
948 		goto err;
949 
950 	/* First look for RedBoot table or partitions on the command
951 	 * line, these take precedence over device tree information */
952 	ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
953 	if (ret)
954 		goto cleanup_nand;
955 
956 	pr_info("eLBC NAND device at 0x%llx, bank %d\n",
957 		(unsigned long long)res.start, priv->bank);
958 
959 	return 0;
960 
961 cleanup_nand:
962 	nand_cleanup(&priv->chip);
963 err:
964 	fsl_elbc_chip_remove(priv);
965 
966 	return ret;
967 }
968 
969 static int fsl_elbc_nand_remove(struct platform_device *pdev)
970 {
971 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
972 	struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev);
973 
974 	nand_release(&priv->chip);
975 	fsl_elbc_chip_remove(priv);
976 
977 	mutex_lock(&fsl_elbc_nand_mutex);
978 	elbc_fcm_ctrl->counter--;
979 	if (!elbc_fcm_ctrl->counter) {
980 		fsl_lbc_ctrl_dev->nand = NULL;
981 		kfree(elbc_fcm_ctrl);
982 	}
983 	mutex_unlock(&fsl_elbc_nand_mutex);
984 
985 	return 0;
986 
987 }
988 
989 static const struct of_device_id fsl_elbc_nand_match[] = {
990 	{ .compatible = "fsl,elbc-fcm-nand", },
991 	{}
992 };
993 MODULE_DEVICE_TABLE(of, fsl_elbc_nand_match);
994 
995 static struct platform_driver fsl_elbc_nand_driver = {
996 	.driver = {
997 		.name = "fsl,elbc-fcm-nand",
998 		.of_match_table = fsl_elbc_nand_match,
999 	},
1000 	.probe = fsl_elbc_nand_probe,
1001 	.remove = fsl_elbc_nand_remove,
1002 };
1003 
1004 module_platform_driver(fsl_elbc_nand_driver);
1005 
1006 MODULE_LICENSE("GPL");
1007 MODULE_AUTHOR("Freescale");
1008 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
1009