1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NAND Flash Controller Device Driver for DT 4 * 5 * Copyright © 2011, Picochip. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/ioport.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 18 #include "denali.h" 19 20 struct denali_dt { 21 struct denali_controller controller; 22 struct clk *clk; /* core clock */ 23 struct clk *clk_x; /* bus interface clock */ 24 struct clk *clk_ecc; /* ECC circuit clock */ 25 }; 26 27 struct denali_dt_data { 28 unsigned int revision; 29 unsigned int caps; 30 const struct nand_ecc_caps *ecc_caps; 31 }; 32 33 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes, 34 512, 8, 15); 35 static const struct denali_dt_data denali_socfpga_data = { 36 .caps = DENALI_CAP_HW_ECC_FIXUP, 37 .ecc_caps = &denali_socfpga_ecc_caps, 38 }; 39 40 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes, 41 1024, 8, 16, 24); 42 static const struct denali_dt_data denali_uniphier_v5a_data = { 43 .caps = DENALI_CAP_HW_ECC_FIXUP | 44 DENALI_CAP_DMA_64BIT, 45 .ecc_caps = &denali_uniphier_v5a_ecc_caps, 46 }; 47 48 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes, 49 1024, 8, 16); 50 static const struct denali_dt_data denali_uniphier_v5b_data = { 51 .revision = 0x0501, 52 .caps = DENALI_CAP_HW_ECC_FIXUP | 53 DENALI_CAP_DMA_64BIT, 54 .ecc_caps = &denali_uniphier_v5b_ecc_caps, 55 }; 56 57 static const struct of_device_id denali_nand_dt_ids[] = { 58 { 59 .compatible = "altr,socfpga-denali-nand", 60 .data = &denali_socfpga_data, 61 }, 62 { 63 .compatible = "socionext,uniphier-denali-nand-v5a", 64 .data = &denali_uniphier_v5a_data, 65 }, 66 { 67 .compatible = "socionext,uniphier-denali-nand-v5b", 68 .data = &denali_uniphier_v5b_data, 69 }, 70 { /* sentinel */ } 71 }; 72 MODULE_DEVICE_TABLE(of, denali_nand_dt_ids); 73 74 static int denali_dt_chip_init(struct denali_controller *denali, 75 struct device_node *chip_np) 76 { 77 struct denali_chip *dchip; 78 u32 bank; 79 int nsels, i, ret; 80 81 nsels = of_property_count_u32_elems(chip_np, "reg"); 82 if (nsels < 0) 83 return nsels; 84 85 dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), 86 GFP_KERNEL); 87 if (!dchip) 88 return -ENOMEM; 89 90 dchip->nsels = nsels; 91 92 for (i = 0; i < nsels; i++) { 93 ret = of_property_read_u32_index(chip_np, "reg", i, &bank); 94 if (ret) 95 return ret; 96 97 dchip->sels[i].bank = bank; 98 99 nand_set_flash_node(&dchip->chip, chip_np); 100 } 101 102 return denali_chip_init(denali, dchip); 103 } 104 105 static int denali_dt_probe(struct platform_device *pdev) 106 { 107 struct device *dev = &pdev->dev; 108 struct resource *res; 109 struct denali_dt *dt; 110 const struct denali_dt_data *data; 111 struct denali_controller *denali; 112 struct device_node *np; 113 int ret; 114 115 dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL); 116 if (!dt) 117 return -ENOMEM; 118 denali = &dt->controller; 119 120 data = of_device_get_match_data(dev); 121 if (data) { 122 denali->revision = data->revision; 123 denali->caps = data->caps; 124 denali->ecc_caps = data->ecc_caps; 125 } 126 127 denali->dev = dev; 128 denali->irq = platform_get_irq(pdev, 0); 129 if (denali->irq < 0) 130 return denali->irq; 131 132 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg"); 133 denali->reg = devm_ioremap_resource(dev, res); 134 if (IS_ERR(denali->reg)) 135 return PTR_ERR(denali->reg); 136 137 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); 138 denali->host = devm_ioremap_resource(dev, res); 139 if (IS_ERR(denali->host)) 140 return PTR_ERR(denali->host); 141 142 dt->clk = devm_clk_get(dev, "nand"); 143 if (IS_ERR(dt->clk)) 144 return PTR_ERR(dt->clk); 145 146 dt->clk_x = devm_clk_get(dev, "nand_x"); 147 if (IS_ERR(dt->clk_x)) 148 return PTR_ERR(dt->clk_x); 149 150 dt->clk_ecc = devm_clk_get(dev, "ecc"); 151 if (IS_ERR(dt->clk_ecc)) 152 return PTR_ERR(dt->clk_ecc); 153 154 ret = clk_prepare_enable(dt->clk); 155 if (ret) 156 return ret; 157 158 ret = clk_prepare_enable(dt->clk_x); 159 if (ret) 160 goto out_disable_clk; 161 162 ret = clk_prepare_enable(dt->clk_ecc); 163 if (ret) 164 goto out_disable_clk_x; 165 166 denali->clk_rate = clk_get_rate(dt->clk); 167 denali->clk_x_rate = clk_get_rate(dt->clk_x); 168 169 ret = denali_init(denali); 170 if (ret) 171 goto out_disable_clk_ecc; 172 173 for_each_child_of_node(dev->of_node, np) { 174 ret = denali_dt_chip_init(denali, np); 175 if (ret) { 176 of_node_put(np); 177 goto out_remove_denali; 178 } 179 } 180 181 platform_set_drvdata(pdev, dt); 182 183 return 0; 184 185 out_remove_denali: 186 denali_remove(denali); 187 out_disable_clk_ecc: 188 clk_disable_unprepare(dt->clk_ecc); 189 out_disable_clk_x: 190 clk_disable_unprepare(dt->clk_x); 191 out_disable_clk: 192 clk_disable_unprepare(dt->clk); 193 194 return ret; 195 } 196 197 static int denali_dt_remove(struct platform_device *pdev) 198 { 199 struct denali_dt *dt = platform_get_drvdata(pdev); 200 201 denali_remove(&dt->controller); 202 clk_disable_unprepare(dt->clk_ecc); 203 clk_disable_unprepare(dt->clk_x); 204 clk_disable_unprepare(dt->clk); 205 206 return 0; 207 } 208 209 static struct platform_driver denali_dt_driver = { 210 .probe = denali_dt_probe, 211 .remove = denali_dt_remove, 212 .driver = { 213 .name = "denali-nand-dt", 214 .of_match_table = denali_nand_dt_ids, 215 }, 216 }; 217 module_platform_driver(denali_dt_driver); 218 219 MODULE_LICENSE("GPL v2"); 220 MODULE_AUTHOR("Jamie Iles"); 221 MODULE_DESCRIPTION("DT driver for Denali NAND controller"); 222