1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NAND Flash Controller Device Driver for DT 4 * 5 * Copyright © 2011, Picochip. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/ioport.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 18 #include "denali.h" 19 20 struct denali_dt { 21 struct denali_nand_info denali; 22 struct clk *clk; /* core clock */ 23 struct clk *clk_x; /* bus interface clock */ 24 struct clk *clk_ecc; /* ECC circuit clock */ 25 }; 26 27 struct denali_dt_data { 28 unsigned int revision; 29 unsigned int caps; 30 const struct nand_ecc_caps *ecc_caps; 31 }; 32 33 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes, 34 512, 8, 15); 35 static const struct denali_dt_data denali_socfpga_data = { 36 .caps = DENALI_CAP_HW_ECC_FIXUP, 37 .ecc_caps = &denali_socfpga_ecc_caps, 38 }; 39 40 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes, 41 1024, 8, 16, 24); 42 static const struct denali_dt_data denali_uniphier_v5a_data = { 43 .caps = DENALI_CAP_HW_ECC_FIXUP | 44 DENALI_CAP_DMA_64BIT, 45 .ecc_caps = &denali_uniphier_v5a_ecc_caps, 46 }; 47 48 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes, 49 1024, 8, 16); 50 static const struct denali_dt_data denali_uniphier_v5b_data = { 51 .revision = 0x0501, 52 .caps = DENALI_CAP_HW_ECC_FIXUP | 53 DENALI_CAP_DMA_64BIT, 54 .ecc_caps = &denali_uniphier_v5b_ecc_caps, 55 }; 56 57 static const struct of_device_id denali_nand_dt_ids[] = { 58 { 59 .compatible = "altr,socfpga-denali-nand", 60 .data = &denali_socfpga_data, 61 }, 62 { 63 .compatible = "socionext,uniphier-denali-nand-v5a", 64 .data = &denali_uniphier_v5a_data, 65 }, 66 { 67 .compatible = "socionext,uniphier-denali-nand-v5b", 68 .data = &denali_uniphier_v5b_data, 69 }, 70 { /* sentinel */ } 71 }; 72 MODULE_DEVICE_TABLE(of, denali_nand_dt_ids); 73 74 static int denali_dt_probe(struct platform_device *pdev) 75 { 76 struct device *dev = &pdev->dev; 77 struct resource *res; 78 struct denali_dt *dt; 79 const struct denali_dt_data *data; 80 struct denali_nand_info *denali; 81 int ret; 82 83 dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL); 84 if (!dt) 85 return -ENOMEM; 86 denali = &dt->denali; 87 88 data = of_device_get_match_data(dev); 89 if (data) { 90 denali->revision = data->revision; 91 denali->caps = data->caps; 92 denali->ecc_caps = data->ecc_caps; 93 } 94 95 denali->dev = dev; 96 denali->irq = platform_get_irq(pdev, 0); 97 if (denali->irq < 0) { 98 dev_err(dev, "no irq defined\n"); 99 return denali->irq; 100 } 101 102 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg"); 103 denali->reg = devm_ioremap_resource(dev, res); 104 if (IS_ERR(denali->reg)) 105 return PTR_ERR(denali->reg); 106 107 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); 108 denali->host = devm_ioremap_resource(dev, res); 109 if (IS_ERR(denali->host)) 110 return PTR_ERR(denali->host); 111 112 /* 113 * A single anonymous clock is supported for the backward compatibility. 114 * New platforms should support all the named clocks. 115 */ 116 dt->clk = devm_clk_get(dev, "nand"); 117 if (IS_ERR(dt->clk)) 118 dt->clk = devm_clk_get(dev, NULL); 119 if (IS_ERR(dt->clk)) { 120 dev_err(dev, "no clk available\n"); 121 return PTR_ERR(dt->clk); 122 } 123 124 dt->clk_x = devm_clk_get(dev, "nand_x"); 125 if (IS_ERR(dt->clk_x)) 126 dt->clk_x = NULL; 127 128 dt->clk_ecc = devm_clk_get(dev, "ecc"); 129 if (IS_ERR(dt->clk_ecc)) 130 dt->clk_ecc = NULL; 131 132 ret = clk_prepare_enable(dt->clk); 133 if (ret) 134 return ret; 135 136 ret = clk_prepare_enable(dt->clk_x); 137 if (ret) 138 goto out_disable_clk; 139 140 ret = clk_prepare_enable(dt->clk_ecc); 141 if (ret) 142 goto out_disable_clk_x; 143 144 if (dt->clk_x) { 145 denali->clk_rate = clk_get_rate(dt->clk); 146 denali->clk_x_rate = clk_get_rate(dt->clk_x); 147 } else { 148 /* 149 * Hardcode the clock rates for the backward compatibility. 150 * This works for both SOCFPGA and UniPhier. 151 */ 152 dev_notice(dev, 153 "necessary clock is missing. default clock rates are used.\n"); 154 denali->clk_rate = 50000000; 155 denali->clk_x_rate = 200000000; 156 } 157 158 ret = denali_init(denali); 159 if (ret) 160 goto out_disable_clk_ecc; 161 162 platform_set_drvdata(pdev, dt); 163 return 0; 164 165 out_disable_clk_ecc: 166 clk_disable_unprepare(dt->clk_ecc); 167 out_disable_clk_x: 168 clk_disable_unprepare(dt->clk_x); 169 out_disable_clk: 170 clk_disable_unprepare(dt->clk); 171 172 return ret; 173 } 174 175 static int denali_dt_remove(struct platform_device *pdev) 176 { 177 struct denali_dt *dt = platform_get_drvdata(pdev); 178 179 denali_remove(&dt->denali); 180 clk_disable_unprepare(dt->clk_ecc); 181 clk_disable_unprepare(dt->clk_x); 182 clk_disable_unprepare(dt->clk); 183 184 return 0; 185 } 186 187 static struct platform_driver denali_dt_driver = { 188 .probe = denali_dt_probe, 189 .remove = denali_dt_remove, 190 .driver = { 191 .name = "denali-nand-dt", 192 .of_match_table = denali_nand_dt_ids, 193 }, 194 }; 195 module_platform_driver(denali_dt_driver); 196 197 MODULE_LICENSE("GPL v2"); 198 MODULE_AUTHOR("Jamie Iles"); 199 MODULE_DESCRIPTION("DT driver for Denali NAND controller"); 200