1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NAND Flash Controller Device Driver for DT 4 * 5 * Copyright © 2011, Picochip. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/ioport.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 18 #include "denali.h" 19 20 struct denali_dt { 21 struct denali_controller controller; 22 struct clk *clk; /* core clock */ 23 struct clk *clk_x; /* bus interface clock */ 24 struct clk *clk_ecc; /* ECC circuit clock */ 25 }; 26 27 struct denali_dt_data { 28 unsigned int revision; 29 unsigned int caps; 30 const struct nand_ecc_caps *ecc_caps; 31 }; 32 33 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes, 34 512, 8, 15); 35 static const struct denali_dt_data denali_socfpga_data = { 36 .caps = DENALI_CAP_HW_ECC_FIXUP, 37 .ecc_caps = &denali_socfpga_ecc_caps, 38 }; 39 40 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes, 41 1024, 8, 16, 24); 42 static const struct denali_dt_data denali_uniphier_v5a_data = { 43 .caps = DENALI_CAP_HW_ECC_FIXUP | 44 DENALI_CAP_DMA_64BIT, 45 .ecc_caps = &denali_uniphier_v5a_ecc_caps, 46 }; 47 48 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes, 49 1024, 8, 16); 50 static const struct denali_dt_data denali_uniphier_v5b_data = { 51 .revision = 0x0501, 52 .caps = DENALI_CAP_HW_ECC_FIXUP | 53 DENALI_CAP_DMA_64BIT, 54 .ecc_caps = &denali_uniphier_v5b_ecc_caps, 55 }; 56 57 static const struct of_device_id denali_nand_dt_ids[] = { 58 { 59 .compatible = "altr,socfpga-denali-nand", 60 .data = &denali_socfpga_data, 61 }, 62 { 63 .compatible = "socionext,uniphier-denali-nand-v5a", 64 .data = &denali_uniphier_v5a_data, 65 }, 66 { 67 .compatible = "socionext,uniphier-denali-nand-v5b", 68 .data = &denali_uniphier_v5b_data, 69 }, 70 { /* sentinel */ } 71 }; 72 MODULE_DEVICE_TABLE(of, denali_nand_dt_ids); 73 74 static int denali_dt_chip_init(struct denali_controller *denali, 75 struct device_node *chip_np) 76 { 77 struct denali_chip *dchip; 78 u32 bank; 79 int nsels, i, ret; 80 81 nsels = of_property_count_u32_elems(chip_np, "reg"); 82 if (nsels < 0) 83 return nsels; 84 85 dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), 86 GFP_KERNEL); 87 if (!dchip) 88 return -ENOMEM; 89 90 dchip->nsels = nsels; 91 92 for (i = 0; i < nsels; i++) { 93 ret = of_property_read_u32_index(chip_np, "reg", i, &bank); 94 if (ret) 95 return ret; 96 97 dchip->sels[i].bank = bank; 98 99 nand_set_flash_node(&dchip->chip, chip_np); 100 } 101 102 return denali_chip_init(denali, dchip); 103 } 104 105 /* Backward compatibility for old platforms */ 106 static int denali_dt_legacy_chip_init(struct denali_controller *denali) 107 { 108 struct denali_chip *dchip; 109 int nsels, i; 110 111 nsels = denali->nbanks; 112 113 dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), 114 GFP_KERNEL); 115 if (!dchip) 116 return -ENOMEM; 117 118 dchip->nsels = nsels; 119 120 for (i = 0; i < nsels; i++) 121 dchip->sels[i].bank = i; 122 123 nand_set_flash_node(&dchip->chip, denali->dev->of_node); 124 125 return denali_chip_init(denali, dchip); 126 } 127 128 /* 129 * Check the DT binding. 130 * The new binding expects chip subnodes in the controller node. 131 * So, #address-cells = <1>; #size-cells = <0>; are required. 132 * Check the #size-cells to distinguish the binding. 133 */ 134 static bool denali_dt_is_legacy_binding(struct device_node *np) 135 { 136 u32 cells; 137 int ret; 138 139 ret = of_property_read_u32(np, "#size-cells", &cells); 140 if (ret) 141 return true; 142 143 return cells != 0; 144 } 145 146 static int denali_dt_probe(struct platform_device *pdev) 147 { 148 struct device *dev = &pdev->dev; 149 struct resource *res; 150 struct denali_dt *dt; 151 const struct denali_dt_data *data; 152 struct denali_controller *denali; 153 struct device_node *np; 154 int ret; 155 156 dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL); 157 if (!dt) 158 return -ENOMEM; 159 denali = &dt->controller; 160 161 data = of_device_get_match_data(dev); 162 if (data) { 163 denali->revision = data->revision; 164 denali->caps = data->caps; 165 denali->ecc_caps = data->ecc_caps; 166 } 167 168 denali->dev = dev; 169 denali->irq = platform_get_irq(pdev, 0); 170 if (denali->irq < 0) { 171 dev_err(dev, "no irq defined\n"); 172 return denali->irq; 173 } 174 175 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg"); 176 denali->reg = devm_ioremap_resource(dev, res); 177 if (IS_ERR(denali->reg)) 178 return PTR_ERR(denali->reg); 179 180 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); 181 denali->host = devm_ioremap_resource(dev, res); 182 if (IS_ERR(denali->host)) 183 return PTR_ERR(denali->host); 184 185 dt->clk = devm_clk_get(dev, "nand"); 186 if (IS_ERR(dt->clk)) 187 return PTR_ERR(dt->clk); 188 189 dt->clk_x = devm_clk_get(dev, "nand_x"); 190 if (IS_ERR(dt->clk_x)) 191 return PTR_ERR(dt->clk_x); 192 193 dt->clk_ecc = devm_clk_get(dev, "ecc"); 194 if (IS_ERR(dt->clk_ecc)) 195 return PTR_ERR(dt->clk_ecc); 196 197 ret = clk_prepare_enable(dt->clk); 198 if (ret) 199 return ret; 200 201 ret = clk_prepare_enable(dt->clk_x); 202 if (ret) 203 goto out_disable_clk; 204 205 ret = clk_prepare_enable(dt->clk_ecc); 206 if (ret) 207 goto out_disable_clk_x; 208 209 denali->clk_rate = clk_get_rate(dt->clk); 210 denali->clk_x_rate = clk_get_rate(dt->clk_x); 211 212 ret = denali_init(denali); 213 if (ret) 214 goto out_disable_clk_ecc; 215 216 if (denali_dt_is_legacy_binding(dev->of_node)) { 217 ret = denali_dt_legacy_chip_init(denali); 218 if (ret) 219 goto out_remove_denali; 220 } else { 221 for_each_child_of_node(dev->of_node, np) { 222 ret = denali_dt_chip_init(denali, np); 223 if (ret) { 224 of_node_put(np); 225 goto out_remove_denali; 226 } 227 } 228 } 229 230 platform_set_drvdata(pdev, dt); 231 232 return 0; 233 234 out_remove_denali: 235 denali_remove(denali); 236 out_disable_clk_ecc: 237 clk_disable_unprepare(dt->clk_ecc); 238 out_disable_clk_x: 239 clk_disable_unprepare(dt->clk_x); 240 out_disable_clk: 241 clk_disable_unprepare(dt->clk); 242 243 return ret; 244 } 245 246 static int denali_dt_remove(struct platform_device *pdev) 247 { 248 struct denali_dt *dt = platform_get_drvdata(pdev); 249 250 denali_remove(&dt->controller); 251 clk_disable_unprepare(dt->clk_ecc); 252 clk_disable_unprepare(dt->clk_x); 253 clk_disable_unprepare(dt->clk); 254 255 return 0; 256 } 257 258 static struct platform_driver denali_dt_driver = { 259 .probe = denali_dt_probe, 260 .remove = denali_dt_remove, 261 .driver = { 262 .name = "denali-nand-dt", 263 .of_match_table = denali_nand_dt_ids, 264 }, 265 }; 266 module_platform_driver(denali_dt_driver); 267 268 MODULE_LICENSE("GPL v2"); 269 MODULE_AUTHOR("Jamie Iles"); 270 MODULE_DESCRIPTION("DT driver for Denali NAND controller"); 271