1 /* 2 * NAND Flash Controller Device Driver 3 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef __DENALI_H__ 16 #define __DENALI_H__ 17 18 #include <linux/bitops.h> 19 #include <linux/completion.h> 20 #include <linux/mtd/rawnand.h> 21 #include <linux/spinlock_types.h> 22 #include <linux/types.h> 23 24 #define DEVICE_RESET 0x0 25 #define DEVICE_RESET__BANK(bank) BIT(bank) 26 27 #define TRANSFER_SPARE_REG 0x10 28 #define TRANSFER_SPARE_REG__FLAG BIT(0) 29 30 #define LOAD_WAIT_CNT 0x20 31 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0) 32 33 #define PROGRAM_WAIT_CNT 0x30 34 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0) 35 36 #define ERASE_WAIT_CNT 0x40 37 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0) 38 39 #define INT_MON_CYCCNT 0x50 40 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0) 41 42 #define RB_PIN_ENABLED 0x60 43 #define RB_PIN_ENABLED__BANK(bank) BIT(bank) 44 45 #define MULTIPLANE_OPERATION 0x70 46 #define MULTIPLANE_OPERATION__FLAG BIT(0) 47 48 #define MULTIPLANE_READ_ENABLE 0x80 49 #define MULTIPLANE_READ_ENABLE__FLAG BIT(0) 50 51 #define COPYBACK_DISABLE 0x90 52 #define COPYBACK_DISABLE__FLAG BIT(0) 53 54 #define CACHE_WRITE_ENABLE 0xa0 55 #define CACHE_WRITE_ENABLE__FLAG BIT(0) 56 57 #define CACHE_READ_ENABLE 0xb0 58 #define CACHE_READ_ENABLE__FLAG BIT(0) 59 60 #define PREFETCH_MODE 0xc0 61 #define PREFETCH_MODE__PREFETCH_EN BIT(0) 62 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4) 63 64 #define CHIP_ENABLE_DONT_CARE 0xd0 65 #define CHIP_EN_DONT_CARE__FLAG BIT(0) 66 67 #define ECC_ENABLE 0xe0 68 #define ECC_ENABLE__FLAG BIT(0) 69 70 #define GLOBAL_INT_ENABLE 0xf0 71 #define GLOBAL_INT_EN_FLAG BIT(0) 72 73 #define TWHR2_AND_WE_2_RE 0x100 74 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0) 75 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8) 76 77 #define TCWAW_AND_ADDR_2_DATA 0x110 78 /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */ 79 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0) 80 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8) 81 82 #define RE_2_WE 0x120 83 #define RE_2_WE__VALUE GENMASK(5, 0) 84 85 #define ACC_CLKS 0x130 86 #define ACC_CLKS__VALUE GENMASK(3, 0) 87 88 #define NUMBER_OF_PLANES 0x140 89 #define NUMBER_OF_PLANES__VALUE GENMASK(2, 0) 90 91 #define PAGES_PER_BLOCK 0x150 92 #define PAGES_PER_BLOCK__VALUE GENMASK(15, 0) 93 94 #define DEVICE_WIDTH 0x160 95 #define DEVICE_WIDTH__VALUE GENMASK(1, 0) 96 97 #define DEVICE_MAIN_AREA_SIZE 0x170 98 #define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0) 99 100 #define DEVICE_SPARE_AREA_SIZE 0x180 101 #define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0) 102 103 #define TWO_ROW_ADDR_CYCLES 0x190 104 #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0) 105 106 #define MULTIPLANE_ADDR_RESTRICT 0x1a0 107 #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0) 108 109 #define ECC_CORRECTION 0x1b0 110 #define ECC_CORRECTION__VALUE GENMASK(4, 0) 111 #define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16) 112 113 #define READ_MODE 0x1c0 114 #define READ_MODE__VALUE GENMASK(3, 0) 115 116 #define WRITE_MODE 0x1d0 117 #define WRITE_MODE__VALUE GENMASK(3, 0) 118 119 #define COPYBACK_MODE 0x1e0 120 #define COPYBACK_MODE__VALUE GENMASK(3, 0) 121 122 #define RDWR_EN_LO_CNT 0x1f0 123 #define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0) 124 125 #define RDWR_EN_HI_CNT 0x200 126 #define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0) 127 128 #define MAX_RD_DELAY 0x210 129 #define MAX_RD_DELAY__VALUE GENMASK(3, 0) 130 131 #define CS_SETUP_CNT 0x220 132 #define CS_SETUP_CNT__VALUE GENMASK(4, 0) 133 #define CS_SETUP_CNT__TWB GENMASK(17, 12) 134 135 #define SPARE_AREA_SKIP_BYTES 0x230 136 #define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0) 137 138 #define SPARE_AREA_MARKER 0x240 139 #define SPARE_AREA_MARKER__VALUE GENMASK(15, 0) 140 141 #define DEVICES_CONNECTED 0x250 142 #define DEVICES_CONNECTED__VALUE GENMASK(2, 0) 143 144 #define DIE_MASK 0x260 145 #define DIE_MASK__VALUE GENMASK(7, 0) 146 147 #define FIRST_BLOCK_OF_NEXT_PLANE 0x270 148 #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0) 149 150 #define WRITE_PROTECT 0x280 151 #define WRITE_PROTECT__FLAG BIT(0) 152 153 #define RE_2_RE 0x290 154 #define RE_2_RE__VALUE GENMASK(5, 0) 155 156 #define MANUFACTURER_ID 0x300 157 #define MANUFACTURER_ID__VALUE GENMASK(7, 0) 158 159 #define DEVICE_ID 0x310 160 #define DEVICE_ID__VALUE GENMASK(7, 0) 161 162 #define DEVICE_PARAM_0 0x320 163 #define DEVICE_PARAM_0__VALUE GENMASK(7, 0) 164 165 #define DEVICE_PARAM_1 0x330 166 #define DEVICE_PARAM_1__VALUE GENMASK(7, 0) 167 168 #define DEVICE_PARAM_2 0x340 169 #define DEVICE_PARAM_2__VALUE GENMASK(7, 0) 170 171 #define LOGICAL_PAGE_DATA_SIZE 0x350 172 #define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0) 173 174 #define LOGICAL_PAGE_SPARE_SIZE 0x360 175 #define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0) 176 177 #define REVISION 0x370 178 #define REVISION__VALUE GENMASK(15, 0) 179 180 #define ONFI_DEVICE_FEATURES 0x380 181 #define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0) 182 183 #define ONFI_OPTIONAL_COMMANDS 0x390 184 #define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0) 185 186 #define ONFI_TIMING_MODE 0x3a0 187 #define ONFI_TIMING_MODE__VALUE GENMASK(5, 0) 188 189 #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 190 #define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0) 191 192 #define ONFI_DEVICE_NO_OF_LUNS 0x3c0 193 #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0) 194 #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8) 195 196 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 197 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0) 198 199 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 200 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0) 201 202 #define FEATURES 0x3f0 203 #define FEATURES__N_BANKS GENMASK(1, 0) 204 #define FEATURES__ECC_MAX_ERR GENMASK(5, 2) 205 #define FEATURES__DMA BIT(6) 206 #define FEATURES__CMD_DMA BIT(7) 207 #define FEATURES__PARTITION BIT(8) 208 #define FEATURES__XDMA_SIDEBAND BIT(9) 209 #define FEATURES__GPREG BIT(10) 210 #define FEATURES__INDEX_ADDR BIT(11) 211 212 #define TRANSFER_MODE 0x400 213 #define TRANSFER_MODE__VALUE GENMASK(1, 0) 214 215 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) 216 #define INTR_EN(bank) (0x420 + (bank) * 0x50) 217 /* bit[1:0] is used differently depending on IP version */ 218 #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */ 219 #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */ 220 #define INTR__ECC_ERR BIT(1) /* old IP */ 221 #define INTR__DMA_CMD_COMP BIT(2) 222 #define INTR__TIME_OUT BIT(3) 223 #define INTR__PROGRAM_FAIL BIT(4) 224 #define INTR__ERASE_FAIL BIT(5) 225 #define INTR__LOAD_COMP BIT(6) 226 #define INTR__PROGRAM_COMP BIT(7) 227 #define INTR__ERASE_COMP BIT(8) 228 #define INTR__PIPE_CPYBCK_CMD_COMP BIT(9) 229 #define INTR__LOCKED_BLK BIT(10) 230 #define INTR__UNSUP_CMD BIT(11) 231 #define INTR__INT_ACT BIT(12) 232 #define INTR__RST_COMP BIT(13) 233 #define INTR__PIPE_CMD_ERR BIT(14) 234 #define INTR__PAGE_XFER_INC BIT(15) 235 #define INTR__ERASED_PAGE BIT(16) 236 237 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) 238 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) 239 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) 240 241 #define ECC_THRESHOLD 0x600 242 #define ECC_THRESHOLD__VALUE GENMASK(9, 0) 243 244 #define ECC_ERROR_BLOCK_ADDRESS 0x610 245 #define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0) 246 247 #define ECC_ERROR_PAGE_ADDRESS 0x620 248 #define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0) 249 #define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12) 250 251 #define ECC_ERROR_ADDRESS 0x630 252 #define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0) 253 #define ECC_ERROR_ADDRESS__SECTOR GENMASK(15, 12) 254 255 #define ERR_CORRECTION_INFO 0x640 256 #define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0) 257 #define ERR_CORRECTION_INFO__DEVICE GENMASK(11, 8) 258 #define ERR_CORRECTION_INFO__UNCOR BIT(14) 259 #define ERR_CORRECTION_INFO__LAST_ERR BIT(15) 260 261 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) 262 #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8) 263 #define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0) 264 #define ECC_COR_INFO__UNCOR_ERR BIT(7) 265 266 #define CFG_DATA_BLOCK_SIZE 0x6b0 267 268 #define CFG_LAST_DATA_BLOCK_SIZE 0x6c0 269 270 #define CFG_NUM_DATA_BLOCKS 0x6d0 271 272 #define CFG_META_DATA_SIZE 0x6e0 273 274 #define DMA_ENABLE 0x700 275 #define DMA_ENABLE__FLAG BIT(0) 276 277 #define IGNORE_ECC_DONE 0x710 278 #define IGNORE_ECC_DONE__FLAG BIT(0) 279 280 #define DMA_INTR 0x720 281 #define DMA_INTR_EN 0x730 282 #define DMA_INTR__TARGET_ERROR BIT(0) 283 #define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1) 284 #define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2) 285 #define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3) 286 #define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4) 287 #define DMA_INTR__MEMCOPY_DESC_COMP BIT(5) 288 289 #define TARGET_ERR_ADDR_LO 0x740 290 #define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0) 291 292 #define TARGET_ERR_ADDR_HI 0x750 293 #define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0) 294 295 #define CHNL_ACTIVE 0x760 296 #define CHNL_ACTIVE__CHANNEL0 BIT(0) 297 #define CHNL_ACTIVE__CHANNEL1 BIT(1) 298 #define CHNL_ACTIVE__CHANNEL2 BIT(2) 299 #define CHNL_ACTIVE__CHANNEL3 BIT(3) 300 301 struct denali_nand_info { 302 struct nand_chip nand; 303 unsigned long clk_x_rate; /* bus interface clock rate */ 304 int active_bank; /* currently selected bank */ 305 struct device *dev; 306 void __iomem *reg; /* Register Interface */ 307 void __iomem *host; /* Host Data/Command Interface */ 308 struct completion complete; 309 spinlock_t irq_lock; /* protect irq_mask and irq_status */ 310 u32 irq_mask; /* interrupts we are waiting for */ 311 u32 irq_status; /* interrupts that have happened */ 312 int irq; 313 void *buf; /* for syndrome layout conversion */ 314 dma_addr_t dma_addr; 315 int dma_avail; /* can support DMA? */ 316 int devs_per_cs; /* devices connected in parallel */ 317 int oob_skip_bytes; /* number of bytes reserved for BBM */ 318 int max_banks; 319 unsigned int revision; /* IP revision */ 320 unsigned int caps; /* IP capability (or quirk) */ 321 const struct nand_ecc_caps *ecc_caps; 322 u32 (*host_read)(struct denali_nand_info *denali, u32 addr); 323 void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data); 324 void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr, 325 int page, int write); 326 }; 327 328 #define DENALI_CAP_HW_ECC_FIXUP BIT(0) 329 #define DENALI_CAP_DMA_64BIT BIT(1) 330 331 int denali_calc_ecc_bytes(int step_size, int strength); 332 int denali_init(struct denali_nand_info *denali); 333 void denali_remove(struct denali_nand_info *denali); 334 335 #endif /* __DENALI_H__ */ 336