1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NAND Flash Controller Device Driver 4 * Copyright © 2009-2010, Intel Corporation and its suppliers. 5 * 6 * Copyright (c) 2017-2019 Socionext Inc. 7 * Reworked by Masahiro Yamada <yamada.masahiro@socionext.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/completion.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/rawnand.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 21 #include "denali.h" 22 23 #define DENALI_NAND_NAME "denali-nand" 24 #define DENALI_DEFAULT_OOB_SKIP_BYTES 8 25 26 /* for Indexed Addressing */ 27 #define DENALI_INDEXED_CTRL 0x00 28 #define DENALI_INDEXED_DATA 0x10 29 30 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */ 31 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */ 32 #define DENALI_MAP10 (2 << 26) /* high-level control plane */ 33 #define DENALI_MAP11 (3 << 26) /* direct controller access */ 34 35 /* MAP11 access cycle type */ 36 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */ 37 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */ 38 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */ 39 40 #define DENALI_BANK(denali) ((denali)->active_bank << 24) 41 42 #define DENALI_INVALID_BANK -1 43 44 static struct denali_chip *to_denali_chip(struct nand_chip *chip) 45 { 46 return container_of(chip, struct denali_chip, chip); 47 } 48 49 static struct denali_controller *to_denali_controller(struct nand_chip *chip) 50 { 51 return container_of(chip->controller, struct denali_controller, 52 controller); 53 } 54 55 /* 56 * Direct Addressing - the slave address forms the control information (command 57 * type, bank, block, and page address). The slave data is the actual data to 58 * be transferred. This mode requires 28 bits of address region allocated. 59 */ 60 static u32 denali_direct_read(struct denali_controller *denali, u32 addr) 61 { 62 return ioread32(denali->host + addr); 63 } 64 65 static void denali_direct_write(struct denali_controller *denali, u32 addr, 66 u32 data) 67 { 68 iowrite32(data, denali->host + addr); 69 } 70 71 /* 72 * Indexed Addressing - address translation module intervenes in passing the 73 * control information. This mode reduces the required address range. The 74 * control information and transferred data are latched by the registers in 75 * the translation module. 76 */ 77 static u32 denali_indexed_read(struct denali_controller *denali, u32 addr) 78 { 79 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); 80 return ioread32(denali->host + DENALI_INDEXED_DATA); 81 } 82 83 static void denali_indexed_write(struct denali_controller *denali, u32 addr, 84 u32 data) 85 { 86 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); 87 iowrite32(data, denali->host + DENALI_INDEXED_DATA); 88 } 89 90 static void denali_enable_irq(struct denali_controller *denali) 91 { 92 int i; 93 94 for (i = 0; i < denali->nbanks; i++) 95 iowrite32(U32_MAX, denali->reg + INTR_EN(i)); 96 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); 97 } 98 99 static void denali_disable_irq(struct denali_controller *denali) 100 { 101 int i; 102 103 for (i = 0; i < denali->nbanks; i++) 104 iowrite32(0, denali->reg + INTR_EN(i)); 105 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); 106 } 107 108 static void denali_clear_irq(struct denali_controller *denali, 109 int bank, u32 irq_status) 110 { 111 /* write one to clear bits */ 112 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); 113 } 114 115 static void denali_clear_irq_all(struct denali_controller *denali) 116 { 117 int i; 118 119 for (i = 0; i < denali->nbanks; i++) 120 denali_clear_irq(denali, i, U32_MAX); 121 } 122 123 static irqreturn_t denali_isr(int irq, void *dev_id) 124 { 125 struct denali_controller *denali = dev_id; 126 irqreturn_t ret = IRQ_NONE; 127 u32 irq_status; 128 int i; 129 130 spin_lock(&denali->irq_lock); 131 132 for (i = 0; i < denali->nbanks; i++) { 133 irq_status = ioread32(denali->reg + INTR_STATUS(i)); 134 if (irq_status) 135 ret = IRQ_HANDLED; 136 137 denali_clear_irq(denali, i, irq_status); 138 139 if (i != denali->active_bank) 140 continue; 141 142 denali->irq_status |= irq_status; 143 144 if (denali->irq_status & denali->irq_mask) 145 complete(&denali->complete); 146 } 147 148 spin_unlock(&denali->irq_lock); 149 150 return ret; 151 } 152 153 static void denali_reset_irq(struct denali_controller *denali) 154 { 155 unsigned long flags; 156 157 spin_lock_irqsave(&denali->irq_lock, flags); 158 denali->irq_status = 0; 159 denali->irq_mask = 0; 160 spin_unlock_irqrestore(&denali->irq_lock, flags); 161 } 162 163 static u32 denali_wait_for_irq(struct denali_controller *denali, u32 irq_mask) 164 { 165 unsigned long time_left, flags; 166 u32 irq_status; 167 168 spin_lock_irqsave(&denali->irq_lock, flags); 169 170 irq_status = denali->irq_status; 171 172 if (irq_mask & irq_status) { 173 /* return immediately if the IRQ has already happened. */ 174 spin_unlock_irqrestore(&denali->irq_lock, flags); 175 return irq_status; 176 } 177 178 denali->irq_mask = irq_mask; 179 reinit_completion(&denali->complete); 180 spin_unlock_irqrestore(&denali->irq_lock, flags); 181 182 time_left = wait_for_completion_timeout(&denali->complete, 183 msecs_to_jiffies(1000)); 184 if (!time_left) { 185 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", 186 irq_mask); 187 return 0; 188 } 189 190 return denali->irq_status; 191 } 192 193 static void denali_select_target(struct nand_chip *chip, int cs) 194 { 195 struct denali_controller *denali = to_denali_controller(chip); 196 struct denali_chip_sel *sel = &to_denali_chip(chip)->sels[cs]; 197 struct mtd_info *mtd = nand_to_mtd(chip); 198 199 denali->active_bank = sel->bank; 200 201 iowrite32(1 << (chip->phys_erase_shift - chip->page_shift), 202 denali->reg + PAGES_PER_BLOCK); 203 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, 204 denali->reg + DEVICE_WIDTH); 205 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); 206 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); 207 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 208 0 : TWO_ROW_ADDR_CYCLES__FLAG, 209 denali->reg + TWO_ROW_ADDR_CYCLES); 210 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) | 211 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), 212 denali->reg + ECC_CORRECTION); 213 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); 214 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); 215 iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS); 216 217 if (chip->options & NAND_KEEP_TIMINGS) 218 return; 219 220 /* update timing registers unless NAND_KEEP_TIMINGS is set */ 221 iowrite32(sel->hwhr2_and_we_2_re, denali->reg + TWHR2_AND_WE_2_RE); 222 iowrite32(sel->tcwaw_and_addr_2_data, 223 denali->reg + TCWAW_AND_ADDR_2_DATA); 224 iowrite32(sel->re_2_we, denali->reg + RE_2_WE); 225 iowrite32(sel->acc_clks, denali->reg + ACC_CLKS); 226 iowrite32(sel->rdwr_en_lo_cnt, denali->reg + RDWR_EN_LO_CNT); 227 iowrite32(sel->rdwr_en_hi_cnt, denali->reg + RDWR_EN_HI_CNT); 228 iowrite32(sel->cs_setup_cnt, denali->reg + CS_SETUP_CNT); 229 iowrite32(sel->re_2_re, denali->reg + RE_2_RE); 230 } 231 232 static int denali_change_column(struct nand_chip *chip, unsigned int offset, 233 void *buf, unsigned int len, bool write) 234 { 235 if (write) 236 return nand_change_write_column_op(chip, offset, buf, len, 237 false); 238 else 239 return nand_change_read_column_op(chip, offset, buf, len, 240 false); 241 } 242 243 static int denali_payload_xfer(struct nand_chip *chip, void *buf, bool write) 244 { 245 struct denali_controller *denali = to_denali_controller(chip); 246 struct mtd_info *mtd = nand_to_mtd(chip); 247 struct nand_ecc_ctrl *ecc = &chip->ecc; 248 int writesize = mtd->writesize; 249 int oob_skip = denali->oob_skip_bytes; 250 int ret, i, pos, len; 251 252 for (i = 0; i < ecc->steps; i++) { 253 pos = i * (ecc->size + ecc->bytes); 254 len = ecc->size; 255 256 if (pos >= writesize) { 257 pos += oob_skip; 258 } else if (pos + len > writesize) { 259 /* This chunk overwraps the BBM area. Must be split */ 260 ret = denali_change_column(chip, pos, buf, 261 writesize - pos, write); 262 if (ret) 263 return ret; 264 265 buf += writesize - pos; 266 len -= writesize - pos; 267 pos = writesize + oob_skip; 268 } 269 270 ret = denali_change_column(chip, pos, buf, len, write); 271 if (ret) 272 return ret; 273 274 buf += len; 275 } 276 277 return 0; 278 } 279 280 static int denali_oob_xfer(struct nand_chip *chip, void *buf, bool write) 281 { 282 struct denali_controller *denali = to_denali_controller(chip); 283 struct mtd_info *mtd = nand_to_mtd(chip); 284 struct nand_ecc_ctrl *ecc = &chip->ecc; 285 int writesize = mtd->writesize; 286 int oobsize = mtd->oobsize; 287 int oob_skip = denali->oob_skip_bytes; 288 int ret, i, pos, len; 289 290 /* BBM at the beginning of the OOB area */ 291 ret = denali_change_column(chip, writesize, buf, oob_skip, write); 292 if (ret) 293 return ret; 294 295 buf += oob_skip; 296 297 for (i = 0; i < ecc->steps; i++) { 298 pos = ecc->size + i * (ecc->size + ecc->bytes); 299 300 if (i == ecc->steps - 1) 301 /* The last chunk includes OOB free */ 302 len = writesize + oobsize - pos - oob_skip; 303 else 304 len = ecc->bytes; 305 306 if (pos >= writesize) { 307 pos += oob_skip; 308 } else if (pos + len > writesize) { 309 /* This chunk overwraps the BBM area. Must be split */ 310 ret = denali_change_column(chip, pos, buf, 311 writesize - pos, write); 312 if (ret) 313 return ret; 314 315 buf += writesize - pos; 316 len -= writesize - pos; 317 pos = writesize + oob_skip; 318 } 319 320 ret = denali_change_column(chip, pos, buf, len, write); 321 if (ret) 322 return ret; 323 324 buf += len; 325 } 326 327 return 0; 328 } 329 330 static int denali_read_raw(struct nand_chip *chip, void *buf, void *oob_buf, 331 int page) 332 { 333 int ret; 334 335 if (!buf && !oob_buf) 336 return -EINVAL; 337 338 ret = nand_read_page_op(chip, page, 0, NULL, 0); 339 if (ret) 340 return ret; 341 342 if (buf) { 343 ret = denali_payload_xfer(chip, buf, false); 344 if (ret) 345 return ret; 346 } 347 348 if (oob_buf) { 349 ret = denali_oob_xfer(chip, oob_buf, false); 350 if (ret) 351 return ret; 352 } 353 354 return 0; 355 } 356 357 static int denali_write_raw(struct nand_chip *chip, const void *buf, 358 const void *oob_buf, int page) 359 { 360 int ret; 361 362 if (!buf && !oob_buf) 363 return -EINVAL; 364 365 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 366 if (ret) 367 return ret; 368 369 if (buf) { 370 ret = denali_payload_xfer(chip, (void *)buf, true); 371 if (ret) 372 return ret; 373 } 374 375 if (oob_buf) { 376 ret = denali_oob_xfer(chip, (void *)oob_buf, true); 377 if (ret) 378 return ret; 379 } 380 381 return nand_prog_page_end_op(chip); 382 } 383 384 static int denali_read_page_raw(struct nand_chip *chip, u8 *buf, 385 int oob_required, int page) 386 { 387 return denali_read_raw(chip, buf, oob_required ? chip->oob_poi : NULL, 388 page); 389 } 390 391 static int denali_write_page_raw(struct nand_chip *chip, const u8 *buf, 392 int oob_required, int page) 393 { 394 return denali_write_raw(chip, buf, oob_required ? chip->oob_poi : NULL, 395 page); 396 } 397 398 static int denali_read_oob(struct nand_chip *chip, int page) 399 { 400 return denali_read_raw(chip, NULL, chip->oob_poi, page); 401 } 402 403 static int denali_write_oob(struct nand_chip *chip, int page) 404 { 405 return denali_write_raw(chip, NULL, chip->oob_poi, page); 406 } 407 408 static int denali_check_erased_page(struct nand_chip *chip, u8 *buf, 409 unsigned long uncor_ecc_flags, 410 unsigned int max_bitflips) 411 { 412 struct denali_controller *denali = to_denali_controller(chip); 413 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; 414 struct nand_ecc_ctrl *ecc = &chip->ecc; 415 u8 *ecc_code = chip->oob_poi + denali->oob_skip_bytes; 416 int i, stat; 417 418 for (i = 0; i < ecc->steps; i++) { 419 if (!(uncor_ecc_flags & BIT(i))) 420 continue; 421 422 stat = nand_check_erased_ecc_chunk(buf, ecc->size, ecc_code, 423 ecc->bytes, NULL, 0, 424 ecc->strength); 425 if (stat < 0) { 426 ecc_stats->failed++; 427 } else { 428 ecc_stats->corrected += stat; 429 max_bitflips = max_t(unsigned int, max_bitflips, stat); 430 } 431 432 buf += ecc->size; 433 ecc_code += ecc->bytes; 434 } 435 436 return max_bitflips; 437 } 438 439 static int denali_hw_ecc_fixup(struct nand_chip *chip, 440 unsigned long *uncor_ecc_flags) 441 { 442 struct denali_controller *denali = to_denali_controller(chip); 443 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; 444 int bank = denali->active_bank; 445 u32 ecc_cor; 446 unsigned int max_bitflips; 447 448 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); 449 ecc_cor >>= ECC_COR_INFO__SHIFT(bank); 450 451 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) { 452 /* 453 * This flag is set when uncorrectable error occurs at least in 454 * one ECC sector. We can not know "how many sectors", or 455 * "which sector(s)". We need erase-page check for all sectors. 456 */ 457 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0); 458 return 0; 459 } 460 461 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor); 462 463 /* 464 * The register holds the maximum of per-sector corrected bitflips. 465 * This is suitable for the return value of the ->read_page() callback. 466 * Unfortunately, we can not know the total number of corrected bits in 467 * the page. Increase the stats by max_bitflips. (compromised solution) 468 */ 469 ecc_stats->corrected += max_bitflips; 470 471 return max_bitflips; 472 } 473 474 static int denali_sw_ecc_fixup(struct nand_chip *chip, 475 unsigned long *uncor_ecc_flags, u8 *buf) 476 { 477 struct denali_controller *denali = to_denali_controller(chip); 478 struct mtd_ecc_stats *ecc_stats = &nand_to_mtd(chip)->ecc_stats; 479 unsigned int ecc_size = chip->ecc.size; 480 unsigned int bitflips = 0; 481 unsigned int max_bitflips = 0; 482 u32 err_addr, err_cor_info; 483 unsigned int err_byte, err_sector, err_device; 484 u8 err_cor_value; 485 unsigned int prev_sector = 0; 486 u32 irq_status; 487 488 denali_reset_irq(denali); 489 490 do { 491 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); 492 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr); 493 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr); 494 495 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); 496 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE, 497 err_cor_info); 498 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE, 499 err_cor_info); 500 501 /* reset the bitflip counter when crossing ECC sector */ 502 if (err_sector != prev_sector) 503 bitflips = 0; 504 505 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) { 506 /* 507 * Check later if this is a real ECC error, or 508 * an erased sector. 509 */ 510 *uncor_ecc_flags |= BIT(err_sector); 511 } else if (err_byte < ecc_size) { 512 /* 513 * If err_byte is larger than ecc_size, means error 514 * happened in OOB, so we ignore it. It's no need for 515 * us to correct it err_device is represented the NAND 516 * error bits are happened in if there are more than 517 * one NAND connected. 518 */ 519 int offset; 520 unsigned int flips_in_byte; 521 522 offset = (err_sector * ecc_size + err_byte) * 523 denali->devs_per_cs + err_device; 524 525 /* correct the ECC error */ 526 flips_in_byte = hweight8(buf[offset] ^ err_cor_value); 527 buf[offset] ^= err_cor_value; 528 ecc_stats->corrected += flips_in_byte; 529 bitflips += flips_in_byte; 530 531 max_bitflips = max(max_bitflips, bitflips); 532 } 533 534 prev_sector = err_sector; 535 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR)); 536 537 /* 538 * Once handle all ECC errors, controller will trigger an 539 * ECC_TRANSACTION_DONE interrupt. 540 */ 541 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); 542 if (!(irq_status & INTR__ECC_TRANSACTION_DONE)) 543 return -EIO; 544 545 return max_bitflips; 546 } 547 548 static void denali_setup_dma64(struct denali_controller *denali, 549 dma_addr_t dma_addr, int page, bool write) 550 { 551 u32 mode; 552 const int page_count = 1; 553 554 mode = DENALI_MAP10 | DENALI_BANK(denali) | page; 555 556 /* DMA is a three step process */ 557 558 /* 559 * 1. setup transfer type, interrupt when complete, 560 * burst len = 64 bytes, the number of pages 561 */ 562 denali->host_write(denali, mode, 563 0x01002000 | (64 << 16) | 564 (write ? BIT(8) : 0) | page_count); 565 566 /* 2. set memory low address */ 567 denali->host_write(denali, mode, lower_32_bits(dma_addr)); 568 569 /* 3. set memory high address */ 570 denali->host_write(denali, mode, upper_32_bits(dma_addr)); 571 } 572 573 static void denali_setup_dma32(struct denali_controller *denali, 574 dma_addr_t dma_addr, int page, bool write) 575 { 576 u32 mode; 577 const int page_count = 1; 578 579 mode = DENALI_MAP10 | DENALI_BANK(denali); 580 581 /* DMA is a four step process */ 582 583 /* 1. setup transfer type and # of pages */ 584 denali->host_write(denali, mode | page, 585 0x2000 | (write ? BIT(8) : 0) | page_count); 586 587 /* 2. set memory high address bits 23:8 */ 588 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); 589 590 /* 3. set memory low address bits 23:8 */ 591 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); 592 593 /* 4. interrupt when complete, burst len = 64 bytes */ 594 denali->host_write(denali, mode | 0x14000, 0x2400); 595 } 596 597 static int denali_pio_read(struct denali_controller *denali, u32 *buf, 598 size_t size, int page) 599 { 600 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; 601 u32 irq_status, ecc_err_mask; 602 int i; 603 604 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) 605 ecc_err_mask = INTR__ECC_UNCOR_ERR; 606 else 607 ecc_err_mask = INTR__ECC_ERR; 608 609 denali_reset_irq(denali); 610 611 for (i = 0; i < size / 4; i++) 612 buf[i] = denali->host_read(denali, addr); 613 614 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); 615 if (!(irq_status & INTR__PAGE_XFER_INC)) 616 return -EIO; 617 618 if (irq_status & INTR__ERASED_PAGE) 619 memset(buf, 0xff, size); 620 621 return irq_status & ecc_err_mask ? -EBADMSG : 0; 622 } 623 624 static int denali_pio_write(struct denali_controller *denali, const u32 *buf, 625 size_t size, int page) 626 { 627 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; 628 u32 irq_status; 629 int i; 630 631 denali_reset_irq(denali); 632 633 for (i = 0; i < size / 4; i++) 634 denali->host_write(denali, addr, buf[i]); 635 636 irq_status = denali_wait_for_irq(denali, 637 INTR__PROGRAM_COMP | 638 INTR__PROGRAM_FAIL); 639 if (!(irq_status & INTR__PROGRAM_COMP)) 640 return -EIO; 641 642 return 0; 643 } 644 645 static int denali_pio_xfer(struct denali_controller *denali, void *buf, 646 size_t size, int page, bool write) 647 { 648 if (write) 649 return denali_pio_write(denali, buf, size, page); 650 else 651 return denali_pio_read(denali, buf, size, page); 652 } 653 654 static int denali_dma_xfer(struct denali_controller *denali, void *buf, 655 size_t size, int page, bool write) 656 { 657 dma_addr_t dma_addr; 658 u32 irq_mask, irq_status, ecc_err_mask; 659 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 660 int ret = 0; 661 662 dma_addr = dma_map_single(denali->dev, buf, size, dir); 663 if (dma_mapping_error(denali->dev, dma_addr)) { 664 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n"); 665 return denali_pio_xfer(denali, buf, size, page, write); 666 } 667 668 if (write) { 669 /* 670 * INTR__PROGRAM_COMP is never asserted for the DMA transfer. 671 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted 672 * when the page program is completed. 673 */ 674 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL; 675 ecc_err_mask = 0; 676 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) { 677 irq_mask = INTR__DMA_CMD_COMP; 678 ecc_err_mask = INTR__ECC_UNCOR_ERR; 679 } else { 680 irq_mask = INTR__DMA_CMD_COMP; 681 ecc_err_mask = INTR__ECC_ERR; 682 } 683 684 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); 685 /* 686 * The ->setup_dma() hook kicks DMA by using the data/command 687 * interface, which belongs to a different AXI port from the 688 * register interface. Read back the register to avoid a race. 689 */ 690 ioread32(denali->reg + DMA_ENABLE); 691 692 denali_reset_irq(denali); 693 denali->setup_dma(denali, dma_addr, page, write); 694 695 irq_status = denali_wait_for_irq(denali, irq_mask); 696 if (!(irq_status & INTR__DMA_CMD_COMP)) 697 ret = -EIO; 698 else if (irq_status & ecc_err_mask) 699 ret = -EBADMSG; 700 701 iowrite32(0, denali->reg + DMA_ENABLE); 702 703 dma_unmap_single(denali->dev, dma_addr, size, dir); 704 705 if (irq_status & INTR__ERASED_PAGE) 706 memset(buf, 0xff, size); 707 708 return ret; 709 } 710 711 static int denali_page_xfer(struct nand_chip *chip, void *buf, size_t size, 712 int page, bool write) 713 { 714 struct denali_controller *denali = to_denali_controller(chip); 715 716 denali_select_target(chip, chip->cur_cs); 717 718 if (denali->dma_avail) 719 return denali_dma_xfer(denali, buf, size, page, write); 720 else 721 return denali_pio_xfer(denali, buf, size, page, write); 722 } 723 724 static int denali_read_page(struct nand_chip *chip, u8 *buf, 725 int oob_required, int page) 726 { 727 struct denali_controller *denali = to_denali_controller(chip); 728 struct mtd_info *mtd = nand_to_mtd(chip); 729 unsigned long uncor_ecc_flags = 0; 730 int stat = 0; 731 int ret; 732 733 ret = denali_page_xfer(chip, buf, mtd->writesize, page, false); 734 if (ret && ret != -EBADMSG) 735 return ret; 736 737 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) 738 stat = denali_hw_ecc_fixup(chip, &uncor_ecc_flags); 739 else if (ret == -EBADMSG) 740 stat = denali_sw_ecc_fixup(chip, &uncor_ecc_flags, buf); 741 742 if (stat < 0) 743 return stat; 744 745 if (uncor_ecc_flags) { 746 ret = denali_read_oob(chip, page); 747 if (ret) 748 return ret; 749 750 stat = denali_check_erased_page(chip, buf, 751 uncor_ecc_flags, stat); 752 } 753 754 return stat; 755 } 756 757 static int denali_write_page(struct nand_chip *chip, const u8 *buf, 758 int oob_required, int page) 759 { 760 struct mtd_info *mtd = nand_to_mtd(chip); 761 762 return denali_page_xfer(chip, (void *)buf, mtd->writesize, page, true); 763 } 764 765 static int denali_setup_data_interface(struct nand_chip *chip, int chipnr, 766 const struct nand_data_interface *conf) 767 { 768 struct denali_controller *denali = to_denali_controller(chip); 769 struct denali_chip_sel *sel; 770 const struct nand_sdr_timings *timings; 771 unsigned long t_x, mult_x; 772 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; 773 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; 774 int addr_2_data_mask; 775 u32 tmp; 776 777 timings = nand_get_sdr_timings(conf); 778 if (IS_ERR(timings)) 779 return PTR_ERR(timings); 780 781 /* clk_x period in picoseconds */ 782 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); 783 if (!t_x) 784 return -EINVAL; 785 786 /* 787 * The bus interface clock, clk_x, is phase aligned with the core clock. 788 * The clk_x is an integral multiple N of the core clk. The value N is 789 * configured at IP delivery time, and its available value is 4, 5, 6. 790 */ 791 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); 792 if (mult_x < 4 || mult_x > 6) 793 return -EINVAL; 794 795 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) 796 return 0; 797 798 sel = &to_denali_chip(chip)->sels[chipnr]; 799 800 /* tREA -> ACC_CLKS */ 801 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); 802 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); 803 804 tmp = ioread32(denali->reg + ACC_CLKS); 805 tmp &= ~ACC_CLKS__VALUE; 806 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks); 807 sel->acc_clks = tmp; 808 809 /* tRWH -> RE_2_WE */ 810 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); 811 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); 812 813 tmp = ioread32(denali->reg + RE_2_WE); 814 tmp &= ~RE_2_WE__VALUE; 815 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we); 816 sel->re_2_we = tmp; 817 818 /* tRHZ -> RE_2_RE */ 819 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); 820 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); 821 822 tmp = ioread32(denali->reg + RE_2_RE); 823 tmp &= ~RE_2_RE__VALUE; 824 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re); 825 sel->re_2_re = tmp; 826 827 /* 828 * tCCS, tWHR -> WE_2_RE 829 * 830 * With WE_2_RE properly set, the Denali controller automatically takes 831 * care of the delay; the driver need not set NAND_WAIT_TCCS. 832 */ 833 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); 834 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); 835 836 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); 837 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE; 838 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re); 839 sel->hwhr2_and_we_2_re = tmp; 840 841 /* tADL -> ADDR_2_DATA */ 842 843 /* for older versions, ADDR_2_DATA is only 6 bit wide */ 844 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; 845 if (denali->revision < 0x0501) 846 addr_2_data_mask >>= 1; 847 848 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); 849 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); 850 851 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); 852 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; 853 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data); 854 sel->tcwaw_and_addr_2_data = tmp; 855 856 /* tREH, tWH -> RDWR_EN_HI_CNT */ 857 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), 858 t_x); 859 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); 860 861 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); 862 tmp &= ~RDWR_EN_HI_CNT__VALUE; 863 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi); 864 sel->rdwr_en_hi_cnt = tmp; 865 866 /* tRP, tWP -> RDWR_EN_LO_CNT */ 867 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); 868 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), 869 t_x); 870 rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x); 871 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); 872 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); 873 874 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); 875 tmp &= ~RDWR_EN_LO_CNT__VALUE; 876 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo); 877 sel->rdwr_en_lo_cnt = tmp; 878 879 /* tCS, tCEA -> CS_SETUP_CNT */ 880 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, 881 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, 882 0); 883 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); 884 885 tmp = ioread32(denali->reg + CS_SETUP_CNT); 886 tmp &= ~CS_SETUP_CNT__VALUE; 887 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup); 888 sel->cs_setup_cnt = tmp; 889 890 return 0; 891 } 892 893 int denali_calc_ecc_bytes(int step_size, int strength) 894 { 895 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */ 896 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2; 897 } 898 EXPORT_SYMBOL(denali_calc_ecc_bytes); 899 900 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, 901 struct mtd_oob_region *oobregion) 902 { 903 struct nand_chip *chip = mtd_to_nand(mtd); 904 struct denali_controller *denali = to_denali_controller(chip); 905 906 if (section > 0) 907 return -ERANGE; 908 909 oobregion->offset = denali->oob_skip_bytes; 910 oobregion->length = chip->ecc.total; 911 912 return 0; 913 } 914 915 static int denali_ooblayout_free(struct mtd_info *mtd, int section, 916 struct mtd_oob_region *oobregion) 917 { 918 struct nand_chip *chip = mtd_to_nand(mtd); 919 struct denali_controller *denali = to_denali_controller(chip); 920 921 if (section > 0) 922 return -ERANGE; 923 924 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; 925 oobregion->length = mtd->oobsize - oobregion->offset; 926 927 return 0; 928 } 929 930 static const struct mtd_ooblayout_ops denali_ooblayout_ops = { 931 .ecc = denali_ooblayout_ecc, 932 .free = denali_ooblayout_free, 933 }; 934 935 static int denali_multidev_fixup(struct nand_chip *chip) 936 { 937 struct denali_controller *denali = to_denali_controller(chip); 938 struct mtd_info *mtd = nand_to_mtd(chip); 939 struct nand_memory_organization *memorg; 940 941 memorg = nanddev_get_memorg(&chip->base); 942 943 /* 944 * Support for multi device: 945 * When the IP configuration is x16 capable and two x8 chips are 946 * connected in parallel, DEVICES_CONNECTED should be set to 2. 947 * In this case, the core framework knows nothing about this fact, 948 * so we should tell it the _logical_ pagesize and anything necessary. 949 */ 950 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); 951 952 /* 953 * On some SoCs, DEVICES_CONNECTED is not auto-detected. 954 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case. 955 */ 956 if (denali->devs_per_cs == 0) { 957 denali->devs_per_cs = 1; 958 iowrite32(1, denali->reg + DEVICES_CONNECTED); 959 } 960 961 if (denali->devs_per_cs == 1) 962 return 0; 963 964 if (denali->devs_per_cs != 2) { 965 dev_err(denali->dev, "unsupported number of devices %d\n", 966 denali->devs_per_cs); 967 return -EINVAL; 968 } 969 970 /* 2 chips in parallel */ 971 memorg->pagesize <<= 1; 972 memorg->oobsize <<= 1; 973 mtd->size <<= 1; 974 mtd->erasesize <<= 1; 975 mtd->writesize <<= 1; 976 mtd->oobsize <<= 1; 977 chip->page_shift += 1; 978 chip->phys_erase_shift += 1; 979 chip->bbt_erase_shift += 1; 980 chip->chip_shift += 1; 981 chip->pagemask <<= 1; 982 chip->ecc.size <<= 1; 983 chip->ecc.bytes <<= 1; 984 chip->ecc.strength <<= 1; 985 denali->oob_skip_bytes <<= 1; 986 987 return 0; 988 } 989 990 static int denali_attach_chip(struct nand_chip *chip) 991 { 992 struct denali_controller *denali = to_denali_controller(chip); 993 struct mtd_info *mtd = nand_to_mtd(chip); 994 int ret; 995 996 ret = nand_ecc_choose_conf(chip, denali->ecc_caps, 997 mtd->oobsize - denali->oob_skip_bytes); 998 if (ret) { 999 dev_err(denali->dev, "Failed to setup ECC settings.\n"); 1000 return ret; 1001 } 1002 1003 dev_dbg(denali->dev, 1004 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", 1005 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); 1006 1007 ret = denali_multidev_fixup(chip); 1008 if (ret) 1009 return ret; 1010 1011 return 0; 1012 } 1013 1014 static void denali_exec_in8(struct denali_controller *denali, u32 type, 1015 u8 *buf, unsigned int len) 1016 { 1017 int i; 1018 1019 for (i = 0; i < len; i++) 1020 buf[i] = denali->host_read(denali, type | DENALI_BANK(denali)); 1021 } 1022 1023 static void denali_exec_in16(struct denali_controller *denali, u32 type, 1024 u8 *buf, unsigned int len) 1025 { 1026 u32 data; 1027 int i; 1028 1029 for (i = 0; i < len; i += 2) { 1030 data = denali->host_read(denali, type | DENALI_BANK(denali)); 1031 /* bit 31:24 and 15:8 are used for DDR */ 1032 buf[i] = data; 1033 buf[i + 1] = data >> 16; 1034 } 1035 } 1036 1037 static void denali_exec_in(struct denali_controller *denali, u32 type, 1038 u8 *buf, unsigned int len, bool width16) 1039 { 1040 if (width16) 1041 denali_exec_in16(denali, type, buf, len); 1042 else 1043 denali_exec_in8(denali, type, buf, len); 1044 } 1045 1046 static void denali_exec_out8(struct denali_controller *denali, u32 type, 1047 const u8 *buf, unsigned int len) 1048 { 1049 int i; 1050 1051 for (i = 0; i < len; i++) 1052 denali->host_write(denali, type | DENALI_BANK(denali), buf[i]); 1053 } 1054 1055 static void denali_exec_out16(struct denali_controller *denali, u32 type, 1056 const u8 *buf, unsigned int len) 1057 { 1058 int i; 1059 1060 for (i = 0; i < len; i += 2) 1061 denali->host_write(denali, type | DENALI_BANK(denali), 1062 buf[i + 1] << 16 | buf[i]); 1063 } 1064 1065 static void denali_exec_out(struct denali_controller *denali, u32 type, 1066 const u8 *buf, unsigned int len, bool width16) 1067 { 1068 if (width16) 1069 denali_exec_out16(denali, type, buf, len); 1070 else 1071 denali_exec_out8(denali, type, buf, len); 1072 } 1073 1074 static int denali_exec_waitrdy(struct denali_controller *denali) 1075 { 1076 u32 irq_stat; 1077 1078 /* R/B# pin transitioned from low to high? */ 1079 irq_stat = denali_wait_for_irq(denali, INTR__INT_ACT); 1080 1081 /* Just in case nand_operation has multiple NAND_OP_WAITRDY_INSTR. */ 1082 denali_reset_irq(denali); 1083 1084 return irq_stat & INTR__INT_ACT ? 0 : -EIO; 1085 } 1086 1087 static int denali_exec_instr(struct nand_chip *chip, 1088 const struct nand_op_instr *instr) 1089 { 1090 struct denali_controller *denali = to_denali_controller(chip); 1091 1092 switch (instr->type) { 1093 case NAND_OP_CMD_INSTR: 1094 denali_exec_out8(denali, DENALI_MAP11_CMD, 1095 &instr->ctx.cmd.opcode, 1); 1096 return 0; 1097 case NAND_OP_ADDR_INSTR: 1098 denali_exec_out8(denali, DENALI_MAP11_ADDR, 1099 instr->ctx.addr.addrs, 1100 instr->ctx.addr.naddrs); 1101 return 0; 1102 case NAND_OP_DATA_IN_INSTR: 1103 denali_exec_in(denali, DENALI_MAP11_DATA, 1104 instr->ctx.data.buf.in, 1105 instr->ctx.data.len, 1106 !instr->ctx.data.force_8bit && 1107 chip->options & NAND_BUSWIDTH_16); 1108 return 0; 1109 case NAND_OP_DATA_OUT_INSTR: 1110 denali_exec_out(denali, DENALI_MAP11_DATA, 1111 instr->ctx.data.buf.out, 1112 instr->ctx.data.len, 1113 !instr->ctx.data.force_8bit && 1114 chip->options & NAND_BUSWIDTH_16); 1115 return 0; 1116 case NAND_OP_WAITRDY_INSTR: 1117 return denali_exec_waitrdy(denali); 1118 default: 1119 WARN_ONCE(1, "unsupported NAND instruction type: %d\n", 1120 instr->type); 1121 1122 return -EINVAL; 1123 } 1124 } 1125 1126 static int denali_exec_op(struct nand_chip *chip, 1127 const struct nand_operation *op, bool check_only) 1128 { 1129 int i, ret; 1130 1131 if (check_only) 1132 return 0; 1133 1134 denali_select_target(chip, op->cs); 1135 1136 /* 1137 * Some commands contain NAND_OP_WAITRDY_INSTR. 1138 * irq must be cleared here to catch the R/B# interrupt there. 1139 */ 1140 denali_reset_irq(to_denali_controller(chip)); 1141 1142 for (i = 0; i < op->ninstrs; i++) { 1143 ret = denali_exec_instr(chip, &op->instrs[i]); 1144 if (ret) 1145 return ret; 1146 } 1147 1148 return 0; 1149 } 1150 1151 static const struct nand_controller_ops denali_controller_ops = { 1152 .attach_chip = denali_attach_chip, 1153 .exec_op = denali_exec_op, 1154 .setup_data_interface = denali_setup_data_interface, 1155 }; 1156 1157 int denali_chip_init(struct denali_controller *denali, 1158 struct denali_chip *dchip) 1159 { 1160 struct nand_chip *chip = &dchip->chip; 1161 struct mtd_info *mtd = nand_to_mtd(chip); 1162 struct denali_chip *dchip2; 1163 int i, j, ret; 1164 1165 chip->controller = &denali->controller; 1166 1167 /* sanity checks for bank numbers */ 1168 for (i = 0; i < dchip->nsels; i++) { 1169 unsigned int bank = dchip->sels[i].bank; 1170 1171 if (bank >= denali->nbanks) { 1172 dev_err(denali->dev, "unsupported bank %d\n", bank); 1173 return -EINVAL; 1174 } 1175 1176 for (j = 0; j < i; j++) { 1177 if (bank == dchip->sels[j].bank) { 1178 dev_err(denali->dev, 1179 "bank %d is assigned twice in the same chip\n", 1180 bank); 1181 return -EINVAL; 1182 } 1183 } 1184 1185 list_for_each_entry(dchip2, &denali->chips, node) { 1186 for (j = 0; j < dchip2->nsels; j++) { 1187 if (bank == dchip2->sels[j].bank) { 1188 dev_err(denali->dev, 1189 "bank %d is already used\n", 1190 bank); 1191 return -EINVAL; 1192 } 1193 } 1194 } 1195 } 1196 1197 mtd->dev.parent = denali->dev; 1198 1199 /* 1200 * Fallback to the default name if DT did not give "label" property. 1201 * Use "label" property if multiple chips are connected. 1202 */ 1203 if (!mtd->name && list_empty(&denali->chips)) 1204 mtd->name = "denali-nand"; 1205 1206 if (denali->dma_avail) { 1207 chip->options |= NAND_USE_BOUNCE_BUFFER; 1208 chip->buf_align = 16; 1209 } 1210 1211 /* clk rate info is needed for setup_data_interface */ 1212 if (!denali->clk_rate || !denali->clk_x_rate) 1213 chip->options |= NAND_KEEP_TIMINGS; 1214 1215 chip->bbt_options |= NAND_BBT_USE_FLASH; 1216 chip->bbt_options |= NAND_BBT_NO_OOB; 1217 chip->options |= NAND_NO_SUBPAGE_WRITE; 1218 chip->ecc.mode = NAND_ECC_HW_SYNDROME; 1219 chip->ecc.read_page = denali_read_page; 1220 chip->ecc.write_page = denali_write_page; 1221 chip->ecc.read_page_raw = denali_read_page_raw; 1222 chip->ecc.write_page_raw = denali_write_page_raw; 1223 chip->ecc.read_oob = denali_read_oob; 1224 chip->ecc.write_oob = denali_write_oob; 1225 1226 mtd_set_ooblayout(mtd, &denali_ooblayout_ops); 1227 1228 ret = nand_scan(chip, dchip->nsels); 1229 if (ret) 1230 return ret; 1231 1232 ret = mtd_device_register(mtd, NULL, 0); 1233 if (ret) { 1234 dev_err(denali->dev, "Failed to register MTD: %d\n", ret); 1235 goto cleanup_nand; 1236 } 1237 1238 list_add_tail(&dchip->node, &denali->chips); 1239 1240 return 0; 1241 1242 cleanup_nand: 1243 nand_cleanup(chip); 1244 1245 return ret; 1246 } 1247 EXPORT_SYMBOL_GPL(denali_chip_init); 1248 1249 int denali_init(struct denali_controller *denali) 1250 { 1251 u32 features = ioread32(denali->reg + FEATURES); 1252 int ret; 1253 1254 nand_controller_init(&denali->controller); 1255 denali->controller.ops = &denali_controller_ops; 1256 init_completion(&denali->complete); 1257 spin_lock_init(&denali->irq_lock); 1258 INIT_LIST_HEAD(&denali->chips); 1259 denali->active_bank = DENALI_INVALID_BANK; 1260 1261 /* 1262 * The REVISION register may not be reliable. Platforms are allowed to 1263 * override it. 1264 */ 1265 if (!denali->revision) 1266 denali->revision = swab16(ioread32(denali->reg + REVISION)); 1267 1268 denali->nbanks = 1 << FIELD_GET(FEATURES__N_BANKS, features); 1269 1270 /* the encoding changed from rev 5.0 to 5.1 */ 1271 if (denali->revision < 0x0501) 1272 denali->nbanks <<= 1; 1273 1274 if (features & FEATURES__DMA) 1275 denali->dma_avail = true; 1276 1277 if (denali->dma_avail) { 1278 int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32; 1279 1280 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit)); 1281 if (ret) { 1282 dev_info(denali->dev, 1283 "Failed to set DMA mask. Disabling DMA.\n"); 1284 denali->dma_avail = false; 1285 } 1286 } 1287 1288 if (denali->dma_avail) { 1289 if (denali->caps & DENALI_CAP_DMA_64BIT) 1290 denali->setup_dma = denali_setup_dma64; 1291 else 1292 denali->setup_dma = denali_setup_dma32; 1293 } 1294 1295 if (features & FEATURES__INDEX_ADDR) { 1296 denali->host_read = denali_indexed_read; 1297 denali->host_write = denali_indexed_write; 1298 } else { 1299 denali->host_read = denali_direct_read; 1300 denali->host_write = denali_direct_write; 1301 } 1302 1303 /* 1304 * Set how many bytes should be skipped before writing data in OOB. 1305 * If a non-zero value has already been set (by firmware or something), 1306 * just use it. Otherwise, set the driver's default. 1307 */ 1308 denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES); 1309 if (!denali->oob_skip_bytes) { 1310 denali->oob_skip_bytes = DENALI_DEFAULT_OOB_SKIP_BYTES; 1311 iowrite32(denali->oob_skip_bytes, 1312 denali->reg + SPARE_AREA_SKIP_BYTES); 1313 } 1314 1315 iowrite32(0, denali->reg + TRANSFER_SPARE_REG); 1316 iowrite32(GENMASK(denali->nbanks - 1, 0), denali->reg + RB_PIN_ENABLED); 1317 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); 1318 iowrite32(ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); 1319 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); 1320 1321 denali_clear_irq_all(denali); 1322 1323 ret = devm_request_irq(denali->dev, denali->irq, denali_isr, 1324 IRQF_SHARED, DENALI_NAND_NAME, denali); 1325 if (ret) { 1326 dev_err(denali->dev, "Unable to request IRQ\n"); 1327 return ret; 1328 } 1329 1330 denali_enable_irq(denali); 1331 1332 return 0; 1333 } 1334 EXPORT_SYMBOL(denali_init); 1335 1336 void denali_remove(struct denali_controller *denali) 1337 { 1338 struct denali_chip *dchip; 1339 1340 list_for_each_entry(dchip, &denali->chips, node) 1341 nand_release(&dchip->chip); 1342 1343 denali_disable_irq(denali); 1344 } 1345 EXPORT_SYMBOL(denali_remove); 1346 1347 MODULE_DESCRIPTION("Driver core for Denali NAND controller"); 1348 MODULE_AUTHOR("Intel Corporation and its suppliers"); 1349 MODULE_LICENSE("GPL v2"); 1350