1 /* 2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01 3 * 4 * The data sheet for this device can be found at: 5 * http://wiki.laptop.org/go/Datasheets 6 * 7 * Copyright © 2006 Red Hat, Inc. 8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> 9 */ 10 11 #define DEBUG 12 13 #include <linux/device.h> 14 #undef DEBUG 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/rawnand.h> 17 #include <linux/mtd/partitions.h> 18 #include <linux/rslib.h> 19 #include <linux/pci.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <asm/io.h> 26 27 #define CAFE_NAND_CTRL1 0x00 28 #define CAFE_NAND_CTRL2 0x04 29 #define CAFE_NAND_CTRL3 0x08 30 #define CAFE_NAND_STATUS 0x0c 31 #define CAFE_NAND_IRQ 0x10 32 #define CAFE_NAND_IRQ_MASK 0x14 33 #define CAFE_NAND_DATA_LEN 0x18 34 #define CAFE_NAND_ADDR1 0x1c 35 #define CAFE_NAND_ADDR2 0x20 36 #define CAFE_NAND_TIMING1 0x24 37 #define CAFE_NAND_TIMING2 0x28 38 #define CAFE_NAND_TIMING3 0x2c 39 #define CAFE_NAND_NONMEM 0x30 40 #define CAFE_NAND_ECC_RESULT 0x3C 41 #define CAFE_NAND_DMA_CTRL 0x40 42 #define CAFE_NAND_DMA_ADDR0 0x44 43 #define CAFE_NAND_DMA_ADDR1 0x48 44 #define CAFE_NAND_ECC_SYN01 0x50 45 #define CAFE_NAND_ECC_SYN23 0x54 46 #define CAFE_NAND_ECC_SYN45 0x58 47 #define CAFE_NAND_ECC_SYN67 0x5c 48 #define CAFE_NAND_READ_DATA 0x1000 49 #define CAFE_NAND_WRITE_DATA 0x2000 50 51 #define CAFE_GLOBAL_CTRL 0x3004 52 #define CAFE_GLOBAL_IRQ 0x3008 53 #define CAFE_GLOBAL_IRQ_MASK 0x300c 54 #define CAFE_NAND_RESET 0x3034 55 56 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */ 57 #define CTRL1_CHIPSELECT (1<<19) 58 59 struct cafe_priv { 60 struct nand_chip nand; 61 struct pci_dev *pdev; 62 void __iomem *mmio; 63 struct rs_control *rs; 64 uint32_t ctl1; 65 uint32_t ctl2; 66 int datalen; 67 int nr_data; 68 int data_pos; 69 int page_addr; 70 dma_addr_t dmaaddr; 71 unsigned char *dmabuf; 72 }; 73 74 static int usedma = 1; 75 module_param(usedma, int, 0644); 76 77 static int skipbbt = 0; 78 module_param(skipbbt, int, 0644); 79 80 static int debug = 0; 81 module_param(debug, int, 0644); 82 83 static int regdebug = 0; 84 module_param(regdebug, int, 0644); 85 86 static int checkecc = 1; 87 module_param(checkecc, int, 0644); 88 89 static unsigned int numtimings; 90 static int timing[3]; 91 module_param_array(timing, int, &numtimings, 0644); 92 93 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; 94 95 /* Hrm. Why isn't this already conditional on something in the struct device? */ 96 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) 97 98 /* Make it easier to switch to PIO if we need to */ 99 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr) 100 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr) 101 102 static int cafe_device_ready(struct mtd_info *mtd) 103 { 104 struct nand_chip *chip = mtd_to_nand(mtd); 105 struct cafe_priv *cafe = nand_get_controller_data(chip); 106 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000); 107 uint32_t irqs = cafe_readl(cafe, NAND_IRQ); 108 109 cafe_writel(cafe, irqs, NAND_IRQ); 110 111 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", 112 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ), 113 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK)); 114 115 return result; 116 } 117 118 119 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 120 { 121 struct nand_chip *chip = mtd_to_nand(mtd); 122 struct cafe_priv *cafe = nand_get_controller_data(chip); 123 124 if (usedma) 125 memcpy(cafe->dmabuf + cafe->datalen, buf, len); 126 else 127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); 128 129 cafe->datalen += len; 130 131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n", 132 len, cafe->datalen); 133 } 134 135 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 136 { 137 struct nand_chip *chip = mtd_to_nand(mtd); 138 struct cafe_priv *cafe = nand_get_controller_data(chip); 139 140 if (usedma) 141 memcpy(buf, cafe->dmabuf + cafe->datalen, len); 142 else 143 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len); 144 145 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n", 146 len, cafe->datalen); 147 cafe->datalen += len; 148 } 149 150 static uint8_t cafe_read_byte(struct mtd_info *mtd) 151 { 152 struct nand_chip *chip = mtd_to_nand(mtd); 153 struct cafe_priv *cafe = nand_get_controller_data(chip); 154 uint8_t d; 155 156 cafe_read_buf(mtd, &d, 1); 157 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d); 158 159 return d; 160 } 161 162 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command, 163 int column, int page_addr) 164 { 165 struct nand_chip *chip = mtd_to_nand(mtd); 166 struct cafe_priv *cafe = nand_get_controller_data(chip); 167 int adrbytes = 0; 168 uint32_t ctl1; 169 uint32_t doneint = 0x80000000; 170 171 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n", 172 command, column, page_addr); 173 174 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) { 175 /* Second half of a command we already calculated */ 176 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); 177 ctl1 = cafe->ctl1; 178 cafe->ctl2 &= ~(1<<30); 179 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n", 180 cafe->ctl1, cafe->nr_data); 181 goto do_command; 182 } 183 /* Reset ECC engine */ 184 cafe_writel(cafe, 0, NAND_CTRL2); 185 186 /* Emulate NAND_CMD_READOOB on large-page chips */ 187 if (mtd->writesize > 512 && 188 command == NAND_CMD_READOOB) { 189 column += mtd->writesize; 190 command = NAND_CMD_READ0; 191 } 192 193 /* FIXME: Do we need to send read command before sending data 194 for small-page chips, to position the buffer correctly? */ 195 196 if (column != -1) { 197 cafe_writel(cafe, column, NAND_ADDR1); 198 adrbytes = 2; 199 if (page_addr != -1) 200 goto write_adr2; 201 } else if (page_addr != -1) { 202 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1); 203 page_addr >>= 16; 204 write_adr2: 205 cafe_writel(cafe, page_addr, NAND_ADDR2); 206 adrbytes += 2; 207 if (mtd->size > mtd->writesize << 16) 208 adrbytes++; 209 } 210 211 cafe->data_pos = cafe->datalen = 0; 212 213 /* Set command valid bit, mask in the chip select bit */ 214 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT); 215 216 /* Set RD or WR bits as appropriate */ 217 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) { 218 ctl1 |= (1<<26); /* rd */ 219 /* Always 5 bytes, for now */ 220 cafe->datalen = 4; 221 /* And one address cycle -- even for STATUS, since the controller doesn't work without */ 222 adrbytes = 1; 223 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || 224 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) { 225 ctl1 |= 1<<26; /* rd */ 226 /* For now, assume just read to end of page */ 227 cafe->datalen = mtd->writesize + mtd->oobsize - column; 228 } else if (command == NAND_CMD_SEQIN) 229 ctl1 |= 1<<25; /* wr */ 230 231 /* Set number of address bytes */ 232 if (adrbytes) 233 ctl1 |= ((adrbytes-1)|8) << 27; 234 235 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) { 236 /* Ignore the first command of a pair; the hardware 237 deals with them both at once, later */ 238 cafe->ctl1 = ctl1; 239 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n", 240 cafe->ctl1, cafe->datalen); 241 return; 242 } 243 /* RNDOUT and READ0 commands need a following byte */ 244 if (command == NAND_CMD_RNDOUT) 245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); 246 else if (command == NAND_CMD_READ0 && mtd->writesize > 512) 247 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); 248 249 do_command: 250 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", 251 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2)); 252 253 /* NB: The datasheet lies -- we really should be subtracting 1 here */ 254 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN); 255 cafe_writel(cafe, 0x90000000, NAND_IRQ); 256 if (usedma && (ctl1 & (3<<25))) { 257 uint32_t dmactl = 0xc0000000 + cafe->datalen; 258 /* If WR or RD bits set, set up DMA */ 259 if (ctl1 & (1<<26)) { 260 /* It's a read */ 261 dmactl |= (1<<29); 262 /* ... so it's done when the DMA is done, not just 263 the command. */ 264 doneint = 0x10000000; 265 } 266 cafe_writel(cafe, dmactl, NAND_DMA_CTRL); 267 } 268 cafe->datalen = 0; 269 270 if (unlikely(regdebug)) { 271 int i; 272 printk("About to write command %08x to register 0\n", ctl1); 273 for (i=4; i< 0x5c; i+=4) 274 printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); 275 } 276 277 cafe_writel(cafe, ctl1, NAND_CTRL1); 278 /* Apply this short delay always to ensure that we do wait tWB in 279 * any case on any machine. */ 280 ndelay(100); 281 282 if (1) { 283 int c; 284 uint32_t irqs; 285 286 for (c = 500000; c != 0; c--) { 287 irqs = cafe_readl(cafe, NAND_IRQ); 288 if (irqs & doneint) 289 break; 290 udelay(1); 291 if (!(c % 100000)) 292 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs); 293 cpu_relax(); 294 } 295 cafe_writel(cafe, doneint, NAND_IRQ); 296 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", 297 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ)); 298 } 299 300 WARN_ON(cafe->ctl2 & (1<<30)); 301 302 switch (command) { 303 304 case NAND_CMD_CACHEDPROG: 305 case NAND_CMD_PAGEPROG: 306 case NAND_CMD_ERASE1: 307 case NAND_CMD_ERASE2: 308 case NAND_CMD_SEQIN: 309 case NAND_CMD_RNDIN: 310 case NAND_CMD_STATUS: 311 case NAND_CMD_RNDOUT: 312 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); 313 return; 314 } 315 nand_wait_ready(mtd); 316 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); 317 } 318 319 static void cafe_select_chip(struct mtd_info *mtd, int chipnr) 320 { 321 struct nand_chip *chip = mtd_to_nand(mtd); 322 struct cafe_priv *cafe = nand_get_controller_data(chip); 323 324 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr); 325 326 /* Mask the appropriate bit into the stored value of ctl1 327 which will be used by cafe_nand_cmdfunc() */ 328 if (chipnr) 329 cafe->ctl1 |= CTRL1_CHIPSELECT; 330 else 331 cafe->ctl1 &= ~CTRL1_CHIPSELECT; 332 } 333 334 static irqreturn_t cafe_nand_interrupt(int irq, void *id) 335 { 336 struct mtd_info *mtd = id; 337 struct nand_chip *chip = mtd_to_nand(mtd); 338 struct cafe_priv *cafe = nand_get_controller_data(chip); 339 uint32_t irqs = cafe_readl(cafe, NAND_IRQ); 340 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ); 341 if (!irqs) 342 return IRQ_NONE; 343 344 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ)); 345 return IRQ_HANDLED; 346 } 347 348 static void cafe_nand_bug(struct mtd_info *mtd) 349 { 350 BUG(); 351 } 352 353 static int cafe_nand_write_oob(struct mtd_info *mtd, 354 struct nand_chip *chip, int page) 355 { 356 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, 357 mtd->oobsize); 358 } 359 360 /* Don't use -- use nand_read_oob_std for now */ 361 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 362 int page) 363 { 364 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 365 } 366 /** 367 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read 368 * @mtd: mtd info structure 369 * @chip: nand chip info structure 370 * @buf: buffer to store read data 371 * @oob_required: caller expects OOB data read to chip->oob_poi 372 * 373 * The hw generator calculates the error syndrome automatically. Therefore 374 * we need a special oob layout and handling. 375 */ 376 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, 377 uint8_t *buf, int oob_required, int page) 378 { 379 struct cafe_priv *cafe = nand_get_controller_data(chip); 380 unsigned int max_bitflips = 0; 381 382 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", 383 cafe_readl(cafe, NAND_ECC_RESULT), 384 cafe_readl(cafe, NAND_ECC_SYN01)); 385 386 nand_read_page_op(chip, page, 0, buf, mtd->writesize); 387 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 388 389 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) { 390 unsigned short syn[8], pat[4]; 391 int pos[4]; 392 u8 *oob = chip->oob_poi; 393 int i, n; 394 395 for (i=0; i<8; i+=2) { 396 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2)); 397 398 syn[i] = cafe->rs->codec->index_of[tmp & 0xfff]; 399 syn[i+1] = cafe->rs->codec->index_of[(tmp >> 16) & 0xfff]; 400 } 401 402 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0, 403 pat); 404 405 for (i = 0; i < n; i++) { 406 int p = pos[i]; 407 408 /* The 12-bit symbols are mapped to bytes here */ 409 410 if (p > 1374) { 411 /* out of range */ 412 n = -1374; 413 } else if (p == 0) { 414 /* high four bits do not correspond to data */ 415 if (pat[i] > 0xff) 416 n = -2048; 417 else 418 buf[0] ^= pat[i]; 419 } else if (p == 1365) { 420 buf[2047] ^= pat[i] >> 4; 421 oob[0] ^= pat[i] << 4; 422 } else if (p > 1365) { 423 if ((p & 1) == 1) { 424 oob[3*p/2 - 2048] ^= pat[i] >> 4; 425 oob[3*p/2 - 2047] ^= pat[i] << 4; 426 } else { 427 oob[3*p/2 - 2049] ^= pat[i] >> 8; 428 oob[3*p/2 - 2048] ^= pat[i]; 429 } 430 } else if ((p & 1) == 1) { 431 buf[3*p/2] ^= pat[i] >> 4; 432 buf[3*p/2 + 1] ^= pat[i] << 4; 433 } else { 434 buf[3*p/2 - 1] ^= pat[i] >> 8; 435 buf[3*p/2] ^= pat[i]; 436 } 437 } 438 439 if (n < 0) { 440 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n", 441 cafe_readl(cafe, NAND_ADDR2) * 2048); 442 for (i = 0; i < 0x5c; i += 4) 443 printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); 444 mtd->ecc_stats.failed++; 445 } else { 446 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n); 447 mtd->ecc_stats.corrected += n; 448 max_bitflips = max_t(unsigned int, max_bitflips, n); 449 } 450 } 451 452 return max_bitflips; 453 } 454 455 static int cafe_ooblayout_ecc(struct mtd_info *mtd, int section, 456 struct mtd_oob_region *oobregion) 457 { 458 struct nand_chip *chip = mtd_to_nand(mtd); 459 460 if (section) 461 return -ERANGE; 462 463 oobregion->offset = 0; 464 oobregion->length = chip->ecc.total; 465 466 return 0; 467 } 468 469 static int cafe_ooblayout_free(struct mtd_info *mtd, int section, 470 struct mtd_oob_region *oobregion) 471 { 472 struct nand_chip *chip = mtd_to_nand(mtd); 473 474 if (section) 475 return -ERANGE; 476 477 oobregion->offset = chip->ecc.total; 478 oobregion->length = mtd->oobsize - chip->ecc.total; 479 480 return 0; 481 } 482 483 static const struct mtd_ooblayout_ops cafe_ooblayout_ops = { 484 .ecc = cafe_ooblayout_ecc, 485 .free = cafe_ooblayout_free, 486 }; 487 488 /* Ick. The BBT code really ought to be able to work this bit out 489 for itself from the above, at least for the 2KiB case */ 490 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' }; 491 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' }; 492 493 static uint8_t cafe_bbt_pattern_512[] = { 0xBB }; 494 static uint8_t cafe_mirror_pattern_512[] = { 0xBC }; 495 496 497 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = { 498 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 499 | NAND_BBT_2BIT | NAND_BBT_VERSION, 500 .offs = 14, 501 .len = 4, 502 .veroffs = 18, 503 .maxblocks = 4, 504 .pattern = cafe_bbt_pattern_2048 505 }; 506 507 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = { 508 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 509 | NAND_BBT_2BIT | NAND_BBT_VERSION, 510 .offs = 14, 511 .len = 4, 512 .veroffs = 18, 513 .maxblocks = 4, 514 .pattern = cafe_mirror_pattern_2048 515 }; 516 517 static struct nand_bbt_descr cafe_bbt_main_descr_512 = { 518 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 519 | NAND_BBT_2BIT | NAND_BBT_VERSION, 520 .offs = 14, 521 .len = 1, 522 .veroffs = 15, 523 .maxblocks = 4, 524 .pattern = cafe_bbt_pattern_512 525 }; 526 527 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = { 528 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 529 | NAND_BBT_2BIT | NAND_BBT_VERSION, 530 .offs = 14, 531 .len = 1, 532 .veroffs = 15, 533 .maxblocks = 4, 534 .pattern = cafe_mirror_pattern_512 535 }; 536 537 538 static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd, 539 struct nand_chip *chip, 540 const uint8_t *buf, int oob_required, 541 int page) 542 { 543 struct cafe_priv *cafe = nand_get_controller_data(chip); 544 545 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); 546 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 547 548 /* Set up ECC autogeneration */ 549 cafe->ctl2 |= (1<<30); 550 551 return nand_prog_page_end_op(chip); 552 } 553 554 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs) 555 { 556 return 0; 557 } 558 559 /* F_2[X]/(X**6+X+1) */ 560 static unsigned short gf64_mul(u8 a, u8 b) 561 { 562 u8 c; 563 unsigned int i; 564 565 c = 0; 566 for (i = 0; i < 6; i++) { 567 if (a & 1) 568 c ^= b; 569 a >>= 1; 570 b <<= 1; 571 if ((b & 0x40) != 0) 572 b ^= 0x43; 573 } 574 575 return c; 576 } 577 578 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */ 579 static u16 gf4096_mul(u16 a, u16 b) 580 { 581 u8 ah, al, bh, bl, ch, cl; 582 583 ah = a >> 6; 584 al = a & 0x3f; 585 bh = b >> 6; 586 bl = b & 0x3f; 587 588 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl); 589 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl); 590 591 return (ch << 6) ^ cl; 592 } 593 594 static int cafe_mul(int x) 595 { 596 if (x == 0) 597 return 1; 598 return gf4096_mul(x, 0xe01); 599 } 600 601 static int cafe_nand_probe(struct pci_dev *pdev, 602 const struct pci_device_id *ent) 603 { 604 struct mtd_info *mtd; 605 struct cafe_priv *cafe; 606 uint32_t ctrl; 607 int err = 0; 608 int old_dma; 609 610 /* Very old versions shared the same PCI ident for all three 611 functions on the chip. Verify the class too... */ 612 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH) 613 return -ENODEV; 614 615 err = pci_enable_device(pdev); 616 if (err) 617 return err; 618 619 pci_set_master(pdev); 620 621 cafe = kzalloc(sizeof(*cafe), GFP_KERNEL); 622 if (!cafe) 623 return -ENOMEM; 624 625 mtd = nand_to_mtd(&cafe->nand); 626 mtd->dev.parent = &pdev->dev; 627 nand_set_controller_data(&cafe->nand, cafe); 628 629 cafe->pdev = pdev; 630 cafe->mmio = pci_iomap(pdev, 0, 0); 631 if (!cafe->mmio) { 632 dev_warn(&pdev->dev, "failed to iomap\n"); 633 err = -ENOMEM; 634 goto out_free_mtd; 635 } 636 637 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8); 638 if (!cafe->rs) { 639 err = -ENOMEM; 640 goto out_ior; 641 } 642 643 cafe->nand.cmdfunc = cafe_nand_cmdfunc; 644 cafe->nand.dev_ready = cafe_device_ready; 645 cafe->nand.read_byte = cafe_read_byte; 646 cafe->nand.read_buf = cafe_read_buf; 647 cafe->nand.write_buf = cafe_write_buf; 648 cafe->nand.select_chip = cafe_select_chip; 649 cafe->nand.set_features = nand_get_set_features_notsupp; 650 cafe->nand.get_features = nand_get_set_features_notsupp; 651 652 cafe->nand.chip_delay = 0; 653 654 /* Enable the following for a flash based bad block table */ 655 cafe->nand.bbt_options = NAND_BBT_USE_FLASH; 656 657 if (skipbbt) { 658 cafe->nand.options |= NAND_SKIP_BBTSCAN; 659 cafe->nand.block_bad = cafe_nand_block_bad; 660 } 661 662 if (numtimings && numtimings != 3) { 663 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings); 664 } 665 666 if (numtimings == 3) { 667 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n", 668 timing[0], timing[1], timing[2]); 669 } else { 670 timing[0] = cafe_readl(cafe, NAND_TIMING1); 671 timing[1] = cafe_readl(cafe, NAND_TIMING2); 672 timing[2] = cafe_readl(cafe, NAND_TIMING3); 673 674 if (timing[0] | timing[1] | timing[2]) { 675 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n", 676 timing[0], timing[1], timing[2]); 677 } else { 678 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n"); 679 timing[0] = timing[1] = timing[2] = 0xffffffff; 680 } 681 } 682 683 /* Start off by resetting the NAND controller completely */ 684 cafe_writel(cafe, 1, NAND_RESET); 685 cafe_writel(cafe, 0, NAND_RESET); 686 687 cafe_writel(cafe, timing[0], NAND_TIMING1); 688 cafe_writel(cafe, timing[1], NAND_TIMING2); 689 cafe_writel(cafe, timing[2], NAND_TIMING3); 690 691 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); 692 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED, 693 "CAFE NAND", mtd); 694 if (err) { 695 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq); 696 goto out_ior; 697 } 698 699 /* Disable master reset, enable NAND clock */ 700 ctrl = cafe_readl(cafe, GLOBAL_CTRL); 701 ctrl &= 0xffffeff0; 702 ctrl |= 0x00007000; 703 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); 704 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); 705 cafe_writel(cafe, 0, NAND_DMA_CTRL); 706 707 cafe_writel(cafe, 0x7006, GLOBAL_CTRL); 708 cafe_writel(cafe, 0x700a, GLOBAL_CTRL); 709 710 /* Enable NAND IRQ in global IRQ mask register */ 711 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); 712 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n", 713 cafe_readl(cafe, GLOBAL_CTRL), 714 cafe_readl(cafe, GLOBAL_IRQ_MASK)); 715 716 /* Do not use the DMA for the nand_scan_ident() */ 717 old_dma = usedma; 718 usedma = 0; 719 720 /* Scan to find existence of the device */ 721 err = nand_scan_ident(mtd, 2, NULL); 722 if (err) 723 goto out_irq; 724 725 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112, 726 &cafe->dmaaddr, GFP_KERNEL); 727 if (!cafe->dmabuf) { 728 err = -ENOMEM; 729 goto out_irq; 730 } 731 732 /* Set up DMA address */ 733 cafe_writel(cafe, lower_32_bits(cafe->dmaaddr), NAND_DMA_ADDR0); 734 cafe_writel(cafe, upper_32_bits(cafe->dmaaddr), NAND_DMA_ADDR1); 735 736 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n", 737 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf); 738 739 /* Restore the DMA flag */ 740 usedma = old_dma; 741 742 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */ 743 if (mtd->writesize == 2048) 744 cafe->ctl2 |= 1<<29; /* 2KiB page size */ 745 746 /* Set up ECC according to the type of chip we found */ 747 mtd_set_ooblayout(mtd, &cafe_ooblayout_ops); 748 if (mtd->writesize == 2048) { 749 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048; 750 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048; 751 } else if (mtd->writesize == 512) { 752 cafe->nand.bbt_td = &cafe_bbt_main_descr_512; 753 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512; 754 } else { 755 pr_warn("Unexpected NAND flash writesize %d. Aborting\n", 756 mtd->writesize); 757 goto out_free_dma; 758 } 759 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 760 cafe->nand.ecc.size = mtd->writesize; 761 cafe->nand.ecc.bytes = 14; 762 cafe->nand.ecc.strength = 4; 763 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug; 764 cafe->nand.ecc.calculate = (void *)cafe_nand_bug; 765 cafe->nand.ecc.correct = (void *)cafe_nand_bug; 766 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel; 767 cafe->nand.ecc.write_oob = cafe_nand_write_oob; 768 cafe->nand.ecc.read_page = cafe_nand_read_page; 769 cafe->nand.ecc.read_oob = cafe_nand_read_oob; 770 771 err = nand_scan_tail(mtd); 772 if (err) 773 goto out_free_dma; 774 775 pci_set_drvdata(pdev, mtd); 776 777 mtd->name = "cafe_nand"; 778 err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0); 779 if (err) 780 goto out_cleanup_nand; 781 782 goto out; 783 784 out_cleanup_nand: 785 nand_cleanup(&cafe->nand); 786 out_free_dma: 787 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); 788 out_irq: 789 /* Disable NAND IRQ in global IRQ mask register */ 790 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); 791 free_irq(pdev->irq, mtd); 792 out_ior: 793 pci_iounmap(pdev, cafe->mmio); 794 out_free_mtd: 795 kfree(cafe); 796 out: 797 return err; 798 } 799 800 static void cafe_nand_remove(struct pci_dev *pdev) 801 { 802 struct mtd_info *mtd = pci_get_drvdata(pdev); 803 struct nand_chip *chip = mtd_to_nand(mtd); 804 struct cafe_priv *cafe = nand_get_controller_data(chip); 805 806 /* Disable NAND IRQ in global IRQ mask register */ 807 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); 808 free_irq(pdev->irq, mtd); 809 nand_release(mtd); 810 free_rs(cafe->rs); 811 pci_iounmap(pdev, cafe->mmio); 812 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); 813 kfree(cafe); 814 } 815 816 static const struct pci_device_id cafe_nand_tbl[] = { 817 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND, 818 PCI_ANY_ID, PCI_ANY_ID }, 819 { } 820 }; 821 822 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); 823 824 static int cafe_nand_resume(struct pci_dev *pdev) 825 { 826 uint32_t ctrl; 827 struct mtd_info *mtd = pci_get_drvdata(pdev); 828 struct nand_chip *chip = mtd_to_nand(mtd); 829 struct cafe_priv *cafe = nand_get_controller_data(chip); 830 831 /* Start off by resetting the NAND controller completely */ 832 cafe_writel(cafe, 1, NAND_RESET); 833 cafe_writel(cafe, 0, NAND_RESET); 834 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); 835 836 /* Restore timing configuration */ 837 cafe_writel(cafe, timing[0], NAND_TIMING1); 838 cafe_writel(cafe, timing[1], NAND_TIMING2); 839 cafe_writel(cafe, timing[2], NAND_TIMING3); 840 841 /* Disable master reset, enable NAND clock */ 842 ctrl = cafe_readl(cafe, GLOBAL_CTRL); 843 ctrl &= 0xffffeff0; 844 ctrl |= 0x00007000; 845 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); 846 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); 847 cafe_writel(cafe, 0, NAND_DMA_CTRL); 848 cafe_writel(cafe, 0x7006, GLOBAL_CTRL); 849 cafe_writel(cafe, 0x700a, GLOBAL_CTRL); 850 851 /* Set up DMA address */ 852 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); 853 if (sizeof(cafe->dmaaddr) > 4) 854 /* Shift in two parts to shut the compiler up */ 855 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); 856 else 857 cafe_writel(cafe, 0, NAND_DMA_ADDR1); 858 859 /* Enable NAND IRQ in global IRQ mask register */ 860 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); 861 return 0; 862 } 863 864 static struct pci_driver cafe_nand_pci_driver = { 865 .name = "CAFÉ NAND", 866 .id_table = cafe_nand_tbl, 867 .probe = cafe_nand_probe, 868 .remove = cafe_nand_remove, 869 .resume = cafe_nand_resume, 870 }; 871 872 module_pci_driver(cafe_nand_pci_driver); 873 874 MODULE_LICENSE("GPL"); 875 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); 876 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip"); 877