193db446aSBoris Brezillon /* 293db446aSBoris Brezillon * Copyright © 2010-2015 Broadcom Corporation 393db446aSBoris Brezillon * 493db446aSBoris Brezillon * This program is free software; you can redistribute it and/or modify 593db446aSBoris Brezillon * it under the terms of the GNU General Public License version 2 as 693db446aSBoris Brezillon * published by the Free Software Foundation. 793db446aSBoris Brezillon * 893db446aSBoris Brezillon * This program is distributed in the hope that it will be useful, 993db446aSBoris Brezillon * but WITHOUT ANY WARRANTY; without even the implied warranty of 1093db446aSBoris Brezillon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1193db446aSBoris Brezillon * GNU General Public License for more details. 1293db446aSBoris Brezillon */ 1393db446aSBoris Brezillon 1493db446aSBoris Brezillon #include <linux/clk.h> 1593db446aSBoris Brezillon #include <linux/version.h> 1693db446aSBoris Brezillon #include <linux/module.h> 1793db446aSBoris Brezillon #include <linux/init.h> 1893db446aSBoris Brezillon #include <linux/delay.h> 1993db446aSBoris Brezillon #include <linux/device.h> 2093db446aSBoris Brezillon #include <linux/platform_device.h> 2193db446aSBoris Brezillon #include <linux/err.h> 2293db446aSBoris Brezillon #include <linux/completion.h> 2393db446aSBoris Brezillon #include <linux/interrupt.h> 2493db446aSBoris Brezillon #include <linux/spinlock.h> 2593db446aSBoris Brezillon #include <linux/dma-mapping.h> 2693db446aSBoris Brezillon #include <linux/ioport.h> 2793db446aSBoris Brezillon #include <linux/bug.h> 2893db446aSBoris Brezillon #include <linux/kernel.h> 2993db446aSBoris Brezillon #include <linux/bitops.h> 3093db446aSBoris Brezillon #include <linux/mm.h> 3193db446aSBoris Brezillon #include <linux/mtd/mtd.h> 3293db446aSBoris Brezillon #include <linux/mtd/rawnand.h> 3393db446aSBoris Brezillon #include <linux/mtd/partitions.h> 3493db446aSBoris Brezillon #include <linux/of.h> 3593db446aSBoris Brezillon #include <linux/of_platform.h> 3693db446aSBoris Brezillon #include <linux/slab.h> 3793db446aSBoris Brezillon #include <linux/list.h> 3893db446aSBoris Brezillon #include <linux/log2.h> 3993db446aSBoris Brezillon 4093db446aSBoris Brezillon #include "brcmnand.h" 4193db446aSBoris Brezillon 4293db446aSBoris Brezillon /* 4393db446aSBoris Brezillon * This flag controls if WP stays on between erase/write commands to mitigate 4493db446aSBoris Brezillon * flash corruption due to power glitches. Values: 4593db446aSBoris Brezillon * 0: NAND_WP is not used or not available 4693db446aSBoris Brezillon * 1: NAND_WP is set by default, cleared for erase/write operations 4793db446aSBoris Brezillon * 2: NAND_WP is always cleared 4893db446aSBoris Brezillon */ 4993db446aSBoris Brezillon static int wp_on = 1; 5093db446aSBoris Brezillon module_param(wp_on, int, 0444); 5193db446aSBoris Brezillon 5293db446aSBoris Brezillon /*********************************************************************** 5393db446aSBoris Brezillon * Definitions 5493db446aSBoris Brezillon ***********************************************************************/ 5593db446aSBoris Brezillon 5693db446aSBoris Brezillon #define DRV_NAME "brcmnand" 5793db446aSBoris Brezillon 5893db446aSBoris Brezillon #define CMD_NULL 0x00 5993db446aSBoris Brezillon #define CMD_PAGE_READ 0x01 6093db446aSBoris Brezillon #define CMD_SPARE_AREA_READ 0x02 6193db446aSBoris Brezillon #define CMD_STATUS_READ 0x03 6293db446aSBoris Brezillon #define CMD_PROGRAM_PAGE 0x04 6393db446aSBoris Brezillon #define CMD_PROGRAM_SPARE_AREA 0x05 6493db446aSBoris Brezillon #define CMD_COPY_BACK 0x06 6593db446aSBoris Brezillon #define CMD_DEVICE_ID_READ 0x07 6693db446aSBoris Brezillon #define CMD_BLOCK_ERASE 0x08 6793db446aSBoris Brezillon #define CMD_FLASH_RESET 0x09 6893db446aSBoris Brezillon #define CMD_BLOCKS_LOCK 0x0a 6993db446aSBoris Brezillon #define CMD_BLOCKS_LOCK_DOWN 0x0b 7093db446aSBoris Brezillon #define CMD_BLOCKS_UNLOCK 0x0c 7193db446aSBoris Brezillon #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d 7293db446aSBoris Brezillon #define CMD_PARAMETER_READ 0x0e 7393db446aSBoris Brezillon #define CMD_PARAMETER_CHANGE_COL 0x0f 7493db446aSBoris Brezillon #define CMD_LOW_LEVEL_OP 0x10 7593db446aSBoris Brezillon 7693db446aSBoris Brezillon struct brcm_nand_dma_desc { 7793db446aSBoris Brezillon u32 next_desc; 7893db446aSBoris Brezillon u32 next_desc_ext; 7993db446aSBoris Brezillon u32 cmd_irq; 8093db446aSBoris Brezillon u32 dram_addr; 8193db446aSBoris Brezillon u32 dram_addr_ext; 8293db446aSBoris Brezillon u32 tfr_len; 8393db446aSBoris Brezillon u32 total_len; 8493db446aSBoris Brezillon u32 flash_addr; 8593db446aSBoris Brezillon u32 flash_addr_ext; 8693db446aSBoris Brezillon u32 cs; 8793db446aSBoris Brezillon u32 pad2[5]; 8893db446aSBoris Brezillon u32 status_valid; 8993db446aSBoris Brezillon } __packed; 9093db446aSBoris Brezillon 9193db446aSBoris Brezillon /* Bitfields for brcm_nand_dma_desc::status_valid */ 9293db446aSBoris Brezillon #define FLASH_DMA_ECC_ERROR (1 << 8) 9393db446aSBoris Brezillon #define FLASH_DMA_CORR_ERROR (1 << 9) 9493db446aSBoris Brezillon 9593db446aSBoris Brezillon /* 512B flash cache in the NAND controller HW */ 9693db446aSBoris Brezillon #define FC_SHIFT 9U 9793db446aSBoris Brezillon #define FC_BYTES 512U 9893db446aSBoris Brezillon #define FC_WORDS (FC_BYTES >> 2) 9993db446aSBoris Brezillon 10093db446aSBoris Brezillon #define BRCMNAND_MIN_PAGESIZE 512 10193db446aSBoris Brezillon #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024) 10293db446aSBoris Brezillon #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024) 10393db446aSBoris Brezillon 10493db446aSBoris Brezillon #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) 10593db446aSBoris Brezillon #define NAND_POLL_STATUS_TIMEOUT_MS 100 10693db446aSBoris Brezillon 10793db446aSBoris Brezillon /* Controller feature flags */ 10893db446aSBoris Brezillon enum { 10993db446aSBoris Brezillon BRCMNAND_HAS_1K_SECTORS = BIT(0), 11093db446aSBoris Brezillon BRCMNAND_HAS_PREFETCH = BIT(1), 11193db446aSBoris Brezillon BRCMNAND_HAS_CACHE_MODE = BIT(2), 11293db446aSBoris Brezillon BRCMNAND_HAS_WP = BIT(3), 11393db446aSBoris Brezillon }; 11493db446aSBoris Brezillon 11593db446aSBoris Brezillon struct brcmnand_controller { 11693db446aSBoris Brezillon struct device *dev; 1177da45139SMiquel Raynal struct nand_controller controller; 11893db446aSBoris Brezillon void __iomem *nand_base; 11993db446aSBoris Brezillon void __iomem *nand_fc; /* flash cache */ 12093db446aSBoris Brezillon void __iomem *flash_dma_base; 12193db446aSBoris Brezillon unsigned int irq; 12293db446aSBoris Brezillon unsigned int dma_irq; 12393db446aSBoris Brezillon int nand_version; 12493db446aSBoris Brezillon 12593db446aSBoris Brezillon /* Some SoCs provide custom interrupt status register(s) */ 12693db446aSBoris Brezillon struct brcmnand_soc *soc; 12793db446aSBoris Brezillon 12893db446aSBoris Brezillon /* Some SoCs have a gateable clock for the controller */ 12993db446aSBoris Brezillon struct clk *clk; 13093db446aSBoris Brezillon 13193db446aSBoris Brezillon int cmd_pending; 13293db446aSBoris Brezillon bool dma_pending; 13393db446aSBoris Brezillon struct completion done; 13493db446aSBoris Brezillon struct completion dma_done; 13593db446aSBoris Brezillon 13693db446aSBoris Brezillon /* List of NAND hosts (one for each chip-select) */ 13793db446aSBoris Brezillon struct list_head host_list; 13893db446aSBoris Brezillon 13993db446aSBoris Brezillon struct brcm_nand_dma_desc *dma_desc; 14093db446aSBoris Brezillon dma_addr_t dma_pa; 14193db446aSBoris Brezillon 14293db446aSBoris Brezillon /* in-memory cache of the FLASH_CACHE, used only for some commands */ 14393db446aSBoris Brezillon u8 flash_cache[FC_BYTES]; 14493db446aSBoris Brezillon 14593db446aSBoris Brezillon /* Controller revision details */ 14693db446aSBoris Brezillon const u16 *reg_offsets; 14793db446aSBoris Brezillon unsigned int reg_spacing; /* between CS1, CS2, ... regs */ 14893db446aSBoris Brezillon const u8 *cs_offsets; /* within each chip-select */ 14993db446aSBoris Brezillon const u8 *cs0_offsets; /* within CS0, if different */ 15093db446aSBoris Brezillon unsigned int max_block_size; 15193db446aSBoris Brezillon const unsigned int *block_sizes; 15293db446aSBoris Brezillon unsigned int max_page_size; 15393db446aSBoris Brezillon const unsigned int *page_sizes; 15493db446aSBoris Brezillon unsigned int max_oob; 15593db446aSBoris Brezillon u32 features; 15693db446aSBoris Brezillon 15793db446aSBoris Brezillon /* for low-power standby/resume only */ 15893db446aSBoris Brezillon u32 nand_cs_nand_select; 15993db446aSBoris Brezillon u32 nand_cs_nand_xor; 16093db446aSBoris Brezillon u32 corr_stat_threshold; 16193db446aSBoris Brezillon u32 flash_dma_mode; 16293db446aSBoris Brezillon }; 16393db446aSBoris Brezillon 16493db446aSBoris Brezillon struct brcmnand_cfg { 16593db446aSBoris Brezillon u64 device_size; 16693db446aSBoris Brezillon unsigned int block_size; 16793db446aSBoris Brezillon unsigned int page_size; 16893db446aSBoris Brezillon unsigned int spare_area_size; 16993db446aSBoris Brezillon unsigned int device_width; 17093db446aSBoris Brezillon unsigned int col_adr_bytes; 17193db446aSBoris Brezillon unsigned int blk_adr_bytes; 17293db446aSBoris Brezillon unsigned int ful_adr_bytes; 17393db446aSBoris Brezillon unsigned int sector_size_1k; 17493db446aSBoris Brezillon unsigned int ecc_level; 17593db446aSBoris Brezillon /* use for low-power standby/resume only */ 17693db446aSBoris Brezillon u32 acc_control; 17793db446aSBoris Brezillon u32 config; 17893db446aSBoris Brezillon u32 config_ext; 17993db446aSBoris Brezillon u32 timing_1; 18093db446aSBoris Brezillon u32 timing_2; 18193db446aSBoris Brezillon }; 18293db446aSBoris Brezillon 18393db446aSBoris Brezillon struct brcmnand_host { 18493db446aSBoris Brezillon struct list_head node; 18593db446aSBoris Brezillon 18693db446aSBoris Brezillon struct nand_chip chip; 18793db446aSBoris Brezillon struct platform_device *pdev; 18893db446aSBoris Brezillon int cs; 18993db446aSBoris Brezillon 19093db446aSBoris Brezillon unsigned int last_cmd; 19193db446aSBoris Brezillon unsigned int last_byte; 19293db446aSBoris Brezillon u64 last_addr; 19393db446aSBoris Brezillon struct brcmnand_cfg hwcfg; 19493db446aSBoris Brezillon struct brcmnand_controller *ctrl; 19593db446aSBoris Brezillon }; 19693db446aSBoris Brezillon 19793db446aSBoris Brezillon enum brcmnand_reg { 19893db446aSBoris Brezillon BRCMNAND_CMD_START = 0, 19993db446aSBoris Brezillon BRCMNAND_CMD_EXT_ADDRESS, 20093db446aSBoris Brezillon BRCMNAND_CMD_ADDRESS, 20193db446aSBoris Brezillon BRCMNAND_INTFC_STATUS, 20293db446aSBoris Brezillon BRCMNAND_CS_SELECT, 20393db446aSBoris Brezillon BRCMNAND_CS_XOR, 20493db446aSBoris Brezillon BRCMNAND_LL_OP, 20593db446aSBoris Brezillon BRCMNAND_CS0_BASE, 20693db446aSBoris Brezillon BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */ 20793db446aSBoris Brezillon BRCMNAND_CORR_THRESHOLD, 20893db446aSBoris Brezillon BRCMNAND_CORR_THRESHOLD_EXT, 20993db446aSBoris Brezillon BRCMNAND_UNCORR_COUNT, 21093db446aSBoris Brezillon BRCMNAND_CORR_COUNT, 21193db446aSBoris Brezillon BRCMNAND_CORR_EXT_ADDR, 21293db446aSBoris Brezillon BRCMNAND_CORR_ADDR, 21393db446aSBoris Brezillon BRCMNAND_UNCORR_EXT_ADDR, 21493db446aSBoris Brezillon BRCMNAND_UNCORR_ADDR, 21593db446aSBoris Brezillon BRCMNAND_SEMAPHORE, 21693db446aSBoris Brezillon BRCMNAND_ID, 21793db446aSBoris Brezillon BRCMNAND_ID_EXT, 21893db446aSBoris Brezillon BRCMNAND_LL_RDATA, 21993db446aSBoris Brezillon BRCMNAND_OOB_READ_BASE, 22093db446aSBoris Brezillon BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */ 22193db446aSBoris Brezillon BRCMNAND_OOB_WRITE_BASE, 22293db446aSBoris Brezillon BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */ 22393db446aSBoris Brezillon BRCMNAND_FC_BASE, 22493db446aSBoris Brezillon }; 22593db446aSBoris Brezillon 22693db446aSBoris Brezillon /* BRCMNAND v4.0 */ 22793db446aSBoris Brezillon static const u16 brcmnand_regs_v40[] = { 22893db446aSBoris Brezillon [BRCMNAND_CMD_START] = 0x04, 22993db446aSBoris Brezillon [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 23093db446aSBoris Brezillon [BRCMNAND_CMD_ADDRESS] = 0x0c, 23193db446aSBoris Brezillon [BRCMNAND_INTFC_STATUS] = 0x6c, 23293db446aSBoris Brezillon [BRCMNAND_CS_SELECT] = 0x14, 23393db446aSBoris Brezillon [BRCMNAND_CS_XOR] = 0x18, 23493db446aSBoris Brezillon [BRCMNAND_LL_OP] = 0x178, 23593db446aSBoris Brezillon [BRCMNAND_CS0_BASE] = 0x40, 23693db446aSBoris Brezillon [BRCMNAND_CS1_BASE] = 0xd0, 23793db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD] = 0x84, 23893db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 23993db446aSBoris Brezillon [BRCMNAND_UNCORR_COUNT] = 0, 24093db446aSBoris Brezillon [BRCMNAND_CORR_COUNT] = 0, 24193db446aSBoris Brezillon [BRCMNAND_CORR_EXT_ADDR] = 0x70, 24293db446aSBoris Brezillon [BRCMNAND_CORR_ADDR] = 0x74, 24393db446aSBoris Brezillon [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 24493db446aSBoris Brezillon [BRCMNAND_UNCORR_ADDR] = 0x7c, 24593db446aSBoris Brezillon [BRCMNAND_SEMAPHORE] = 0x58, 24693db446aSBoris Brezillon [BRCMNAND_ID] = 0x60, 24793db446aSBoris Brezillon [BRCMNAND_ID_EXT] = 0x64, 24893db446aSBoris Brezillon [BRCMNAND_LL_RDATA] = 0x17c, 24993db446aSBoris Brezillon [BRCMNAND_OOB_READ_BASE] = 0x20, 25093db446aSBoris Brezillon [BRCMNAND_OOB_READ_10_BASE] = 0x130, 25193db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_BASE] = 0x30, 25293db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_10_BASE] = 0, 25393db446aSBoris Brezillon [BRCMNAND_FC_BASE] = 0x200, 25493db446aSBoris Brezillon }; 25593db446aSBoris Brezillon 25693db446aSBoris Brezillon /* BRCMNAND v5.0 */ 25793db446aSBoris Brezillon static const u16 brcmnand_regs_v50[] = { 25893db446aSBoris Brezillon [BRCMNAND_CMD_START] = 0x04, 25993db446aSBoris Brezillon [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 26093db446aSBoris Brezillon [BRCMNAND_CMD_ADDRESS] = 0x0c, 26193db446aSBoris Brezillon [BRCMNAND_INTFC_STATUS] = 0x6c, 26293db446aSBoris Brezillon [BRCMNAND_CS_SELECT] = 0x14, 26393db446aSBoris Brezillon [BRCMNAND_CS_XOR] = 0x18, 26493db446aSBoris Brezillon [BRCMNAND_LL_OP] = 0x178, 26593db446aSBoris Brezillon [BRCMNAND_CS0_BASE] = 0x40, 26693db446aSBoris Brezillon [BRCMNAND_CS1_BASE] = 0xd0, 26793db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD] = 0x84, 26893db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 26993db446aSBoris Brezillon [BRCMNAND_UNCORR_COUNT] = 0, 27093db446aSBoris Brezillon [BRCMNAND_CORR_COUNT] = 0, 27193db446aSBoris Brezillon [BRCMNAND_CORR_EXT_ADDR] = 0x70, 27293db446aSBoris Brezillon [BRCMNAND_CORR_ADDR] = 0x74, 27393db446aSBoris Brezillon [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 27493db446aSBoris Brezillon [BRCMNAND_UNCORR_ADDR] = 0x7c, 27593db446aSBoris Brezillon [BRCMNAND_SEMAPHORE] = 0x58, 27693db446aSBoris Brezillon [BRCMNAND_ID] = 0x60, 27793db446aSBoris Brezillon [BRCMNAND_ID_EXT] = 0x64, 27893db446aSBoris Brezillon [BRCMNAND_LL_RDATA] = 0x17c, 27993db446aSBoris Brezillon [BRCMNAND_OOB_READ_BASE] = 0x20, 28093db446aSBoris Brezillon [BRCMNAND_OOB_READ_10_BASE] = 0x130, 28193db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_BASE] = 0x30, 28293db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_10_BASE] = 0x140, 28393db446aSBoris Brezillon [BRCMNAND_FC_BASE] = 0x200, 28493db446aSBoris Brezillon }; 28593db446aSBoris Brezillon 28693db446aSBoris Brezillon /* BRCMNAND v6.0 - v7.1 */ 28793db446aSBoris Brezillon static const u16 brcmnand_regs_v60[] = { 28893db446aSBoris Brezillon [BRCMNAND_CMD_START] = 0x04, 28993db446aSBoris Brezillon [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 29093db446aSBoris Brezillon [BRCMNAND_CMD_ADDRESS] = 0x0c, 29193db446aSBoris Brezillon [BRCMNAND_INTFC_STATUS] = 0x14, 29293db446aSBoris Brezillon [BRCMNAND_CS_SELECT] = 0x18, 29393db446aSBoris Brezillon [BRCMNAND_CS_XOR] = 0x1c, 29493db446aSBoris Brezillon [BRCMNAND_LL_OP] = 0x20, 29593db446aSBoris Brezillon [BRCMNAND_CS0_BASE] = 0x50, 29693db446aSBoris Brezillon [BRCMNAND_CS1_BASE] = 0, 29793db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD] = 0xc0, 29893db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4, 29993db446aSBoris Brezillon [BRCMNAND_UNCORR_COUNT] = 0xfc, 30093db446aSBoris Brezillon [BRCMNAND_CORR_COUNT] = 0x100, 30193db446aSBoris Brezillon [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 30293db446aSBoris Brezillon [BRCMNAND_CORR_ADDR] = 0x110, 30393db446aSBoris Brezillon [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 30493db446aSBoris Brezillon [BRCMNAND_UNCORR_ADDR] = 0x118, 30593db446aSBoris Brezillon [BRCMNAND_SEMAPHORE] = 0x150, 30693db446aSBoris Brezillon [BRCMNAND_ID] = 0x194, 30793db446aSBoris Brezillon [BRCMNAND_ID_EXT] = 0x198, 30893db446aSBoris Brezillon [BRCMNAND_LL_RDATA] = 0x19c, 30993db446aSBoris Brezillon [BRCMNAND_OOB_READ_BASE] = 0x200, 31093db446aSBoris Brezillon [BRCMNAND_OOB_READ_10_BASE] = 0, 31193db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_BASE] = 0x280, 31293db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_10_BASE] = 0, 31393db446aSBoris Brezillon [BRCMNAND_FC_BASE] = 0x400, 31493db446aSBoris Brezillon }; 31593db446aSBoris Brezillon 31693db446aSBoris Brezillon /* BRCMNAND v7.1 */ 31793db446aSBoris Brezillon static const u16 brcmnand_regs_v71[] = { 31893db446aSBoris Brezillon [BRCMNAND_CMD_START] = 0x04, 31993db446aSBoris Brezillon [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 32093db446aSBoris Brezillon [BRCMNAND_CMD_ADDRESS] = 0x0c, 32193db446aSBoris Brezillon [BRCMNAND_INTFC_STATUS] = 0x14, 32293db446aSBoris Brezillon [BRCMNAND_CS_SELECT] = 0x18, 32393db446aSBoris Brezillon [BRCMNAND_CS_XOR] = 0x1c, 32493db446aSBoris Brezillon [BRCMNAND_LL_OP] = 0x20, 32593db446aSBoris Brezillon [BRCMNAND_CS0_BASE] = 0x50, 32693db446aSBoris Brezillon [BRCMNAND_CS1_BASE] = 0, 32793db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD] = 0xdc, 32893db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 32993db446aSBoris Brezillon [BRCMNAND_UNCORR_COUNT] = 0xfc, 33093db446aSBoris Brezillon [BRCMNAND_CORR_COUNT] = 0x100, 33193db446aSBoris Brezillon [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 33293db446aSBoris Brezillon [BRCMNAND_CORR_ADDR] = 0x110, 33393db446aSBoris Brezillon [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 33493db446aSBoris Brezillon [BRCMNAND_UNCORR_ADDR] = 0x118, 33593db446aSBoris Brezillon [BRCMNAND_SEMAPHORE] = 0x150, 33693db446aSBoris Brezillon [BRCMNAND_ID] = 0x194, 33793db446aSBoris Brezillon [BRCMNAND_ID_EXT] = 0x198, 33893db446aSBoris Brezillon [BRCMNAND_LL_RDATA] = 0x19c, 33993db446aSBoris Brezillon [BRCMNAND_OOB_READ_BASE] = 0x200, 34093db446aSBoris Brezillon [BRCMNAND_OOB_READ_10_BASE] = 0, 34193db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_BASE] = 0x280, 34293db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_10_BASE] = 0, 34393db446aSBoris Brezillon [BRCMNAND_FC_BASE] = 0x400, 34493db446aSBoris Brezillon }; 34593db446aSBoris Brezillon 34693db446aSBoris Brezillon /* BRCMNAND v7.2 */ 34793db446aSBoris Brezillon static const u16 brcmnand_regs_v72[] = { 34893db446aSBoris Brezillon [BRCMNAND_CMD_START] = 0x04, 34993db446aSBoris Brezillon [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 35093db446aSBoris Brezillon [BRCMNAND_CMD_ADDRESS] = 0x0c, 35193db446aSBoris Brezillon [BRCMNAND_INTFC_STATUS] = 0x14, 35293db446aSBoris Brezillon [BRCMNAND_CS_SELECT] = 0x18, 35393db446aSBoris Brezillon [BRCMNAND_CS_XOR] = 0x1c, 35493db446aSBoris Brezillon [BRCMNAND_LL_OP] = 0x20, 35593db446aSBoris Brezillon [BRCMNAND_CS0_BASE] = 0x50, 35693db446aSBoris Brezillon [BRCMNAND_CS1_BASE] = 0, 35793db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD] = 0xdc, 35893db446aSBoris Brezillon [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 35993db446aSBoris Brezillon [BRCMNAND_UNCORR_COUNT] = 0xfc, 36093db446aSBoris Brezillon [BRCMNAND_CORR_COUNT] = 0x100, 36193db446aSBoris Brezillon [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 36293db446aSBoris Brezillon [BRCMNAND_CORR_ADDR] = 0x110, 36393db446aSBoris Brezillon [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 36493db446aSBoris Brezillon [BRCMNAND_UNCORR_ADDR] = 0x118, 36593db446aSBoris Brezillon [BRCMNAND_SEMAPHORE] = 0x150, 36693db446aSBoris Brezillon [BRCMNAND_ID] = 0x194, 36793db446aSBoris Brezillon [BRCMNAND_ID_EXT] = 0x198, 36893db446aSBoris Brezillon [BRCMNAND_LL_RDATA] = 0x19c, 36993db446aSBoris Brezillon [BRCMNAND_OOB_READ_BASE] = 0x200, 37093db446aSBoris Brezillon [BRCMNAND_OOB_READ_10_BASE] = 0, 37193db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_BASE] = 0x400, 37293db446aSBoris Brezillon [BRCMNAND_OOB_WRITE_10_BASE] = 0, 37393db446aSBoris Brezillon [BRCMNAND_FC_BASE] = 0x600, 37493db446aSBoris Brezillon }; 37593db446aSBoris Brezillon 37693db446aSBoris Brezillon enum brcmnand_cs_reg { 37793db446aSBoris Brezillon BRCMNAND_CS_CFG_EXT = 0, 37893db446aSBoris Brezillon BRCMNAND_CS_CFG, 37993db446aSBoris Brezillon BRCMNAND_CS_ACC_CONTROL, 38093db446aSBoris Brezillon BRCMNAND_CS_TIMING1, 38193db446aSBoris Brezillon BRCMNAND_CS_TIMING2, 38293db446aSBoris Brezillon }; 38393db446aSBoris Brezillon 38493db446aSBoris Brezillon /* Per chip-select offsets for v7.1 */ 38593db446aSBoris Brezillon static const u8 brcmnand_cs_offsets_v71[] = { 38693db446aSBoris Brezillon [BRCMNAND_CS_ACC_CONTROL] = 0x00, 38793db446aSBoris Brezillon [BRCMNAND_CS_CFG_EXT] = 0x04, 38893db446aSBoris Brezillon [BRCMNAND_CS_CFG] = 0x08, 38993db446aSBoris Brezillon [BRCMNAND_CS_TIMING1] = 0x0c, 39093db446aSBoris Brezillon [BRCMNAND_CS_TIMING2] = 0x10, 39193db446aSBoris Brezillon }; 39293db446aSBoris Brezillon 39393db446aSBoris Brezillon /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */ 39493db446aSBoris Brezillon static const u8 brcmnand_cs_offsets[] = { 39593db446aSBoris Brezillon [BRCMNAND_CS_ACC_CONTROL] = 0x00, 39693db446aSBoris Brezillon [BRCMNAND_CS_CFG_EXT] = 0x04, 39793db446aSBoris Brezillon [BRCMNAND_CS_CFG] = 0x04, 39893db446aSBoris Brezillon [BRCMNAND_CS_TIMING1] = 0x08, 39993db446aSBoris Brezillon [BRCMNAND_CS_TIMING2] = 0x0c, 40093db446aSBoris Brezillon }; 40193db446aSBoris Brezillon 40293db446aSBoris Brezillon /* Per chip-select offset for <= v5.0 on CS0 only */ 40393db446aSBoris Brezillon static const u8 brcmnand_cs_offsets_cs0[] = { 40493db446aSBoris Brezillon [BRCMNAND_CS_ACC_CONTROL] = 0x00, 40593db446aSBoris Brezillon [BRCMNAND_CS_CFG_EXT] = 0x08, 40693db446aSBoris Brezillon [BRCMNAND_CS_CFG] = 0x08, 40793db446aSBoris Brezillon [BRCMNAND_CS_TIMING1] = 0x10, 40893db446aSBoris Brezillon [BRCMNAND_CS_TIMING2] = 0x14, 40993db446aSBoris Brezillon }; 41093db446aSBoris Brezillon 41193db446aSBoris Brezillon /* 41293db446aSBoris Brezillon * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had 41393db446aSBoris Brezillon * one config register, but once the bitfields overflowed, newer controllers 41493db446aSBoris Brezillon * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around. 41593db446aSBoris Brezillon */ 41693db446aSBoris Brezillon enum { 41793db446aSBoris Brezillon CFG_BLK_ADR_BYTES_SHIFT = 8, 41893db446aSBoris Brezillon CFG_COL_ADR_BYTES_SHIFT = 12, 41993db446aSBoris Brezillon CFG_FUL_ADR_BYTES_SHIFT = 16, 42093db446aSBoris Brezillon CFG_BUS_WIDTH_SHIFT = 23, 42193db446aSBoris Brezillon CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT), 42293db446aSBoris Brezillon CFG_DEVICE_SIZE_SHIFT = 24, 42393db446aSBoris Brezillon 42493db446aSBoris Brezillon /* Only for pre-v7.1 (with no CFG_EXT register) */ 42593db446aSBoris Brezillon CFG_PAGE_SIZE_SHIFT = 20, 42693db446aSBoris Brezillon CFG_BLK_SIZE_SHIFT = 28, 42793db446aSBoris Brezillon 42893db446aSBoris Brezillon /* Only for v7.1+ (with CFG_EXT register) */ 42993db446aSBoris Brezillon CFG_EXT_PAGE_SIZE_SHIFT = 0, 43093db446aSBoris Brezillon CFG_EXT_BLK_SIZE_SHIFT = 4, 43193db446aSBoris Brezillon }; 43293db446aSBoris Brezillon 43393db446aSBoris Brezillon /* BRCMNAND_INTFC_STATUS */ 43493db446aSBoris Brezillon enum { 43593db446aSBoris Brezillon INTFC_FLASH_STATUS = GENMASK(7, 0), 43693db446aSBoris Brezillon 43793db446aSBoris Brezillon INTFC_ERASED = BIT(27), 43893db446aSBoris Brezillon INTFC_OOB_VALID = BIT(28), 43993db446aSBoris Brezillon INTFC_CACHE_VALID = BIT(29), 44093db446aSBoris Brezillon INTFC_FLASH_READY = BIT(30), 44193db446aSBoris Brezillon INTFC_CTLR_READY = BIT(31), 44293db446aSBoris Brezillon }; 44393db446aSBoris Brezillon 44493db446aSBoris Brezillon static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) 44593db446aSBoris Brezillon { 44693db446aSBoris Brezillon return brcmnand_readl(ctrl->nand_base + offs); 44793db446aSBoris Brezillon } 44893db446aSBoris Brezillon 44993db446aSBoris Brezillon static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, 45093db446aSBoris Brezillon u32 val) 45193db446aSBoris Brezillon { 45293db446aSBoris Brezillon brcmnand_writel(val, ctrl->nand_base + offs); 45393db446aSBoris Brezillon } 45493db446aSBoris Brezillon 45593db446aSBoris Brezillon static int brcmnand_revision_init(struct brcmnand_controller *ctrl) 45693db446aSBoris Brezillon { 45793db446aSBoris Brezillon static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 }; 45893db446aSBoris Brezillon static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 }; 45993db446aSBoris Brezillon static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 }; 46093db446aSBoris Brezillon 46193db446aSBoris Brezillon ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; 46293db446aSBoris Brezillon 46393db446aSBoris Brezillon /* Only support v4.0+? */ 46493db446aSBoris Brezillon if (ctrl->nand_version < 0x0400) { 46593db446aSBoris Brezillon dev_err(ctrl->dev, "version %#x not supported\n", 46693db446aSBoris Brezillon ctrl->nand_version); 46793db446aSBoris Brezillon return -ENODEV; 46893db446aSBoris Brezillon } 46993db446aSBoris Brezillon 47093db446aSBoris Brezillon /* Register offsets */ 47193db446aSBoris Brezillon if (ctrl->nand_version >= 0x0702) 47293db446aSBoris Brezillon ctrl->reg_offsets = brcmnand_regs_v72; 47393db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0701) 47493db446aSBoris Brezillon ctrl->reg_offsets = brcmnand_regs_v71; 47593db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0600) 47693db446aSBoris Brezillon ctrl->reg_offsets = brcmnand_regs_v60; 47793db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0500) 47893db446aSBoris Brezillon ctrl->reg_offsets = brcmnand_regs_v50; 47993db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0400) 48093db446aSBoris Brezillon ctrl->reg_offsets = brcmnand_regs_v40; 48193db446aSBoris Brezillon 48293db446aSBoris Brezillon /* Chip-select stride */ 48393db446aSBoris Brezillon if (ctrl->nand_version >= 0x0701) 48493db446aSBoris Brezillon ctrl->reg_spacing = 0x14; 48593db446aSBoris Brezillon else 48693db446aSBoris Brezillon ctrl->reg_spacing = 0x10; 48793db446aSBoris Brezillon 48893db446aSBoris Brezillon /* Per chip-select registers */ 48993db446aSBoris Brezillon if (ctrl->nand_version >= 0x0701) { 49093db446aSBoris Brezillon ctrl->cs_offsets = brcmnand_cs_offsets_v71; 49193db446aSBoris Brezillon } else { 49293db446aSBoris Brezillon ctrl->cs_offsets = brcmnand_cs_offsets; 49393db446aSBoris Brezillon 49493db446aSBoris Brezillon /* v5.0 and earlier has a different CS0 offset layout */ 49593db446aSBoris Brezillon if (ctrl->nand_version <= 0x0500) 49693db446aSBoris Brezillon ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; 49793db446aSBoris Brezillon } 49893db446aSBoris Brezillon 49993db446aSBoris Brezillon /* Page / block sizes */ 50093db446aSBoris Brezillon if (ctrl->nand_version >= 0x0701) { 50193db446aSBoris Brezillon /* >= v7.1 use nice power-of-2 values! */ 50293db446aSBoris Brezillon ctrl->max_page_size = 16 * 1024; 50393db446aSBoris Brezillon ctrl->max_block_size = 2 * 1024 * 1024; 50493db446aSBoris Brezillon } else { 50593db446aSBoris Brezillon ctrl->page_sizes = page_sizes; 50693db446aSBoris Brezillon if (ctrl->nand_version >= 0x0600) 50793db446aSBoris Brezillon ctrl->block_sizes = block_sizes_v6; 50893db446aSBoris Brezillon else 50993db446aSBoris Brezillon ctrl->block_sizes = block_sizes_v4; 51093db446aSBoris Brezillon 51193db446aSBoris Brezillon if (ctrl->nand_version < 0x0400) { 51293db446aSBoris Brezillon ctrl->max_page_size = 4096; 51393db446aSBoris Brezillon ctrl->max_block_size = 512 * 1024; 51493db446aSBoris Brezillon } 51593db446aSBoris Brezillon } 51693db446aSBoris Brezillon 51793db446aSBoris Brezillon /* Maximum spare area sector size (per 512B) */ 51893db446aSBoris Brezillon if (ctrl->nand_version >= 0x0702) 51993db446aSBoris Brezillon ctrl->max_oob = 128; 52093db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0600) 52193db446aSBoris Brezillon ctrl->max_oob = 64; 52293db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0500) 52393db446aSBoris Brezillon ctrl->max_oob = 32; 52493db446aSBoris Brezillon else 52593db446aSBoris Brezillon ctrl->max_oob = 16; 52693db446aSBoris Brezillon 52793db446aSBoris Brezillon /* v6.0 and newer (except v6.1) have prefetch support */ 52893db446aSBoris Brezillon if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) 52993db446aSBoris Brezillon ctrl->features |= BRCMNAND_HAS_PREFETCH; 53093db446aSBoris Brezillon 53193db446aSBoris Brezillon /* 53293db446aSBoris Brezillon * v6.x has cache mode, but it's implemented differently. Ignore it for 53393db446aSBoris Brezillon * now. 53493db446aSBoris Brezillon */ 53593db446aSBoris Brezillon if (ctrl->nand_version >= 0x0700) 53693db446aSBoris Brezillon ctrl->features |= BRCMNAND_HAS_CACHE_MODE; 53793db446aSBoris Brezillon 53893db446aSBoris Brezillon if (ctrl->nand_version >= 0x0500) 53993db446aSBoris Brezillon ctrl->features |= BRCMNAND_HAS_1K_SECTORS; 54093db446aSBoris Brezillon 54193db446aSBoris Brezillon if (ctrl->nand_version >= 0x0700) 54293db446aSBoris Brezillon ctrl->features |= BRCMNAND_HAS_WP; 54393db446aSBoris Brezillon else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) 54493db446aSBoris Brezillon ctrl->features |= BRCMNAND_HAS_WP; 54593db446aSBoris Brezillon 54693db446aSBoris Brezillon return 0; 54793db446aSBoris Brezillon } 54893db446aSBoris Brezillon 54993db446aSBoris Brezillon static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, 55093db446aSBoris Brezillon enum brcmnand_reg reg) 55193db446aSBoris Brezillon { 55293db446aSBoris Brezillon u16 offs = ctrl->reg_offsets[reg]; 55393db446aSBoris Brezillon 55493db446aSBoris Brezillon if (offs) 55593db446aSBoris Brezillon return nand_readreg(ctrl, offs); 55693db446aSBoris Brezillon else 55793db446aSBoris Brezillon return 0; 55893db446aSBoris Brezillon } 55993db446aSBoris Brezillon 56093db446aSBoris Brezillon static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, 56193db446aSBoris Brezillon enum brcmnand_reg reg, u32 val) 56293db446aSBoris Brezillon { 56393db446aSBoris Brezillon u16 offs = ctrl->reg_offsets[reg]; 56493db446aSBoris Brezillon 56593db446aSBoris Brezillon if (offs) 56693db446aSBoris Brezillon nand_writereg(ctrl, offs, val); 56793db446aSBoris Brezillon } 56893db446aSBoris Brezillon 56993db446aSBoris Brezillon static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, 57093db446aSBoris Brezillon enum brcmnand_reg reg, u32 mask, unsigned 57193db446aSBoris Brezillon int shift, u32 val) 57293db446aSBoris Brezillon { 57393db446aSBoris Brezillon u32 tmp = brcmnand_read_reg(ctrl, reg); 57493db446aSBoris Brezillon 57593db446aSBoris Brezillon tmp &= ~mask; 57693db446aSBoris Brezillon tmp |= val << shift; 57793db446aSBoris Brezillon brcmnand_write_reg(ctrl, reg, tmp); 57893db446aSBoris Brezillon } 57993db446aSBoris Brezillon 58093db446aSBoris Brezillon static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) 58193db446aSBoris Brezillon { 58293db446aSBoris Brezillon return __raw_readl(ctrl->nand_fc + word * 4); 58393db446aSBoris Brezillon } 58493db446aSBoris Brezillon 58593db446aSBoris Brezillon static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, 58693db446aSBoris Brezillon int word, u32 val) 58793db446aSBoris Brezillon { 58893db446aSBoris Brezillon __raw_writel(val, ctrl->nand_fc + word * 4); 58993db446aSBoris Brezillon } 59093db446aSBoris Brezillon 59193db446aSBoris Brezillon static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, 59293db446aSBoris Brezillon enum brcmnand_cs_reg reg) 59393db446aSBoris Brezillon { 59493db446aSBoris Brezillon u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; 59593db446aSBoris Brezillon u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; 59693db446aSBoris Brezillon u8 cs_offs; 59793db446aSBoris Brezillon 59893db446aSBoris Brezillon if (cs == 0 && ctrl->cs0_offsets) 59993db446aSBoris Brezillon cs_offs = ctrl->cs0_offsets[reg]; 60093db446aSBoris Brezillon else 60193db446aSBoris Brezillon cs_offs = ctrl->cs_offsets[reg]; 60293db446aSBoris Brezillon 60393db446aSBoris Brezillon if (cs && offs_cs1) 60493db446aSBoris Brezillon return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; 60593db446aSBoris Brezillon 60693db446aSBoris Brezillon return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; 60793db446aSBoris Brezillon } 60893db446aSBoris Brezillon 60993db446aSBoris Brezillon static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) 61093db446aSBoris Brezillon { 61193db446aSBoris Brezillon if (ctrl->nand_version < 0x0600) 61293db446aSBoris Brezillon return 1; 61393db446aSBoris Brezillon return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); 61493db446aSBoris Brezillon } 61593db446aSBoris Brezillon 61693db446aSBoris Brezillon static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val) 61793db446aSBoris Brezillon { 61893db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 61993db446aSBoris Brezillon unsigned int shift = 0, bits; 62093db446aSBoris Brezillon enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD; 62193db446aSBoris Brezillon int cs = host->cs; 62293db446aSBoris Brezillon 62393db446aSBoris Brezillon if (ctrl->nand_version >= 0x0702) 62493db446aSBoris Brezillon bits = 7; 62593db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0600) 62693db446aSBoris Brezillon bits = 6; 62793db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0500) 62893db446aSBoris Brezillon bits = 5; 62993db446aSBoris Brezillon else 63093db446aSBoris Brezillon bits = 4; 63193db446aSBoris Brezillon 63293db446aSBoris Brezillon if (ctrl->nand_version >= 0x0702) { 63393db446aSBoris Brezillon if (cs >= 4) 63493db446aSBoris Brezillon reg = BRCMNAND_CORR_THRESHOLD_EXT; 63593db446aSBoris Brezillon shift = (cs % 4) * bits; 63693db446aSBoris Brezillon } else if (ctrl->nand_version >= 0x0600) { 63793db446aSBoris Brezillon if (cs >= 5) 63893db446aSBoris Brezillon reg = BRCMNAND_CORR_THRESHOLD_EXT; 63993db446aSBoris Brezillon shift = (cs % 5) * bits; 64093db446aSBoris Brezillon } 64193db446aSBoris Brezillon brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); 64293db446aSBoris Brezillon } 64393db446aSBoris Brezillon 64493db446aSBoris Brezillon static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) 64593db446aSBoris Brezillon { 64693db446aSBoris Brezillon if (ctrl->nand_version < 0x0602) 64793db446aSBoris Brezillon return 24; 64893db446aSBoris Brezillon return 0; 64993db446aSBoris Brezillon } 65093db446aSBoris Brezillon 65193db446aSBoris Brezillon /*********************************************************************** 65293db446aSBoris Brezillon * NAND ACC CONTROL bitfield 65393db446aSBoris Brezillon * 65493db446aSBoris Brezillon * Some bits have remained constant throughout hardware revision, while 65593db446aSBoris Brezillon * others have shifted around. 65693db446aSBoris Brezillon ***********************************************************************/ 65793db446aSBoris Brezillon 65893db446aSBoris Brezillon /* Constant for all versions (where supported) */ 65993db446aSBoris Brezillon enum { 66093db446aSBoris Brezillon /* See BRCMNAND_HAS_CACHE_MODE */ 66193db446aSBoris Brezillon ACC_CONTROL_CACHE_MODE = BIT(22), 66293db446aSBoris Brezillon 66393db446aSBoris Brezillon /* See BRCMNAND_HAS_PREFETCH */ 66493db446aSBoris Brezillon ACC_CONTROL_PREFETCH = BIT(23), 66593db446aSBoris Brezillon 66693db446aSBoris Brezillon ACC_CONTROL_PAGE_HIT = BIT(24), 66793db446aSBoris Brezillon ACC_CONTROL_WR_PREEMPT = BIT(25), 66893db446aSBoris Brezillon ACC_CONTROL_PARTIAL_PAGE = BIT(26), 66993db446aSBoris Brezillon ACC_CONTROL_RD_ERASED = BIT(27), 67093db446aSBoris Brezillon ACC_CONTROL_FAST_PGM_RDIN = BIT(28), 67193db446aSBoris Brezillon ACC_CONTROL_WR_ECC = BIT(30), 67293db446aSBoris Brezillon ACC_CONTROL_RD_ECC = BIT(31), 67393db446aSBoris Brezillon }; 67493db446aSBoris Brezillon 67593db446aSBoris Brezillon static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) 67693db446aSBoris Brezillon { 67793db446aSBoris Brezillon if (ctrl->nand_version >= 0x0702) 67893db446aSBoris Brezillon return GENMASK(7, 0); 67993db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0600) 68093db446aSBoris Brezillon return GENMASK(6, 0); 68193db446aSBoris Brezillon else 68293db446aSBoris Brezillon return GENMASK(5, 0); 68393db446aSBoris Brezillon } 68493db446aSBoris Brezillon 68593db446aSBoris Brezillon #define NAND_ACC_CONTROL_ECC_SHIFT 16 68693db446aSBoris Brezillon #define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13 68793db446aSBoris Brezillon 68893db446aSBoris Brezillon static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) 68993db446aSBoris Brezillon { 69093db446aSBoris Brezillon u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; 69193db446aSBoris Brezillon 69293db446aSBoris Brezillon mask <<= NAND_ACC_CONTROL_ECC_SHIFT; 69393db446aSBoris Brezillon 69493db446aSBoris Brezillon /* v7.2 includes additional ECC levels */ 69593db446aSBoris Brezillon if (ctrl->nand_version >= 0x0702) 69693db446aSBoris Brezillon mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; 69793db446aSBoris Brezillon 69893db446aSBoris Brezillon return mask; 69993db446aSBoris Brezillon } 70093db446aSBoris Brezillon 70193db446aSBoris Brezillon static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) 70293db446aSBoris Brezillon { 70393db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 70493db446aSBoris Brezillon u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 70593db446aSBoris Brezillon u32 acc_control = nand_readreg(ctrl, offs); 70693db446aSBoris Brezillon u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC; 70793db446aSBoris Brezillon 70893db446aSBoris Brezillon if (en) { 70993db446aSBoris Brezillon acc_control |= ecc_flags; /* enable RD/WR ECC */ 71093db446aSBoris Brezillon acc_control |= host->hwcfg.ecc_level 71193db446aSBoris Brezillon << NAND_ACC_CONTROL_ECC_SHIFT; 71293db446aSBoris Brezillon } else { 71393db446aSBoris Brezillon acc_control &= ~ecc_flags; /* disable RD/WR ECC */ 71493db446aSBoris Brezillon acc_control &= ~brcmnand_ecc_level_mask(ctrl); 71593db446aSBoris Brezillon } 71693db446aSBoris Brezillon 71793db446aSBoris Brezillon nand_writereg(ctrl, offs, acc_control); 71893db446aSBoris Brezillon } 71993db446aSBoris Brezillon 72093db446aSBoris Brezillon static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) 72193db446aSBoris Brezillon { 72293db446aSBoris Brezillon if (ctrl->nand_version >= 0x0702) 72393db446aSBoris Brezillon return 9; 72493db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0600) 72593db446aSBoris Brezillon return 7; 72693db446aSBoris Brezillon else if (ctrl->nand_version >= 0x0500) 72793db446aSBoris Brezillon return 6; 72893db446aSBoris Brezillon else 72993db446aSBoris Brezillon return -1; 73093db446aSBoris Brezillon } 73193db446aSBoris Brezillon 73293db446aSBoris Brezillon static int brcmnand_get_sector_size_1k(struct brcmnand_host *host) 73393db446aSBoris Brezillon { 73493db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 73593db446aSBoris Brezillon int shift = brcmnand_sector_1k_shift(ctrl); 73693db446aSBoris Brezillon u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 73793db446aSBoris Brezillon BRCMNAND_CS_ACC_CONTROL); 73893db446aSBoris Brezillon 73993db446aSBoris Brezillon if (shift < 0) 74093db446aSBoris Brezillon return 0; 74193db446aSBoris Brezillon 74293db446aSBoris Brezillon return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; 74393db446aSBoris Brezillon } 74493db446aSBoris Brezillon 74593db446aSBoris Brezillon static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val) 74693db446aSBoris Brezillon { 74793db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 74893db446aSBoris Brezillon int shift = brcmnand_sector_1k_shift(ctrl); 74993db446aSBoris Brezillon u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 75093db446aSBoris Brezillon BRCMNAND_CS_ACC_CONTROL); 75193db446aSBoris Brezillon u32 tmp; 75293db446aSBoris Brezillon 75393db446aSBoris Brezillon if (shift < 0) 75493db446aSBoris Brezillon return; 75593db446aSBoris Brezillon 75693db446aSBoris Brezillon tmp = nand_readreg(ctrl, acc_control_offs); 75793db446aSBoris Brezillon tmp &= ~(1 << shift); 75893db446aSBoris Brezillon tmp |= (!!val) << shift; 75993db446aSBoris Brezillon nand_writereg(ctrl, acc_control_offs, tmp); 76093db446aSBoris Brezillon } 76193db446aSBoris Brezillon 76293db446aSBoris Brezillon /*********************************************************************** 76393db446aSBoris Brezillon * CS_NAND_SELECT 76493db446aSBoris Brezillon ***********************************************************************/ 76593db446aSBoris Brezillon 76693db446aSBoris Brezillon enum { 76793db446aSBoris Brezillon CS_SELECT_NAND_WP = BIT(29), 76893db446aSBoris Brezillon CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30), 76993db446aSBoris Brezillon }; 77093db446aSBoris Brezillon 77193db446aSBoris Brezillon static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, 77293db446aSBoris Brezillon u32 mask, u32 expected_val, 77393db446aSBoris Brezillon unsigned long timeout_ms) 77493db446aSBoris Brezillon { 77593db446aSBoris Brezillon unsigned long limit; 77693db446aSBoris Brezillon u32 val; 77793db446aSBoris Brezillon 77893db446aSBoris Brezillon if (!timeout_ms) 77993db446aSBoris Brezillon timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS; 78093db446aSBoris Brezillon 78193db446aSBoris Brezillon limit = jiffies + msecs_to_jiffies(timeout_ms); 78293db446aSBoris Brezillon do { 78393db446aSBoris Brezillon val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); 78493db446aSBoris Brezillon if ((val & mask) == expected_val) 78593db446aSBoris Brezillon return 0; 78693db446aSBoris Brezillon 78793db446aSBoris Brezillon cpu_relax(); 78893db446aSBoris Brezillon } while (time_after(limit, jiffies)); 78993db446aSBoris Brezillon 79093db446aSBoris Brezillon dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", 79193db446aSBoris Brezillon expected_val, val & mask); 79293db446aSBoris Brezillon 79393db446aSBoris Brezillon return -ETIMEDOUT; 79493db446aSBoris Brezillon } 79593db446aSBoris Brezillon 79693db446aSBoris Brezillon static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) 79793db446aSBoris Brezillon { 79893db446aSBoris Brezillon u32 val = en ? CS_SELECT_NAND_WP : 0; 79993db446aSBoris Brezillon 80093db446aSBoris Brezillon brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); 80193db446aSBoris Brezillon } 80293db446aSBoris Brezillon 80393db446aSBoris Brezillon /*********************************************************************** 80493db446aSBoris Brezillon * Flash DMA 80593db446aSBoris Brezillon ***********************************************************************/ 80693db446aSBoris Brezillon 80793db446aSBoris Brezillon enum flash_dma_reg { 80893db446aSBoris Brezillon FLASH_DMA_REVISION = 0x00, 80993db446aSBoris Brezillon FLASH_DMA_FIRST_DESC = 0x04, 81093db446aSBoris Brezillon FLASH_DMA_FIRST_DESC_EXT = 0x08, 81193db446aSBoris Brezillon FLASH_DMA_CTRL = 0x0c, 81293db446aSBoris Brezillon FLASH_DMA_MODE = 0x10, 81393db446aSBoris Brezillon FLASH_DMA_STATUS = 0x14, 81493db446aSBoris Brezillon FLASH_DMA_INTERRUPT_DESC = 0x18, 81593db446aSBoris Brezillon FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c, 81693db446aSBoris Brezillon FLASH_DMA_ERROR_STATUS = 0x20, 81793db446aSBoris Brezillon FLASH_DMA_CURRENT_DESC = 0x24, 81893db446aSBoris Brezillon FLASH_DMA_CURRENT_DESC_EXT = 0x28, 81993db446aSBoris Brezillon }; 82093db446aSBoris Brezillon 82193db446aSBoris Brezillon static inline bool has_flash_dma(struct brcmnand_controller *ctrl) 82293db446aSBoris Brezillon { 82393db446aSBoris Brezillon return ctrl->flash_dma_base; 82493db446aSBoris Brezillon } 82593db446aSBoris Brezillon 82693db446aSBoris Brezillon static inline bool flash_dma_buf_ok(const void *buf) 82793db446aSBoris Brezillon { 82893db446aSBoris Brezillon return buf && !is_vmalloc_addr(buf) && 82993db446aSBoris Brezillon likely(IS_ALIGNED((uintptr_t)buf, 4)); 83093db446aSBoris Brezillon } 83193db446aSBoris Brezillon 83293db446aSBoris Brezillon static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs, 83393db446aSBoris Brezillon u32 val) 83493db446aSBoris Brezillon { 83593db446aSBoris Brezillon brcmnand_writel(val, ctrl->flash_dma_base + offs); 83693db446aSBoris Brezillon } 83793db446aSBoris Brezillon 83893db446aSBoris Brezillon static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs) 83993db446aSBoris Brezillon { 84093db446aSBoris Brezillon return brcmnand_readl(ctrl->flash_dma_base + offs); 84193db446aSBoris Brezillon } 84293db446aSBoris Brezillon 84393db446aSBoris Brezillon /* Low-level operation types: command, address, write, or read */ 84493db446aSBoris Brezillon enum brcmnand_llop_type { 84593db446aSBoris Brezillon LL_OP_CMD, 84693db446aSBoris Brezillon LL_OP_ADDR, 84793db446aSBoris Brezillon LL_OP_WR, 84893db446aSBoris Brezillon LL_OP_RD, 84993db446aSBoris Brezillon }; 85093db446aSBoris Brezillon 85193db446aSBoris Brezillon /*********************************************************************** 85293db446aSBoris Brezillon * Internal support functions 85393db446aSBoris Brezillon ***********************************************************************/ 85493db446aSBoris Brezillon 85593db446aSBoris Brezillon static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, 85693db446aSBoris Brezillon struct brcmnand_cfg *cfg) 85793db446aSBoris Brezillon { 85893db446aSBoris Brezillon if (ctrl->nand_version <= 0x0701) 85993db446aSBoris Brezillon return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && 86093db446aSBoris Brezillon cfg->ecc_level == 15; 86193db446aSBoris Brezillon else 86293db446aSBoris Brezillon return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && 86393db446aSBoris Brezillon cfg->ecc_level == 15) || 86493db446aSBoris Brezillon (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); 86593db446aSBoris Brezillon } 86693db446aSBoris Brezillon 86793db446aSBoris Brezillon /* 86893db446aSBoris Brezillon * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given 86993db446aSBoris Brezillon * the layout/configuration. 87093db446aSBoris Brezillon * Returns -ERRCODE on failure. 87193db446aSBoris Brezillon */ 87293db446aSBoris Brezillon static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section, 87393db446aSBoris Brezillon struct mtd_oob_region *oobregion) 87493db446aSBoris Brezillon { 87593db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 87693db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 87793db446aSBoris Brezillon struct brcmnand_cfg *cfg = &host->hwcfg; 87893db446aSBoris Brezillon int sas = cfg->spare_area_size << cfg->sector_size_1k; 87993db446aSBoris Brezillon int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 88093db446aSBoris Brezillon 88193db446aSBoris Brezillon if (section >= sectors) 88293db446aSBoris Brezillon return -ERANGE; 88393db446aSBoris Brezillon 88493db446aSBoris Brezillon oobregion->offset = (section * sas) + 6; 88593db446aSBoris Brezillon oobregion->length = 3; 88693db446aSBoris Brezillon 88793db446aSBoris Brezillon return 0; 88893db446aSBoris Brezillon } 88993db446aSBoris Brezillon 89093db446aSBoris Brezillon static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section, 89193db446aSBoris Brezillon struct mtd_oob_region *oobregion) 89293db446aSBoris Brezillon { 89393db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 89493db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 89593db446aSBoris Brezillon struct brcmnand_cfg *cfg = &host->hwcfg; 89693db446aSBoris Brezillon int sas = cfg->spare_area_size << cfg->sector_size_1k; 89793db446aSBoris Brezillon int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 89893db446aSBoris Brezillon 89993db446aSBoris Brezillon if (section >= sectors * 2) 90093db446aSBoris Brezillon return -ERANGE; 90193db446aSBoris Brezillon 90293db446aSBoris Brezillon oobregion->offset = (section / 2) * sas; 90393db446aSBoris Brezillon 90493db446aSBoris Brezillon if (section & 1) { 90593db446aSBoris Brezillon oobregion->offset += 9; 90693db446aSBoris Brezillon oobregion->length = 7; 90793db446aSBoris Brezillon } else { 90893db446aSBoris Brezillon oobregion->length = 6; 90993db446aSBoris Brezillon 91093db446aSBoris Brezillon /* First sector of each page may have BBI */ 91193db446aSBoris Brezillon if (!section) { 91293db446aSBoris Brezillon /* 91393db446aSBoris Brezillon * Small-page NAND use byte 6 for BBI while large-page 91493db446aSBoris Brezillon * NAND use byte 0. 91593db446aSBoris Brezillon */ 91693db446aSBoris Brezillon if (cfg->page_size > 512) 91793db446aSBoris Brezillon oobregion->offset++; 91893db446aSBoris Brezillon oobregion->length--; 91993db446aSBoris Brezillon } 92093db446aSBoris Brezillon } 92193db446aSBoris Brezillon 92293db446aSBoris Brezillon return 0; 92393db446aSBoris Brezillon } 92493db446aSBoris Brezillon 92593db446aSBoris Brezillon static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = { 92693db446aSBoris Brezillon .ecc = brcmnand_hamming_ooblayout_ecc, 92793db446aSBoris Brezillon .free = brcmnand_hamming_ooblayout_free, 92893db446aSBoris Brezillon }; 92993db446aSBoris Brezillon 93093db446aSBoris Brezillon static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section, 93193db446aSBoris Brezillon struct mtd_oob_region *oobregion) 93293db446aSBoris Brezillon { 93393db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 93493db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 93593db446aSBoris Brezillon struct brcmnand_cfg *cfg = &host->hwcfg; 93693db446aSBoris Brezillon int sas = cfg->spare_area_size << cfg->sector_size_1k; 93793db446aSBoris Brezillon int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 93893db446aSBoris Brezillon 93993db446aSBoris Brezillon if (section >= sectors) 94093db446aSBoris Brezillon return -ERANGE; 94193db446aSBoris Brezillon 94293db446aSBoris Brezillon oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes; 94393db446aSBoris Brezillon oobregion->length = chip->ecc.bytes; 94493db446aSBoris Brezillon 94593db446aSBoris Brezillon return 0; 94693db446aSBoris Brezillon } 94793db446aSBoris Brezillon 94893db446aSBoris Brezillon static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section, 94993db446aSBoris Brezillon struct mtd_oob_region *oobregion) 95093db446aSBoris Brezillon { 95193db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 95293db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 95393db446aSBoris Brezillon struct brcmnand_cfg *cfg = &host->hwcfg; 95493db446aSBoris Brezillon int sas = cfg->spare_area_size << cfg->sector_size_1k; 95593db446aSBoris Brezillon int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 95693db446aSBoris Brezillon 95793db446aSBoris Brezillon if (section >= sectors) 95893db446aSBoris Brezillon return -ERANGE; 95993db446aSBoris Brezillon 96093db446aSBoris Brezillon if (sas <= chip->ecc.bytes) 96193db446aSBoris Brezillon return 0; 96293db446aSBoris Brezillon 96393db446aSBoris Brezillon oobregion->offset = section * sas; 96493db446aSBoris Brezillon oobregion->length = sas - chip->ecc.bytes; 96593db446aSBoris Brezillon 96693db446aSBoris Brezillon if (!section) { 96793db446aSBoris Brezillon oobregion->offset++; 96893db446aSBoris Brezillon oobregion->length--; 96993db446aSBoris Brezillon } 97093db446aSBoris Brezillon 97193db446aSBoris Brezillon return 0; 97293db446aSBoris Brezillon } 97393db446aSBoris Brezillon 97493db446aSBoris Brezillon static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section, 97593db446aSBoris Brezillon struct mtd_oob_region *oobregion) 97693db446aSBoris Brezillon { 97793db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 97893db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 97993db446aSBoris Brezillon struct brcmnand_cfg *cfg = &host->hwcfg; 98093db446aSBoris Brezillon int sas = cfg->spare_area_size << cfg->sector_size_1k; 98193db446aSBoris Brezillon 98293db446aSBoris Brezillon if (section > 1 || sas - chip->ecc.bytes < 6 || 98393db446aSBoris Brezillon (section && sas - chip->ecc.bytes == 6)) 98493db446aSBoris Brezillon return -ERANGE; 98593db446aSBoris Brezillon 98693db446aSBoris Brezillon if (!section) { 98793db446aSBoris Brezillon oobregion->offset = 0; 98893db446aSBoris Brezillon oobregion->length = 5; 98993db446aSBoris Brezillon } else { 99093db446aSBoris Brezillon oobregion->offset = 6; 99193db446aSBoris Brezillon oobregion->length = sas - chip->ecc.bytes - 6; 99293db446aSBoris Brezillon } 99393db446aSBoris Brezillon 99493db446aSBoris Brezillon return 0; 99593db446aSBoris Brezillon } 99693db446aSBoris Brezillon 99793db446aSBoris Brezillon static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = { 99893db446aSBoris Brezillon .ecc = brcmnand_bch_ooblayout_ecc, 99993db446aSBoris Brezillon .free = brcmnand_bch_ooblayout_free_lp, 100093db446aSBoris Brezillon }; 100193db446aSBoris Brezillon 100293db446aSBoris Brezillon static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = { 100393db446aSBoris Brezillon .ecc = brcmnand_bch_ooblayout_ecc, 100493db446aSBoris Brezillon .free = brcmnand_bch_ooblayout_free_sp, 100593db446aSBoris Brezillon }; 100693db446aSBoris Brezillon 100793db446aSBoris Brezillon static int brcmstb_choose_ecc_layout(struct brcmnand_host *host) 100893db446aSBoris Brezillon { 100993db446aSBoris Brezillon struct brcmnand_cfg *p = &host->hwcfg; 101093db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(&host->chip); 101193db446aSBoris Brezillon struct nand_ecc_ctrl *ecc = &host->chip.ecc; 101293db446aSBoris Brezillon unsigned int ecc_level = p->ecc_level; 101393db446aSBoris Brezillon int sas = p->spare_area_size << p->sector_size_1k; 101493db446aSBoris Brezillon int sectors = p->page_size / (512 << p->sector_size_1k); 101593db446aSBoris Brezillon 101693db446aSBoris Brezillon if (p->sector_size_1k) 101793db446aSBoris Brezillon ecc_level <<= 1; 101893db446aSBoris Brezillon 101993db446aSBoris Brezillon if (is_hamming_ecc(host->ctrl, p)) { 102093db446aSBoris Brezillon ecc->bytes = 3 * sectors; 102193db446aSBoris Brezillon mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops); 102293db446aSBoris Brezillon return 0; 102393db446aSBoris Brezillon } 102493db446aSBoris Brezillon 102593db446aSBoris Brezillon /* 102693db446aSBoris Brezillon * CONTROLLER_VERSION: 102793db446aSBoris Brezillon * < v5.0: ECC_REQ = ceil(BCH_T * 13/8) 102893db446aSBoris Brezillon * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8) 102993db446aSBoris Brezillon * But we will just be conservative. 103093db446aSBoris Brezillon */ 103193db446aSBoris Brezillon ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); 103293db446aSBoris Brezillon if (p->page_size == 512) 103393db446aSBoris Brezillon mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops); 103493db446aSBoris Brezillon else 103593db446aSBoris Brezillon mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops); 103693db446aSBoris Brezillon 103793db446aSBoris Brezillon if (ecc->bytes >= sas) { 103893db446aSBoris Brezillon dev_err(&host->pdev->dev, 103993db446aSBoris Brezillon "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", 104093db446aSBoris Brezillon ecc->bytes, sas); 104193db446aSBoris Brezillon return -EINVAL; 104293db446aSBoris Brezillon } 104393db446aSBoris Brezillon 104493db446aSBoris Brezillon return 0; 104593db446aSBoris Brezillon } 104693db446aSBoris Brezillon 104793db446aSBoris Brezillon static void brcmnand_wp(struct mtd_info *mtd, int wp) 104893db446aSBoris Brezillon { 104993db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 105093db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 105193db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 105293db446aSBoris Brezillon 105393db446aSBoris Brezillon if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { 105493db446aSBoris Brezillon static int old_wp = -1; 105593db446aSBoris Brezillon int ret; 105693db446aSBoris Brezillon 105793db446aSBoris Brezillon if (old_wp != wp) { 105893db446aSBoris Brezillon dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); 105993db446aSBoris Brezillon old_wp = wp; 106093db446aSBoris Brezillon } 106193db446aSBoris Brezillon 106293db446aSBoris Brezillon /* 106393db446aSBoris Brezillon * make sure ctrl/flash ready before and after 106493db446aSBoris Brezillon * changing state of #WP pin 106593db446aSBoris Brezillon */ 106693db446aSBoris Brezillon ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY | 106793db446aSBoris Brezillon NAND_STATUS_READY, 106893db446aSBoris Brezillon NAND_CTRL_RDY | 106993db446aSBoris Brezillon NAND_STATUS_READY, 0); 107093db446aSBoris Brezillon if (ret) 107193db446aSBoris Brezillon return; 107293db446aSBoris Brezillon 107393db446aSBoris Brezillon brcmnand_set_wp(ctrl, wp); 107493db446aSBoris Brezillon nand_status_op(chip, NULL); 107593db446aSBoris Brezillon /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */ 107693db446aSBoris Brezillon ret = bcmnand_ctrl_poll_status(ctrl, 107793db446aSBoris Brezillon NAND_CTRL_RDY | 107893db446aSBoris Brezillon NAND_STATUS_READY | 107993db446aSBoris Brezillon NAND_STATUS_WP, 108093db446aSBoris Brezillon NAND_CTRL_RDY | 108193db446aSBoris Brezillon NAND_STATUS_READY | 108293db446aSBoris Brezillon (wp ? 0 : NAND_STATUS_WP), 0); 108393db446aSBoris Brezillon 108493db446aSBoris Brezillon if (ret) 108593db446aSBoris Brezillon dev_err_ratelimited(&host->pdev->dev, 108693db446aSBoris Brezillon "nand #WP expected %s\n", 108793db446aSBoris Brezillon wp ? "on" : "off"); 108893db446aSBoris Brezillon } 108993db446aSBoris Brezillon } 109093db446aSBoris Brezillon 109193db446aSBoris Brezillon /* Helper functions for reading and writing OOB registers */ 109293db446aSBoris Brezillon static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) 109393db446aSBoris Brezillon { 109493db446aSBoris Brezillon u16 offset0, offset10, reg_offs; 109593db446aSBoris Brezillon 109693db446aSBoris Brezillon offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; 109793db446aSBoris Brezillon offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; 109893db446aSBoris Brezillon 109993db446aSBoris Brezillon if (offs >= ctrl->max_oob) 110093db446aSBoris Brezillon return 0x77; 110193db446aSBoris Brezillon 110293db446aSBoris Brezillon if (offs >= 16 && offset10) 110393db446aSBoris Brezillon reg_offs = offset10 + ((offs - 0x10) & ~0x03); 110493db446aSBoris Brezillon else 110593db446aSBoris Brezillon reg_offs = offset0 + (offs & ~0x03); 110693db446aSBoris Brezillon 110793db446aSBoris Brezillon return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); 110893db446aSBoris Brezillon } 110993db446aSBoris Brezillon 111093db446aSBoris Brezillon static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, 111193db446aSBoris Brezillon u32 data) 111293db446aSBoris Brezillon { 111393db446aSBoris Brezillon u16 offset0, offset10, reg_offs; 111493db446aSBoris Brezillon 111593db446aSBoris Brezillon offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; 111693db446aSBoris Brezillon offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; 111793db446aSBoris Brezillon 111893db446aSBoris Brezillon if (offs >= ctrl->max_oob) 111993db446aSBoris Brezillon return; 112093db446aSBoris Brezillon 112193db446aSBoris Brezillon if (offs >= 16 && offset10) 112293db446aSBoris Brezillon reg_offs = offset10 + ((offs - 0x10) & ~0x03); 112393db446aSBoris Brezillon else 112493db446aSBoris Brezillon reg_offs = offset0 + (offs & ~0x03); 112593db446aSBoris Brezillon 112693db446aSBoris Brezillon nand_writereg(ctrl, reg_offs, data); 112793db446aSBoris Brezillon } 112893db446aSBoris Brezillon 112993db446aSBoris Brezillon /* 113093db446aSBoris Brezillon * read_oob_from_regs - read data from OOB registers 113193db446aSBoris Brezillon * @ctrl: NAND controller 113293db446aSBoris Brezillon * @i: sub-page sector index 113393db446aSBoris Brezillon * @oob: buffer to read to 113493db446aSBoris Brezillon * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 113593db446aSBoris Brezillon * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 113693db446aSBoris Brezillon */ 113793db446aSBoris Brezillon static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, 113893db446aSBoris Brezillon int sas, int sector_1k) 113993db446aSBoris Brezillon { 114093db446aSBoris Brezillon int tbytes = sas << sector_1k; 114193db446aSBoris Brezillon int j; 114293db446aSBoris Brezillon 114393db446aSBoris Brezillon /* Adjust OOB values for 1K sector size */ 114493db446aSBoris Brezillon if (sector_1k && (i & 0x01)) 114593db446aSBoris Brezillon tbytes = max(0, tbytes - (int)ctrl->max_oob); 114693db446aSBoris Brezillon tbytes = min_t(int, tbytes, ctrl->max_oob); 114793db446aSBoris Brezillon 114893db446aSBoris Brezillon for (j = 0; j < tbytes; j++) 114993db446aSBoris Brezillon oob[j] = oob_reg_read(ctrl, j); 115093db446aSBoris Brezillon return tbytes; 115193db446aSBoris Brezillon } 115293db446aSBoris Brezillon 115393db446aSBoris Brezillon /* 115493db446aSBoris Brezillon * write_oob_to_regs - write data to OOB registers 115593db446aSBoris Brezillon * @i: sub-page sector index 115693db446aSBoris Brezillon * @oob: buffer to write from 115793db446aSBoris Brezillon * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 115893db446aSBoris Brezillon * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 115993db446aSBoris Brezillon */ 116093db446aSBoris Brezillon static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, 116193db446aSBoris Brezillon const u8 *oob, int sas, int sector_1k) 116293db446aSBoris Brezillon { 116393db446aSBoris Brezillon int tbytes = sas << sector_1k; 116493db446aSBoris Brezillon int j; 116593db446aSBoris Brezillon 116693db446aSBoris Brezillon /* Adjust OOB values for 1K sector size */ 116793db446aSBoris Brezillon if (sector_1k && (i & 0x01)) 116893db446aSBoris Brezillon tbytes = max(0, tbytes - (int)ctrl->max_oob); 116993db446aSBoris Brezillon tbytes = min_t(int, tbytes, ctrl->max_oob); 117093db446aSBoris Brezillon 117193db446aSBoris Brezillon for (j = 0; j < tbytes; j += 4) 117293db446aSBoris Brezillon oob_reg_write(ctrl, j, 117393db446aSBoris Brezillon (oob[j + 0] << 24) | 117493db446aSBoris Brezillon (oob[j + 1] << 16) | 117593db446aSBoris Brezillon (oob[j + 2] << 8) | 117693db446aSBoris Brezillon (oob[j + 3] << 0)); 117793db446aSBoris Brezillon return tbytes; 117893db446aSBoris Brezillon } 117993db446aSBoris Brezillon 118093db446aSBoris Brezillon static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data) 118193db446aSBoris Brezillon { 118293db446aSBoris Brezillon struct brcmnand_controller *ctrl = data; 118393db446aSBoris Brezillon 118493db446aSBoris Brezillon /* Discard all NAND_CTLRDY interrupts during DMA */ 118593db446aSBoris Brezillon if (ctrl->dma_pending) 118693db446aSBoris Brezillon return IRQ_HANDLED; 118793db446aSBoris Brezillon 118893db446aSBoris Brezillon complete(&ctrl->done); 118993db446aSBoris Brezillon return IRQ_HANDLED; 119093db446aSBoris Brezillon } 119193db446aSBoris Brezillon 119293db446aSBoris Brezillon /* Handle SoC-specific interrupt hardware */ 119393db446aSBoris Brezillon static irqreturn_t brcmnand_irq(int irq, void *data) 119493db446aSBoris Brezillon { 119593db446aSBoris Brezillon struct brcmnand_controller *ctrl = data; 119693db446aSBoris Brezillon 119793db446aSBoris Brezillon if (ctrl->soc->ctlrdy_ack(ctrl->soc)) 119893db446aSBoris Brezillon return brcmnand_ctlrdy_irq(irq, data); 119993db446aSBoris Brezillon 120093db446aSBoris Brezillon return IRQ_NONE; 120193db446aSBoris Brezillon } 120293db446aSBoris Brezillon 120393db446aSBoris Brezillon static irqreturn_t brcmnand_dma_irq(int irq, void *data) 120493db446aSBoris Brezillon { 120593db446aSBoris Brezillon struct brcmnand_controller *ctrl = data; 120693db446aSBoris Brezillon 120793db446aSBoris Brezillon complete(&ctrl->dma_done); 120893db446aSBoris Brezillon 120993db446aSBoris Brezillon return IRQ_HANDLED; 121093db446aSBoris Brezillon } 121193db446aSBoris Brezillon 121293db446aSBoris Brezillon static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) 121393db446aSBoris Brezillon { 121493db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 121593db446aSBoris Brezillon int ret; 121693db446aSBoris Brezillon 121793db446aSBoris Brezillon dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd, 121893db446aSBoris Brezillon brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS)); 121993db446aSBoris Brezillon BUG_ON(ctrl->cmd_pending != 0); 122093db446aSBoris Brezillon ctrl->cmd_pending = cmd; 122193db446aSBoris Brezillon 122293db446aSBoris Brezillon ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); 122393db446aSBoris Brezillon WARN_ON(ret); 122493db446aSBoris Brezillon 122593db446aSBoris Brezillon mb(); /* flush previous writes */ 122693db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, 122793db446aSBoris Brezillon cmd << brcmnand_cmd_shift(ctrl)); 122893db446aSBoris Brezillon } 122993db446aSBoris Brezillon 123093db446aSBoris Brezillon /*********************************************************************** 123193db446aSBoris Brezillon * NAND MTD API: read/program/erase 123293db446aSBoris Brezillon ***********************************************************************/ 123393db446aSBoris Brezillon 123493db446aSBoris Brezillon static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat, 123593db446aSBoris Brezillon unsigned int ctrl) 123693db446aSBoris Brezillon { 123793db446aSBoris Brezillon /* intentionally left blank */ 123893db446aSBoris Brezillon } 123993db446aSBoris Brezillon 124093db446aSBoris Brezillon static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) 124193db446aSBoris Brezillon { 124293db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 124393db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 124493db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 124593db446aSBoris Brezillon unsigned long timeo = msecs_to_jiffies(100); 124693db446aSBoris Brezillon 124793db446aSBoris Brezillon dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); 124893db446aSBoris Brezillon if (ctrl->cmd_pending && 124993db446aSBoris Brezillon wait_for_completion_timeout(&ctrl->done, timeo) <= 0) { 125093db446aSBoris Brezillon u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) 125193db446aSBoris Brezillon >> brcmnand_cmd_shift(ctrl); 125293db446aSBoris Brezillon 125393db446aSBoris Brezillon dev_err_ratelimited(ctrl->dev, 125493db446aSBoris Brezillon "timeout waiting for command %#02x\n", cmd); 125593db446aSBoris Brezillon dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", 125693db446aSBoris Brezillon brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); 125793db446aSBoris Brezillon } 125893db446aSBoris Brezillon ctrl->cmd_pending = 0; 125993db446aSBoris Brezillon return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 126093db446aSBoris Brezillon INTFC_FLASH_STATUS; 126193db446aSBoris Brezillon } 126293db446aSBoris Brezillon 126393db446aSBoris Brezillon enum { 126493db446aSBoris Brezillon LLOP_RE = BIT(16), 126593db446aSBoris Brezillon LLOP_WE = BIT(17), 126693db446aSBoris Brezillon LLOP_ALE = BIT(18), 126793db446aSBoris Brezillon LLOP_CLE = BIT(19), 126893db446aSBoris Brezillon LLOP_RETURN_IDLE = BIT(31), 126993db446aSBoris Brezillon 127093db446aSBoris Brezillon LLOP_DATA_MASK = GENMASK(15, 0), 127193db446aSBoris Brezillon }; 127293db446aSBoris Brezillon 127393db446aSBoris Brezillon static int brcmnand_low_level_op(struct brcmnand_host *host, 127493db446aSBoris Brezillon enum brcmnand_llop_type type, u32 data, 127593db446aSBoris Brezillon bool last_op) 127693db446aSBoris Brezillon { 127793db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(&host->chip); 127893db446aSBoris Brezillon struct nand_chip *chip = &host->chip; 127993db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 128093db446aSBoris Brezillon u32 tmp; 128193db446aSBoris Brezillon 128293db446aSBoris Brezillon tmp = data & LLOP_DATA_MASK; 128393db446aSBoris Brezillon switch (type) { 128493db446aSBoris Brezillon case LL_OP_CMD: 128593db446aSBoris Brezillon tmp |= LLOP_WE | LLOP_CLE; 128693db446aSBoris Brezillon break; 128793db446aSBoris Brezillon case LL_OP_ADDR: 128893db446aSBoris Brezillon /* WE | ALE */ 128993db446aSBoris Brezillon tmp |= LLOP_WE | LLOP_ALE; 129093db446aSBoris Brezillon break; 129193db446aSBoris Brezillon case LL_OP_WR: 129293db446aSBoris Brezillon /* WE */ 129393db446aSBoris Brezillon tmp |= LLOP_WE; 129493db446aSBoris Brezillon break; 129593db446aSBoris Brezillon case LL_OP_RD: 129693db446aSBoris Brezillon /* RE */ 129793db446aSBoris Brezillon tmp |= LLOP_RE; 129893db446aSBoris Brezillon break; 129993db446aSBoris Brezillon } 130093db446aSBoris Brezillon if (last_op) 130193db446aSBoris Brezillon /* RETURN_IDLE */ 130293db446aSBoris Brezillon tmp |= LLOP_RETURN_IDLE; 130393db446aSBoris Brezillon 130493db446aSBoris Brezillon dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); 130593db446aSBoris Brezillon 130693db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); 130793db446aSBoris Brezillon (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); 130893db446aSBoris Brezillon 130993db446aSBoris Brezillon brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP); 131093db446aSBoris Brezillon return brcmnand_waitfunc(mtd, chip); 131193db446aSBoris Brezillon } 131293db446aSBoris Brezillon 131393db446aSBoris Brezillon static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command, 131493db446aSBoris Brezillon int column, int page_addr) 131593db446aSBoris Brezillon { 131693db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 131793db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 131893db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 131993db446aSBoris Brezillon u64 addr = (u64)page_addr << chip->page_shift; 132093db446aSBoris Brezillon int native_cmd = 0; 132193db446aSBoris Brezillon 132293db446aSBoris Brezillon if (command == NAND_CMD_READID || command == NAND_CMD_PARAM || 132393db446aSBoris Brezillon command == NAND_CMD_RNDOUT) 132493db446aSBoris Brezillon addr = (u64)column; 132593db446aSBoris Brezillon /* Avoid propagating a negative, don't-care address */ 132693db446aSBoris Brezillon else if (page_addr < 0) 132793db446aSBoris Brezillon addr = 0; 132893db446aSBoris Brezillon 132993db446aSBoris Brezillon dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, 133093db446aSBoris Brezillon (unsigned long long)addr); 133193db446aSBoris Brezillon 133293db446aSBoris Brezillon host->last_cmd = command; 133393db446aSBoris Brezillon host->last_byte = 0; 133493db446aSBoris Brezillon host->last_addr = addr; 133593db446aSBoris Brezillon 133693db446aSBoris Brezillon switch (command) { 133793db446aSBoris Brezillon case NAND_CMD_RESET: 133893db446aSBoris Brezillon native_cmd = CMD_FLASH_RESET; 133993db446aSBoris Brezillon break; 134093db446aSBoris Brezillon case NAND_CMD_STATUS: 134193db446aSBoris Brezillon native_cmd = CMD_STATUS_READ; 134293db446aSBoris Brezillon break; 134393db446aSBoris Brezillon case NAND_CMD_READID: 134493db446aSBoris Brezillon native_cmd = CMD_DEVICE_ID_READ; 134593db446aSBoris Brezillon break; 134693db446aSBoris Brezillon case NAND_CMD_READOOB: 134793db446aSBoris Brezillon native_cmd = CMD_SPARE_AREA_READ; 134893db446aSBoris Brezillon break; 134993db446aSBoris Brezillon case NAND_CMD_ERASE1: 135093db446aSBoris Brezillon native_cmd = CMD_BLOCK_ERASE; 135193db446aSBoris Brezillon brcmnand_wp(mtd, 0); 135293db446aSBoris Brezillon break; 135393db446aSBoris Brezillon case NAND_CMD_PARAM: 135493db446aSBoris Brezillon native_cmd = CMD_PARAMETER_READ; 135593db446aSBoris Brezillon break; 135693db446aSBoris Brezillon case NAND_CMD_SET_FEATURES: 135793db446aSBoris Brezillon case NAND_CMD_GET_FEATURES: 135893db446aSBoris Brezillon brcmnand_low_level_op(host, LL_OP_CMD, command, false); 135993db446aSBoris Brezillon brcmnand_low_level_op(host, LL_OP_ADDR, column, false); 136093db446aSBoris Brezillon break; 136193db446aSBoris Brezillon case NAND_CMD_RNDOUT: 136293db446aSBoris Brezillon native_cmd = CMD_PARAMETER_CHANGE_COL; 136393db446aSBoris Brezillon addr &= ~((u64)(FC_BYTES - 1)); 136493db446aSBoris Brezillon /* 136593db446aSBoris Brezillon * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0 136693db446aSBoris Brezillon * NB: hwcfg.sector_size_1k may not be initialized yet 136793db446aSBoris Brezillon */ 136893db446aSBoris Brezillon if (brcmnand_get_sector_size_1k(host)) { 136993db446aSBoris Brezillon host->hwcfg.sector_size_1k = 137093db446aSBoris Brezillon brcmnand_get_sector_size_1k(host); 137193db446aSBoris Brezillon brcmnand_set_sector_size_1k(host, 0); 137293db446aSBoris Brezillon } 137393db446aSBoris Brezillon break; 137493db446aSBoris Brezillon } 137593db446aSBoris Brezillon 137693db446aSBoris Brezillon if (!native_cmd) 137793db446aSBoris Brezillon return; 137893db446aSBoris Brezillon 137993db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, 138093db446aSBoris Brezillon (host->cs << 16) | ((addr >> 32) & 0xffff)); 138193db446aSBoris Brezillon (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); 138293db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr)); 138393db446aSBoris Brezillon (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 138493db446aSBoris Brezillon 138593db446aSBoris Brezillon brcmnand_send_cmd(host, native_cmd); 138693db446aSBoris Brezillon brcmnand_waitfunc(mtd, chip); 138793db446aSBoris Brezillon 138893db446aSBoris Brezillon if (native_cmd == CMD_PARAMETER_READ || 138993db446aSBoris Brezillon native_cmd == CMD_PARAMETER_CHANGE_COL) { 139093db446aSBoris Brezillon /* Copy flash cache word-wise */ 139193db446aSBoris Brezillon u32 *flash_cache = (u32 *)ctrl->flash_cache; 139293db446aSBoris Brezillon int i; 139393db446aSBoris Brezillon 139493db446aSBoris Brezillon brcmnand_soc_data_bus_prepare(ctrl->soc, true); 139593db446aSBoris Brezillon 139693db446aSBoris Brezillon /* 139793db446aSBoris Brezillon * Must cache the FLASH_CACHE now, since changes in 139893db446aSBoris Brezillon * SECTOR_SIZE_1K may invalidate it 139993db446aSBoris Brezillon */ 140093db446aSBoris Brezillon for (i = 0; i < FC_WORDS; i++) 140193db446aSBoris Brezillon /* 140293db446aSBoris Brezillon * Flash cache is big endian for parameter pages, at 140393db446aSBoris Brezillon * least on STB SoCs 140493db446aSBoris Brezillon */ 140593db446aSBoris Brezillon flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i)); 140693db446aSBoris Brezillon 140793db446aSBoris Brezillon brcmnand_soc_data_bus_unprepare(ctrl->soc, true); 140893db446aSBoris Brezillon 140993db446aSBoris Brezillon /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */ 141093db446aSBoris Brezillon if (host->hwcfg.sector_size_1k) 141193db446aSBoris Brezillon brcmnand_set_sector_size_1k(host, 141293db446aSBoris Brezillon host->hwcfg.sector_size_1k); 141393db446aSBoris Brezillon } 141493db446aSBoris Brezillon 141593db446aSBoris Brezillon /* Re-enable protection is necessary only after erase */ 141693db446aSBoris Brezillon if (command == NAND_CMD_ERASE1) 141793db446aSBoris Brezillon brcmnand_wp(mtd, 1); 141893db446aSBoris Brezillon } 141993db446aSBoris Brezillon 142093db446aSBoris Brezillon static uint8_t brcmnand_read_byte(struct mtd_info *mtd) 142193db446aSBoris Brezillon { 142293db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 142393db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 142493db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 142593db446aSBoris Brezillon uint8_t ret = 0; 142693db446aSBoris Brezillon int addr, offs; 142793db446aSBoris Brezillon 142893db446aSBoris Brezillon switch (host->last_cmd) { 142993db446aSBoris Brezillon case NAND_CMD_READID: 143093db446aSBoris Brezillon if (host->last_byte < 4) 143193db446aSBoris Brezillon ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >> 143293db446aSBoris Brezillon (24 - (host->last_byte << 3)); 143393db446aSBoris Brezillon else if (host->last_byte < 8) 143493db446aSBoris Brezillon ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >> 143593db446aSBoris Brezillon (56 - (host->last_byte << 3)); 143693db446aSBoris Brezillon break; 143793db446aSBoris Brezillon 143893db446aSBoris Brezillon case NAND_CMD_READOOB: 143993db446aSBoris Brezillon ret = oob_reg_read(ctrl, host->last_byte); 144093db446aSBoris Brezillon break; 144193db446aSBoris Brezillon 144293db446aSBoris Brezillon case NAND_CMD_STATUS: 144393db446aSBoris Brezillon ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 144493db446aSBoris Brezillon INTFC_FLASH_STATUS; 144593db446aSBoris Brezillon if (wp_on) /* hide WP status */ 144693db446aSBoris Brezillon ret |= NAND_STATUS_WP; 144793db446aSBoris Brezillon break; 144893db446aSBoris Brezillon 144993db446aSBoris Brezillon case NAND_CMD_PARAM: 145093db446aSBoris Brezillon case NAND_CMD_RNDOUT: 145193db446aSBoris Brezillon addr = host->last_addr + host->last_byte; 145293db446aSBoris Brezillon offs = addr & (FC_BYTES - 1); 145393db446aSBoris Brezillon 145493db446aSBoris Brezillon /* At FC_BYTES boundary, switch to next column */ 145593db446aSBoris Brezillon if (host->last_byte > 0 && offs == 0) 145693db446aSBoris Brezillon nand_change_read_column_op(chip, addr, NULL, 0, false); 145793db446aSBoris Brezillon 145893db446aSBoris Brezillon ret = ctrl->flash_cache[offs]; 145993db446aSBoris Brezillon break; 146093db446aSBoris Brezillon case NAND_CMD_GET_FEATURES: 146193db446aSBoris Brezillon if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { 146293db446aSBoris Brezillon ret = 0; 146393db446aSBoris Brezillon } else { 146493db446aSBoris Brezillon bool last = host->last_byte == 146593db446aSBoris Brezillon ONFI_SUBFEATURE_PARAM_LEN - 1; 146693db446aSBoris Brezillon brcmnand_low_level_op(host, LL_OP_RD, 0, last); 146793db446aSBoris Brezillon ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff; 146893db446aSBoris Brezillon } 146993db446aSBoris Brezillon } 147093db446aSBoris Brezillon 147193db446aSBoris Brezillon dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); 147293db446aSBoris Brezillon host->last_byte++; 147393db446aSBoris Brezillon 147493db446aSBoris Brezillon return ret; 147593db446aSBoris Brezillon } 147693db446aSBoris Brezillon 147793db446aSBoris Brezillon static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 147893db446aSBoris Brezillon { 147993db446aSBoris Brezillon int i; 148093db446aSBoris Brezillon 148193db446aSBoris Brezillon for (i = 0; i < len; i++, buf++) 148293db446aSBoris Brezillon *buf = brcmnand_read_byte(mtd); 148393db446aSBoris Brezillon } 148493db446aSBoris Brezillon 148593db446aSBoris Brezillon static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf, 148693db446aSBoris Brezillon int len) 148793db446aSBoris Brezillon { 148893db446aSBoris Brezillon int i; 148993db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd); 149093db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 149193db446aSBoris Brezillon 149293db446aSBoris Brezillon switch (host->last_cmd) { 149393db446aSBoris Brezillon case NAND_CMD_SET_FEATURES: 149493db446aSBoris Brezillon for (i = 0; i < len; i++) 149593db446aSBoris Brezillon brcmnand_low_level_op(host, LL_OP_WR, buf[i], 149693db446aSBoris Brezillon (i + 1) == len); 149793db446aSBoris Brezillon break; 149893db446aSBoris Brezillon default: 149993db446aSBoris Brezillon BUG(); 150093db446aSBoris Brezillon break; 150193db446aSBoris Brezillon } 150293db446aSBoris Brezillon } 150393db446aSBoris Brezillon 150493db446aSBoris Brezillon /** 150593db446aSBoris Brezillon * Construct a FLASH_DMA descriptor as part of a linked list. You must know the 150693db446aSBoris Brezillon * following ahead of time: 150793db446aSBoris Brezillon * - Is this descriptor the beginning or end of a linked list? 150893db446aSBoris Brezillon * - What is the (DMA) address of the next descriptor in the linked list? 150993db446aSBoris Brezillon */ 151093db446aSBoris Brezillon static int brcmnand_fill_dma_desc(struct brcmnand_host *host, 151193db446aSBoris Brezillon struct brcm_nand_dma_desc *desc, u64 addr, 151293db446aSBoris Brezillon dma_addr_t buf, u32 len, u8 dma_cmd, 151393db446aSBoris Brezillon bool begin, bool end, 151493db446aSBoris Brezillon dma_addr_t next_desc) 151593db446aSBoris Brezillon { 151693db446aSBoris Brezillon memset(desc, 0, sizeof(*desc)); 151793db446aSBoris Brezillon /* Descriptors are written in native byte order (wordwise) */ 151893db446aSBoris Brezillon desc->next_desc = lower_32_bits(next_desc); 151993db446aSBoris Brezillon desc->next_desc_ext = upper_32_bits(next_desc); 152093db446aSBoris Brezillon desc->cmd_irq = (dma_cmd << 24) | 152193db446aSBoris Brezillon (end ? (0x03 << 8) : 0) | /* IRQ | STOP */ 152293db446aSBoris Brezillon (!!begin) | ((!!end) << 1); /* head, tail */ 152393db446aSBoris Brezillon #ifdef CONFIG_CPU_BIG_ENDIAN 152493db446aSBoris Brezillon desc->cmd_irq |= 0x01 << 12; 152593db446aSBoris Brezillon #endif 152693db446aSBoris Brezillon desc->dram_addr = lower_32_bits(buf); 152793db446aSBoris Brezillon desc->dram_addr_ext = upper_32_bits(buf); 152893db446aSBoris Brezillon desc->tfr_len = len; 152993db446aSBoris Brezillon desc->total_len = len; 153093db446aSBoris Brezillon desc->flash_addr = lower_32_bits(addr); 153193db446aSBoris Brezillon desc->flash_addr_ext = upper_32_bits(addr); 153293db446aSBoris Brezillon desc->cs = host->cs; 153393db446aSBoris Brezillon desc->status_valid = 0x01; 153493db446aSBoris Brezillon return 0; 153593db446aSBoris Brezillon } 153693db446aSBoris Brezillon 153793db446aSBoris Brezillon /** 153893db446aSBoris Brezillon * Kick the FLASH_DMA engine, with a given DMA descriptor 153993db446aSBoris Brezillon */ 154093db446aSBoris Brezillon static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc) 154193db446aSBoris Brezillon { 154293db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 154393db446aSBoris Brezillon unsigned long timeo = msecs_to_jiffies(100); 154493db446aSBoris Brezillon 154593db446aSBoris Brezillon flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); 154693db446aSBoris Brezillon (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); 154793db446aSBoris Brezillon flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc)); 154893db446aSBoris Brezillon (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); 154993db446aSBoris Brezillon 155093db446aSBoris Brezillon /* Start FLASH_DMA engine */ 155193db446aSBoris Brezillon ctrl->dma_pending = true; 155293db446aSBoris Brezillon mb(); /* flush previous writes */ 155393db446aSBoris Brezillon flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ 155493db446aSBoris Brezillon 155593db446aSBoris Brezillon if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { 155693db446aSBoris Brezillon dev_err(ctrl->dev, 155793db446aSBoris Brezillon "timeout waiting for DMA; status %#x, error status %#x\n", 155893db446aSBoris Brezillon flash_dma_readl(ctrl, FLASH_DMA_STATUS), 155993db446aSBoris Brezillon flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); 156093db446aSBoris Brezillon } 156193db446aSBoris Brezillon ctrl->dma_pending = false; 156293db446aSBoris Brezillon flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ 156393db446aSBoris Brezillon } 156493db446aSBoris Brezillon 156593db446aSBoris Brezillon static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf, 156693db446aSBoris Brezillon u32 len, u8 dma_cmd) 156793db446aSBoris Brezillon { 156893db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 156993db446aSBoris Brezillon dma_addr_t buf_pa; 157093db446aSBoris Brezillon int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 157193db446aSBoris Brezillon 157293db446aSBoris Brezillon buf_pa = dma_map_single(ctrl->dev, buf, len, dir); 157393db446aSBoris Brezillon if (dma_mapping_error(ctrl->dev, buf_pa)) { 157493db446aSBoris Brezillon dev_err(ctrl->dev, "unable to map buffer for DMA\n"); 157593db446aSBoris Brezillon return -ENOMEM; 157693db446aSBoris Brezillon } 157793db446aSBoris Brezillon 157893db446aSBoris Brezillon brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, 157993db446aSBoris Brezillon dma_cmd, true, true, 0); 158093db446aSBoris Brezillon 158193db446aSBoris Brezillon brcmnand_dma_run(host, ctrl->dma_pa); 158293db446aSBoris Brezillon 158393db446aSBoris Brezillon dma_unmap_single(ctrl->dev, buf_pa, len, dir); 158493db446aSBoris Brezillon 158593db446aSBoris Brezillon if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) 158693db446aSBoris Brezillon return -EBADMSG; 158793db446aSBoris Brezillon else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) 158893db446aSBoris Brezillon return -EUCLEAN; 158993db446aSBoris Brezillon 159093db446aSBoris Brezillon return 0; 159193db446aSBoris Brezillon } 159293db446aSBoris Brezillon 159393db446aSBoris Brezillon /* 159493db446aSBoris Brezillon * Assumes proper CS is already set 159593db446aSBoris Brezillon */ 159693db446aSBoris Brezillon static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, 159793db446aSBoris Brezillon u64 addr, unsigned int trans, u32 *buf, 159893db446aSBoris Brezillon u8 *oob, u64 *err_addr) 159993db446aSBoris Brezillon { 160093db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 160193db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 160293db446aSBoris Brezillon int i, j, ret = 0; 160393db446aSBoris Brezillon 160493db446aSBoris Brezillon /* Clear error addresses */ 160593db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); 160693db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); 160793db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); 160893db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); 160993db446aSBoris Brezillon 161093db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, 161193db446aSBoris Brezillon (host->cs << 16) | ((addr >> 32) & 0xffff)); 161293db446aSBoris Brezillon (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); 161393db446aSBoris Brezillon 161493db446aSBoris Brezillon for (i = 0; i < trans; i++, addr += FC_BYTES) { 161593db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 161693db446aSBoris Brezillon lower_32_bits(addr)); 161793db446aSBoris Brezillon (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 161893db446aSBoris Brezillon /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ 161993db446aSBoris Brezillon brcmnand_send_cmd(host, CMD_PAGE_READ); 162093db446aSBoris Brezillon brcmnand_waitfunc(mtd, chip); 162193db446aSBoris Brezillon 162293db446aSBoris Brezillon if (likely(buf)) { 162393db446aSBoris Brezillon brcmnand_soc_data_bus_prepare(ctrl->soc, false); 162493db446aSBoris Brezillon 162593db446aSBoris Brezillon for (j = 0; j < FC_WORDS; j++, buf++) 162693db446aSBoris Brezillon *buf = brcmnand_read_fc(ctrl, j); 162793db446aSBoris Brezillon 162893db446aSBoris Brezillon brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 162993db446aSBoris Brezillon } 163093db446aSBoris Brezillon 163193db446aSBoris Brezillon if (oob) 163293db446aSBoris Brezillon oob += read_oob_from_regs(ctrl, i, oob, 163393db446aSBoris Brezillon mtd->oobsize / trans, 163493db446aSBoris Brezillon host->hwcfg.sector_size_1k); 163593db446aSBoris Brezillon 163693db446aSBoris Brezillon if (!ret) { 163793db446aSBoris Brezillon *err_addr = brcmnand_read_reg(ctrl, 163893db446aSBoris Brezillon BRCMNAND_UNCORR_ADDR) | 163993db446aSBoris Brezillon ((u64)(brcmnand_read_reg(ctrl, 164093db446aSBoris Brezillon BRCMNAND_UNCORR_EXT_ADDR) 164193db446aSBoris Brezillon & 0xffff) << 32); 164293db446aSBoris Brezillon if (*err_addr) 164393db446aSBoris Brezillon ret = -EBADMSG; 164493db446aSBoris Brezillon } 164593db446aSBoris Brezillon 164693db446aSBoris Brezillon if (!ret) { 164793db446aSBoris Brezillon *err_addr = brcmnand_read_reg(ctrl, 164893db446aSBoris Brezillon BRCMNAND_CORR_ADDR) | 164993db446aSBoris Brezillon ((u64)(brcmnand_read_reg(ctrl, 165093db446aSBoris Brezillon BRCMNAND_CORR_EXT_ADDR) 165193db446aSBoris Brezillon & 0xffff) << 32); 165293db446aSBoris Brezillon if (*err_addr) 165393db446aSBoris Brezillon ret = -EUCLEAN; 165493db446aSBoris Brezillon } 165593db446aSBoris Brezillon } 165693db446aSBoris Brezillon 165793db446aSBoris Brezillon return ret; 165893db446aSBoris Brezillon } 165993db446aSBoris Brezillon 166093db446aSBoris Brezillon /* 166193db446aSBoris Brezillon * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC 166293db446aSBoris Brezillon * error 166393db446aSBoris Brezillon * 166493db446aSBoris Brezillon * Because the HW ECC signals an ECC error if an erase paged has even a single 166593db446aSBoris Brezillon * bitflip, we must check each ECC error to see if it is actually an erased 166693db446aSBoris Brezillon * page with bitflips, not a truly corrupted page. 166793db446aSBoris Brezillon * 166893db446aSBoris Brezillon * On a real error, return a negative error code (-EBADMSG for ECC error), and 166993db446aSBoris Brezillon * buf will contain raw data. 167093db446aSBoris Brezillon * Otherwise, buf gets filled with 0xffs and return the maximum number of 167193db446aSBoris Brezillon * bitflips-per-ECC-sector to the caller. 167293db446aSBoris Brezillon * 167393db446aSBoris Brezillon */ 167493db446aSBoris Brezillon static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd, 167593db446aSBoris Brezillon struct nand_chip *chip, void *buf, u64 addr) 167693db446aSBoris Brezillon { 167793db446aSBoris Brezillon int i, sas; 167893db446aSBoris Brezillon void *oob = chip->oob_poi; 167993db446aSBoris Brezillon int bitflips = 0; 168093db446aSBoris Brezillon int page = addr >> chip->page_shift; 168193db446aSBoris Brezillon int ret; 168293db446aSBoris Brezillon 168393db446aSBoris Brezillon if (!buf) { 168493db446aSBoris Brezillon buf = chip->data_buf; 168593db446aSBoris Brezillon /* Invalidate page cache */ 168693db446aSBoris Brezillon chip->pagebuf = -1; 168793db446aSBoris Brezillon } 168893db446aSBoris Brezillon 168993db446aSBoris Brezillon sas = mtd->oobsize / chip->ecc.steps; 169093db446aSBoris Brezillon 169193db446aSBoris Brezillon /* read without ecc for verification */ 169293db446aSBoris Brezillon ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page); 169393db446aSBoris Brezillon if (ret) 169493db446aSBoris Brezillon return ret; 169593db446aSBoris Brezillon 169693db446aSBoris Brezillon for (i = 0; i < chip->ecc.steps; i++, oob += sas) { 169793db446aSBoris Brezillon ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size, 169893db446aSBoris Brezillon oob, sas, NULL, 0, 169993db446aSBoris Brezillon chip->ecc.strength); 170093db446aSBoris Brezillon if (ret < 0) 170193db446aSBoris Brezillon return ret; 170293db446aSBoris Brezillon 170393db446aSBoris Brezillon bitflips = max(bitflips, ret); 170493db446aSBoris Brezillon } 170593db446aSBoris Brezillon 170693db446aSBoris Brezillon return bitflips; 170793db446aSBoris Brezillon } 170893db446aSBoris Brezillon 170993db446aSBoris Brezillon static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, 171093db446aSBoris Brezillon u64 addr, unsigned int trans, u32 *buf, u8 *oob) 171193db446aSBoris Brezillon { 171293db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 171393db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 171493db446aSBoris Brezillon u64 err_addr = 0; 171593db446aSBoris Brezillon int err; 171693db446aSBoris Brezillon bool retry = true; 171793db446aSBoris Brezillon 171893db446aSBoris Brezillon dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); 171993db446aSBoris Brezillon 172093db446aSBoris Brezillon try_dmaread: 172193db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0); 172293db446aSBoris Brezillon 172393db446aSBoris Brezillon if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { 172493db446aSBoris Brezillon err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES, 172593db446aSBoris Brezillon CMD_PAGE_READ); 172693db446aSBoris Brezillon if (err) { 172793db446aSBoris Brezillon if (mtd_is_bitflip_or_eccerr(err)) 172893db446aSBoris Brezillon err_addr = addr; 172993db446aSBoris Brezillon else 173093db446aSBoris Brezillon return -EIO; 173193db446aSBoris Brezillon } 173293db446aSBoris Brezillon } else { 173393db446aSBoris Brezillon if (oob) 173493db446aSBoris Brezillon memset(oob, 0x99, mtd->oobsize); 173593db446aSBoris Brezillon 173693db446aSBoris Brezillon err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, 173793db446aSBoris Brezillon oob, &err_addr); 173893db446aSBoris Brezillon } 173993db446aSBoris Brezillon 174093db446aSBoris Brezillon if (mtd_is_eccerr(err)) { 174193db446aSBoris Brezillon /* 174293db446aSBoris Brezillon * On controller version and 7.0, 7.1 , DMA read after a 174393db446aSBoris Brezillon * prior PIO read that reported uncorrectable error, 174493db446aSBoris Brezillon * the DMA engine captures this error following DMA read 174593db446aSBoris Brezillon * cleared only on subsequent DMA read, so just retry once 174693db446aSBoris Brezillon * to clear a possible false error reported for current DMA 174793db446aSBoris Brezillon * read 174893db446aSBoris Brezillon */ 174993db446aSBoris Brezillon if ((ctrl->nand_version == 0x0700) || 175093db446aSBoris Brezillon (ctrl->nand_version == 0x0701)) { 175193db446aSBoris Brezillon if (retry) { 175293db446aSBoris Brezillon retry = false; 175393db446aSBoris Brezillon goto try_dmaread; 175493db446aSBoris Brezillon } 175593db446aSBoris Brezillon } 175693db446aSBoris Brezillon 175793db446aSBoris Brezillon /* 175893db446aSBoris Brezillon * Controller version 7.2 has hw encoder to detect erased page 175993db446aSBoris Brezillon * bitflips, apply sw verification for older controllers only 176093db446aSBoris Brezillon */ 176193db446aSBoris Brezillon if (ctrl->nand_version < 0x0702) { 176293db446aSBoris Brezillon err = brcmstb_nand_verify_erased_page(mtd, chip, buf, 176393db446aSBoris Brezillon addr); 176493db446aSBoris Brezillon /* erased page bitflips corrected */ 176593db446aSBoris Brezillon if (err >= 0) 176693db446aSBoris Brezillon return err; 176793db446aSBoris Brezillon } 176893db446aSBoris Brezillon 176993db446aSBoris Brezillon dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", 177093db446aSBoris Brezillon (unsigned long long)err_addr); 177193db446aSBoris Brezillon mtd->ecc_stats.failed++; 177293db446aSBoris Brezillon /* NAND layer expects zero on ECC errors */ 177393db446aSBoris Brezillon return 0; 177493db446aSBoris Brezillon } 177593db446aSBoris Brezillon 177693db446aSBoris Brezillon if (mtd_is_bitflip(err)) { 177793db446aSBoris Brezillon unsigned int corrected = brcmnand_count_corrected(ctrl); 177893db446aSBoris Brezillon 177993db446aSBoris Brezillon dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", 178093db446aSBoris Brezillon (unsigned long long)err_addr); 178193db446aSBoris Brezillon mtd->ecc_stats.corrected += corrected; 178293db446aSBoris Brezillon /* Always exceed the software-imposed threshold */ 178393db446aSBoris Brezillon return max(mtd->bitflip_threshold, corrected); 178493db446aSBoris Brezillon } 178593db446aSBoris Brezillon 178693db446aSBoris Brezillon return 0; 178793db446aSBoris Brezillon } 178893db446aSBoris Brezillon 178993db446aSBoris Brezillon static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip, 179093db446aSBoris Brezillon uint8_t *buf, int oob_required, int page) 179193db446aSBoris Brezillon { 179293db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 179393db446aSBoris Brezillon u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 179493db446aSBoris Brezillon 179593db446aSBoris Brezillon nand_read_page_op(chip, page, 0, NULL, 0); 179693db446aSBoris Brezillon 179793db446aSBoris Brezillon return brcmnand_read(mtd, chip, host->last_addr, 179893db446aSBoris Brezillon mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); 179993db446aSBoris Brezillon } 180093db446aSBoris Brezillon 180193db446aSBoris Brezillon static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 180293db446aSBoris Brezillon uint8_t *buf, int oob_required, int page) 180393db446aSBoris Brezillon { 180493db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 180593db446aSBoris Brezillon u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 180693db446aSBoris Brezillon int ret; 180793db446aSBoris Brezillon 180893db446aSBoris Brezillon nand_read_page_op(chip, page, 0, NULL, 0); 180993db446aSBoris Brezillon 181093db446aSBoris Brezillon brcmnand_set_ecc_enabled(host, 0); 181193db446aSBoris Brezillon ret = brcmnand_read(mtd, chip, host->last_addr, 181293db446aSBoris Brezillon mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); 181393db446aSBoris Brezillon brcmnand_set_ecc_enabled(host, 1); 181493db446aSBoris Brezillon return ret; 181593db446aSBoris Brezillon } 181693db446aSBoris Brezillon 181793db446aSBoris Brezillon static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 181893db446aSBoris Brezillon int page) 181993db446aSBoris Brezillon { 182093db446aSBoris Brezillon return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 182193db446aSBoris Brezillon mtd->writesize >> FC_SHIFT, 182293db446aSBoris Brezillon NULL, (u8 *)chip->oob_poi); 182393db446aSBoris Brezillon } 182493db446aSBoris Brezillon 182593db446aSBoris Brezillon static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, 182693db446aSBoris Brezillon int page) 182793db446aSBoris Brezillon { 182893db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 182993db446aSBoris Brezillon 183093db446aSBoris Brezillon brcmnand_set_ecc_enabled(host, 0); 183193db446aSBoris Brezillon brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 183293db446aSBoris Brezillon mtd->writesize >> FC_SHIFT, 183393db446aSBoris Brezillon NULL, (u8 *)chip->oob_poi); 183493db446aSBoris Brezillon brcmnand_set_ecc_enabled(host, 1); 183593db446aSBoris Brezillon return 0; 183693db446aSBoris Brezillon } 183793db446aSBoris Brezillon 183893db446aSBoris Brezillon static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, 183993db446aSBoris Brezillon u64 addr, const u32 *buf, u8 *oob) 184093db446aSBoris Brezillon { 184193db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 184293db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 184393db446aSBoris Brezillon unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; 184493db446aSBoris Brezillon int status, ret = 0; 184593db446aSBoris Brezillon 184693db446aSBoris Brezillon dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); 184793db446aSBoris Brezillon 184893db446aSBoris Brezillon if (unlikely((unsigned long)buf & 0x03)) { 184993db446aSBoris Brezillon dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); 185093db446aSBoris Brezillon buf = (u32 *)((unsigned long)buf & ~0x03); 185193db446aSBoris Brezillon } 185293db446aSBoris Brezillon 185393db446aSBoris Brezillon brcmnand_wp(mtd, 0); 185493db446aSBoris Brezillon 185593db446aSBoris Brezillon for (i = 0; i < ctrl->max_oob; i += 4) 185693db446aSBoris Brezillon oob_reg_write(ctrl, i, 0xffffffff); 185793db446aSBoris Brezillon 185893db446aSBoris Brezillon if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { 185993db446aSBoris Brezillon if (brcmnand_dma_trans(host, addr, (u32 *)buf, 186093db446aSBoris Brezillon mtd->writesize, CMD_PROGRAM_PAGE)) 186193db446aSBoris Brezillon ret = -EIO; 186293db446aSBoris Brezillon goto out; 186393db446aSBoris Brezillon } 186493db446aSBoris Brezillon 186593db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, 186693db446aSBoris Brezillon (host->cs << 16) | ((addr >> 32) & 0xffff)); 186793db446aSBoris Brezillon (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); 186893db446aSBoris Brezillon 186993db446aSBoris Brezillon for (i = 0; i < trans; i++, addr += FC_BYTES) { 187093db446aSBoris Brezillon /* full address MUST be set before populating FC */ 187193db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 187293db446aSBoris Brezillon lower_32_bits(addr)); 187393db446aSBoris Brezillon (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 187493db446aSBoris Brezillon 187593db446aSBoris Brezillon if (buf) { 187693db446aSBoris Brezillon brcmnand_soc_data_bus_prepare(ctrl->soc, false); 187793db446aSBoris Brezillon 187893db446aSBoris Brezillon for (j = 0; j < FC_WORDS; j++, buf++) 187993db446aSBoris Brezillon brcmnand_write_fc(ctrl, j, *buf); 188093db446aSBoris Brezillon 188193db446aSBoris Brezillon brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 188293db446aSBoris Brezillon } else if (oob) { 188393db446aSBoris Brezillon for (j = 0; j < FC_WORDS; j++) 188493db446aSBoris Brezillon brcmnand_write_fc(ctrl, j, 0xffffffff); 188593db446aSBoris Brezillon } 188693db446aSBoris Brezillon 188793db446aSBoris Brezillon if (oob) { 188893db446aSBoris Brezillon oob += write_oob_to_regs(ctrl, i, oob, 188993db446aSBoris Brezillon mtd->oobsize / trans, 189093db446aSBoris Brezillon host->hwcfg.sector_size_1k); 189193db446aSBoris Brezillon } 189293db446aSBoris Brezillon 189393db446aSBoris Brezillon /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */ 189493db446aSBoris Brezillon brcmnand_send_cmd(host, CMD_PROGRAM_PAGE); 189593db446aSBoris Brezillon status = brcmnand_waitfunc(mtd, chip); 189693db446aSBoris Brezillon 189793db446aSBoris Brezillon if (status & NAND_STATUS_FAIL) { 189893db446aSBoris Brezillon dev_info(ctrl->dev, "program failed at %llx\n", 189993db446aSBoris Brezillon (unsigned long long)addr); 190093db446aSBoris Brezillon ret = -EIO; 190193db446aSBoris Brezillon goto out; 190293db446aSBoris Brezillon } 190393db446aSBoris Brezillon } 190493db446aSBoris Brezillon out: 190593db446aSBoris Brezillon brcmnand_wp(mtd, 1); 190693db446aSBoris Brezillon return ret; 190793db446aSBoris Brezillon } 190893db446aSBoris Brezillon 190993db446aSBoris Brezillon static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip, 191093db446aSBoris Brezillon const uint8_t *buf, int oob_required, int page) 191193db446aSBoris Brezillon { 191293db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 191393db446aSBoris Brezillon void *oob = oob_required ? chip->oob_poi : NULL; 191493db446aSBoris Brezillon 191593db446aSBoris Brezillon nand_prog_page_begin_op(chip, page, 0, NULL, 0); 191693db446aSBoris Brezillon brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); 191793db446aSBoris Brezillon 191893db446aSBoris Brezillon return nand_prog_page_end_op(chip); 191993db446aSBoris Brezillon } 192093db446aSBoris Brezillon 192193db446aSBoris Brezillon static int brcmnand_write_page_raw(struct mtd_info *mtd, 192293db446aSBoris Brezillon struct nand_chip *chip, const uint8_t *buf, 192393db446aSBoris Brezillon int oob_required, int page) 192493db446aSBoris Brezillon { 192593db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 192693db446aSBoris Brezillon void *oob = oob_required ? chip->oob_poi : NULL; 192793db446aSBoris Brezillon 192893db446aSBoris Brezillon nand_prog_page_begin_op(chip, page, 0, NULL, 0); 192993db446aSBoris Brezillon brcmnand_set_ecc_enabled(host, 0); 193093db446aSBoris Brezillon brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); 193193db446aSBoris Brezillon brcmnand_set_ecc_enabled(host, 1); 193293db446aSBoris Brezillon 193393db446aSBoris Brezillon return nand_prog_page_end_op(chip); 193493db446aSBoris Brezillon } 193593db446aSBoris Brezillon 193693db446aSBoris Brezillon static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 193793db446aSBoris Brezillon int page) 193893db446aSBoris Brezillon { 193993db446aSBoris Brezillon return brcmnand_write(mtd, chip, (u64)page << chip->page_shift, 194093db446aSBoris Brezillon NULL, chip->oob_poi); 194193db446aSBoris Brezillon } 194293db446aSBoris Brezillon 194393db446aSBoris Brezillon static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, 194493db446aSBoris Brezillon int page) 194593db446aSBoris Brezillon { 194693db446aSBoris Brezillon struct brcmnand_host *host = nand_get_controller_data(chip); 194793db446aSBoris Brezillon int ret; 194893db446aSBoris Brezillon 194993db446aSBoris Brezillon brcmnand_set_ecc_enabled(host, 0); 195093db446aSBoris Brezillon ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, 195193db446aSBoris Brezillon (u8 *)chip->oob_poi); 195293db446aSBoris Brezillon brcmnand_set_ecc_enabled(host, 1); 195393db446aSBoris Brezillon 195493db446aSBoris Brezillon return ret; 195593db446aSBoris Brezillon } 195693db446aSBoris Brezillon 195793db446aSBoris Brezillon /*********************************************************************** 195893db446aSBoris Brezillon * Per-CS setup (1 NAND device) 195993db446aSBoris Brezillon ***********************************************************************/ 196093db446aSBoris Brezillon 196193db446aSBoris Brezillon static int brcmnand_set_cfg(struct brcmnand_host *host, 196293db446aSBoris Brezillon struct brcmnand_cfg *cfg) 196393db446aSBoris Brezillon { 196493db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 196593db446aSBoris Brezillon struct nand_chip *chip = &host->chip; 196693db446aSBoris Brezillon u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 196793db446aSBoris Brezillon u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 196893db446aSBoris Brezillon BRCMNAND_CS_CFG_EXT); 196993db446aSBoris Brezillon u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 197093db446aSBoris Brezillon BRCMNAND_CS_ACC_CONTROL); 197193db446aSBoris Brezillon u8 block_size = 0, page_size = 0, device_size = 0; 197293db446aSBoris Brezillon u32 tmp; 197393db446aSBoris Brezillon 197493db446aSBoris Brezillon if (ctrl->block_sizes) { 197593db446aSBoris Brezillon int i, found; 197693db446aSBoris Brezillon 197793db446aSBoris Brezillon for (i = 0, found = 0; ctrl->block_sizes[i]; i++) 197893db446aSBoris Brezillon if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { 197993db446aSBoris Brezillon block_size = i; 198093db446aSBoris Brezillon found = 1; 198193db446aSBoris Brezillon } 198293db446aSBoris Brezillon if (!found) { 198393db446aSBoris Brezillon dev_warn(ctrl->dev, "invalid block size %u\n", 198493db446aSBoris Brezillon cfg->block_size); 198593db446aSBoris Brezillon return -EINVAL; 198693db446aSBoris Brezillon } 198793db446aSBoris Brezillon } else { 198893db446aSBoris Brezillon block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); 198993db446aSBoris Brezillon } 199093db446aSBoris Brezillon 199193db446aSBoris Brezillon if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && 199293db446aSBoris Brezillon cfg->block_size > ctrl->max_block_size)) { 199393db446aSBoris Brezillon dev_warn(ctrl->dev, "invalid block size %u\n", 199493db446aSBoris Brezillon cfg->block_size); 199593db446aSBoris Brezillon block_size = 0; 199693db446aSBoris Brezillon } 199793db446aSBoris Brezillon 199893db446aSBoris Brezillon if (ctrl->page_sizes) { 199993db446aSBoris Brezillon int i, found; 200093db446aSBoris Brezillon 200193db446aSBoris Brezillon for (i = 0, found = 0; ctrl->page_sizes[i]; i++) 200293db446aSBoris Brezillon if (ctrl->page_sizes[i] == cfg->page_size) { 200393db446aSBoris Brezillon page_size = i; 200493db446aSBoris Brezillon found = 1; 200593db446aSBoris Brezillon } 200693db446aSBoris Brezillon if (!found) { 200793db446aSBoris Brezillon dev_warn(ctrl->dev, "invalid page size %u\n", 200893db446aSBoris Brezillon cfg->page_size); 200993db446aSBoris Brezillon return -EINVAL; 201093db446aSBoris Brezillon } 201193db446aSBoris Brezillon } else { 201293db446aSBoris Brezillon page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); 201393db446aSBoris Brezillon } 201493db446aSBoris Brezillon 201593db446aSBoris Brezillon if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && 201693db446aSBoris Brezillon cfg->page_size > ctrl->max_page_size)) { 201793db446aSBoris Brezillon dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); 201893db446aSBoris Brezillon return -EINVAL; 201993db446aSBoris Brezillon } 202093db446aSBoris Brezillon 202193db446aSBoris Brezillon if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { 202293db446aSBoris Brezillon dev_warn(ctrl->dev, "invalid device size 0x%llx\n", 202393db446aSBoris Brezillon (unsigned long long)cfg->device_size); 202493db446aSBoris Brezillon return -EINVAL; 202593db446aSBoris Brezillon } 202693db446aSBoris Brezillon device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); 202793db446aSBoris Brezillon 202893db446aSBoris Brezillon tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | 202993db446aSBoris Brezillon (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | 203093db446aSBoris Brezillon (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | 203193db446aSBoris Brezillon (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | 203293db446aSBoris Brezillon (device_size << CFG_DEVICE_SIZE_SHIFT); 203393db446aSBoris Brezillon if (cfg_offs == cfg_ext_offs) { 203493db446aSBoris Brezillon tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) | 203593db446aSBoris Brezillon (block_size << CFG_BLK_SIZE_SHIFT); 203693db446aSBoris Brezillon nand_writereg(ctrl, cfg_offs, tmp); 203793db446aSBoris Brezillon } else { 203893db446aSBoris Brezillon nand_writereg(ctrl, cfg_offs, tmp); 203993db446aSBoris Brezillon tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) | 204093db446aSBoris Brezillon (block_size << CFG_EXT_BLK_SIZE_SHIFT); 204193db446aSBoris Brezillon nand_writereg(ctrl, cfg_ext_offs, tmp); 204293db446aSBoris Brezillon } 204393db446aSBoris Brezillon 204493db446aSBoris Brezillon tmp = nand_readreg(ctrl, acc_control_offs); 204593db446aSBoris Brezillon tmp &= ~brcmnand_ecc_level_mask(ctrl); 204693db446aSBoris Brezillon tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; 204793db446aSBoris Brezillon tmp &= ~brcmnand_spare_area_mask(ctrl); 204893db446aSBoris Brezillon tmp |= cfg->spare_area_size; 204993db446aSBoris Brezillon nand_writereg(ctrl, acc_control_offs, tmp); 205093db446aSBoris Brezillon 205193db446aSBoris Brezillon brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); 205293db446aSBoris Brezillon 205393db446aSBoris Brezillon /* threshold = ceil(BCH-level * 0.75) */ 205493db446aSBoris Brezillon brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); 205593db446aSBoris Brezillon 205693db446aSBoris Brezillon return 0; 205793db446aSBoris Brezillon } 205893db446aSBoris Brezillon 205993db446aSBoris Brezillon static void brcmnand_print_cfg(struct brcmnand_host *host, 206093db446aSBoris Brezillon char *buf, struct brcmnand_cfg *cfg) 206193db446aSBoris Brezillon { 206293db446aSBoris Brezillon buf += sprintf(buf, 206393db446aSBoris Brezillon "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", 206493db446aSBoris Brezillon (unsigned long long)cfg->device_size >> 20, 206593db446aSBoris Brezillon cfg->block_size >> 10, 206693db446aSBoris Brezillon cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, 206793db446aSBoris Brezillon cfg->page_size >= 1024 ? "KiB" : "B", 206893db446aSBoris Brezillon cfg->spare_area_size, cfg->device_width); 206993db446aSBoris Brezillon 207093db446aSBoris Brezillon /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */ 207193db446aSBoris Brezillon if (is_hamming_ecc(host->ctrl, cfg)) 207293db446aSBoris Brezillon sprintf(buf, ", Hamming ECC"); 207393db446aSBoris Brezillon else if (cfg->sector_size_1k) 207493db446aSBoris Brezillon sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); 207593db446aSBoris Brezillon else 207693db446aSBoris Brezillon sprintf(buf, ", BCH-%u", cfg->ecc_level); 207793db446aSBoris Brezillon } 207893db446aSBoris Brezillon 207993db446aSBoris Brezillon /* 208093db446aSBoris Brezillon * Minimum number of bytes to address a page. Calculated as: 208193db446aSBoris Brezillon * roundup(log2(size / page-size) / 8) 208293db446aSBoris Brezillon * 208393db446aSBoris Brezillon * NB: the following does not "round up" for non-power-of-2 'size'; but this is 208493db446aSBoris Brezillon * OK because many other things will break if 'size' is irregular... 208593db446aSBoris Brezillon */ 208693db446aSBoris Brezillon static inline int get_blk_adr_bytes(u64 size, u32 writesize) 208793db446aSBoris Brezillon { 208893db446aSBoris Brezillon return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; 208993db446aSBoris Brezillon } 209093db446aSBoris Brezillon 209193db446aSBoris Brezillon static int brcmnand_setup_dev(struct brcmnand_host *host) 209293db446aSBoris Brezillon { 209393db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(&host->chip); 209493db446aSBoris Brezillon struct nand_chip *chip = &host->chip; 209593db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 209693db446aSBoris Brezillon struct brcmnand_cfg *cfg = &host->hwcfg; 209793db446aSBoris Brezillon char msg[128]; 209893db446aSBoris Brezillon u32 offs, tmp, oob_sector; 209993db446aSBoris Brezillon int ret; 210093db446aSBoris Brezillon 210193db446aSBoris Brezillon memset(cfg, 0, sizeof(*cfg)); 210293db446aSBoris Brezillon 210393db446aSBoris Brezillon ret = of_property_read_u32(nand_get_flash_node(chip), 210493db446aSBoris Brezillon "brcm,nand-oob-sector-size", 210593db446aSBoris Brezillon &oob_sector); 210693db446aSBoris Brezillon if (ret) { 210793db446aSBoris Brezillon /* Use detected size */ 210893db446aSBoris Brezillon cfg->spare_area_size = mtd->oobsize / 210993db446aSBoris Brezillon (mtd->writesize >> FC_SHIFT); 211093db446aSBoris Brezillon } else { 211193db446aSBoris Brezillon cfg->spare_area_size = oob_sector; 211293db446aSBoris Brezillon } 211393db446aSBoris Brezillon if (cfg->spare_area_size > ctrl->max_oob) 211493db446aSBoris Brezillon cfg->spare_area_size = ctrl->max_oob; 211593db446aSBoris Brezillon /* 211693db446aSBoris Brezillon * Set oobsize to be consistent with controller's spare_area_size, as 211793db446aSBoris Brezillon * the rest is inaccessible. 211893db446aSBoris Brezillon */ 211993db446aSBoris Brezillon mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); 212093db446aSBoris Brezillon 212193db446aSBoris Brezillon cfg->device_size = mtd->size; 212293db446aSBoris Brezillon cfg->block_size = mtd->erasesize; 212393db446aSBoris Brezillon cfg->page_size = mtd->writesize; 212493db446aSBoris Brezillon cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; 212593db446aSBoris Brezillon cfg->col_adr_bytes = 2; 212693db446aSBoris Brezillon cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); 212793db446aSBoris Brezillon 212893db446aSBoris Brezillon if (chip->ecc.mode != NAND_ECC_HW) { 212993db446aSBoris Brezillon dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", 213093db446aSBoris Brezillon chip->ecc.mode); 213193db446aSBoris Brezillon return -EINVAL; 213293db446aSBoris Brezillon } 213393db446aSBoris Brezillon 213493db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_UNKNOWN) { 213593db446aSBoris Brezillon if (chip->ecc.strength == 1 && chip->ecc.size == 512) 213693db446aSBoris Brezillon /* Default to Hamming for 1-bit ECC, if unspecified */ 213793db446aSBoris Brezillon chip->ecc.algo = NAND_ECC_HAMMING; 213893db446aSBoris Brezillon else 213993db446aSBoris Brezillon /* Otherwise, BCH */ 214093db446aSBoris Brezillon chip->ecc.algo = NAND_ECC_BCH; 214193db446aSBoris Brezillon } 214293db446aSBoris Brezillon 214393db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 || 214493db446aSBoris Brezillon chip->ecc.size != 512)) { 214593db446aSBoris Brezillon dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", 214693db446aSBoris Brezillon chip->ecc.strength, chip->ecc.size); 214793db446aSBoris Brezillon return -EINVAL; 214893db446aSBoris Brezillon } 214993db446aSBoris Brezillon 215093db446aSBoris Brezillon switch (chip->ecc.size) { 215193db446aSBoris Brezillon case 512: 215293db446aSBoris Brezillon if (chip->ecc.algo == NAND_ECC_HAMMING) 215393db446aSBoris Brezillon cfg->ecc_level = 15; 215493db446aSBoris Brezillon else 215593db446aSBoris Brezillon cfg->ecc_level = chip->ecc.strength; 215693db446aSBoris Brezillon cfg->sector_size_1k = 0; 215793db446aSBoris Brezillon break; 215893db446aSBoris Brezillon case 1024: 215993db446aSBoris Brezillon if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { 216093db446aSBoris Brezillon dev_err(ctrl->dev, "1KB sectors not supported\n"); 216193db446aSBoris Brezillon return -EINVAL; 216293db446aSBoris Brezillon } 216393db446aSBoris Brezillon if (chip->ecc.strength & 0x1) { 216493db446aSBoris Brezillon dev_err(ctrl->dev, 216593db446aSBoris Brezillon "odd ECC not supported with 1KB sectors\n"); 216693db446aSBoris Brezillon return -EINVAL; 216793db446aSBoris Brezillon } 216893db446aSBoris Brezillon 216993db446aSBoris Brezillon cfg->ecc_level = chip->ecc.strength >> 1; 217093db446aSBoris Brezillon cfg->sector_size_1k = 1; 217193db446aSBoris Brezillon break; 217293db446aSBoris Brezillon default: 217393db446aSBoris Brezillon dev_err(ctrl->dev, "unsupported ECC size: %d\n", 217493db446aSBoris Brezillon chip->ecc.size); 217593db446aSBoris Brezillon return -EINVAL; 217693db446aSBoris Brezillon } 217793db446aSBoris Brezillon 217893db446aSBoris Brezillon cfg->ful_adr_bytes = cfg->blk_adr_bytes; 217993db446aSBoris Brezillon if (mtd->writesize > 512) 218093db446aSBoris Brezillon cfg->ful_adr_bytes += cfg->col_adr_bytes; 218193db446aSBoris Brezillon else 218293db446aSBoris Brezillon cfg->ful_adr_bytes += 1; 218393db446aSBoris Brezillon 218493db446aSBoris Brezillon ret = brcmnand_set_cfg(host, cfg); 218593db446aSBoris Brezillon if (ret) 218693db446aSBoris Brezillon return ret; 218793db446aSBoris Brezillon 218893db446aSBoris Brezillon brcmnand_set_ecc_enabled(host, 1); 218993db446aSBoris Brezillon 219093db446aSBoris Brezillon brcmnand_print_cfg(host, msg, cfg); 219193db446aSBoris Brezillon dev_info(ctrl->dev, "detected %s\n", msg); 219293db446aSBoris Brezillon 219393db446aSBoris Brezillon /* Configure ACC_CONTROL */ 219493db446aSBoris Brezillon offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 219593db446aSBoris Brezillon tmp = nand_readreg(ctrl, offs); 219693db446aSBoris Brezillon tmp &= ~ACC_CONTROL_PARTIAL_PAGE; 219793db446aSBoris Brezillon tmp &= ~ACC_CONTROL_RD_ERASED; 219893db446aSBoris Brezillon 219993db446aSBoris Brezillon /* We need to turn on Read from erased paged protected by ECC */ 220093db446aSBoris Brezillon if (ctrl->nand_version >= 0x0702) 220193db446aSBoris Brezillon tmp |= ACC_CONTROL_RD_ERASED; 220293db446aSBoris Brezillon tmp &= ~ACC_CONTROL_FAST_PGM_RDIN; 220393db446aSBoris Brezillon if (ctrl->features & BRCMNAND_HAS_PREFETCH) 220493db446aSBoris Brezillon tmp &= ~ACC_CONTROL_PREFETCH; 220593db446aSBoris Brezillon 220693db446aSBoris Brezillon nand_writereg(ctrl, offs, tmp); 220793db446aSBoris Brezillon 220893db446aSBoris Brezillon return 0; 220993db446aSBoris Brezillon } 221093db446aSBoris Brezillon 22114918b905SMiquel Raynal static int brcmnand_attach_chip(struct nand_chip *chip) 22124918b905SMiquel Raynal { 22134918b905SMiquel Raynal struct mtd_info *mtd = nand_to_mtd(chip); 22144918b905SMiquel Raynal struct brcmnand_host *host = nand_get_controller_data(chip); 22154918b905SMiquel Raynal int ret; 22164918b905SMiquel Raynal 22174918b905SMiquel Raynal chip->options |= NAND_NO_SUBPAGE_WRITE; 22184918b905SMiquel Raynal /* 22194918b905SMiquel Raynal * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA 22204918b905SMiquel Raynal * to/from, and have nand_base pass us a bounce buffer instead, as 22214918b905SMiquel Raynal * needed. 22224918b905SMiquel Raynal */ 22234918b905SMiquel Raynal chip->options |= NAND_USE_BOUNCE_BUFFER; 22244918b905SMiquel Raynal 22254918b905SMiquel Raynal if (chip->bbt_options & NAND_BBT_USE_FLASH) 22264918b905SMiquel Raynal chip->bbt_options |= NAND_BBT_NO_OOB; 22274918b905SMiquel Raynal 22284918b905SMiquel Raynal if (brcmnand_setup_dev(host)) 22294918b905SMiquel Raynal return -ENXIO; 22304918b905SMiquel Raynal 22314918b905SMiquel Raynal chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; 22324918b905SMiquel Raynal 22334918b905SMiquel Raynal /* only use our internal HW threshold */ 22344918b905SMiquel Raynal mtd->bitflip_threshold = 1; 22354918b905SMiquel Raynal 22364918b905SMiquel Raynal ret = brcmstb_choose_ecc_layout(host); 22374918b905SMiquel Raynal 22384918b905SMiquel Raynal return ret; 22394918b905SMiquel Raynal } 22404918b905SMiquel Raynal 22414918b905SMiquel Raynal static const struct nand_controller_ops brcmnand_controller_ops = { 22424918b905SMiquel Raynal .attach_chip = brcmnand_attach_chip, 22434918b905SMiquel Raynal }; 22444918b905SMiquel Raynal 224593db446aSBoris Brezillon static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn) 224693db446aSBoris Brezillon { 224793db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 224893db446aSBoris Brezillon struct platform_device *pdev = host->pdev; 224993db446aSBoris Brezillon struct mtd_info *mtd; 225093db446aSBoris Brezillon struct nand_chip *chip; 225193db446aSBoris Brezillon int ret; 225293db446aSBoris Brezillon u16 cfg_offs; 225393db446aSBoris Brezillon 225493db446aSBoris Brezillon ret = of_property_read_u32(dn, "reg", &host->cs); 225593db446aSBoris Brezillon if (ret) { 225693db446aSBoris Brezillon dev_err(&pdev->dev, "can't get chip-select\n"); 225793db446aSBoris Brezillon return -ENXIO; 225893db446aSBoris Brezillon } 225993db446aSBoris Brezillon 226093db446aSBoris Brezillon mtd = nand_to_mtd(&host->chip); 226193db446aSBoris Brezillon chip = &host->chip; 226293db446aSBoris Brezillon 226393db446aSBoris Brezillon nand_set_flash_node(chip, dn); 226493db446aSBoris Brezillon nand_set_controller_data(chip, host); 226593db446aSBoris Brezillon mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d", 226693db446aSBoris Brezillon host->cs); 226793db446aSBoris Brezillon if (!mtd->name) 226893db446aSBoris Brezillon return -ENOMEM; 226993db446aSBoris Brezillon 227093db446aSBoris Brezillon mtd->owner = THIS_MODULE; 227193db446aSBoris Brezillon mtd->dev.parent = &pdev->dev; 227293db446aSBoris Brezillon 227393db446aSBoris Brezillon chip->IO_ADDR_R = (void __iomem *)0xdeadbeef; 227493db446aSBoris Brezillon chip->IO_ADDR_W = (void __iomem *)0xdeadbeef; 227593db446aSBoris Brezillon 227693db446aSBoris Brezillon chip->cmd_ctrl = brcmnand_cmd_ctrl; 227793db446aSBoris Brezillon chip->cmdfunc = brcmnand_cmdfunc; 227893db446aSBoris Brezillon chip->waitfunc = brcmnand_waitfunc; 227993db446aSBoris Brezillon chip->read_byte = brcmnand_read_byte; 228093db446aSBoris Brezillon chip->read_buf = brcmnand_read_buf; 228193db446aSBoris Brezillon chip->write_buf = brcmnand_write_buf; 228293db446aSBoris Brezillon 228393db446aSBoris Brezillon chip->ecc.mode = NAND_ECC_HW; 228493db446aSBoris Brezillon chip->ecc.read_page = brcmnand_read_page; 228593db446aSBoris Brezillon chip->ecc.write_page = brcmnand_write_page; 228693db446aSBoris Brezillon chip->ecc.read_page_raw = brcmnand_read_page_raw; 228793db446aSBoris Brezillon chip->ecc.write_page_raw = brcmnand_write_page_raw; 228893db446aSBoris Brezillon chip->ecc.write_oob_raw = brcmnand_write_oob_raw; 228993db446aSBoris Brezillon chip->ecc.read_oob_raw = brcmnand_read_oob_raw; 229093db446aSBoris Brezillon chip->ecc.read_oob = brcmnand_read_oob; 229193db446aSBoris Brezillon chip->ecc.write_oob = brcmnand_write_oob; 229293db446aSBoris Brezillon 229393db446aSBoris Brezillon chip->controller = &ctrl->controller; 229493db446aSBoris Brezillon 229593db446aSBoris Brezillon /* 229693db446aSBoris Brezillon * The bootloader might have configured 16bit mode but 229793db446aSBoris Brezillon * NAND READID command only works in 8bit mode. We force 229893db446aSBoris Brezillon * 8bit mode here to ensure that NAND READID commands works. 229993db446aSBoris Brezillon */ 230093db446aSBoris Brezillon cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 230193db446aSBoris Brezillon nand_writereg(ctrl, cfg_offs, 230293db446aSBoris Brezillon nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH); 230393db446aSBoris Brezillon 230400ad378fSBoris Brezillon ret = nand_scan(chip, 1); 230593db446aSBoris Brezillon if (ret) 230693db446aSBoris Brezillon return ret; 230793db446aSBoris Brezillon 23085826b880SMiquel Raynal ret = mtd_device_register(mtd, NULL, 0); 23095826b880SMiquel Raynal if (ret) 23105826b880SMiquel Raynal nand_cleanup(chip); 23115826b880SMiquel Raynal 23125826b880SMiquel Raynal return ret; 231393db446aSBoris Brezillon } 231493db446aSBoris Brezillon 231593db446aSBoris Brezillon static void brcmnand_save_restore_cs_config(struct brcmnand_host *host, 231693db446aSBoris Brezillon int restore) 231793db446aSBoris Brezillon { 231893db446aSBoris Brezillon struct brcmnand_controller *ctrl = host->ctrl; 231993db446aSBoris Brezillon u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 232093db446aSBoris Brezillon u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 232193db446aSBoris Brezillon BRCMNAND_CS_CFG_EXT); 232293db446aSBoris Brezillon u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 232393db446aSBoris Brezillon BRCMNAND_CS_ACC_CONTROL); 232493db446aSBoris Brezillon u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); 232593db446aSBoris Brezillon u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); 232693db446aSBoris Brezillon 232793db446aSBoris Brezillon if (restore) { 232893db446aSBoris Brezillon nand_writereg(ctrl, cfg_offs, host->hwcfg.config); 232993db446aSBoris Brezillon if (cfg_offs != cfg_ext_offs) 233093db446aSBoris Brezillon nand_writereg(ctrl, cfg_ext_offs, 233193db446aSBoris Brezillon host->hwcfg.config_ext); 233293db446aSBoris Brezillon nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); 233393db446aSBoris Brezillon nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); 233493db446aSBoris Brezillon nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); 233593db446aSBoris Brezillon } else { 233693db446aSBoris Brezillon host->hwcfg.config = nand_readreg(ctrl, cfg_offs); 233793db446aSBoris Brezillon if (cfg_offs != cfg_ext_offs) 233893db446aSBoris Brezillon host->hwcfg.config_ext = 233993db446aSBoris Brezillon nand_readreg(ctrl, cfg_ext_offs); 234093db446aSBoris Brezillon host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); 234193db446aSBoris Brezillon host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); 234293db446aSBoris Brezillon host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); 234393db446aSBoris Brezillon } 234493db446aSBoris Brezillon } 234593db446aSBoris Brezillon 234693db446aSBoris Brezillon static int brcmnand_suspend(struct device *dev) 234793db446aSBoris Brezillon { 234893db446aSBoris Brezillon struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 234993db446aSBoris Brezillon struct brcmnand_host *host; 235093db446aSBoris Brezillon 235193db446aSBoris Brezillon list_for_each_entry(host, &ctrl->host_list, node) 235293db446aSBoris Brezillon brcmnand_save_restore_cs_config(host, 0); 235393db446aSBoris Brezillon 235493db446aSBoris Brezillon ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); 235593db446aSBoris Brezillon ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); 235693db446aSBoris Brezillon ctrl->corr_stat_threshold = 235793db446aSBoris Brezillon brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); 235893db446aSBoris Brezillon 235993db446aSBoris Brezillon if (has_flash_dma(ctrl)) 236093db446aSBoris Brezillon ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); 236193db446aSBoris Brezillon 236293db446aSBoris Brezillon return 0; 236393db446aSBoris Brezillon } 236493db446aSBoris Brezillon 236593db446aSBoris Brezillon static int brcmnand_resume(struct device *dev) 236693db446aSBoris Brezillon { 236793db446aSBoris Brezillon struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 236893db446aSBoris Brezillon struct brcmnand_host *host; 236993db446aSBoris Brezillon 237093db446aSBoris Brezillon if (has_flash_dma(ctrl)) { 237193db446aSBoris Brezillon flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); 237293db446aSBoris Brezillon flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 237393db446aSBoris Brezillon } 237493db446aSBoris Brezillon 237593db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); 237693db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); 237793db446aSBoris Brezillon brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, 237893db446aSBoris Brezillon ctrl->corr_stat_threshold); 237993db446aSBoris Brezillon if (ctrl->soc) { 238093db446aSBoris Brezillon /* Clear/re-enable interrupt */ 238193db446aSBoris Brezillon ctrl->soc->ctlrdy_ack(ctrl->soc); 238293db446aSBoris Brezillon ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 238393db446aSBoris Brezillon } 238493db446aSBoris Brezillon 238593db446aSBoris Brezillon list_for_each_entry(host, &ctrl->host_list, node) { 238693db446aSBoris Brezillon struct nand_chip *chip = &host->chip; 238793db446aSBoris Brezillon 238893db446aSBoris Brezillon brcmnand_save_restore_cs_config(host, 1); 238993db446aSBoris Brezillon 239093db446aSBoris Brezillon /* Reset the chip, required by some chips after power-up */ 239193db446aSBoris Brezillon nand_reset_op(chip); 239293db446aSBoris Brezillon } 239393db446aSBoris Brezillon 239493db446aSBoris Brezillon return 0; 239593db446aSBoris Brezillon } 239693db446aSBoris Brezillon 239793db446aSBoris Brezillon const struct dev_pm_ops brcmnand_pm_ops = { 239893db446aSBoris Brezillon .suspend = brcmnand_suspend, 239993db446aSBoris Brezillon .resume = brcmnand_resume, 240093db446aSBoris Brezillon }; 240193db446aSBoris Brezillon EXPORT_SYMBOL_GPL(brcmnand_pm_ops); 240293db446aSBoris Brezillon 240393db446aSBoris Brezillon static const struct of_device_id brcmnand_of_match[] = { 240493db446aSBoris Brezillon { .compatible = "brcm,brcmnand-v4.0" }, 240593db446aSBoris Brezillon { .compatible = "brcm,brcmnand-v5.0" }, 240693db446aSBoris Brezillon { .compatible = "brcm,brcmnand-v6.0" }, 240793db446aSBoris Brezillon { .compatible = "brcm,brcmnand-v6.1" }, 240893db446aSBoris Brezillon { .compatible = "brcm,brcmnand-v6.2" }, 240993db446aSBoris Brezillon { .compatible = "brcm,brcmnand-v7.0" }, 241093db446aSBoris Brezillon { .compatible = "brcm,brcmnand-v7.1" }, 241193db446aSBoris Brezillon { .compatible = "brcm,brcmnand-v7.2" }, 241293db446aSBoris Brezillon {}, 241393db446aSBoris Brezillon }; 241493db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, brcmnand_of_match); 241593db446aSBoris Brezillon 241693db446aSBoris Brezillon /*********************************************************************** 241793db446aSBoris Brezillon * Platform driver setup (per controller) 241893db446aSBoris Brezillon ***********************************************************************/ 241993db446aSBoris Brezillon 242093db446aSBoris Brezillon int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) 242193db446aSBoris Brezillon { 242293db446aSBoris Brezillon struct device *dev = &pdev->dev; 242393db446aSBoris Brezillon struct device_node *dn = dev->of_node, *child; 242493db446aSBoris Brezillon struct brcmnand_controller *ctrl; 242593db446aSBoris Brezillon struct resource *res; 242693db446aSBoris Brezillon int ret; 242793db446aSBoris Brezillon 242893db446aSBoris Brezillon /* We only support device-tree instantiation */ 242993db446aSBoris Brezillon if (!dn) 243093db446aSBoris Brezillon return -ENODEV; 243193db446aSBoris Brezillon 243293db446aSBoris Brezillon if (!of_match_node(brcmnand_of_match, dn)) 243393db446aSBoris Brezillon return -ENODEV; 243493db446aSBoris Brezillon 243593db446aSBoris Brezillon ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 243693db446aSBoris Brezillon if (!ctrl) 243793db446aSBoris Brezillon return -ENOMEM; 243893db446aSBoris Brezillon 243993db446aSBoris Brezillon dev_set_drvdata(dev, ctrl); 244093db446aSBoris Brezillon ctrl->dev = dev; 244193db446aSBoris Brezillon 244293db446aSBoris Brezillon init_completion(&ctrl->done); 244393db446aSBoris Brezillon init_completion(&ctrl->dma_done); 24447da45139SMiquel Raynal nand_controller_init(&ctrl->controller); 24454918b905SMiquel Raynal ctrl->controller.ops = &brcmnand_controller_ops; 244693db446aSBoris Brezillon INIT_LIST_HEAD(&ctrl->host_list); 244793db446aSBoris Brezillon 244893db446aSBoris Brezillon /* NAND register range */ 244993db446aSBoris Brezillon res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 245093db446aSBoris Brezillon ctrl->nand_base = devm_ioremap_resource(dev, res); 245193db446aSBoris Brezillon if (IS_ERR(ctrl->nand_base)) 245293db446aSBoris Brezillon return PTR_ERR(ctrl->nand_base); 245393db446aSBoris Brezillon 245493db446aSBoris Brezillon /* Enable clock before using NAND registers */ 245593db446aSBoris Brezillon ctrl->clk = devm_clk_get(dev, "nand"); 245693db446aSBoris Brezillon if (!IS_ERR(ctrl->clk)) { 245793db446aSBoris Brezillon ret = clk_prepare_enable(ctrl->clk); 245893db446aSBoris Brezillon if (ret) 245993db446aSBoris Brezillon return ret; 246093db446aSBoris Brezillon } else { 246193db446aSBoris Brezillon ret = PTR_ERR(ctrl->clk); 246293db446aSBoris Brezillon if (ret == -EPROBE_DEFER) 246393db446aSBoris Brezillon return ret; 246493db446aSBoris Brezillon 246593db446aSBoris Brezillon ctrl->clk = NULL; 246693db446aSBoris Brezillon } 246793db446aSBoris Brezillon 246893db446aSBoris Brezillon /* Initialize NAND revision */ 246993db446aSBoris Brezillon ret = brcmnand_revision_init(ctrl); 247093db446aSBoris Brezillon if (ret) 247193db446aSBoris Brezillon goto err; 247293db446aSBoris Brezillon 247393db446aSBoris Brezillon /* 247493db446aSBoris Brezillon * Most chips have this cache at a fixed offset within 'nand' block. 247593db446aSBoris Brezillon * Some must specify this region separately. 247693db446aSBoris Brezillon */ 247793db446aSBoris Brezillon res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); 247893db446aSBoris Brezillon if (res) { 247993db446aSBoris Brezillon ctrl->nand_fc = devm_ioremap_resource(dev, res); 248093db446aSBoris Brezillon if (IS_ERR(ctrl->nand_fc)) { 248193db446aSBoris Brezillon ret = PTR_ERR(ctrl->nand_fc); 248293db446aSBoris Brezillon goto err; 248393db446aSBoris Brezillon } 248493db446aSBoris Brezillon } else { 248593db446aSBoris Brezillon ctrl->nand_fc = ctrl->nand_base + 248693db446aSBoris Brezillon ctrl->reg_offsets[BRCMNAND_FC_BASE]; 248793db446aSBoris Brezillon } 248893db446aSBoris Brezillon 248993db446aSBoris Brezillon /* FLASH_DMA */ 249093db446aSBoris Brezillon res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); 249193db446aSBoris Brezillon if (res) { 249293db446aSBoris Brezillon ctrl->flash_dma_base = devm_ioremap_resource(dev, res); 249393db446aSBoris Brezillon if (IS_ERR(ctrl->flash_dma_base)) { 249493db446aSBoris Brezillon ret = PTR_ERR(ctrl->flash_dma_base); 249593db446aSBoris Brezillon goto err; 249693db446aSBoris Brezillon } 249793db446aSBoris Brezillon 249893db446aSBoris Brezillon flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */ 249993db446aSBoris Brezillon flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 250093db446aSBoris Brezillon 250193db446aSBoris Brezillon /* Allocate descriptor(s) */ 250293db446aSBoris Brezillon ctrl->dma_desc = dmam_alloc_coherent(dev, 250393db446aSBoris Brezillon sizeof(*ctrl->dma_desc), 250493db446aSBoris Brezillon &ctrl->dma_pa, GFP_KERNEL); 250593db446aSBoris Brezillon if (!ctrl->dma_desc) { 250693db446aSBoris Brezillon ret = -ENOMEM; 250793db446aSBoris Brezillon goto err; 250893db446aSBoris Brezillon } 250993db446aSBoris Brezillon 251093db446aSBoris Brezillon ctrl->dma_irq = platform_get_irq(pdev, 1); 251193db446aSBoris Brezillon if ((int)ctrl->dma_irq < 0) { 251293db446aSBoris Brezillon dev_err(dev, "missing FLASH_DMA IRQ\n"); 251393db446aSBoris Brezillon ret = -ENODEV; 251493db446aSBoris Brezillon goto err; 251593db446aSBoris Brezillon } 251693db446aSBoris Brezillon 251793db446aSBoris Brezillon ret = devm_request_irq(dev, ctrl->dma_irq, 251893db446aSBoris Brezillon brcmnand_dma_irq, 0, DRV_NAME, 251993db446aSBoris Brezillon ctrl); 252093db446aSBoris Brezillon if (ret < 0) { 252193db446aSBoris Brezillon dev_err(dev, "can't allocate IRQ %d: error %d\n", 252293db446aSBoris Brezillon ctrl->dma_irq, ret); 252393db446aSBoris Brezillon goto err; 252493db446aSBoris Brezillon } 252593db446aSBoris Brezillon 252693db446aSBoris Brezillon dev_info(dev, "enabling FLASH_DMA\n"); 252793db446aSBoris Brezillon } 252893db446aSBoris Brezillon 252993db446aSBoris Brezillon /* Disable automatic device ID config, direct addressing */ 253093db446aSBoris Brezillon brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, 253193db446aSBoris Brezillon CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0); 253293db446aSBoris Brezillon /* Disable XOR addressing */ 253393db446aSBoris Brezillon brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); 253493db446aSBoris Brezillon 253593db446aSBoris Brezillon if (ctrl->features & BRCMNAND_HAS_WP) { 253693db446aSBoris Brezillon /* Permanently disable write protection */ 253793db446aSBoris Brezillon if (wp_on == 2) 253893db446aSBoris Brezillon brcmnand_set_wp(ctrl, false); 253993db446aSBoris Brezillon } else { 254093db446aSBoris Brezillon wp_on = 0; 254193db446aSBoris Brezillon } 254293db446aSBoris Brezillon 254393db446aSBoris Brezillon /* IRQ */ 254493db446aSBoris Brezillon ctrl->irq = platform_get_irq(pdev, 0); 254593db446aSBoris Brezillon if ((int)ctrl->irq < 0) { 254693db446aSBoris Brezillon dev_err(dev, "no IRQ defined\n"); 254793db446aSBoris Brezillon ret = -ENODEV; 254893db446aSBoris Brezillon goto err; 254993db446aSBoris Brezillon } 255093db446aSBoris Brezillon 255193db446aSBoris Brezillon /* 255293db446aSBoris Brezillon * Some SoCs integrate this controller (e.g., its interrupt bits) in 255393db446aSBoris Brezillon * interesting ways 255493db446aSBoris Brezillon */ 255593db446aSBoris Brezillon if (soc) { 255693db446aSBoris Brezillon ctrl->soc = soc; 255793db446aSBoris Brezillon 255893db446aSBoris Brezillon ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, 255993db446aSBoris Brezillon DRV_NAME, ctrl); 256093db446aSBoris Brezillon 256193db446aSBoris Brezillon /* Enable interrupt */ 256293db446aSBoris Brezillon ctrl->soc->ctlrdy_ack(ctrl->soc); 256393db446aSBoris Brezillon ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 256493db446aSBoris Brezillon } else { 256593db446aSBoris Brezillon /* Use standard interrupt infrastructure */ 256693db446aSBoris Brezillon ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, 256793db446aSBoris Brezillon DRV_NAME, ctrl); 256893db446aSBoris Brezillon } 256993db446aSBoris Brezillon if (ret < 0) { 257093db446aSBoris Brezillon dev_err(dev, "can't allocate IRQ %d: error %d\n", 257193db446aSBoris Brezillon ctrl->irq, ret); 257293db446aSBoris Brezillon goto err; 257393db446aSBoris Brezillon } 257493db446aSBoris Brezillon 257593db446aSBoris Brezillon for_each_available_child_of_node(dn, child) { 257693db446aSBoris Brezillon if (of_device_is_compatible(child, "brcm,nandcs")) { 257793db446aSBoris Brezillon struct brcmnand_host *host; 257893db446aSBoris Brezillon 257993db446aSBoris Brezillon host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 258093db446aSBoris Brezillon if (!host) { 258193db446aSBoris Brezillon of_node_put(child); 258293db446aSBoris Brezillon ret = -ENOMEM; 258393db446aSBoris Brezillon goto err; 258493db446aSBoris Brezillon } 258593db446aSBoris Brezillon host->pdev = pdev; 258693db446aSBoris Brezillon host->ctrl = ctrl; 258793db446aSBoris Brezillon 258893db446aSBoris Brezillon ret = brcmnand_init_cs(host, child); 258993db446aSBoris Brezillon if (ret) { 259093db446aSBoris Brezillon devm_kfree(dev, host); 259193db446aSBoris Brezillon continue; /* Try all chip-selects */ 259293db446aSBoris Brezillon } 259393db446aSBoris Brezillon 259493db446aSBoris Brezillon list_add_tail(&host->node, &ctrl->host_list); 259593db446aSBoris Brezillon } 259693db446aSBoris Brezillon } 259793db446aSBoris Brezillon 259893db446aSBoris Brezillon /* No chip-selects could initialize properly */ 259993db446aSBoris Brezillon if (list_empty(&ctrl->host_list)) { 260093db446aSBoris Brezillon ret = -ENODEV; 260193db446aSBoris Brezillon goto err; 260293db446aSBoris Brezillon } 260393db446aSBoris Brezillon 260493db446aSBoris Brezillon return 0; 260593db446aSBoris Brezillon 260693db446aSBoris Brezillon err: 260793db446aSBoris Brezillon clk_disable_unprepare(ctrl->clk); 260893db446aSBoris Brezillon return ret; 260993db446aSBoris Brezillon 261093db446aSBoris Brezillon } 261193db446aSBoris Brezillon EXPORT_SYMBOL_GPL(brcmnand_probe); 261293db446aSBoris Brezillon 261393db446aSBoris Brezillon int brcmnand_remove(struct platform_device *pdev) 261493db446aSBoris Brezillon { 261593db446aSBoris Brezillon struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); 261693db446aSBoris Brezillon struct brcmnand_host *host; 261793db446aSBoris Brezillon 261893db446aSBoris Brezillon list_for_each_entry(host, &ctrl->host_list, node) 261993db446aSBoris Brezillon nand_release(nand_to_mtd(&host->chip)); 262093db446aSBoris Brezillon 262193db446aSBoris Brezillon clk_disable_unprepare(ctrl->clk); 262293db446aSBoris Brezillon 262393db446aSBoris Brezillon dev_set_drvdata(&pdev->dev, NULL); 262493db446aSBoris Brezillon 262593db446aSBoris Brezillon return 0; 262693db446aSBoris Brezillon } 262793db446aSBoris Brezillon EXPORT_SYMBOL_GPL(brcmnand_remove); 262893db446aSBoris Brezillon 262993db446aSBoris Brezillon MODULE_LICENSE("GPL v2"); 263093db446aSBoris Brezillon MODULE_AUTHOR("Kevin Cernekee"); 263193db446aSBoris Brezillon MODULE_AUTHOR("Brian Norris"); 263293db446aSBoris Brezillon MODULE_DESCRIPTION("NAND driver for Broadcom chips"); 263393db446aSBoris Brezillon MODULE_ALIAS("platform:brcmnand"); 2634