1 /* 2 * Copyright (C) 2004 Embedded Edge, LLC 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/slab.h> 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/mtd/mtd.h> 14 #include <linux/mtd/rawnand.h> 15 #include <linux/mtd/partitions.h> 16 #include <linux/platform_device.h> 17 #include <asm/io.h> 18 #include <asm/mach-au1x00/au1000.h> 19 #include <asm/mach-au1x00/au1550nd.h> 20 21 22 struct au1550nd_ctx { 23 struct nand_chip chip; 24 25 int cs; 26 void __iomem *base; 27 void (*write_byte)(struct mtd_info *, u_char); 28 }; 29 30 /** 31 * au_read_byte - read one byte from the chip 32 * @mtd: MTD device structure 33 * 34 * read function for 8bit buswidth 35 */ 36 static u_char au_read_byte(struct mtd_info *mtd) 37 { 38 struct nand_chip *this = mtd_to_nand(mtd); 39 u_char ret = readb(this->IO_ADDR_R); 40 wmb(); /* drain writebuffer */ 41 return ret; 42 } 43 44 /** 45 * au_write_byte - write one byte to the chip 46 * @mtd: MTD device structure 47 * @byte: pointer to data byte to write 48 * 49 * write function for 8it buswidth 50 */ 51 static void au_write_byte(struct mtd_info *mtd, u_char byte) 52 { 53 struct nand_chip *this = mtd_to_nand(mtd); 54 writeb(byte, this->IO_ADDR_W); 55 wmb(); /* drain writebuffer */ 56 } 57 58 /** 59 * au_read_byte16 - read one byte endianness aware from the chip 60 * @mtd: MTD device structure 61 * 62 * read function for 16bit buswidth with endianness conversion 63 */ 64 static u_char au_read_byte16(struct mtd_info *mtd) 65 { 66 struct nand_chip *this = mtd_to_nand(mtd); 67 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); 68 wmb(); /* drain writebuffer */ 69 return ret; 70 } 71 72 /** 73 * au_write_byte16 - write one byte endianness aware to the chip 74 * @mtd: MTD device structure 75 * @byte: pointer to data byte to write 76 * 77 * write function for 16bit buswidth with endianness conversion 78 */ 79 static void au_write_byte16(struct mtd_info *mtd, u_char byte) 80 { 81 struct nand_chip *this = mtd_to_nand(mtd); 82 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); 83 wmb(); /* drain writebuffer */ 84 } 85 86 /** 87 * au_read_word - read one word from the chip 88 * @mtd: MTD device structure 89 * 90 * read function for 16bit buswidth without endianness conversion 91 */ 92 static u16 au_read_word(struct mtd_info *mtd) 93 { 94 struct nand_chip *this = mtd_to_nand(mtd); 95 u16 ret = readw(this->IO_ADDR_R); 96 wmb(); /* drain writebuffer */ 97 return ret; 98 } 99 100 /** 101 * au_write_buf - write buffer to chip 102 * @mtd: MTD device structure 103 * @buf: data buffer 104 * @len: number of bytes to write 105 * 106 * write function for 8bit buswidth 107 */ 108 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 109 { 110 int i; 111 struct nand_chip *this = mtd_to_nand(mtd); 112 113 for (i = 0; i < len; i++) { 114 writeb(buf[i], this->IO_ADDR_W); 115 wmb(); /* drain writebuffer */ 116 } 117 } 118 119 /** 120 * au_read_buf - read chip data into buffer 121 * @mtd: MTD device structure 122 * @buf: buffer to store date 123 * @len: number of bytes to read 124 * 125 * read function for 8bit buswidth 126 */ 127 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) 128 { 129 int i; 130 struct nand_chip *this = mtd_to_nand(mtd); 131 132 for (i = 0; i < len; i++) { 133 buf[i] = readb(this->IO_ADDR_R); 134 wmb(); /* drain writebuffer */ 135 } 136 } 137 138 /** 139 * au_write_buf16 - write buffer to chip 140 * @mtd: MTD device structure 141 * @buf: data buffer 142 * @len: number of bytes to write 143 * 144 * write function for 16bit buswidth 145 */ 146 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) 147 { 148 int i; 149 struct nand_chip *this = mtd_to_nand(mtd); 150 u16 *p = (u16 *) buf; 151 len >>= 1; 152 153 for (i = 0; i < len; i++) { 154 writew(p[i], this->IO_ADDR_W); 155 wmb(); /* drain writebuffer */ 156 } 157 158 } 159 160 /** 161 * au_read_buf16 - read chip data into buffer 162 * @mtd: MTD device structure 163 * @buf: buffer to store date 164 * @len: number of bytes to read 165 * 166 * read function for 16bit buswidth 167 */ 168 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) 169 { 170 int i; 171 struct nand_chip *this = mtd_to_nand(mtd); 172 u16 *p = (u16 *) buf; 173 len >>= 1; 174 175 for (i = 0; i < len; i++) { 176 p[i] = readw(this->IO_ADDR_R); 177 wmb(); /* drain writebuffer */ 178 } 179 } 180 181 /* Select the chip by setting nCE to low */ 182 #define NAND_CTL_SETNCE 1 183 /* Deselect the chip by setting nCE to high */ 184 #define NAND_CTL_CLRNCE 2 185 /* Select the command latch by setting CLE to high */ 186 #define NAND_CTL_SETCLE 3 187 /* Deselect the command latch by setting CLE to low */ 188 #define NAND_CTL_CLRCLE 4 189 /* Select the address latch by setting ALE to high */ 190 #define NAND_CTL_SETALE 5 191 /* Deselect the address latch by setting ALE to low */ 192 #define NAND_CTL_CLRALE 6 193 194 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) 195 { 196 struct nand_chip *this = mtd_to_nand(mtd); 197 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx, 198 chip); 199 200 switch (cmd) { 201 202 case NAND_CTL_SETCLE: 203 this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD; 204 break; 205 206 case NAND_CTL_CLRCLE: 207 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA; 208 break; 209 210 case NAND_CTL_SETALE: 211 this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR; 212 break; 213 214 case NAND_CTL_CLRALE: 215 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA; 216 /* FIXME: Nobody knows why this is necessary, 217 * but it works only that way */ 218 udelay(1); 219 break; 220 221 case NAND_CTL_SETNCE: 222 /* assert (force assert) chip enable */ 223 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL); 224 break; 225 226 case NAND_CTL_CLRNCE: 227 /* deassert chip enable */ 228 alchemy_wrsmem(0, AU1000_MEM_STNDCTL); 229 break; 230 } 231 232 this->IO_ADDR_R = this->IO_ADDR_W; 233 234 wmb(); /* Drain the writebuffer */ 235 } 236 237 int au1550_device_ready(struct mtd_info *mtd) 238 { 239 return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0; 240 } 241 242 /** 243 * au1550_select_chip - control -CE line 244 * Forbid driving -CE manually permitting the NAND controller to do this. 245 * Keeping -CE asserted during the whole sector reads interferes with the 246 * NOR flash and PCMCIA drivers as it causes contention on the static bus. 247 * We only have to hold -CE low for the NAND read commands since the flash 248 * chip needs it to be asserted during chip not ready time but the NAND 249 * controller keeps it released. 250 * 251 * @mtd: MTD device structure 252 * @chip: chipnumber to select, -1 for deselect 253 */ 254 static void au1550_select_chip(struct mtd_info *mtd, int chip) 255 { 256 } 257 258 /** 259 * au1550_command - Send command to NAND device 260 * @mtd: MTD device structure 261 * @command: the command to be sent 262 * @column: the column address for this command, -1 if none 263 * @page_addr: the page address for this command, -1 if none 264 */ 265 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) 266 { 267 struct nand_chip *this = mtd_to_nand(mtd); 268 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx, 269 chip); 270 int ce_override = 0, i; 271 unsigned long flags = 0; 272 273 /* Begin command latch cycle */ 274 au1550_hwcontrol(mtd, NAND_CTL_SETCLE); 275 /* 276 * Write out the command to the device. 277 */ 278 if (command == NAND_CMD_SEQIN) { 279 int readcmd; 280 281 if (column >= mtd->writesize) { 282 /* OOB area */ 283 column -= mtd->writesize; 284 readcmd = NAND_CMD_READOOB; 285 } else if (column < 256) { 286 /* First 256 bytes --> READ0 */ 287 readcmd = NAND_CMD_READ0; 288 } else { 289 column -= 256; 290 readcmd = NAND_CMD_READ1; 291 } 292 ctx->write_byte(mtd, readcmd); 293 } 294 ctx->write_byte(mtd, command); 295 296 /* Set ALE and clear CLE to start address cycle */ 297 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); 298 299 if (column != -1 || page_addr != -1) { 300 au1550_hwcontrol(mtd, NAND_CTL_SETALE); 301 302 /* Serially input address */ 303 if (column != -1) { 304 /* Adjust columns for 16 bit buswidth */ 305 if (this->options & NAND_BUSWIDTH_16 && 306 !nand_opcode_8bits(command)) 307 column >>= 1; 308 ctx->write_byte(mtd, column); 309 } 310 if (page_addr != -1) { 311 ctx->write_byte(mtd, (u8)(page_addr & 0xff)); 312 313 if (command == NAND_CMD_READ0 || 314 command == NAND_CMD_READ1 || 315 command == NAND_CMD_READOOB) { 316 /* 317 * NAND controller will release -CE after 318 * the last address byte is written, so we'll 319 * have to forcibly assert it. No interrupts 320 * are allowed while we do this as we don't 321 * want the NOR flash or PCMCIA drivers to 322 * steal our precious bytes of data... 323 */ 324 ce_override = 1; 325 local_irq_save(flags); 326 au1550_hwcontrol(mtd, NAND_CTL_SETNCE); 327 } 328 329 ctx->write_byte(mtd, (u8)(page_addr >> 8)); 330 331 if (this->options & NAND_ROW_ADDR_3) 332 ctx->write_byte(mtd, 333 ((page_addr >> 16) & 0x0f)); 334 } 335 /* Latch in address */ 336 au1550_hwcontrol(mtd, NAND_CTL_CLRALE); 337 } 338 339 /* 340 * Program and erase have their own busy handlers. 341 * Status and sequential in need no delay. 342 */ 343 switch (command) { 344 345 case NAND_CMD_PAGEPROG: 346 case NAND_CMD_ERASE1: 347 case NAND_CMD_ERASE2: 348 case NAND_CMD_SEQIN: 349 case NAND_CMD_STATUS: 350 return; 351 352 case NAND_CMD_RESET: 353 break; 354 355 case NAND_CMD_READ0: 356 case NAND_CMD_READ1: 357 case NAND_CMD_READOOB: 358 /* Check if we're really driving -CE low (just in case) */ 359 if (unlikely(!ce_override)) 360 break; 361 362 /* Apply a short delay always to ensure that we do wait tWB. */ 363 ndelay(100); 364 /* Wait for a chip to become ready... */ 365 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) 366 udelay(1); 367 368 /* Release -CE and re-enable interrupts. */ 369 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); 370 local_irq_restore(flags); 371 return; 372 } 373 /* Apply this short delay always to ensure that we do wait tWB. */ 374 ndelay(100); 375 376 while(!this->dev_ready(mtd)); 377 } 378 379 static int find_nand_cs(unsigned long nand_base) 380 { 381 void __iomem *base = 382 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR); 383 unsigned long addr, staddr, start, mask, end; 384 int i; 385 386 for (i = 0; i < 4; i++) { 387 addr = 0x1000 + (i * 0x10); /* CSx */ 388 staddr = __raw_readl(base + addr + 0x08); /* STADDRx */ 389 /* figure out the decoded range of this CS */ 390 start = (staddr << 4) & 0xfffc0000; 391 mask = (staddr << 18) & 0xfffc0000; 392 end = (start | (start - 1)) & ~(start ^ mask); 393 if ((nand_base >= start) && (nand_base < end)) 394 return i; 395 } 396 397 return -ENODEV; 398 } 399 400 static int au1550nd_probe(struct platform_device *pdev) 401 { 402 struct au1550nd_platdata *pd; 403 struct au1550nd_ctx *ctx; 404 struct nand_chip *this; 405 struct mtd_info *mtd; 406 struct resource *r; 407 int ret, cs; 408 409 pd = dev_get_platdata(&pdev->dev); 410 if (!pd) { 411 dev_err(&pdev->dev, "missing platform data\n"); 412 return -ENODEV; 413 } 414 415 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 416 if (!ctx) 417 return -ENOMEM; 418 419 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 420 if (!r) { 421 dev_err(&pdev->dev, "no NAND memory resource\n"); 422 ret = -ENODEV; 423 goto out1; 424 } 425 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) { 426 dev_err(&pdev->dev, "cannot claim NAND memory area\n"); 427 ret = -ENOMEM; 428 goto out1; 429 } 430 431 ctx->base = ioremap_nocache(r->start, 0x1000); 432 if (!ctx->base) { 433 dev_err(&pdev->dev, "cannot remap NAND memory area\n"); 434 ret = -ENODEV; 435 goto out2; 436 } 437 438 this = &ctx->chip; 439 mtd = nand_to_mtd(this); 440 mtd->dev.parent = &pdev->dev; 441 442 /* figure out which CS# r->start belongs to */ 443 cs = find_nand_cs(r->start); 444 if (cs < 0) { 445 dev_err(&pdev->dev, "cannot detect NAND chipselect\n"); 446 ret = -ENODEV; 447 goto out3; 448 } 449 ctx->cs = cs; 450 451 this->dev_ready = au1550_device_ready; 452 this->select_chip = au1550_select_chip; 453 this->cmdfunc = au1550_command; 454 455 /* 30 us command delay time */ 456 this->chip_delay = 30; 457 this->ecc.mode = NAND_ECC_SOFT; 458 this->ecc.algo = NAND_ECC_HAMMING; 459 460 if (pd->devwidth) 461 this->options |= NAND_BUSWIDTH_16; 462 463 this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte; 464 ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte; 465 this->read_word = au_read_word; 466 this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf; 467 this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf; 468 469 ret = nand_scan(mtd, 1); 470 if (ret) { 471 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret); 472 goto out3; 473 } 474 475 mtd_device_register(mtd, pd->parts, pd->num_parts); 476 477 platform_set_drvdata(pdev, ctx); 478 479 return 0; 480 481 out3: 482 iounmap(ctx->base); 483 out2: 484 release_mem_region(r->start, resource_size(r)); 485 out1: 486 kfree(ctx); 487 return ret; 488 } 489 490 static int au1550nd_remove(struct platform_device *pdev) 491 { 492 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev); 493 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 494 495 nand_release(nand_to_mtd(&ctx->chip)); 496 iounmap(ctx->base); 497 release_mem_region(r->start, 0x1000); 498 kfree(ctx); 499 return 0; 500 } 501 502 static struct platform_driver au1550nd_driver = { 503 .driver = { 504 .name = "au1550-nand", 505 }, 506 .probe = au1550nd_probe, 507 .remove = au1550nd_remove, 508 }; 509 510 module_platform_driver(au1550nd_driver); 511 512 MODULE_LICENSE("GPL"); 513 MODULE_AUTHOR("Embedded Edge, LLC"); 514 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board"); 515