1 /* 2 * Copyright (C) 2004 Embedded Edge, LLC 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 10 #include <linux/slab.h> 11 #include <linux/gpio.h> 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/mtd/mtd.h> 15 #include <linux/mtd/rawnand.h> 16 #include <linux/mtd/partitions.h> 17 #include <linux/platform_device.h> 18 #include <asm/io.h> 19 #include <asm/mach-au1x00/au1000.h> 20 #include <asm/mach-au1x00/au1550nd.h> 21 22 23 struct au1550nd_ctx { 24 struct nand_chip chip; 25 26 int cs; 27 void __iomem *base; 28 void (*write_byte)(struct mtd_info *, u_char); 29 }; 30 31 /** 32 * au_read_byte - read one byte from the chip 33 * @mtd: MTD device structure 34 * 35 * read function for 8bit buswidth 36 */ 37 static u_char au_read_byte(struct mtd_info *mtd) 38 { 39 struct nand_chip *this = mtd_to_nand(mtd); 40 u_char ret = readb(this->IO_ADDR_R); 41 wmb(); /* drain writebuffer */ 42 return ret; 43 } 44 45 /** 46 * au_write_byte - write one byte to the chip 47 * @mtd: MTD device structure 48 * @byte: pointer to data byte to write 49 * 50 * write function for 8it buswidth 51 */ 52 static void au_write_byte(struct mtd_info *mtd, u_char byte) 53 { 54 struct nand_chip *this = mtd_to_nand(mtd); 55 writeb(byte, this->IO_ADDR_W); 56 wmb(); /* drain writebuffer */ 57 } 58 59 /** 60 * au_read_byte16 - read one byte endianness aware from the chip 61 * @mtd: MTD device structure 62 * 63 * read function for 16bit buswidth with endianness conversion 64 */ 65 static u_char au_read_byte16(struct mtd_info *mtd) 66 { 67 struct nand_chip *this = mtd_to_nand(mtd); 68 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); 69 wmb(); /* drain writebuffer */ 70 return ret; 71 } 72 73 /** 74 * au_write_byte16 - write one byte endianness aware to the chip 75 * @mtd: MTD device structure 76 * @byte: pointer to data byte to write 77 * 78 * write function for 16bit buswidth with endianness conversion 79 */ 80 static void au_write_byte16(struct mtd_info *mtd, u_char byte) 81 { 82 struct nand_chip *this = mtd_to_nand(mtd); 83 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); 84 wmb(); /* drain writebuffer */ 85 } 86 87 /** 88 * au_read_word - read one word from the chip 89 * @mtd: MTD device structure 90 * 91 * read function for 16bit buswidth without endianness conversion 92 */ 93 static u16 au_read_word(struct mtd_info *mtd) 94 { 95 struct nand_chip *this = mtd_to_nand(mtd); 96 u16 ret = readw(this->IO_ADDR_R); 97 wmb(); /* drain writebuffer */ 98 return ret; 99 } 100 101 /** 102 * au_write_buf - write buffer to chip 103 * @mtd: MTD device structure 104 * @buf: data buffer 105 * @len: number of bytes to write 106 * 107 * write function for 8bit buswidth 108 */ 109 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 110 { 111 int i; 112 struct nand_chip *this = mtd_to_nand(mtd); 113 114 for (i = 0; i < len; i++) { 115 writeb(buf[i], this->IO_ADDR_W); 116 wmb(); /* drain writebuffer */ 117 } 118 } 119 120 /** 121 * au_read_buf - read chip data into buffer 122 * @mtd: MTD device structure 123 * @buf: buffer to store date 124 * @len: number of bytes to read 125 * 126 * read function for 8bit buswidth 127 */ 128 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) 129 { 130 int i; 131 struct nand_chip *this = mtd_to_nand(mtd); 132 133 for (i = 0; i < len; i++) { 134 buf[i] = readb(this->IO_ADDR_R); 135 wmb(); /* drain writebuffer */ 136 } 137 } 138 139 /** 140 * au_write_buf16 - write buffer to chip 141 * @mtd: MTD device structure 142 * @buf: data buffer 143 * @len: number of bytes to write 144 * 145 * write function for 16bit buswidth 146 */ 147 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) 148 { 149 int i; 150 struct nand_chip *this = mtd_to_nand(mtd); 151 u16 *p = (u16 *) buf; 152 len >>= 1; 153 154 for (i = 0; i < len; i++) { 155 writew(p[i], this->IO_ADDR_W); 156 wmb(); /* drain writebuffer */ 157 } 158 159 } 160 161 /** 162 * au_read_buf16 - read chip data into buffer 163 * @mtd: MTD device structure 164 * @buf: buffer to store date 165 * @len: number of bytes to read 166 * 167 * read function for 16bit buswidth 168 */ 169 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) 170 { 171 int i; 172 struct nand_chip *this = mtd_to_nand(mtd); 173 u16 *p = (u16 *) buf; 174 len >>= 1; 175 176 for (i = 0; i < len; i++) { 177 p[i] = readw(this->IO_ADDR_R); 178 wmb(); /* drain writebuffer */ 179 } 180 } 181 182 /* Select the chip by setting nCE to low */ 183 #define NAND_CTL_SETNCE 1 184 /* Deselect the chip by setting nCE to high */ 185 #define NAND_CTL_CLRNCE 2 186 /* Select the command latch by setting CLE to high */ 187 #define NAND_CTL_SETCLE 3 188 /* Deselect the command latch by setting CLE to low */ 189 #define NAND_CTL_CLRCLE 4 190 /* Select the address latch by setting ALE to high */ 191 #define NAND_CTL_SETALE 5 192 /* Deselect the address latch by setting ALE to low */ 193 #define NAND_CTL_CLRALE 6 194 195 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) 196 { 197 struct nand_chip *this = mtd_to_nand(mtd); 198 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx, 199 chip); 200 201 switch (cmd) { 202 203 case NAND_CTL_SETCLE: 204 this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD; 205 break; 206 207 case NAND_CTL_CLRCLE: 208 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA; 209 break; 210 211 case NAND_CTL_SETALE: 212 this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR; 213 break; 214 215 case NAND_CTL_CLRALE: 216 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA; 217 /* FIXME: Nobody knows why this is necessary, 218 * but it works only that way */ 219 udelay(1); 220 break; 221 222 case NAND_CTL_SETNCE: 223 /* assert (force assert) chip enable */ 224 alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL); 225 break; 226 227 case NAND_CTL_CLRNCE: 228 /* deassert chip enable */ 229 alchemy_wrsmem(0, AU1000_MEM_STNDCTL); 230 break; 231 } 232 233 this->IO_ADDR_R = this->IO_ADDR_W; 234 235 wmb(); /* Drain the writebuffer */ 236 } 237 238 int au1550_device_ready(struct mtd_info *mtd) 239 { 240 return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0; 241 } 242 243 /** 244 * au1550_select_chip - control -CE line 245 * Forbid driving -CE manually permitting the NAND controller to do this. 246 * Keeping -CE asserted during the whole sector reads interferes with the 247 * NOR flash and PCMCIA drivers as it causes contention on the static bus. 248 * We only have to hold -CE low for the NAND read commands since the flash 249 * chip needs it to be asserted during chip not ready time but the NAND 250 * controller keeps it released. 251 * 252 * @mtd: MTD device structure 253 * @chip: chipnumber to select, -1 for deselect 254 */ 255 static void au1550_select_chip(struct mtd_info *mtd, int chip) 256 { 257 } 258 259 /** 260 * au1550_command - Send command to NAND device 261 * @mtd: MTD device structure 262 * @command: the command to be sent 263 * @column: the column address for this command, -1 if none 264 * @page_addr: the page address for this command, -1 if none 265 */ 266 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) 267 { 268 struct nand_chip *this = mtd_to_nand(mtd); 269 struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx, 270 chip); 271 int ce_override = 0, i; 272 unsigned long flags = 0; 273 274 /* Begin command latch cycle */ 275 au1550_hwcontrol(mtd, NAND_CTL_SETCLE); 276 /* 277 * Write out the command to the device. 278 */ 279 if (command == NAND_CMD_SEQIN) { 280 int readcmd; 281 282 if (column >= mtd->writesize) { 283 /* OOB area */ 284 column -= mtd->writesize; 285 readcmd = NAND_CMD_READOOB; 286 } else if (column < 256) { 287 /* First 256 bytes --> READ0 */ 288 readcmd = NAND_CMD_READ0; 289 } else { 290 column -= 256; 291 readcmd = NAND_CMD_READ1; 292 } 293 ctx->write_byte(mtd, readcmd); 294 } 295 ctx->write_byte(mtd, command); 296 297 /* Set ALE and clear CLE to start address cycle */ 298 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); 299 300 if (column != -1 || page_addr != -1) { 301 au1550_hwcontrol(mtd, NAND_CTL_SETALE); 302 303 /* Serially input address */ 304 if (column != -1) { 305 /* Adjust columns for 16 bit buswidth */ 306 if (this->options & NAND_BUSWIDTH_16 && 307 !nand_opcode_8bits(command)) 308 column >>= 1; 309 ctx->write_byte(mtd, column); 310 } 311 if (page_addr != -1) { 312 ctx->write_byte(mtd, (u8)(page_addr & 0xff)); 313 314 if (command == NAND_CMD_READ0 || 315 command == NAND_CMD_READ1 || 316 command == NAND_CMD_READOOB) { 317 /* 318 * NAND controller will release -CE after 319 * the last address byte is written, so we'll 320 * have to forcibly assert it. No interrupts 321 * are allowed while we do this as we don't 322 * want the NOR flash or PCMCIA drivers to 323 * steal our precious bytes of data... 324 */ 325 ce_override = 1; 326 local_irq_save(flags); 327 au1550_hwcontrol(mtd, NAND_CTL_SETNCE); 328 } 329 330 ctx->write_byte(mtd, (u8)(page_addr >> 8)); 331 332 if (this->options & NAND_ROW_ADDR_3) 333 ctx->write_byte(mtd, 334 ((page_addr >> 16) & 0x0f)); 335 } 336 /* Latch in address */ 337 au1550_hwcontrol(mtd, NAND_CTL_CLRALE); 338 } 339 340 /* 341 * Program and erase have their own busy handlers. 342 * Status and sequential in need no delay. 343 */ 344 switch (command) { 345 346 case NAND_CMD_PAGEPROG: 347 case NAND_CMD_ERASE1: 348 case NAND_CMD_ERASE2: 349 case NAND_CMD_SEQIN: 350 case NAND_CMD_STATUS: 351 return; 352 353 case NAND_CMD_RESET: 354 break; 355 356 case NAND_CMD_READ0: 357 case NAND_CMD_READ1: 358 case NAND_CMD_READOOB: 359 /* Check if we're really driving -CE low (just in case) */ 360 if (unlikely(!ce_override)) 361 break; 362 363 /* Apply a short delay always to ensure that we do wait tWB. */ 364 ndelay(100); 365 /* Wait for a chip to become ready... */ 366 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) 367 udelay(1); 368 369 /* Release -CE and re-enable interrupts. */ 370 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); 371 local_irq_restore(flags); 372 return; 373 } 374 /* Apply this short delay always to ensure that we do wait tWB. */ 375 ndelay(100); 376 377 while(!this->dev_ready(mtd)); 378 } 379 380 static int find_nand_cs(unsigned long nand_base) 381 { 382 void __iomem *base = 383 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR); 384 unsigned long addr, staddr, start, mask, end; 385 int i; 386 387 for (i = 0; i < 4; i++) { 388 addr = 0x1000 + (i * 0x10); /* CSx */ 389 staddr = __raw_readl(base + addr + 0x08); /* STADDRx */ 390 /* figure out the decoded range of this CS */ 391 start = (staddr << 4) & 0xfffc0000; 392 mask = (staddr << 18) & 0xfffc0000; 393 end = (start | (start - 1)) & ~(start ^ mask); 394 if ((nand_base >= start) && (nand_base < end)) 395 return i; 396 } 397 398 return -ENODEV; 399 } 400 401 static int au1550nd_probe(struct platform_device *pdev) 402 { 403 struct au1550nd_platdata *pd; 404 struct au1550nd_ctx *ctx; 405 struct nand_chip *this; 406 struct mtd_info *mtd; 407 struct resource *r; 408 int ret, cs; 409 410 pd = dev_get_platdata(&pdev->dev); 411 if (!pd) { 412 dev_err(&pdev->dev, "missing platform data\n"); 413 return -ENODEV; 414 } 415 416 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 417 if (!ctx) 418 return -ENOMEM; 419 420 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 421 if (!r) { 422 dev_err(&pdev->dev, "no NAND memory resource\n"); 423 ret = -ENODEV; 424 goto out1; 425 } 426 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) { 427 dev_err(&pdev->dev, "cannot claim NAND memory area\n"); 428 ret = -ENOMEM; 429 goto out1; 430 } 431 432 ctx->base = ioremap_nocache(r->start, 0x1000); 433 if (!ctx->base) { 434 dev_err(&pdev->dev, "cannot remap NAND memory area\n"); 435 ret = -ENODEV; 436 goto out2; 437 } 438 439 this = &ctx->chip; 440 mtd = nand_to_mtd(this); 441 mtd->dev.parent = &pdev->dev; 442 443 /* figure out which CS# r->start belongs to */ 444 cs = find_nand_cs(r->start); 445 if (cs < 0) { 446 dev_err(&pdev->dev, "cannot detect NAND chipselect\n"); 447 ret = -ENODEV; 448 goto out3; 449 } 450 ctx->cs = cs; 451 452 this->dev_ready = au1550_device_ready; 453 this->select_chip = au1550_select_chip; 454 this->cmdfunc = au1550_command; 455 456 /* 30 us command delay time */ 457 this->chip_delay = 30; 458 this->ecc.mode = NAND_ECC_SOFT; 459 this->ecc.algo = NAND_ECC_HAMMING; 460 461 if (pd->devwidth) 462 this->options |= NAND_BUSWIDTH_16; 463 464 this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte; 465 ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte; 466 this->read_word = au_read_word; 467 this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf; 468 this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf; 469 470 ret = nand_scan(mtd, 1); 471 if (ret) { 472 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret); 473 goto out3; 474 } 475 476 mtd_device_register(mtd, pd->parts, pd->num_parts); 477 478 platform_set_drvdata(pdev, ctx); 479 480 return 0; 481 482 out3: 483 iounmap(ctx->base); 484 out2: 485 release_mem_region(r->start, resource_size(r)); 486 out1: 487 kfree(ctx); 488 return ret; 489 } 490 491 static int au1550nd_remove(struct platform_device *pdev) 492 { 493 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev); 494 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 495 496 nand_release(nand_to_mtd(&ctx->chip)); 497 iounmap(ctx->base); 498 release_mem_region(r->start, 0x1000); 499 kfree(ctx); 500 return 0; 501 } 502 503 static struct platform_driver au1550nd_driver = { 504 .driver = { 505 .name = "au1550-nand", 506 }, 507 .probe = au1550nd_probe, 508 .remove = au1550nd_remove, 509 }; 510 511 module_platform_driver(au1550nd_driver); 512 513 MODULE_LICENSE("GPL"); 514 MODULE_AUTHOR("Embedded Edge, LLC"); 515 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board"); 516