xref: /openbmc/linux/drivers/mtd/nand/raw/au1550nd.c (revision 4f727ece) 
1 /*
2  *  Copyright (C) 2004 Embedded Edge, LLC
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  */
9 
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/rawnand.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/platform_device.h>
17 #include <asm/io.h>
18 #include <asm/mach-au1x00/au1000.h>
19 #include <asm/mach-au1x00/au1550nd.h>
20 
21 
22 struct au1550nd_ctx {
23 	struct nand_chip chip;
24 
25 	int cs;
26 	void __iomem *base;
27 	void (*write_byte)(struct nand_chip *, u_char);
28 };
29 
30 /**
31  * au_read_byte -  read one byte from the chip
32  * @this:	NAND chip object
33  *
34  * read function for 8bit buswidth
35  */
36 static u_char au_read_byte(struct nand_chip *this)
37 {
38 	u_char ret = readb(this->legacy.IO_ADDR_R);
39 	wmb(); /* drain writebuffer */
40 	return ret;
41 }
42 
43 /**
44  * au_write_byte -  write one byte to the chip
45  * @this:	NAND chip object
46  * @byte:	pointer to data byte to write
47  *
48  * write function for 8it buswidth
49  */
50 static void au_write_byte(struct nand_chip *this, u_char byte)
51 {
52 	writeb(byte, this->legacy.IO_ADDR_W);
53 	wmb(); /* drain writebuffer */
54 }
55 
56 /**
57  * au_read_byte16 -  read one byte endianness aware from the chip
58  * @this:	NAND chip object
59  *
60  * read function for 16bit buswidth with endianness conversion
61  */
62 static u_char au_read_byte16(struct nand_chip *this)
63 {
64 	u_char ret = (u_char) cpu_to_le16(readw(this->legacy.IO_ADDR_R));
65 	wmb(); /* drain writebuffer */
66 	return ret;
67 }
68 
69 /**
70  * au_write_byte16 -  write one byte endianness aware to the chip
71  * @this:	NAND chip object
72  * @byte:	pointer to data byte to write
73  *
74  * write function for 16bit buswidth with endianness conversion
75  */
76 static void au_write_byte16(struct nand_chip *this, u_char byte)
77 {
78 	writew(le16_to_cpu((u16) byte), this->legacy.IO_ADDR_W);
79 	wmb(); /* drain writebuffer */
80 }
81 
82 /**
83  * au_write_buf -  write buffer to chip
84  * @this:	NAND chip object
85  * @buf:	data buffer
86  * @len:	number of bytes to write
87  *
88  * write function for 8bit buswidth
89  */
90 static void au_write_buf(struct nand_chip *this, const u_char *buf, int len)
91 {
92 	int i;
93 
94 	for (i = 0; i < len; i++) {
95 		writeb(buf[i], this->legacy.IO_ADDR_W);
96 		wmb(); /* drain writebuffer */
97 	}
98 }
99 
100 /**
101  * au_read_buf -  read chip data into buffer
102  * @this:	NAND chip object
103  * @buf:	buffer to store date
104  * @len:	number of bytes to read
105  *
106  * read function for 8bit buswidth
107  */
108 static void au_read_buf(struct nand_chip *this, u_char *buf, int len)
109 {
110 	int i;
111 
112 	for (i = 0; i < len; i++) {
113 		buf[i] = readb(this->legacy.IO_ADDR_R);
114 		wmb(); /* drain writebuffer */
115 	}
116 }
117 
118 /**
119  * au_write_buf16 -  write buffer to chip
120  * @this:	NAND chip object
121  * @buf:	data buffer
122  * @len:	number of bytes to write
123  *
124  * write function for 16bit buswidth
125  */
126 static void au_write_buf16(struct nand_chip *this, const u_char *buf, int len)
127 {
128 	int i;
129 	u16 *p = (u16 *) buf;
130 	len >>= 1;
131 
132 	for (i = 0; i < len; i++) {
133 		writew(p[i], this->legacy.IO_ADDR_W);
134 		wmb(); /* drain writebuffer */
135 	}
136 
137 }
138 
139 /**
140  * au_read_buf16 -  read chip data into buffer
141  * @mtd:	MTD device structure
142  * @buf:	buffer to store date
143  * @len:	number of bytes to read
144  *
145  * read function for 16bit buswidth
146  */
147 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
148 {
149 	int i;
150 	struct nand_chip *this = mtd_to_nand(mtd);
151 	u16 *p = (u16 *) buf;
152 	len >>= 1;
153 
154 	for (i = 0; i < len; i++) {
155 		p[i] = readw(this->legacy.IO_ADDR_R);
156 		wmb(); /* drain writebuffer */
157 	}
158 }
159 
160 /* Select the chip by setting nCE to low */
161 #define NAND_CTL_SETNCE		1
162 /* Deselect the chip by setting nCE to high */
163 #define NAND_CTL_CLRNCE		2
164 /* Select the command latch by setting CLE to high */
165 #define NAND_CTL_SETCLE		3
166 /* Deselect the command latch by setting CLE to low */
167 #define NAND_CTL_CLRCLE		4
168 /* Select the address latch by setting ALE to high */
169 #define NAND_CTL_SETALE		5
170 /* Deselect the address latch by setting ALE to low */
171 #define NAND_CTL_CLRALE		6
172 
173 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
174 {
175 	struct nand_chip *this = mtd_to_nand(mtd);
176 	struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
177 						chip);
178 
179 	switch (cmd) {
180 
181 	case NAND_CTL_SETCLE:
182 		this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
183 		break;
184 
185 	case NAND_CTL_CLRCLE:
186 		this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
187 		break;
188 
189 	case NAND_CTL_SETALE:
190 		this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
191 		break;
192 
193 	case NAND_CTL_CLRALE:
194 		this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
195 		/* FIXME: Nobody knows why this is necessary,
196 		 * but it works only that way */
197 		udelay(1);
198 		break;
199 
200 	case NAND_CTL_SETNCE:
201 		/* assert (force assert) chip enable */
202 		alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
203 		break;
204 
205 	case NAND_CTL_CLRNCE:
206 		/* deassert chip enable */
207 		alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
208 		break;
209 	}
210 
211 	this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W;
212 
213 	wmb(); /* Drain the writebuffer */
214 }
215 
216 int au1550_device_ready(struct nand_chip *this)
217 {
218 	return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
219 }
220 
221 /**
222  * au1550_select_chip - control -CE line
223  *	Forbid driving -CE manually permitting the NAND controller to do this.
224  *	Keeping -CE asserted during the whole sector reads interferes with the
225  *	NOR flash and PCMCIA drivers as it causes contention on the static bus.
226  *	We only have to hold -CE low for the NAND read commands since the flash
227  *	chip needs it to be asserted during chip not ready time but the NAND
228  *	controller keeps it released.
229  *
230  * @this:	NAND chip object
231  * @chip:	chipnumber to select, -1 for deselect
232  */
233 static void au1550_select_chip(struct nand_chip *this, int chip)
234 {
235 }
236 
237 /**
238  * au1550_command - Send command to NAND device
239  * @this:	NAND chip object
240  * @command:	the command to be sent
241  * @column:	the column address for this command, -1 if none
242  * @page_addr:	the page address for this command, -1 if none
243  */
244 static void au1550_command(struct nand_chip *this, unsigned command,
245 			   int column, int page_addr)
246 {
247 	struct mtd_info *mtd = nand_to_mtd(this);
248 	struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
249 						chip);
250 	int ce_override = 0, i;
251 	unsigned long flags = 0;
252 
253 	/* Begin command latch cycle */
254 	au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
255 	/*
256 	 * Write out the command to the device.
257 	 */
258 	if (command == NAND_CMD_SEQIN) {
259 		int readcmd;
260 
261 		if (column >= mtd->writesize) {
262 			/* OOB area */
263 			column -= mtd->writesize;
264 			readcmd = NAND_CMD_READOOB;
265 		} else if (column < 256) {
266 			/* First 256 bytes --> READ0 */
267 			readcmd = NAND_CMD_READ0;
268 		} else {
269 			column -= 256;
270 			readcmd = NAND_CMD_READ1;
271 		}
272 		ctx->write_byte(this, readcmd);
273 	}
274 	ctx->write_byte(this, command);
275 
276 	/* Set ALE and clear CLE to start address cycle */
277 	au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
278 
279 	if (column != -1 || page_addr != -1) {
280 		au1550_hwcontrol(mtd, NAND_CTL_SETALE);
281 
282 		/* Serially input address */
283 		if (column != -1) {
284 			/* Adjust columns for 16 bit buswidth */
285 			if (this->options & NAND_BUSWIDTH_16 &&
286 					!nand_opcode_8bits(command))
287 				column >>= 1;
288 			ctx->write_byte(this, column);
289 		}
290 		if (page_addr != -1) {
291 			ctx->write_byte(this, (u8)(page_addr & 0xff));
292 
293 			if (command == NAND_CMD_READ0 ||
294 			    command == NAND_CMD_READ1 ||
295 			    command == NAND_CMD_READOOB) {
296 				/*
297 				 * NAND controller will release -CE after
298 				 * the last address byte is written, so we'll
299 				 * have to forcibly assert it. No interrupts
300 				 * are allowed while we do this as we don't
301 				 * want the NOR flash or PCMCIA drivers to
302 				 * steal our precious bytes of data...
303 				 */
304 				ce_override = 1;
305 				local_irq_save(flags);
306 				au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
307 			}
308 
309 			ctx->write_byte(this, (u8)(page_addr >> 8));
310 
311 			if (this->options & NAND_ROW_ADDR_3)
312 				ctx->write_byte(this,
313 						((page_addr >> 16) & 0x0f));
314 		}
315 		/* Latch in address */
316 		au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
317 	}
318 
319 	/*
320 	 * Program and erase have their own busy handlers.
321 	 * Status and sequential in need no delay.
322 	 */
323 	switch (command) {
324 
325 	case NAND_CMD_PAGEPROG:
326 	case NAND_CMD_ERASE1:
327 	case NAND_CMD_ERASE2:
328 	case NAND_CMD_SEQIN:
329 	case NAND_CMD_STATUS:
330 		return;
331 
332 	case NAND_CMD_RESET:
333 		break;
334 
335 	case NAND_CMD_READ0:
336 	case NAND_CMD_READ1:
337 	case NAND_CMD_READOOB:
338 		/* Check if we're really driving -CE low (just in case) */
339 		if (unlikely(!ce_override))
340 			break;
341 
342 		/* Apply a short delay always to ensure that we do wait tWB. */
343 		ndelay(100);
344 		/* Wait for a chip to become ready... */
345 		for (i = this->legacy.chip_delay;
346 		     !this->legacy.dev_ready(this) && i > 0; --i)
347 			udelay(1);
348 
349 		/* Release -CE and re-enable interrupts. */
350 		au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
351 		local_irq_restore(flags);
352 		return;
353 	}
354 	/* Apply this short delay always to ensure that we do wait tWB. */
355 	ndelay(100);
356 
357 	while(!this->legacy.dev_ready(this));
358 }
359 
360 static int find_nand_cs(unsigned long nand_base)
361 {
362 	void __iomem *base =
363 			(void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
364 	unsigned long addr, staddr, start, mask, end;
365 	int i;
366 
367 	for (i = 0; i < 4; i++) {
368 		addr = 0x1000 + (i * 0x10);			/* CSx */
369 		staddr = __raw_readl(base + addr + 0x08);	/* STADDRx */
370 		/* figure out the decoded range of this CS */
371 		start = (staddr << 4) & 0xfffc0000;
372 		mask = (staddr << 18) & 0xfffc0000;
373 		end = (start | (start - 1)) & ~(start ^ mask);
374 		if ((nand_base >= start) && (nand_base < end))
375 			return i;
376 	}
377 
378 	return -ENODEV;
379 }
380 
381 static int au1550nd_probe(struct platform_device *pdev)
382 {
383 	struct au1550nd_platdata *pd;
384 	struct au1550nd_ctx *ctx;
385 	struct nand_chip *this;
386 	struct mtd_info *mtd;
387 	struct resource *r;
388 	int ret, cs;
389 
390 	pd = dev_get_platdata(&pdev->dev);
391 	if (!pd) {
392 		dev_err(&pdev->dev, "missing platform data\n");
393 		return -ENODEV;
394 	}
395 
396 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
397 	if (!ctx)
398 		return -ENOMEM;
399 
400 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
401 	if (!r) {
402 		dev_err(&pdev->dev, "no NAND memory resource\n");
403 		ret = -ENODEV;
404 		goto out1;
405 	}
406 	if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
407 		dev_err(&pdev->dev, "cannot claim NAND memory area\n");
408 		ret = -ENOMEM;
409 		goto out1;
410 	}
411 
412 	ctx->base = ioremap_nocache(r->start, 0x1000);
413 	if (!ctx->base) {
414 		dev_err(&pdev->dev, "cannot remap NAND memory area\n");
415 		ret = -ENODEV;
416 		goto out2;
417 	}
418 
419 	this = &ctx->chip;
420 	mtd = nand_to_mtd(this);
421 	mtd->dev.parent = &pdev->dev;
422 
423 	/* figure out which CS# r->start belongs to */
424 	cs = find_nand_cs(r->start);
425 	if (cs < 0) {
426 		dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
427 		ret = -ENODEV;
428 		goto out3;
429 	}
430 	ctx->cs = cs;
431 
432 	this->legacy.dev_ready = au1550_device_ready;
433 	this->legacy.select_chip = au1550_select_chip;
434 	this->legacy.cmdfunc = au1550_command;
435 
436 	/* 30 us command delay time */
437 	this->legacy.chip_delay = 30;
438 	this->ecc.mode = NAND_ECC_SOFT;
439 	this->ecc.algo = NAND_ECC_HAMMING;
440 
441 	if (pd->devwidth)
442 		this->options |= NAND_BUSWIDTH_16;
443 
444 	this->legacy.read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
445 	ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
446 	this->legacy.write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
447 	this->legacy.read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
448 
449 	ret = nand_scan(this, 1);
450 	if (ret) {
451 		dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
452 		goto out3;
453 	}
454 
455 	mtd_device_register(mtd, pd->parts, pd->num_parts);
456 
457 	platform_set_drvdata(pdev, ctx);
458 
459 	return 0;
460 
461 out3:
462 	iounmap(ctx->base);
463 out2:
464 	release_mem_region(r->start, resource_size(r));
465 out1:
466 	kfree(ctx);
467 	return ret;
468 }
469 
470 static int au1550nd_remove(struct platform_device *pdev)
471 {
472 	struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
473 	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474 
475 	nand_release(&ctx->chip);
476 	iounmap(ctx->base);
477 	release_mem_region(r->start, 0x1000);
478 	kfree(ctx);
479 	return 0;
480 }
481 
482 static struct platform_driver au1550nd_driver = {
483 	.driver = {
484 		.name	= "au1550-nand",
485 	},
486 	.probe		= au1550nd_probe,
487 	.remove		= au1550nd_remove,
488 };
489 
490 module_platform_driver(au1550nd_driver);
491 
492 MODULE_LICENSE("GPL");
493 MODULE_AUTHOR("Embedded Edge, LLC");
494 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
495