1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Arasan NAND Flash Controller Driver 4 * 5 * Copyright (C) 2014 - 2020 Xilinx, Inc. 6 * Author: 7 * Miquel Raynal <miquel.raynal@bootlin.com> 8 * Original work (fully rewritten): 9 * Punnaiah Choudary Kalluri <punnaia@xilinx.com> 10 * Naga Sureshkumar Relli <nagasure@xilinx.com> 11 */ 12 13 #include <linux/bch.h> 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/interrupt.h> 19 #include <linux/iopoll.h> 20 #include <linux/module.h> 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/partitions.h> 23 #include <linux/mtd/rawnand.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 28 #define PKT_REG 0x00 29 #define PKT_SIZE(x) FIELD_PREP(GENMASK(10, 0), (x)) 30 #define PKT_STEPS(x) FIELD_PREP(GENMASK(23, 12), (x)) 31 32 #define MEM_ADDR1_REG 0x04 33 34 #define MEM_ADDR2_REG 0x08 35 #define ADDR2_STRENGTH(x) FIELD_PREP(GENMASK(27, 25), (x)) 36 #define ADDR2_CS(x) FIELD_PREP(GENMASK(31, 30), (x)) 37 38 #define CMD_REG 0x0C 39 #define CMD_1(x) FIELD_PREP(GENMASK(7, 0), (x)) 40 #define CMD_2(x) FIELD_PREP(GENMASK(15, 8), (x)) 41 #define CMD_PAGE_SIZE(x) FIELD_PREP(GENMASK(25, 23), (x)) 42 #define CMD_DMA_ENABLE BIT(27) 43 #define CMD_NADDRS(x) FIELD_PREP(GENMASK(30, 28), (x)) 44 #define CMD_ECC_ENABLE BIT(31) 45 46 #define PROG_REG 0x10 47 #define PROG_PGRD BIT(0) 48 #define PROG_ERASE BIT(2) 49 #define PROG_STATUS BIT(3) 50 #define PROG_PGPROG BIT(4) 51 #define PROG_RDID BIT(6) 52 #define PROG_RDPARAM BIT(7) 53 #define PROG_RST BIT(8) 54 #define PROG_GET_FEATURE BIT(9) 55 #define PROG_SET_FEATURE BIT(10) 56 57 #define INTR_STS_EN_REG 0x14 58 #define INTR_SIG_EN_REG 0x18 59 #define INTR_STS_REG 0x1C 60 #define WRITE_READY BIT(0) 61 #define READ_READY BIT(1) 62 #define XFER_COMPLETE BIT(2) 63 #define DMA_BOUNDARY BIT(6) 64 #define EVENT_MASK GENMASK(7, 0) 65 66 #define READY_STS_REG 0x20 67 68 #define DMA_ADDR0_REG 0x50 69 #define DMA_ADDR1_REG 0x24 70 71 #define FLASH_STS_REG 0x28 72 73 #define DATA_PORT_REG 0x30 74 75 #define ECC_CONF_REG 0x34 76 #define ECC_CONF_COL(x) FIELD_PREP(GENMASK(15, 0), (x)) 77 #define ECC_CONF_LEN(x) FIELD_PREP(GENMASK(26, 16), (x)) 78 #define ECC_CONF_BCH_EN BIT(27) 79 80 #define ECC_ERR_CNT_REG 0x38 81 #define GET_PKT_ERR_CNT(x) FIELD_GET(GENMASK(7, 0), (x)) 82 #define GET_PAGE_ERR_CNT(x) FIELD_GET(GENMASK(16, 8), (x)) 83 84 #define ECC_SP_REG 0x3C 85 #define ECC_SP_CMD1(x) FIELD_PREP(GENMASK(7, 0), (x)) 86 #define ECC_SP_CMD2(x) FIELD_PREP(GENMASK(15, 8), (x)) 87 #define ECC_SP_ADDRS(x) FIELD_PREP(GENMASK(30, 28), (x)) 88 89 #define ECC_1ERR_CNT_REG 0x40 90 #define ECC_2ERR_CNT_REG 0x44 91 92 #define DATA_INTERFACE_REG 0x6C 93 #define DIFACE_SDR_MODE(x) FIELD_PREP(GENMASK(2, 0), (x)) 94 #define DIFACE_DDR_MODE(x) FIELD_PREP(GENMASK(5, 3), (X)) 95 #define DIFACE_SDR 0 96 #define DIFACE_NVDDR BIT(9) 97 98 #define ANFC_MAX_CS 2 99 #define ANFC_DFLT_TIMEOUT_US 1000000 100 #define ANFC_MAX_CHUNK_SIZE SZ_1M 101 #define ANFC_MAX_PARAM_SIZE SZ_4K 102 #define ANFC_MAX_STEPS SZ_2K 103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1) 104 #define ANFC_MAX_ADDR_CYC 5U 105 #define ANFC_RSVD_ECC_BYTES 21 106 107 #define ANFC_XLNX_SDR_DFLT_CORE_CLK 100000000 108 #define ANFC_XLNX_SDR_HS_CORE_CLK 80000000 109 110 /** 111 * struct anfc_op - Defines how to execute an operation 112 * @pkt_reg: Packet register 113 * @addr1_reg: Memory address 1 register 114 * @addr2_reg: Memory address 2 register 115 * @cmd_reg: Command register 116 * @prog_reg: Program register 117 * @steps: Number of "packets" to read/write 118 * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin 119 * @len: Data transfer length 120 * @read: Data transfer direction from the controller point of view 121 * @buf: Data buffer 122 */ 123 struct anfc_op { 124 u32 pkt_reg; 125 u32 addr1_reg; 126 u32 addr2_reg; 127 u32 cmd_reg; 128 u32 prog_reg; 129 int steps; 130 unsigned int rdy_timeout_ms; 131 unsigned int len; 132 bool read; 133 u8 *buf; 134 }; 135 136 /** 137 * struct anand - Defines the NAND chip related information 138 * @node: Used to store NAND chips into a list 139 * @chip: NAND chip information structure 140 * @cs: Chip select line 141 * @rb: Ready-busy line 142 * @page_sz: Register value of the page_sz field to use 143 * @clk: Expected clock frequency to use 144 * @timings: Data interface timing mode to use 145 * @ecc_conf: Hardware ECC configuration value 146 * @strength: Register value of the ECC strength 147 * @raddr_cycles: Row address cycle information 148 * @caddr_cycles: Column address cycle information 149 * @ecc_bits: Exact number of ECC bits per syndrome 150 * @ecc_total: Total number of ECC bytes 151 * @errloc: Array of errors located with soft BCH 152 * @hw_ecc: Buffer to store syndromes computed by hardware 153 * @bch: BCH structure 154 */ 155 struct anand { 156 struct list_head node; 157 struct nand_chip chip; 158 unsigned int cs; 159 unsigned int rb; 160 unsigned int page_sz; 161 unsigned long clk; 162 u32 timings; 163 u32 ecc_conf; 164 u32 strength; 165 u16 raddr_cycles; 166 u16 caddr_cycles; 167 unsigned int ecc_bits; 168 unsigned int ecc_total; 169 unsigned int *errloc; 170 u8 *hw_ecc; 171 struct bch_control *bch; 172 }; 173 174 /** 175 * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance 176 * @dev: Pointer to the device structure 177 * @base: Remapped register area 178 * @controller_clk: Pointer to the system clock 179 * @bus_clk: Pointer to the flash clock 180 * @controller: Base controller structure 181 * @chips: List of all NAND chips attached to the controller 182 * @assigned_cs: Bitmask describing already assigned CS lines 183 * @cur_clk: Current clock rate 184 */ 185 struct arasan_nfc { 186 struct device *dev; 187 void __iomem *base; 188 struct clk *controller_clk; 189 struct clk *bus_clk; 190 struct nand_controller controller; 191 struct list_head chips; 192 unsigned long assigned_cs; 193 unsigned int cur_clk; 194 }; 195 196 static struct anand *to_anand(struct nand_chip *nand) 197 { 198 return container_of(nand, struct anand, chip); 199 } 200 201 static struct arasan_nfc *to_anfc(struct nand_controller *ctrl) 202 { 203 return container_of(ctrl, struct arasan_nfc, controller); 204 } 205 206 static int anfc_wait_for_event(struct arasan_nfc *nfc, unsigned int event) 207 { 208 u32 val; 209 int ret; 210 211 ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val, 212 val & event, 0, 213 ANFC_DFLT_TIMEOUT_US); 214 if (ret) { 215 dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event); 216 return -ETIMEDOUT; 217 } 218 219 writel_relaxed(event, nfc->base + INTR_STS_REG); 220 221 return 0; 222 } 223 224 static int anfc_wait_for_rb(struct arasan_nfc *nfc, struct nand_chip *chip, 225 unsigned int timeout_ms) 226 { 227 struct anand *anand = to_anand(chip); 228 u32 val; 229 int ret; 230 231 /* There is no R/B interrupt, we must poll a register */ 232 ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val, 233 val & BIT(anand->rb), 234 1, timeout_ms * 1000); 235 if (ret) { 236 dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n", 237 readl_relaxed(nfc->base + READY_STS_REG)); 238 return -ETIMEDOUT; 239 } 240 241 return 0; 242 } 243 244 static void anfc_trigger_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op) 245 { 246 writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG); 247 writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG); 248 writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG); 249 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG); 250 writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG); 251 } 252 253 static int anfc_pkt_len_config(unsigned int len, unsigned int *steps, 254 unsigned int *pktsize) 255 { 256 unsigned int nb, sz; 257 258 for (nb = 1; nb < ANFC_MAX_STEPS; nb *= 2) { 259 sz = len / nb; 260 if (sz <= ANFC_MAX_PKT_SIZE) 261 break; 262 } 263 264 if (sz * nb != len) 265 return -ENOTSUPP; 266 267 if (steps) 268 *steps = nb; 269 270 if (pktsize) 271 *pktsize = sz; 272 273 return 0; 274 } 275 276 /* 277 * When using the embedded hardware ECC engine, the controller is in charge of 278 * feeding the engine with, first, the ECC residue present in the data array. 279 * A typical read operation is: 280 * 1/ Assert the read operation by sending the relevant command/address cycles 281 * but targeting the column of the first ECC bytes in the OOB area instead of 282 * the main data directly. 283 * 2/ After having read the relevant number of ECC bytes, the controller uses 284 * the RNDOUT/RNDSTART commands which are set into the "ECC Spare Command 285 * Register" to move the pointer back at the beginning of the main data. 286 * 3/ It will read the content of the main area for a given size (pktsize) and 287 * will feed the ECC engine with this buffer again. 288 * 4/ The ECC engine derives the ECC bytes for the given data and compare them 289 * with the ones already received. It eventually trigger status flags and 290 * then set the "Buffer Read Ready" flag. 291 * 5/ The corrected data is then available for reading from the data port 292 * register. 293 * 294 * The hardware BCH ECC engine is known to be inconstent in BCH mode and never 295 * reports uncorrectable errors. Because of this bug, we have to use the 296 * software BCH implementation in the read path. 297 */ 298 static int anfc_read_page_hw_ecc(struct nand_chip *chip, u8 *buf, 299 int oob_required, int page) 300 { 301 struct arasan_nfc *nfc = to_anfc(chip->controller); 302 struct mtd_info *mtd = nand_to_mtd(chip); 303 struct anand *anand = to_anand(chip); 304 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0); 305 unsigned int max_bitflips = 0; 306 dma_addr_t dma_addr; 307 int step, ret; 308 struct anfc_op nfc_op = { 309 .pkt_reg = 310 PKT_SIZE(chip->ecc.size) | 311 PKT_STEPS(chip->ecc.steps), 312 .addr1_reg = 313 (page & 0xFF) << (8 * (anand->caddr_cycles)) | 314 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))), 315 .addr2_reg = 316 ((page >> 16) & 0xFF) | 317 ADDR2_STRENGTH(anand->strength) | 318 ADDR2_CS(anand->cs), 319 .cmd_reg = 320 CMD_1(NAND_CMD_READ0) | 321 CMD_2(NAND_CMD_READSTART) | 322 CMD_PAGE_SIZE(anand->page_sz) | 323 CMD_DMA_ENABLE | 324 CMD_NADDRS(anand->caddr_cycles + 325 anand->raddr_cycles), 326 .prog_reg = PROG_PGRD, 327 }; 328 329 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE); 330 if (dma_mapping_error(nfc->dev, dma_addr)) { 331 dev_err(nfc->dev, "Buffer mapping error"); 332 return -EIO; 333 } 334 335 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG); 336 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG); 337 338 anfc_trigger_op(nfc, &nfc_op); 339 340 ret = anfc_wait_for_event(nfc, XFER_COMPLETE); 341 dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE); 342 if (ret) { 343 dev_err(nfc->dev, "Error reading page %d\n", page); 344 return ret; 345 } 346 347 /* Store the raw OOB bytes as well */ 348 ret = nand_change_read_column_op(chip, mtd->writesize, chip->oob_poi, 349 mtd->oobsize, 0); 350 if (ret) 351 return ret; 352 353 /* 354 * For each step, compute by softare the BCH syndrome over the raw data. 355 * Compare the theoretical amount of errors and compare with the 356 * hardware engine feedback. 357 */ 358 for (step = 0; step < chip->ecc.steps; step++) { 359 u8 *raw_buf = &buf[step * chip->ecc.size]; 360 unsigned int bit, byte; 361 int bf, i; 362 363 /* Extract the syndrome, it is not necessarily aligned */ 364 memset(anand->hw_ecc, 0, chip->ecc.bytes); 365 nand_extract_bits(anand->hw_ecc, 0, 366 &chip->oob_poi[mtd->oobsize - anand->ecc_total], 367 anand->ecc_bits * step, anand->ecc_bits); 368 369 bf = bch_decode(anand->bch, raw_buf, chip->ecc.size, 370 anand->hw_ecc, NULL, NULL, anand->errloc); 371 if (!bf) { 372 continue; 373 } else if (bf > 0) { 374 for (i = 0; i < bf; i++) { 375 /* Only correct the data, not the syndrome */ 376 if (anand->errloc[i] < (chip->ecc.size * 8)) { 377 bit = BIT(anand->errloc[i] & 7); 378 byte = anand->errloc[i] >> 3; 379 raw_buf[byte] ^= bit; 380 } 381 } 382 383 mtd->ecc_stats.corrected += bf; 384 max_bitflips = max_t(unsigned int, max_bitflips, bf); 385 386 continue; 387 } 388 389 bf = nand_check_erased_ecc_chunk(raw_buf, chip->ecc.size, 390 NULL, 0, NULL, 0, 391 chip->ecc.strength); 392 if (bf > 0) { 393 mtd->ecc_stats.corrected += bf; 394 max_bitflips = max_t(unsigned int, max_bitflips, bf); 395 memset(raw_buf, 0xFF, chip->ecc.size); 396 } else if (bf < 0) { 397 mtd->ecc_stats.failed++; 398 } 399 } 400 401 return 0; 402 } 403 404 static int anfc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf, 405 int oob_required, int page) 406 { 407 struct anand *anand = to_anand(chip); 408 struct arasan_nfc *nfc = to_anfc(chip->controller); 409 struct mtd_info *mtd = nand_to_mtd(chip); 410 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0); 411 dma_addr_t dma_addr; 412 int ret; 413 struct anfc_op nfc_op = { 414 .pkt_reg = 415 PKT_SIZE(chip->ecc.size) | 416 PKT_STEPS(chip->ecc.steps), 417 .addr1_reg = 418 (page & 0xFF) << (8 * (anand->caddr_cycles)) | 419 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))), 420 .addr2_reg = 421 ((page >> 16) & 0xFF) | 422 ADDR2_STRENGTH(anand->strength) | 423 ADDR2_CS(anand->cs), 424 .cmd_reg = 425 CMD_1(NAND_CMD_SEQIN) | 426 CMD_2(NAND_CMD_PAGEPROG) | 427 CMD_PAGE_SIZE(anand->page_sz) | 428 CMD_DMA_ENABLE | 429 CMD_NADDRS(anand->caddr_cycles + 430 anand->raddr_cycles) | 431 CMD_ECC_ENABLE, 432 .prog_reg = PROG_PGPROG, 433 }; 434 435 writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG); 436 writel_relaxed(ECC_SP_CMD1(NAND_CMD_RNDIN) | 437 ECC_SP_ADDRS(anand->caddr_cycles), 438 nfc->base + ECC_SP_REG); 439 440 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE); 441 if (dma_mapping_error(nfc->dev, dma_addr)) { 442 dev_err(nfc->dev, "Buffer mapping error"); 443 return -EIO; 444 } 445 446 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG); 447 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG); 448 449 anfc_trigger_op(nfc, &nfc_op); 450 ret = anfc_wait_for_event(nfc, XFER_COMPLETE); 451 dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE); 452 if (ret) { 453 dev_err(nfc->dev, "Error writing page %d\n", page); 454 return ret; 455 } 456 457 /* Spare data is not protected */ 458 if (oob_required) 459 ret = nand_write_oob_std(chip, page); 460 461 return ret; 462 } 463 464 /* NAND framework ->exec_op() hooks and related helpers */ 465 static int anfc_parse_instructions(struct nand_chip *chip, 466 const struct nand_subop *subop, 467 struct anfc_op *nfc_op) 468 { 469 struct anand *anand = to_anand(chip); 470 const struct nand_op_instr *instr = NULL; 471 bool first_cmd = true; 472 unsigned int op_id; 473 int ret, i; 474 475 memset(nfc_op, 0, sizeof(*nfc_op)); 476 nfc_op->addr2_reg = ADDR2_CS(anand->cs); 477 nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz); 478 479 for (op_id = 0; op_id < subop->ninstrs; op_id++) { 480 unsigned int offset, naddrs, pktsize; 481 const u8 *addrs; 482 u8 *buf; 483 484 instr = &subop->instrs[op_id]; 485 486 switch (instr->type) { 487 case NAND_OP_CMD_INSTR: 488 if (first_cmd) 489 nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode); 490 else 491 nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode); 492 493 first_cmd = false; 494 break; 495 496 case NAND_OP_ADDR_INSTR: 497 offset = nand_subop_get_addr_start_off(subop, op_id); 498 naddrs = nand_subop_get_num_addr_cyc(subop, op_id); 499 addrs = &instr->ctx.addr.addrs[offset]; 500 nfc_op->cmd_reg |= CMD_NADDRS(naddrs); 501 502 for (i = 0; i < min(ANFC_MAX_ADDR_CYC, naddrs); i++) { 503 if (i < 4) 504 nfc_op->addr1_reg |= (u32)addrs[i] << i * 8; 505 else 506 nfc_op->addr2_reg |= addrs[i]; 507 } 508 509 break; 510 case NAND_OP_DATA_IN_INSTR: 511 nfc_op->read = true; 512 fallthrough; 513 case NAND_OP_DATA_OUT_INSTR: 514 offset = nand_subop_get_data_start_off(subop, op_id); 515 buf = instr->ctx.data.buf.in; 516 nfc_op->buf = &buf[offset]; 517 nfc_op->len = nand_subop_get_data_len(subop, op_id); 518 ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps, 519 &pktsize); 520 if (ret) 521 return ret; 522 523 /* 524 * Number of DATA cycles must be aligned on 4, this 525 * means the controller might read/write more than 526 * requested. This is harmless most of the time as extra 527 * DATA are discarded in the write path and read pointer 528 * adjusted in the read path. 529 * 530 * FIXME: The core should mark operations where 531 * reading/writing more is allowed so the exec_op() 532 * implementation can take the right decision when the 533 * alignment constraint is not met: adjust the number of 534 * DATA cycles when it's allowed, reject the operation 535 * otherwise. 536 */ 537 nfc_op->pkt_reg |= PKT_SIZE(round_up(pktsize, 4)) | 538 PKT_STEPS(nfc_op->steps); 539 break; 540 case NAND_OP_WAITRDY_INSTR: 541 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; 542 break; 543 } 544 } 545 546 return 0; 547 } 548 549 static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op) 550 { 551 unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps; 552 unsigned int last_len = nfc_op->len % 4; 553 unsigned int offset, dir; 554 u8 *buf = nfc_op->buf; 555 int ret, i; 556 557 for (i = 0; i < nfc_op->steps; i++) { 558 dir = nfc_op->read ? READ_READY : WRITE_READY; 559 ret = anfc_wait_for_event(nfc, dir); 560 if (ret) { 561 dev_err(nfc->dev, "PIO %s ready signal not received\n", 562 nfc_op->read ? "Read" : "Write"); 563 return ret; 564 } 565 566 offset = i * (dwords * 4); 567 if (nfc_op->read) 568 ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset], 569 dwords); 570 else 571 iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset], 572 dwords); 573 } 574 575 if (last_len) { 576 u32 remainder; 577 578 offset = nfc_op->len - last_len; 579 580 if (nfc_op->read) { 581 remainder = readl_relaxed(nfc->base + DATA_PORT_REG); 582 memcpy(&buf[offset], &remainder, last_len); 583 } else { 584 memcpy(&remainder, &buf[offset], last_len); 585 writel_relaxed(remainder, nfc->base + DATA_PORT_REG); 586 } 587 } 588 589 return anfc_wait_for_event(nfc, XFER_COMPLETE); 590 } 591 592 static int anfc_misc_data_type_exec(struct nand_chip *chip, 593 const struct nand_subop *subop, 594 u32 prog_reg) 595 { 596 struct arasan_nfc *nfc = to_anfc(chip->controller); 597 struct anfc_op nfc_op = {}; 598 int ret; 599 600 ret = anfc_parse_instructions(chip, subop, &nfc_op); 601 if (ret) 602 return ret; 603 604 nfc_op.prog_reg = prog_reg; 605 anfc_trigger_op(nfc, &nfc_op); 606 607 if (nfc_op.rdy_timeout_ms) { 608 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms); 609 if (ret) 610 return ret; 611 } 612 613 return anfc_rw_pio_op(nfc, &nfc_op); 614 } 615 616 static int anfc_param_read_type_exec(struct nand_chip *chip, 617 const struct nand_subop *subop) 618 { 619 return anfc_misc_data_type_exec(chip, subop, PROG_RDPARAM); 620 } 621 622 static int anfc_data_read_type_exec(struct nand_chip *chip, 623 const struct nand_subop *subop) 624 { 625 return anfc_misc_data_type_exec(chip, subop, PROG_PGRD); 626 } 627 628 static int anfc_param_write_type_exec(struct nand_chip *chip, 629 const struct nand_subop *subop) 630 { 631 return anfc_misc_data_type_exec(chip, subop, PROG_SET_FEATURE); 632 } 633 634 static int anfc_data_write_type_exec(struct nand_chip *chip, 635 const struct nand_subop *subop) 636 { 637 return anfc_misc_data_type_exec(chip, subop, PROG_PGPROG); 638 } 639 640 static int anfc_misc_zerolen_type_exec(struct nand_chip *chip, 641 const struct nand_subop *subop, 642 u32 prog_reg) 643 { 644 struct arasan_nfc *nfc = to_anfc(chip->controller); 645 struct anfc_op nfc_op = {}; 646 int ret; 647 648 ret = anfc_parse_instructions(chip, subop, &nfc_op); 649 if (ret) 650 return ret; 651 652 nfc_op.prog_reg = prog_reg; 653 anfc_trigger_op(nfc, &nfc_op); 654 655 ret = anfc_wait_for_event(nfc, XFER_COMPLETE); 656 if (ret) 657 return ret; 658 659 if (nfc_op.rdy_timeout_ms) 660 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms); 661 662 return ret; 663 } 664 665 static int anfc_status_type_exec(struct nand_chip *chip, 666 const struct nand_subop *subop) 667 { 668 struct arasan_nfc *nfc = to_anfc(chip->controller); 669 u32 tmp; 670 int ret; 671 672 /* See anfc_check_op() for details about this constraint */ 673 if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS) 674 return -ENOTSUPP; 675 676 ret = anfc_misc_zerolen_type_exec(chip, subop, PROG_STATUS); 677 if (ret) 678 return ret; 679 680 tmp = readl_relaxed(nfc->base + FLASH_STS_REG); 681 memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1); 682 683 return 0; 684 } 685 686 static int anfc_reset_type_exec(struct nand_chip *chip, 687 const struct nand_subop *subop) 688 { 689 return anfc_misc_zerolen_type_exec(chip, subop, PROG_RST); 690 } 691 692 static int anfc_erase_type_exec(struct nand_chip *chip, 693 const struct nand_subop *subop) 694 { 695 return anfc_misc_zerolen_type_exec(chip, subop, PROG_ERASE); 696 } 697 698 static int anfc_wait_type_exec(struct nand_chip *chip, 699 const struct nand_subop *subop) 700 { 701 struct arasan_nfc *nfc = to_anfc(chip->controller); 702 struct anfc_op nfc_op = {}; 703 int ret; 704 705 ret = anfc_parse_instructions(chip, subop, &nfc_op); 706 if (ret) 707 return ret; 708 709 return anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms); 710 } 711 712 static const struct nand_op_parser anfc_op_parser = NAND_OP_PARSER( 713 NAND_OP_PARSER_PATTERN( 714 anfc_param_read_type_exec, 715 NAND_OP_PARSER_PAT_CMD_ELEM(false), 716 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC), 717 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 718 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)), 719 NAND_OP_PARSER_PATTERN( 720 anfc_param_write_type_exec, 721 NAND_OP_PARSER_PAT_CMD_ELEM(false), 722 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC), 723 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_PARAM_SIZE)), 724 NAND_OP_PARSER_PATTERN( 725 anfc_data_read_type_exec, 726 NAND_OP_PARSER_PAT_CMD_ELEM(false), 727 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC), 728 NAND_OP_PARSER_PAT_CMD_ELEM(false), 729 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 730 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, ANFC_MAX_CHUNK_SIZE)), 731 NAND_OP_PARSER_PATTERN( 732 anfc_data_write_type_exec, 733 NAND_OP_PARSER_PAT_CMD_ELEM(false), 734 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC), 735 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_CHUNK_SIZE), 736 NAND_OP_PARSER_PAT_CMD_ELEM(false)), 737 NAND_OP_PARSER_PATTERN( 738 anfc_reset_type_exec, 739 NAND_OP_PARSER_PAT_CMD_ELEM(false), 740 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 741 NAND_OP_PARSER_PATTERN( 742 anfc_erase_type_exec, 743 NAND_OP_PARSER_PAT_CMD_ELEM(false), 744 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC), 745 NAND_OP_PARSER_PAT_CMD_ELEM(false), 746 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 747 NAND_OP_PARSER_PATTERN( 748 anfc_status_type_exec, 749 NAND_OP_PARSER_PAT_CMD_ELEM(false), 750 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)), 751 NAND_OP_PARSER_PATTERN( 752 anfc_wait_type_exec, 753 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 754 ); 755 756 static int anfc_select_target(struct nand_chip *chip, int target) 757 { 758 struct anand *anand = to_anand(chip); 759 struct arasan_nfc *nfc = to_anfc(chip->controller); 760 int ret; 761 762 /* Update the controller timings and the potential ECC configuration */ 763 writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG); 764 765 /* Update clock frequency */ 766 if (nfc->cur_clk != anand->clk) { 767 clk_disable_unprepare(nfc->controller_clk); 768 ret = clk_set_rate(nfc->controller_clk, anand->clk); 769 if (ret) { 770 dev_err(nfc->dev, "Failed to change clock rate\n"); 771 return ret; 772 } 773 774 ret = clk_prepare_enable(nfc->controller_clk); 775 if (ret) { 776 dev_err(nfc->dev, 777 "Failed to re-enable the controller clock\n"); 778 return ret; 779 } 780 781 nfc->cur_clk = anand->clk; 782 } 783 784 return 0; 785 } 786 787 static int anfc_check_op(struct nand_chip *chip, 788 const struct nand_operation *op) 789 { 790 const struct nand_op_instr *instr; 791 int op_id; 792 793 /* 794 * The controller abstracts all the NAND operations and do not support 795 * data only operations. 796 * 797 * TODO: The nand_op_parser framework should be extended to 798 * support custom checks on DATA instructions. 799 */ 800 for (op_id = 0; op_id < op->ninstrs; op_id++) { 801 instr = &op->instrs[op_id]; 802 803 switch (instr->type) { 804 case NAND_OP_ADDR_INSTR: 805 if (instr->ctx.addr.naddrs > ANFC_MAX_ADDR_CYC) 806 return -ENOTSUPP; 807 808 break; 809 case NAND_OP_DATA_IN_INSTR: 810 case NAND_OP_DATA_OUT_INSTR: 811 if (instr->ctx.data.len > ANFC_MAX_CHUNK_SIZE) 812 return -ENOTSUPP; 813 814 if (anfc_pkt_len_config(instr->ctx.data.len, 0, 0)) 815 return -ENOTSUPP; 816 817 break; 818 default: 819 break; 820 } 821 } 822 823 /* 824 * The controller does not allow to proceed with a CMD+DATA_IN cycle 825 * manually on the bus by reading data from the data register. Instead, 826 * the controller abstract a status read operation with its own status 827 * register after ordering a read status operation. Hence, we cannot 828 * support any CMD+DATA_IN operation other than a READ STATUS. 829 * 830 * TODO: The nand_op_parser() framework should be extended to describe 831 * fixed patterns instead of open-coding this check here. 832 */ 833 if (op->ninstrs == 2 && 834 op->instrs[0].type == NAND_OP_CMD_INSTR && 835 op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS && 836 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) 837 return -ENOTSUPP; 838 839 return nand_op_parser_exec_op(chip, &anfc_op_parser, op, true); 840 } 841 842 static int anfc_exec_op(struct nand_chip *chip, 843 const struct nand_operation *op, 844 bool check_only) 845 { 846 int ret; 847 848 if (check_only) 849 return anfc_check_op(chip, op); 850 851 ret = anfc_select_target(chip, op->cs); 852 if (ret) 853 return ret; 854 855 return nand_op_parser_exec_op(chip, &anfc_op_parser, op, check_only); 856 } 857 858 static int anfc_setup_interface(struct nand_chip *chip, int target, 859 const struct nand_interface_config *conf) 860 { 861 struct anand *anand = to_anand(chip); 862 struct arasan_nfc *nfc = to_anfc(chip->controller); 863 struct device_node *np = nfc->dev->of_node; 864 865 if (target < 0) 866 return 0; 867 868 anand->timings = DIFACE_SDR | DIFACE_SDR_MODE(conf->timings.mode); 869 anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; 870 871 /* 872 * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work 873 * with f > 90MHz (default clock is 100MHz) but signals are unstable 874 * with higher modes. Hence we decrease a little bit the clock rate to 875 * 80MHz when using modes 2-5 with this SoC. 876 */ 877 if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") && 878 conf->timings.mode >= 2) 879 anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK; 880 881 return 0; 882 } 883 884 static int anfc_calc_hw_ecc_bytes(int step_size, int strength) 885 { 886 unsigned int bch_gf_mag, ecc_bits; 887 888 switch (step_size) { 889 case SZ_512: 890 bch_gf_mag = 13; 891 break; 892 case SZ_1K: 893 bch_gf_mag = 14; 894 break; 895 default: 896 return -EINVAL; 897 } 898 899 ecc_bits = bch_gf_mag * strength; 900 901 return DIV_ROUND_UP(ecc_bits, 8); 902 } 903 904 static const int anfc_hw_ecc_512_strengths[] = {4, 8, 12}; 905 906 static const int anfc_hw_ecc_1024_strengths[] = {24}; 907 908 static const struct nand_ecc_step_info anfc_hw_ecc_step_infos[] = { 909 { 910 .stepsize = SZ_512, 911 .strengths = anfc_hw_ecc_512_strengths, 912 .nstrengths = ARRAY_SIZE(anfc_hw_ecc_512_strengths), 913 }, 914 { 915 .stepsize = SZ_1K, 916 .strengths = anfc_hw_ecc_1024_strengths, 917 .nstrengths = ARRAY_SIZE(anfc_hw_ecc_1024_strengths), 918 }, 919 }; 920 921 static const struct nand_ecc_caps anfc_hw_ecc_caps = { 922 .stepinfos = anfc_hw_ecc_step_infos, 923 .nstepinfos = ARRAY_SIZE(anfc_hw_ecc_step_infos), 924 .calc_ecc_bytes = anfc_calc_hw_ecc_bytes, 925 }; 926 927 static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc, 928 struct nand_chip *chip) 929 { 930 struct anand *anand = to_anand(chip); 931 struct mtd_info *mtd = nand_to_mtd(chip); 932 struct nand_ecc_ctrl *ecc = &chip->ecc; 933 unsigned int bch_prim_poly = 0, bch_gf_mag = 0, ecc_offset; 934 int ret; 935 936 switch (mtd->writesize) { 937 case SZ_512: 938 case SZ_2K: 939 case SZ_4K: 940 case SZ_8K: 941 case SZ_16K: 942 break; 943 default: 944 dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize); 945 return -EINVAL; 946 } 947 948 ret = nand_ecc_choose_conf(chip, &anfc_hw_ecc_caps, mtd->oobsize); 949 if (ret) 950 return ret; 951 952 switch (ecc->strength) { 953 case 12: 954 anand->strength = 0x1; 955 break; 956 case 8: 957 anand->strength = 0x2; 958 break; 959 case 4: 960 anand->strength = 0x3; 961 break; 962 case 24: 963 anand->strength = 0x4; 964 break; 965 default: 966 dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength); 967 return -EINVAL; 968 } 969 970 switch (ecc->size) { 971 case SZ_512: 972 bch_gf_mag = 13; 973 bch_prim_poly = 0x201b; 974 break; 975 case SZ_1K: 976 bch_gf_mag = 14; 977 bch_prim_poly = 0x4443; 978 break; 979 default: 980 dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength); 981 return -EINVAL; 982 } 983 984 mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); 985 986 ecc->steps = mtd->writesize / ecc->size; 987 ecc->algo = NAND_ECC_ALGO_BCH; 988 anand->ecc_bits = bch_gf_mag * ecc->strength; 989 ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8); 990 anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8); 991 ecc_offset = mtd->writesize + mtd->oobsize - anand->ecc_total; 992 anand->ecc_conf = ECC_CONF_COL(ecc_offset) | 993 ECC_CONF_LEN(anand->ecc_total) | 994 ECC_CONF_BCH_EN; 995 996 anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength, 997 sizeof(*anand->errloc), GFP_KERNEL); 998 if (!anand->errloc) 999 return -ENOMEM; 1000 1001 anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL); 1002 if (!anand->hw_ecc) 1003 return -ENOMEM; 1004 1005 /* Enforce bit swapping to fit the hardware */ 1006 anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true); 1007 if (!anand->bch) 1008 return -EINVAL; 1009 1010 ecc->read_page = anfc_read_page_hw_ecc; 1011 ecc->write_page = anfc_write_page_hw_ecc; 1012 1013 return 0; 1014 } 1015 1016 static int anfc_attach_chip(struct nand_chip *chip) 1017 { 1018 struct anand *anand = to_anand(chip); 1019 struct arasan_nfc *nfc = to_anfc(chip->controller); 1020 struct mtd_info *mtd = nand_to_mtd(chip); 1021 int ret = 0; 1022 1023 if (mtd->writesize <= SZ_512) 1024 anand->caddr_cycles = 1; 1025 else 1026 anand->caddr_cycles = 2; 1027 1028 if (chip->options & NAND_ROW_ADDR_3) 1029 anand->raddr_cycles = 3; 1030 else 1031 anand->raddr_cycles = 2; 1032 1033 switch (mtd->writesize) { 1034 case 512: 1035 anand->page_sz = 0; 1036 break; 1037 case 1024: 1038 anand->page_sz = 5; 1039 break; 1040 case 2048: 1041 anand->page_sz = 1; 1042 break; 1043 case 4096: 1044 anand->page_sz = 2; 1045 break; 1046 case 8192: 1047 anand->page_sz = 3; 1048 break; 1049 case 16384: 1050 anand->page_sz = 4; 1051 break; 1052 default: 1053 return -EINVAL; 1054 } 1055 1056 /* These hooks are valid for all ECC providers */ 1057 chip->ecc.read_page_raw = nand_monolithic_read_page_raw; 1058 chip->ecc.write_page_raw = nand_monolithic_write_page_raw; 1059 1060 switch (chip->ecc.engine_type) { 1061 case NAND_ECC_ENGINE_TYPE_NONE: 1062 case NAND_ECC_ENGINE_TYPE_SOFT: 1063 case NAND_ECC_ENGINE_TYPE_ON_DIE: 1064 break; 1065 case NAND_ECC_ENGINE_TYPE_ON_HOST: 1066 ret = anfc_init_hw_ecc_controller(nfc, chip); 1067 break; 1068 default: 1069 dev_err(nfc->dev, "Unsupported ECC mode: %d\n", 1070 chip->ecc.engine_type); 1071 return -EINVAL; 1072 } 1073 1074 return ret; 1075 } 1076 1077 static void anfc_detach_chip(struct nand_chip *chip) 1078 { 1079 struct anand *anand = to_anand(chip); 1080 1081 if (anand->bch) 1082 bch_free(anand->bch); 1083 } 1084 1085 static const struct nand_controller_ops anfc_ops = { 1086 .exec_op = anfc_exec_op, 1087 .setup_interface = anfc_setup_interface, 1088 .attach_chip = anfc_attach_chip, 1089 .detach_chip = anfc_detach_chip, 1090 }; 1091 1092 static int anfc_chip_init(struct arasan_nfc *nfc, struct device_node *np) 1093 { 1094 struct anand *anand; 1095 struct nand_chip *chip; 1096 struct mtd_info *mtd; 1097 int cs, rb, ret; 1098 1099 anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL); 1100 if (!anand) 1101 return -ENOMEM; 1102 1103 /* We do not support multiple CS per chip yet */ 1104 if (of_property_count_elems_of_size(np, "reg", sizeof(u32)) != 1) { 1105 dev_err(nfc->dev, "Invalid reg property\n"); 1106 return -EINVAL; 1107 } 1108 1109 ret = of_property_read_u32(np, "reg", &cs); 1110 if (ret) 1111 return ret; 1112 1113 ret = of_property_read_u32(np, "nand-rb", &rb); 1114 if (ret) 1115 return ret; 1116 1117 if (cs >= ANFC_MAX_CS || rb >= ANFC_MAX_CS) { 1118 dev_err(nfc->dev, "Wrong CS %d or RB %d\n", cs, rb); 1119 return -EINVAL; 1120 } 1121 1122 if (test_and_set_bit(cs, &nfc->assigned_cs)) { 1123 dev_err(nfc->dev, "Already assigned CS %d\n", cs); 1124 return -EINVAL; 1125 } 1126 1127 anand->cs = cs; 1128 anand->rb = rb; 1129 1130 chip = &anand->chip; 1131 mtd = nand_to_mtd(chip); 1132 mtd->dev.parent = nfc->dev; 1133 chip->controller = &nfc->controller; 1134 chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | 1135 NAND_USES_DMA; 1136 1137 nand_set_flash_node(chip, np); 1138 if (!mtd->name) { 1139 dev_err(nfc->dev, "NAND label property is mandatory\n"); 1140 return -EINVAL; 1141 } 1142 1143 ret = nand_scan(chip, 1); 1144 if (ret) { 1145 dev_err(nfc->dev, "Scan operation failed\n"); 1146 return ret; 1147 } 1148 1149 ret = mtd_device_register(mtd, NULL, 0); 1150 if (ret) { 1151 nand_cleanup(chip); 1152 return ret; 1153 } 1154 1155 list_add_tail(&anand->node, &nfc->chips); 1156 1157 return 0; 1158 } 1159 1160 static void anfc_chips_cleanup(struct arasan_nfc *nfc) 1161 { 1162 struct anand *anand, *tmp; 1163 struct nand_chip *chip; 1164 int ret; 1165 1166 list_for_each_entry_safe(anand, tmp, &nfc->chips, node) { 1167 chip = &anand->chip; 1168 ret = mtd_device_unregister(nand_to_mtd(chip)); 1169 WARN_ON(ret); 1170 nand_cleanup(chip); 1171 list_del(&anand->node); 1172 } 1173 } 1174 1175 static int anfc_chips_init(struct arasan_nfc *nfc) 1176 { 1177 struct device_node *np = nfc->dev->of_node, *nand_np; 1178 int nchips = of_get_child_count(np); 1179 int ret; 1180 1181 if (!nchips || nchips > ANFC_MAX_CS) { 1182 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n", 1183 nchips); 1184 return -EINVAL; 1185 } 1186 1187 for_each_child_of_node(np, nand_np) { 1188 ret = anfc_chip_init(nfc, nand_np); 1189 if (ret) { 1190 of_node_put(nand_np); 1191 anfc_chips_cleanup(nfc); 1192 break; 1193 } 1194 } 1195 1196 return ret; 1197 } 1198 1199 static void anfc_reset(struct arasan_nfc *nfc) 1200 { 1201 /* Disable interrupt signals */ 1202 writel_relaxed(0, nfc->base + INTR_SIG_EN_REG); 1203 1204 /* Enable interrupt status */ 1205 writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG); 1206 } 1207 1208 static int anfc_probe(struct platform_device *pdev) 1209 { 1210 struct arasan_nfc *nfc; 1211 int ret; 1212 1213 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); 1214 if (!nfc) 1215 return -ENOMEM; 1216 1217 nfc->dev = &pdev->dev; 1218 nand_controller_init(&nfc->controller); 1219 nfc->controller.ops = &anfc_ops; 1220 INIT_LIST_HEAD(&nfc->chips); 1221 1222 nfc->base = devm_platform_ioremap_resource(pdev, 0); 1223 if (IS_ERR(nfc->base)) 1224 return PTR_ERR(nfc->base); 1225 1226 anfc_reset(nfc); 1227 1228 nfc->controller_clk = devm_clk_get(&pdev->dev, "controller"); 1229 if (IS_ERR(nfc->controller_clk)) 1230 return PTR_ERR(nfc->controller_clk); 1231 1232 nfc->bus_clk = devm_clk_get(&pdev->dev, "bus"); 1233 if (IS_ERR(nfc->bus_clk)) 1234 return PTR_ERR(nfc->bus_clk); 1235 1236 ret = clk_prepare_enable(nfc->controller_clk); 1237 if (ret) 1238 return ret; 1239 1240 ret = clk_prepare_enable(nfc->bus_clk); 1241 if (ret) 1242 goto disable_controller_clk; 1243 1244 ret = anfc_chips_init(nfc); 1245 if (ret) 1246 goto disable_bus_clk; 1247 1248 platform_set_drvdata(pdev, nfc); 1249 1250 return 0; 1251 1252 disable_bus_clk: 1253 clk_disable_unprepare(nfc->bus_clk); 1254 1255 disable_controller_clk: 1256 clk_disable_unprepare(nfc->controller_clk); 1257 1258 return ret; 1259 } 1260 1261 static int anfc_remove(struct platform_device *pdev) 1262 { 1263 struct arasan_nfc *nfc = platform_get_drvdata(pdev); 1264 1265 anfc_chips_cleanup(nfc); 1266 1267 clk_disable_unprepare(nfc->bus_clk); 1268 clk_disable_unprepare(nfc->controller_clk); 1269 1270 return 0; 1271 } 1272 1273 static const struct of_device_id anfc_ids[] = { 1274 { 1275 .compatible = "xlnx,zynqmp-nand-controller", 1276 }, 1277 { 1278 .compatible = "arasan,nfc-v3p10", 1279 }, 1280 {} 1281 }; 1282 MODULE_DEVICE_TABLE(of, anfc_ids); 1283 1284 static struct platform_driver anfc_driver = { 1285 .driver = { 1286 .name = "arasan-nand-controller", 1287 .of_match_table = anfc_ids, 1288 }, 1289 .probe = anfc_probe, 1290 .remove = anfc_remove, 1291 }; 1292 module_platform_driver(anfc_driver); 1293 1294 MODULE_LICENSE("GPL v2"); 1295 MODULE_AUTHOR("Punnaiah Choudary Kalluri <punnaia@xilinx.com>"); 1296 MODULE_AUTHOR("Naga Sureshkumar Relli <nagasure@xilinx.com>"); 1297 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>"); 1298 MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver"); 1299