1 /* 2 * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li> 3 * 4 * Derived from drivers/mtd/nand/toto.c (removed in v2.6.28) 5 * Copyright (c) 2003 Texas Instruments 6 * Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de> 7 * 8 * Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> 9 * Partially stolen from plat_nand.c 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * Overview: 16 * This is a device driver for the NAND flash device found on the 17 * Amstrad E3 (Delta). 18 */ 19 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/delay.h> 23 #include <linux/gpio/consumer.h> 24 #include <linux/mtd/mtd.h> 25 #include <linux/mtd/rawnand.h> 26 #include <linux/mtd/partitions.h> 27 #include <linux/platform_data/gpio-omap.h> 28 29 #include <asm/io.h> 30 #include <asm/sizes.h> 31 32 #include <mach/hardware.h> 33 34 /* 35 * MTD structure for E3 (Delta) 36 */ 37 38 struct ams_delta_nand { 39 struct nand_chip nand_chip; 40 struct gpio_desc *gpiod_rdy; 41 struct gpio_desc *gpiod_nce; 42 struct gpio_desc *gpiod_nre; 43 struct gpio_desc *gpiod_nwp; 44 struct gpio_desc *gpiod_nwe; 45 struct gpio_desc *gpiod_ale; 46 struct gpio_desc *gpiod_cle; 47 void __iomem *io_base; 48 bool data_in; 49 }; 50 51 /* 52 * Define partitions for flash devices 53 */ 54 55 static const struct mtd_partition partition_info[] = { 56 { .name = "Kernel", 57 .offset = 0, 58 .size = 3 * SZ_1M + SZ_512K }, 59 { .name = "u-boot", 60 .offset = 3 * SZ_1M + SZ_512K, 61 .size = SZ_256K }, 62 { .name = "u-boot params", 63 .offset = 3 * SZ_1M + SZ_512K + SZ_256K, 64 .size = SZ_256K }, 65 { .name = "Amstrad LDR", 66 .offset = 4 * SZ_1M, 67 .size = SZ_256K }, 68 { .name = "File system", 69 .offset = 4 * SZ_1M + 1 * SZ_256K, 70 .size = 27 * SZ_1M }, 71 { .name = "PBL reserved", 72 .offset = 32 * SZ_1M - 3 * SZ_256K, 73 .size = 3 * SZ_256K }, 74 }; 75 76 static void ams_delta_io_write(struct ams_delta_nand *priv, u_char byte) 77 { 78 writew(byte, priv->nand_chip.legacy.IO_ADDR_W); 79 gpiod_set_value(priv->gpiod_nwe, 0); 80 ndelay(40); 81 gpiod_set_value(priv->gpiod_nwe, 1); 82 } 83 84 static u_char ams_delta_io_read(struct ams_delta_nand *priv) 85 { 86 u_char res; 87 88 gpiod_set_value(priv->gpiod_nre, 0); 89 ndelay(40); 90 res = readw(priv->nand_chip.legacy.IO_ADDR_R); 91 gpiod_set_value(priv->gpiod_nre, 1); 92 93 return res; 94 } 95 96 static void ams_delta_dir_input(struct ams_delta_nand *priv, bool in) 97 { 98 writew(in ? ~0 : 0, priv->io_base + OMAP_MPUIO_IO_CNTL); 99 priv->data_in = in; 100 } 101 102 static void ams_delta_write_buf(struct nand_chip *this, const u_char *buf, 103 int len) 104 { 105 struct ams_delta_nand *priv = nand_get_controller_data(this); 106 int i; 107 108 if (priv->data_in) 109 ams_delta_dir_input(priv, false); 110 111 for (i = 0; i < len; i++) 112 ams_delta_io_write(priv, buf[i]); 113 } 114 115 static void ams_delta_read_buf(struct nand_chip *this, u_char *buf, int len) 116 { 117 struct ams_delta_nand *priv = nand_get_controller_data(this); 118 int i; 119 120 if (!priv->data_in) 121 ams_delta_dir_input(priv, true); 122 123 for (i = 0; i < len; i++) 124 buf[i] = ams_delta_io_read(priv); 125 } 126 127 static u_char ams_delta_read_byte(struct nand_chip *this) 128 { 129 u_char res; 130 131 ams_delta_read_buf(this, &res, 1); 132 133 return res; 134 } 135 136 /* 137 * Command control function 138 * 139 * ctrl: 140 * NAND_NCE: bit 0 -> bit 2 141 * NAND_CLE: bit 1 -> bit 7 142 * NAND_ALE: bit 2 -> bit 6 143 */ 144 static void ams_delta_hwcontrol(struct nand_chip *this, int cmd, 145 unsigned int ctrl) 146 { 147 struct ams_delta_nand *priv = nand_get_controller_data(this); 148 149 if (ctrl & NAND_CTRL_CHANGE) { 150 gpiod_set_value(priv->gpiod_nce, !(ctrl & NAND_NCE)); 151 gpiod_set_value(priv->gpiod_cle, !!(ctrl & NAND_CLE)); 152 gpiod_set_value(priv->gpiod_ale, !!(ctrl & NAND_ALE)); 153 } 154 155 if (cmd != NAND_CMD_NONE) { 156 u_char byte = cmd; 157 158 ams_delta_write_buf(this, &byte, 1); 159 } 160 } 161 162 static int ams_delta_nand_ready(struct nand_chip *this) 163 { 164 struct ams_delta_nand *priv = nand_get_controller_data(this); 165 166 return gpiod_get_value(priv->gpiod_rdy); 167 } 168 169 170 /* 171 * Main initialization routine 172 */ 173 static int ams_delta_init(struct platform_device *pdev) 174 { 175 struct ams_delta_nand *priv; 176 struct nand_chip *this; 177 struct mtd_info *mtd; 178 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 179 void __iomem *io_base; 180 int err = 0; 181 182 if (!res) 183 return -ENXIO; 184 185 /* Allocate memory for MTD device structure and private data */ 186 priv = devm_kzalloc(&pdev->dev, sizeof(struct ams_delta_nand), 187 GFP_KERNEL); 188 if (!priv) { 189 pr_warn("Unable to allocate E3 NAND MTD device structure.\n"); 190 return -ENOMEM; 191 } 192 this = &priv->nand_chip; 193 194 mtd = nand_to_mtd(this); 195 mtd->dev.parent = &pdev->dev; 196 197 /* 198 * Don't try to request the memory region from here, 199 * it should have been already requested from the 200 * gpio-omap driver and requesting it again would fail. 201 */ 202 203 io_base = ioremap(res->start, resource_size(res)); 204 if (io_base == NULL) { 205 dev_err(&pdev->dev, "ioremap failed\n"); 206 err = -EIO; 207 goto out_free; 208 } 209 210 priv->io_base = io_base; 211 nand_set_controller_data(this, priv); 212 213 /* Set address of NAND IO lines */ 214 this->legacy.IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH; 215 this->legacy.IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT; 216 this->legacy.read_byte = ams_delta_read_byte; 217 this->legacy.write_buf = ams_delta_write_buf; 218 this->legacy.read_buf = ams_delta_read_buf; 219 this->legacy.cmd_ctrl = ams_delta_hwcontrol; 220 221 priv->gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy", GPIOD_IN); 222 if (IS_ERR(priv->gpiod_rdy)) { 223 err = PTR_ERR(priv->gpiod_rdy); 224 dev_warn(&pdev->dev, "RDY GPIO request failed (%d)\n", err); 225 goto out_mtd; 226 } 227 228 if (priv->gpiod_rdy) 229 this->legacy.dev_ready = ams_delta_nand_ready; 230 231 /* 25 us command delay time */ 232 this->legacy.chip_delay = 30; 233 this->ecc.mode = NAND_ECC_SOFT; 234 this->ecc.algo = NAND_ECC_HAMMING; 235 236 platform_set_drvdata(pdev, priv); 237 238 /* Set chip enabled, but */ 239 priv->gpiod_nwp = devm_gpiod_get(&pdev->dev, "nwp", GPIOD_OUT_HIGH); 240 if (IS_ERR(priv->gpiod_nwp)) { 241 err = PTR_ERR(priv->gpiod_nwp); 242 dev_err(&pdev->dev, "NWP GPIO request failed (%d)\n", err); 243 goto out_mtd; 244 } 245 246 priv->gpiod_nce = devm_gpiod_get(&pdev->dev, "nce", GPIOD_OUT_HIGH); 247 if (IS_ERR(priv->gpiod_nce)) { 248 err = PTR_ERR(priv->gpiod_nce); 249 dev_err(&pdev->dev, "NCE GPIO request failed (%d)\n", err); 250 goto out_mtd; 251 } 252 253 priv->gpiod_nre = devm_gpiod_get(&pdev->dev, "nre", GPIOD_OUT_HIGH); 254 if (IS_ERR(priv->gpiod_nre)) { 255 err = PTR_ERR(priv->gpiod_nre); 256 dev_err(&pdev->dev, "NRE GPIO request failed (%d)\n", err); 257 goto out_mtd; 258 } 259 260 priv->gpiod_nwe = devm_gpiod_get(&pdev->dev, "nwe", GPIOD_OUT_HIGH); 261 if (IS_ERR(priv->gpiod_nwe)) { 262 err = PTR_ERR(priv->gpiod_nwe); 263 dev_err(&pdev->dev, "NWE GPIO request failed (%d)\n", err); 264 goto out_mtd; 265 } 266 267 priv->gpiod_ale = devm_gpiod_get(&pdev->dev, "ale", GPIOD_OUT_LOW); 268 if (IS_ERR(priv->gpiod_ale)) { 269 err = PTR_ERR(priv->gpiod_ale); 270 dev_err(&pdev->dev, "ALE GPIO request failed (%d)\n", err); 271 goto out_mtd; 272 } 273 274 priv->gpiod_cle = devm_gpiod_get(&pdev->dev, "cle", GPIOD_OUT_LOW); 275 if (IS_ERR(priv->gpiod_cle)) { 276 err = PTR_ERR(priv->gpiod_cle); 277 dev_err(&pdev->dev, "CLE GPIO request failed (%d)\n", err); 278 goto out_mtd; 279 } 280 281 /* Initialize data port direction to a known state */ 282 ams_delta_dir_input(priv, true); 283 284 /* Scan to find existence of the device */ 285 err = nand_scan(this, 1); 286 if (err) 287 goto out_mtd; 288 289 /* Register the partitions */ 290 mtd_device_register(mtd, partition_info, ARRAY_SIZE(partition_info)); 291 292 goto out; 293 294 out_mtd: 295 iounmap(io_base); 296 out_free: 297 out: 298 return err; 299 } 300 301 /* 302 * Clean up routine 303 */ 304 static int ams_delta_cleanup(struct platform_device *pdev) 305 { 306 struct ams_delta_nand *priv = platform_get_drvdata(pdev); 307 struct mtd_info *mtd = nand_to_mtd(&priv->nand_chip); 308 void __iomem *io_base = priv->io_base; 309 310 /* Release resources, unregister device */ 311 nand_release(mtd_to_nand(mtd)); 312 313 iounmap(io_base); 314 315 return 0; 316 } 317 318 static struct platform_driver ams_delta_nand_driver = { 319 .probe = ams_delta_init, 320 .remove = ams_delta_cleanup, 321 .driver = { 322 .name = "ams-delta-nand", 323 }, 324 }; 325 326 module_platform_driver(ams_delta_nand_driver); 327 328 MODULE_LICENSE("GPL"); 329 MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>"); 330 MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)"); 331