1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Samsung S3C64XX/S5PC1XX OneNAND driver
4  *
5  *  Copyright © 2008-2010 Samsung Electronics
6  *  Kyungmin Park <kyungmin.park@samsung.com>
7  *  Marek Szyprowski <m.szyprowski@samsung.com>
8  *
9  * Implementation:
10  *	S3C64XX: emulate the pseudo BufferRAM
11  *	S5PC110: use DMA
12  */
13 
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/onenand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 
25 #include "samsung.h"
26 
27 enum soc_type {
28 	TYPE_S3C6400,
29 	TYPE_S3C6410,
30 	TYPE_S5PC110,
31 };
32 
33 #define ONENAND_ERASE_STATUS		0x00
34 #define ONENAND_MULTI_ERASE_SET		0x01
35 #define ONENAND_ERASE_START		0x03
36 #define ONENAND_UNLOCK_START		0x08
37 #define ONENAND_UNLOCK_END		0x09
38 #define ONENAND_LOCK_START		0x0A
39 #define ONENAND_LOCK_END		0x0B
40 #define ONENAND_LOCK_TIGHT_START	0x0C
41 #define ONENAND_LOCK_TIGHT_END		0x0D
42 #define ONENAND_UNLOCK_ALL		0x0E
43 #define ONENAND_OTP_ACCESS		0x12
44 #define ONENAND_SPARE_ACCESS_ONLY	0x13
45 #define ONENAND_MAIN_ACCESS_ONLY	0x14
46 #define ONENAND_ERASE_VERIFY		0x15
47 #define ONENAND_MAIN_SPARE_ACCESS	0x16
48 #define ONENAND_PIPELINE_READ		0x4000
49 
50 #define MAP_00				(0x0)
51 #define MAP_01				(0x1)
52 #define MAP_10				(0x2)
53 #define MAP_11				(0x3)
54 
55 #define S3C64XX_CMD_MAP_SHIFT		24
56 
57 #define S3C6400_FBA_SHIFT		10
58 #define S3C6400_FPA_SHIFT		4
59 #define S3C6400_FSA_SHIFT		2
60 
61 #define S3C6410_FBA_SHIFT		12
62 #define S3C6410_FPA_SHIFT		6
63 #define S3C6410_FSA_SHIFT		4
64 
65 /* S5PC110 specific definitions */
66 #define S5PC110_DMA_SRC_ADDR		0x400
67 #define S5PC110_DMA_SRC_CFG		0x404
68 #define S5PC110_DMA_DST_ADDR		0x408
69 #define S5PC110_DMA_DST_CFG		0x40C
70 #define S5PC110_DMA_TRANS_SIZE		0x414
71 #define S5PC110_DMA_TRANS_CMD		0x418
72 #define S5PC110_DMA_TRANS_STATUS	0x41C
73 #define S5PC110_DMA_TRANS_DIR		0x420
74 #define S5PC110_INTC_DMA_CLR		0x1004
75 #define S5PC110_INTC_ONENAND_CLR	0x1008
76 #define S5PC110_INTC_DMA_MASK		0x1024
77 #define S5PC110_INTC_ONENAND_MASK	0x1028
78 #define S5PC110_INTC_DMA_PEND		0x1044
79 #define S5PC110_INTC_ONENAND_PEND	0x1048
80 #define S5PC110_INTC_DMA_STATUS		0x1064
81 #define S5PC110_INTC_ONENAND_STATUS	0x1068
82 
83 #define S5PC110_INTC_DMA_TD		(1 << 24)
84 #define S5PC110_INTC_DMA_TE		(1 << 16)
85 
86 #define S5PC110_DMA_CFG_SINGLE		(0x0 << 16)
87 #define S5PC110_DMA_CFG_4BURST		(0x2 << 16)
88 #define S5PC110_DMA_CFG_8BURST		(0x3 << 16)
89 #define S5PC110_DMA_CFG_16BURST		(0x4 << 16)
90 
91 #define S5PC110_DMA_CFG_INC		(0x0 << 8)
92 #define S5PC110_DMA_CFG_CNT		(0x1 << 8)
93 
94 #define S5PC110_DMA_CFG_8BIT		(0x0 << 0)
95 #define S5PC110_DMA_CFG_16BIT		(0x1 << 0)
96 #define S5PC110_DMA_CFG_32BIT		(0x2 << 0)
97 
98 #define S5PC110_DMA_SRC_CFG_READ	(S5PC110_DMA_CFG_16BURST | \
99 					S5PC110_DMA_CFG_INC | \
100 					S5PC110_DMA_CFG_16BIT)
101 #define S5PC110_DMA_DST_CFG_READ	(S5PC110_DMA_CFG_16BURST | \
102 					S5PC110_DMA_CFG_INC | \
103 					S5PC110_DMA_CFG_32BIT)
104 #define S5PC110_DMA_SRC_CFG_WRITE	(S5PC110_DMA_CFG_16BURST | \
105 					S5PC110_DMA_CFG_INC | \
106 					S5PC110_DMA_CFG_32BIT)
107 #define S5PC110_DMA_DST_CFG_WRITE	(S5PC110_DMA_CFG_16BURST | \
108 					S5PC110_DMA_CFG_INC | \
109 					S5PC110_DMA_CFG_16BIT)
110 
111 #define S5PC110_DMA_TRANS_CMD_TDC	(0x1 << 18)
112 #define S5PC110_DMA_TRANS_CMD_TEC	(0x1 << 16)
113 #define S5PC110_DMA_TRANS_CMD_TR	(0x1 << 0)
114 
115 #define S5PC110_DMA_TRANS_STATUS_TD	(0x1 << 18)
116 #define S5PC110_DMA_TRANS_STATUS_TB	(0x1 << 17)
117 #define S5PC110_DMA_TRANS_STATUS_TE	(0x1 << 16)
118 
119 #define S5PC110_DMA_DIR_READ		0x0
120 #define S5PC110_DMA_DIR_WRITE		0x1
121 
122 struct s3c_onenand {
123 	struct mtd_info	*mtd;
124 	struct platform_device	*pdev;
125 	enum soc_type	type;
126 	void __iomem	*base;
127 	void __iomem	*ahb_addr;
128 	int		bootram_command;
129 	void		*page_buf;
130 	void		*oob_buf;
131 	unsigned int	(*mem_addr)(int fba, int fpa, int fsa);
132 	unsigned int	(*cmd_map)(unsigned int type, unsigned int val);
133 	void __iomem	*dma_addr;
134 	unsigned long	phys_base;
135 	struct completion	complete;
136 };
137 
138 #define CMD_MAP_00(dev, addr)		(dev->cmd_map(MAP_00, ((addr) << 1)))
139 #define CMD_MAP_01(dev, mem_addr)	(dev->cmd_map(MAP_01, (mem_addr)))
140 #define CMD_MAP_10(dev, mem_addr)	(dev->cmd_map(MAP_10, (mem_addr)))
141 #define CMD_MAP_11(dev, addr)		(dev->cmd_map(MAP_11, ((addr) << 2)))
142 
143 static struct s3c_onenand *onenand;
144 
145 static inline int s3c_read_reg(int offset)
146 {
147 	return readl(onenand->base + offset);
148 }
149 
150 static inline void s3c_write_reg(int value, int offset)
151 {
152 	writel(value, onenand->base + offset);
153 }
154 
155 static inline int s3c_read_cmd(unsigned int cmd)
156 {
157 	return readl(onenand->ahb_addr + cmd);
158 }
159 
160 static inline void s3c_write_cmd(int value, unsigned int cmd)
161 {
162 	writel(value, onenand->ahb_addr + cmd);
163 }
164 
165 #ifdef SAMSUNG_DEBUG
166 static void s3c_dump_reg(void)
167 {
168 	int i;
169 
170 	for (i = 0; i < 0x400; i += 0x40) {
171 		printk(KERN_INFO "0x%08X: 0x%08x 0x%08x 0x%08x 0x%08x\n",
172 			(unsigned int) onenand->base + i,
173 			s3c_read_reg(i), s3c_read_reg(i + 0x10),
174 			s3c_read_reg(i + 0x20), s3c_read_reg(i + 0x30));
175 	}
176 }
177 #endif
178 
179 static unsigned int s3c64xx_cmd_map(unsigned type, unsigned val)
180 {
181 	return (type << S3C64XX_CMD_MAP_SHIFT) | val;
182 }
183 
184 static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa)
185 {
186 	return (fba << S3C6400_FBA_SHIFT) | (fpa << S3C6400_FPA_SHIFT) |
187 		(fsa << S3C6400_FSA_SHIFT);
188 }
189 
190 static unsigned int s3c6410_mem_addr(int fba, int fpa, int fsa)
191 {
192 	return (fba << S3C6410_FBA_SHIFT) | (fpa << S3C6410_FPA_SHIFT) |
193 		(fsa << S3C6410_FSA_SHIFT);
194 }
195 
196 static void s3c_onenand_reset(void)
197 {
198 	unsigned long timeout = 0x10000;
199 	int stat;
200 
201 	s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);
202 	while (1 && timeout--) {
203 		stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
204 		if (stat & RST_CMP)
205 			break;
206 	}
207 	stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
208 	s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
209 
210 	/* Clear interrupt */
211 	s3c_write_reg(0x0, INT_ERR_ACK_OFFSET);
212 	/* Clear the ECC status */
213 	s3c_write_reg(0x0, ECC_ERR_STAT_OFFSET);
214 }
215 
216 static unsigned short s3c_onenand_readw(void __iomem *addr)
217 {
218 	struct onenand_chip *this = onenand->mtd->priv;
219 	struct device *dev = &onenand->pdev->dev;
220 	int reg = addr - this->base;
221 	int word_addr = reg >> 1;
222 	int value;
223 
224 	/* It's used for probing time */
225 	switch (reg) {
226 	case ONENAND_REG_MANUFACTURER_ID:
227 		return s3c_read_reg(MANUFACT_ID_OFFSET);
228 	case ONENAND_REG_DEVICE_ID:
229 		return s3c_read_reg(DEVICE_ID_OFFSET);
230 	case ONENAND_REG_VERSION_ID:
231 		return s3c_read_reg(FLASH_VER_ID_OFFSET);
232 	case ONENAND_REG_DATA_BUFFER_SIZE:
233 		return s3c_read_reg(DATA_BUF_SIZE_OFFSET);
234 	case ONENAND_REG_TECHNOLOGY:
235 		return s3c_read_reg(TECH_OFFSET);
236 	case ONENAND_REG_SYS_CFG1:
237 		return s3c_read_reg(MEM_CFG_OFFSET);
238 
239 	/* Used at unlock all status */
240 	case ONENAND_REG_CTRL_STATUS:
241 		return 0;
242 
243 	case ONENAND_REG_WP_STATUS:
244 		return ONENAND_WP_US;
245 
246 	default:
247 		break;
248 	}
249 
250 	/* BootRAM access control */
251 	if ((unsigned long)addr < ONENAND_DATARAM && onenand->bootram_command) {
252 		if (word_addr == 0)
253 			return s3c_read_reg(MANUFACT_ID_OFFSET);
254 		if (word_addr == 1)
255 			return s3c_read_reg(DEVICE_ID_OFFSET);
256 		if (word_addr == 2)
257 			return s3c_read_reg(FLASH_VER_ID_OFFSET);
258 	}
259 
260 	value = s3c_read_cmd(CMD_MAP_11(onenand, word_addr)) & 0xffff;
261 	dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__,
262 		 word_addr, value);
263 	return value;
264 }
265 
266 static void s3c_onenand_writew(unsigned short value, void __iomem *addr)
267 {
268 	struct onenand_chip *this = onenand->mtd->priv;
269 	struct device *dev = &onenand->pdev->dev;
270 	unsigned int reg = addr - this->base;
271 	unsigned int word_addr = reg >> 1;
272 
273 	/* It's used for probing time */
274 	switch (reg) {
275 	case ONENAND_REG_SYS_CFG1:
276 		s3c_write_reg(value, MEM_CFG_OFFSET);
277 		return;
278 
279 	case ONENAND_REG_START_ADDRESS1:
280 	case ONENAND_REG_START_ADDRESS2:
281 		return;
282 
283 	/* Lock/lock-tight/unlock/unlock_all */
284 	case ONENAND_REG_START_BLOCK_ADDRESS:
285 		return;
286 
287 	default:
288 		break;
289 	}
290 
291 	/* BootRAM access control */
292 	if ((unsigned long)addr < ONENAND_DATARAM) {
293 		if (value == ONENAND_CMD_READID) {
294 			onenand->bootram_command = 1;
295 			return;
296 		}
297 		if (value == ONENAND_CMD_RESET) {
298 			s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);
299 			onenand->bootram_command = 0;
300 			return;
301 		}
302 	}
303 
304 	dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__,
305 		 word_addr, value);
306 
307 	s3c_write_cmd(value, CMD_MAP_11(onenand, word_addr));
308 }
309 
310 static int s3c_onenand_wait(struct mtd_info *mtd, int state)
311 {
312 	struct device *dev = &onenand->pdev->dev;
313 	unsigned int flags = INT_ACT;
314 	unsigned int stat, ecc;
315 	unsigned long timeout;
316 
317 	switch (state) {
318 	case FL_READING:
319 		flags |= BLK_RW_CMP | LOAD_CMP;
320 		break;
321 	case FL_WRITING:
322 		flags |= BLK_RW_CMP | PGM_CMP;
323 		break;
324 	case FL_ERASING:
325 		flags |= BLK_RW_CMP | ERS_CMP;
326 		break;
327 	case FL_LOCKING:
328 		flags |= BLK_RW_CMP;
329 		break;
330 	default:
331 		break;
332 	}
333 
334 	/* The 20 msec is enough */
335 	timeout = jiffies + msecs_to_jiffies(20);
336 	while (time_before(jiffies, timeout)) {
337 		stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
338 		if (stat & flags)
339 			break;
340 
341 		if (state != FL_READING)
342 			cond_resched();
343 	}
344 	/* To get correct interrupt status in timeout case */
345 	stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
346 	s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
347 
348 	/*
349 	 * In the Spec. it checks the controller status first
350 	 * However if you get the correct information in case of
351 	 * power off recovery (POR) test, it should read ECC status first
352 	 */
353 	if (stat & LOAD_CMP) {
354 		ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET);
355 		if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
356 			dev_info(dev, "%s: ECC error = 0x%04x\n", __func__,
357 				 ecc);
358 			mtd->ecc_stats.failed++;
359 			return -EBADMSG;
360 		}
361 	}
362 
363 	if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) {
364 		dev_info(dev, "%s: controller error = 0x%04x\n", __func__,
365 			 stat);
366 		if (stat & LOCKED_BLK)
367 			dev_info(dev, "%s: it's locked error = 0x%04x\n",
368 				 __func__, stat);
369 
370 		return -EIO;
371 	}
372 
373 	return 0;
374 }
375 
376 static int s3c_onenand_command(struct mtd_info *mtd, int cmd, loff_t addr,
377 			       size_t len)
378 {
379 	struct onenand_chip *this = mtd->priv;
380 	unsigned int *m, *s;
381 	int fba, fpa, fsa = 0;
382 	unsigned int mem_addr, cmd_map_01, cmd_map_10;
383 	int i, mcount, scount;
384 	int index;
385 
386 	fba = (int) (addr >> this->erase_shift);
387 	fpa = (int) (addr >> this->page_shift);
388 	fpa &= this->page_mask;
389 
390 	mem_addr = onenand->mem_addr(fba, fpa, fsa);
391 	cmd_map_01 = CMD_MAP_01(onenand, mem_addr);
392 	cmd_map_10 = CMD_MAP_10(onenand, mem_addr);
393 
394 	switch (cmd) {
395 	case ONENAND_CMD_READ:
396 	case ONENAND_CMD_READOOB:
397 	case ONENAND_CMD_BUFFERRAM:
398 		ONENAND_SET_NEXT_BUFFERRAM(this);
399 		break;
400 	default:
401 		break;
402 	}
403 
404 	index = ONENAND_CURRENT_BUFFERRAM(this);
405 
406 	/*
407 	 * Emulate Two BufferRAMs and access with 4 bytes pointer
408 	 */
409 	m = onenand->page_buf;
410 	s = onenand->oob_buf;
411 
412 	if (index) {
413 		m += (this->writesize >> 2);
414 		s += (mtd->oobsize >> 2);
415 	}
416 
417 	mcount = mtd->writesize >> 2;
418 	scount = mtd->oobsize >> 2;
419 
420 	switch (cmd) {
421 	case ONENAND_CMD_READ:
422 		/* Main */
423 		for (i = 0; i < mcount; i++)
424 			*m++ = s3c_read_cmd(cmd_map_01);
425 		return 0;
426 
427 	case ONENAND_CMD_READOOB:
428 		s3c_write_reg(TSRF, TRANS_SPARE_OFFSET);
429 		/* Main */
430 		for (i = 0; i < mcount; i++)
431 			*m++ = s3c_read_cmd(cmd_map_01);
432 
433 		/* Spare */
434 		for (i = 0; i < scount; i++)
435 			*s++ = s3c_read_cmd(cmd_map_01);
436 
437 		s3c_write_reg(0, TRANS_SPARE_OFFSET);
438 		return 0;
439 
440 	case ONENAND_CMD_PROG:
441 		/* Main */
442 		for (i = 0; i < mcount; i++)
443 			s3c_write_cmd(*m++, cmd_map_01);
444 		return 0;
445 
446 	case ONENAND_CMD_PROGOOB:
447 		s3c_write_reg(TSRF, TRANS_SPARE_OFFSET);
448 
449 		/* Main - dummy write */
450 		for (i = 0; i < mcount; i++)
451 			s3c_write_cmd(0xffffffff, cmd_map_01);
452 
453 		/* Spare */
454 		for (i = 0; i < scount; i++)
455 			s3c_write_cmd(*s++, cmd_map_01);
456 
457 		s3c_write_reg(0, TRANS_SPARE_OFFSET);
458 		return 0;
459 
460 	case ONENAND_CMD_UNLOCK_ALL:
461 		s3c_write_cmd(ONENAND_UNLOCK_ALL, cmd_map_10);
462 		return 0;
463 
464 	case ONENAND_CMD_ERASE:
465 		s3c_write_cmd(ONENAND_ERASE_START, cmd_map_10);
466 		return 0;
467 
468 	default:
469 		break;
470 	}
471 
472 	return 0;
473 }
474 
475 static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area)
476 {
477 	struct onenand_chip *this = mtd->priv;
478 	int index = ONENAND_CURRENT_BUFFERRAM(this);
479 	unsigned char *p;
480 
481 	if (area == ONENAND_DATARAM) {
482 		p = onenand->page_buf;
483 		if (index == 1)
484 			p += this->writesize;
485 	} else {
486 		p = onenand->oob_buf;
487 		if (index == 1)
488 			p += mtd->oobsize;
489 	}
490 
491 	return p;
492 }
493 
494 static int onenand_read_bufferram(struct mtd_info *mtd, int area,
495 				  unsigned char *buffer, int offset,
496 				  size_t count)
497 {
498 	unsigned char *p;
499 
500 	p = s3c_get_bufferram(mtd, area);
501 	memcpy(buffer, p + offset, count);
502 	return 0;
503 }
504 
505 static int onenand_write_bufferram(struct mtd_info *mtd, int area,
506 				   const unsigned char *buffer, int offset,
507 				   size_t count)
508 {
509 	unsigned char *p;
510 
511 	p = s3c_get_bufferram(mtd, area);
512 	memcpy(p + offset, buffer, count);
513 	return 0;
514 }
515 
516 static int (*s5pc110_dma_ops)(dma_addr_t dst, dma_addr_t src, size_t count, int direction);
517 
518 static int s5pc110_dma_poll(dma_addr_t dst, dma_addr_t src, size_t count, int direction)
519 {
520 	void __iomem *base = onenand->dma_addr;
521 	int status;
522 	unsigned long timeout;
523 
524 	writel(src, base + S5PC110_DMA_SRC_ADDR);
525 	writel(dst, base + S5PC110_DMA_DST_ADDR);
526 
527 	if (direction == S5PC110_DMA_DIR_READ) {
528 		writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG);
529 		writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG);
530 	} else {
531 		writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG);
532 		writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG);
533 	}
534 
535 	writel(count, base + S5PC110_DMA_TRANS_SIZE);
536 	writel(direction, base + S5PC110_DMA_TRANS_DIR);
537 
538 	writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
539 
540 	/*
541 	 * There's no exact timeout values at Spec.
542 	 * In real case it takes under 1 msec.
543 	 * So 20 msecs are enough.
544 	 */
545 	timeout = jiffies + msecs_to_jiffies(20);
546 
547 	do {
548 		status = readl(base + S5PC110_DMA_TRANS_STATUS);
549 		if (status & S5PC110_DMA_TRANS_STATUS_TE) {
550 			writel(S5PC110_DMA_TRANS_CMD_TEC,
551 					base + S5PC110_DMA_TRANS_CMD);
552 			return -EIO;
553 		}
554 	} while (!(status & S5PC110_DMA_TRANS_STATUS_TD) &&
555 		time_before(jiffies, timeout));
556 
557 	writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);
558 
559 	return 0;
560 }
561 
562 static irqreturn_t s5pc110_onenand_irq(int irq, void *data)
563 {
564 	void __iomem *base = onenand->dma_addr;
565 	int status, cmd = 0;
566 
567 	status = readl(base + S5PC110_INTC_DMA_STATUS);
568 
569 	if (likely(status & S5PC110_INTC_DMA_TD))
570 		cmd = S5PC110_DMA_TRANS_CMD_TDC;
571 
572 	if (unlikely(status & S5PC110_INTC_DMA_TE))
573 		cmd = S5PC110_DMA_TRANS_CMD_TEC;
574 
575 	writel(cmd, base + S5PC110_DMA_TRANS_CMD);
576 	writel(status, base + S5PC110_INTC_DMA_CLR);
577 
578 	if (!onenand->complete.done)
579 		complete(&onenand->complete);
580 
581 	return IRQ_HANDLED;
582 }
583 
584 static int s5pc110_dma_irq(dma_addr_t dst, dma_addr_t src, size_t count, int direction)
585 {
586 	void __iomem *base = onenand->dma_addr;
587 	int status;
588 
589 	status = readl(base + S5PC110_INTC_DMA_MASK);
590 	if (status) {
591 		status &= ~(S5PC110_INTC_DMA_TD | S5PC110_INTC_DMA_TE);
592 		writel(status, base + S5PC110_INTC_DMA_MASK);
593 	}
594 
595 	writel(src, base + S5PC110_DMA_SRC_ADDR);
596 	writel(dst, base + S5PC110_DMA_DST_ADDR);
597 
598 	if (direction == S5PC110_DMA_DIR_READ) {
599 		writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG);
600 		writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG);
601 	} else {
602 		writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG);
603 		writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG);
604 	}
605 
606 	writel(count, base + S5PC110_DMA_TRANS_SIZE);
607 	writel(direction, base + S5PC110_DMA_TRANS_DIR);
608 
609 	writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
610 
611 	wait_for_completion_timeout(&onenand->complete, msecs_to_jiffies(20));
612 
613 	return 0;
614 }
615 
616 static int s5pc110_read_bufferram(struct mtd_info *mtd, int area,
617 		unsigned char *buffer, int offset, size_t count)
618 {
619 	struct onenand_chip *this = mtd->priv;
620 	void __iomem *p;
621 	void *buf = (void *) buffer;
622 	dma_addr_t dma_src, dma_dst;
623 	int err, ofs, page_dma = 0;
624 	struct device *dev = &onenand->pdev->dev;
625 
626 	p = this->base + area;
627 	if (ONENAND_CURRENT_BUFFERRAM(this)) {
628 		if (area == ONENAND_DATARAM)
629 			p += this->writesize;
630 		else
631 			p += mtd->oobsize;
632 	}
633 
634 	if (offset & 3 || (size_t) buf & 3 ||
635 		!onenand->dma_addr || count != mtd->writesize)
636 		goto normal;
637 
638 	/* Handle vmalloc address */
639 	if (buf >= high_memory) {
640 		struct page *page;
641 
642 		if (((size_t) buf & PAGE_MASK) !=
643 		    ((size_t) (buf + count - 1) & PAGE_MASK))
644 			goto normal;
645 		page = vmalloc_to_page(buf);
646 		if (!page)
647 			goto normal;
648 
649 		/* Page offset */
650 		ofs = ((size_t) buf & ~PAGE_MASK);
651 		page_dma = 1;
652 
653 		/* DMA routine */
654 		dma_src = onenand->phys_base + (p - this->base);
655 		dma_dst = dma_map_page(dev, page, ofs, count, DMA_FROM_DEVICE);
656 	} else {
657 		/* DMA routine */
658 		dma_src = onenand->phys_base + (p - this->base);
659 		dma_dst = dma_map_single(dev, buf, count, DMA_FROM_DEVICE);
660 	}
661 	if (dma_mapping_error(dev, dma_dst)) {
662 		dev_err(dev, "Couldn't map a %zu byte buffer for DMA\n", count);
663 		goto normal;
664 	}
665 	err = s5pc110_dma_ops(dma_dst, dma_src,
666 			count, S5PC110_DMA_DIR_READ);
667 
668 	if (page_dma)
669 		dma_unmap_page(dev, dma_dst, count, DMA_FROM_DEVICE);
670 	else
671 		dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE);
672 
673 	if (!err)
674 		return 0;
675 
676 normal:
677 	if (count != mtd->writesize) {
678 		/* Copy the bufferram to memory to prevent unaligned access */
679 		memcpy_fromio(this->page_buf, p, mtd->writesize);
680 		memcpy(buffer, this->page_buf + offset, count);
681 	} else {
682 		memcpy_fromio(buffer, p, count);
683 	}
684 
685 	return 0;
686 }
687 
688 static int s5pc110_chip_probe(struct mtd_info *mtd)
689 {
690 	/* Now just return 0 */
691 	return 0;
692 }
693 
694 static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state)
695 {
696 	unsigned int flags = INT_ACT | LOAD_CMP;
697 	unsigned int stat;
698 	unsigned long timeout;
699 
700 	/* The 20 msec is enough */
701 	timeout = jiffies + msecs_to_jiffies(20);
702 	while (time_before(jiffies, timeout)) {
703 		stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
704 		if (stat & flags)
705 			break;
706 	}
707 	/* To get correct interrupt status in timeout case */
708 	stat = s3c_read_reg(INT_ERR_STAT_OFFSET);
709 	s3c_write_reg(stat, INT_ERR_ACK_OFFSET);
710 
711 	if (stat & LD_FAIL_ECC_ERR) {
712 		s3c_onenand_reset();
713 		return ONENAND_BBT_READ_ERROR;
714 	}
715 
716 	if (stat & LOAD_CMP) {
717 		int ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET);
718 		if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
719 			s3c_onenand_reset();
720 			return ONENAND_BBT_READ_ERROR;
721 		}
722 	}
723 
724 	return 0;
725 }
726 
727 static void s3c_onenand_check_lock_status(struct mtd_info *mtd)
728 {
729 	struct onenand_chip *this = mtd->priv;
730 	struct device *dev = &onenand->pdev->dev;
731 	unsigned int block, end;
732 
733 	end = this->chipsize >> this->erase_shift;
734 
735 	for (block = 0; block < end; block++) {
736 		unsigned int mem_addr = onenand->mem_addr(block, 0, 0);
737 		s3c_read_cmd(CMD_MAP_01(onenand, mem_addr));
738 
739 		if (s3c_read_reg(INT_ERR_STAT_OFFSET) & LOCKED_BLK) {
740 			dev_err(dev, "block %d is write-protected!\n", block);
741 			s3c_write_reg(LOCKED_BLK, INT_ERR_ACK_OFFSET);
742 		}
743 	}
744 }
745 
746 static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs,
747 				    size_t len, int cmd)
748 {
749 	struct onenand_chip *this = mtd->priv;
750 	int start, end, start_mem_addr, end_mem_addr;
751 
752 	start = ofs >> this->erase_shift;
753 	start_mem_addr = onenand->mem_addr(start, 0, 0);
754 	end = start + (len >> this->erase_shift) - 1;
755 	end_mem_addr = onenand->mem_addr(end, 0, 0);
756 
757 	if (cmd == ONENAND_CMD_LOCK) {
758 		s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(onenand,
759 							     start_mem_addr));
760 		s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(onenand,
761 							   end_mem_addr));
762 	} else {
763 		s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(onenand,
764 							       start_mem_addr));
765 		s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(onenand,
766 							     end_mem_addr));
767 	}
768 
769 	this->wait(mtd, FL_LOCKING);
770 }
771 
772 static void s3c_unlock_all(struct mtd_info *mtd)
773 {
774 	struct onenand_chip *this = mtd->priv;
775 	loff_t ofs = 0;
776 	size_t len = this->chipsize;
777 
778 	if (this->options & ONENAND_HAS_UNLOCK_ALL) {
779 		/* Write unlock command */
780 		this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
781 
782 		/* No need to check return value */
783 		this->wait(mtd, FL_LOCKING);
784 
785 		/* Workaround for all block unlock in DDP */
786 		if (!ONENAND_IS_DDP(this)) {
787 			s3c_onenand_check_lock_status(mtd);
788 			return;
789 		}
790 
791 		/* All blocks on another chip */
792 		ofs = this->chipsize >> 1;
793 		len = this->chipsize >> 1;
794 	}
795 
796 	s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
797 
798 	s3c_onenand_check_lock_status(mtd);
799 }
800 
801 static void s3c_onenand_setup(struct mtd_info *mtd)
802 {
803 	struct onenand_chip *this = mtd->priv;
804 
805 	onenand->mtd = mtd;
806 
807 	if (onenand->type == TYPE_S3C6400) {
808 		onenand->mem_addr = s3c6400_mem_addr;
809 		onenand->cmd_map = s3c64xx_cmd_map;
810 	} else if (onenand->type == TYPE_S3C6410) {
811 		onenand->mem_addr = s3c6410_mem_addr;
812 		onenand->cmd_map = s3c64xx_cmd_map;
813 	} else if (onenand->type == TYPE_S5PC110) {
814 		/* Use generic onenand functions */
815 		this->read_bufferram = s5pc110_read_bufferram;
816 		this->chip_probe = s5pc110_chip_probe;
817 		return;
818 	} else {
819 		BUG();
820 	}
821 
822 	this->read_word = s3c_onenand_readw;
823 	this->write_word = s3c_onenand_writew;
824 
825 	this->wait = s3c_onenand_wait;
826 	this->bbt_wait = s3c_onenand_bbt_wait;
827 	this->unlock_all = s3c_unlock_all;
828 	this->command = s3c_onenand_command;
829 
830 	this->read_bufferram = onenand_read_bufferram;
831 	this->write_bufferram = onenand_write_bufferram;
832 }
833 
834 static int s3c_onenand_probe(struct platform_device *pdev)
835 {
836 	struct onenand_platform_data *pdata;
837 	struct onenand_chip *this;
838 	struct mtd_info *mtd;
839 	struct resource *r;
840 	int size, err;
841 
842 	pdata = dev_get_platdata(&pdev->dev);
843 	/* No need to check pdata. the platform data is optional */
844 
845 	size = sizeof(struct mtd_info) + sizeof(struct onenand_chip);
846 	mtd = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
847 	if (!mtd)
848 		return -ENOMEM;
849 
850 	onenand = devm_kzalloc(&pdev->dev, sizeof(struct s3c_onenand),
851 			       GFP_KERNEL);
852 	if (!onenand)
853 		return -ENOMEM;
854 
855 	this = (struct onenand_chip *) &mtd[1];
856 	mtd->priv = this;
857 	mtd->dev.parent = &pdev->dev;
858 	onenand->pdev = pdev;
859 	onenand->type = platform_get_device_id(pdev)->driver_data;
860 
861 	s3c_onenand_setup(mtd);
862 
863 	onenand->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
864 	if (IS_ERR(onenand->base))
865 		return PTR_ERR(onenand->base);
866 
867 	onenand->phys_base = r->start;
868 
869 	/* Set onenand_chip also */
870 	this->base = onenand->base;
871 
872 	/* Use runtime badblock check */
873 	this->options |= ONENAND_SKIP_UNLOCK_CHECK;
874 
875 	if (onenand->type != TYPE_S5PC110) {
876 		onenand->ahb_addr = devm_platform_ioremap_resource(pdev, 1);
877 		if (IS_ERR(onenand->ahb_addr))
878 			return PTR_ERR(onenand->ahb_addr);
879 
880 		/* Allocate 4KiB BufferRAM */
881 		onenand->page_buf = devm_kzalloc(&pdev->dev, SZ_4K,
882 						 GFP_KERNEL);
883 		if (!onenand->page_buf)
884 			return -ENOMEM;
885 
886 		/* Allocate 128 SpareRAM */
887 		onenand->oob_buf = devm_kzalloc(&pdev->dev, 128, GFP_KERNEL);
888 		if (!onenand->oob_buf)
889 			return -ENOMEM;
890 
891 		/* S3C doesn't handle subpage write */
892 		mtd->subpage_sft = 0;
893 		this->subpagesize = mtd->writesize;
894 
895 	} else { /* S5PC110 */
896 		onenand->dma_addr = devm_platform_ioremap_resource(pdev, 1);
897 		if (IS_ERR(onenand->dma_addr))
898 			return PTR_ERR(onenand->dma_addr);
899 
900 		s5pc110_dma_ops = s5pc110_dma_poll;
901 		/* Interrupt support */
902 		r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
903 		if (r) {
904 			init_completion(&onenand->complete);
905 			s5pc110_dma_ops = s5pc110_dma_irq;
906 			err = devm_request_irq(&pdev->dev, r->start,
907 					       s5pc110_onenand_irq,
908 					       IRQF_SHARED, "onenand",
909 					       &onenand);
910 			if (err) {
911 				dev_err(&pdev->dev, "failed to get irq\n");
912 				return err;
913 			}
914 		}
915 	}
916 
917 	err = onenand_scan(mtd, 1);
918 	if (err)
919 		return err;
920 
921 	if (onenand->type != TYPE_S5PC110) {
922 		/* S3C doesn't handle subpage write */
923 		mtd->subpage_sft = 0;
924 		this->subpagesize = mtd->writesize;
925 	}
926 
927 	if (s3c_read_reg(MEM_CFG_OFFSET) & ONENAND_SYS_CFG1_SYNC_READ)
928 		dev_info(&onenand->pdev->dev, "OneNAND Sync. Burst Read enabled\n");
929 
930 	err = mtd_device_register(mtd, pdata ? pdata->parts : NULL,
931 				  pdata ? pdata->nr_parts : 0);
932 	if (err) {
933 		dev_err(&pdev->dev, "failed to parse partitions and register the MTD device\n");
934 		onenand_release(mtd);
935 		return err;
936 	}
937 
938 	platform_set_drvdata(pdev, mtd);
939 
940 	return 0;
941 }
942 
943 static void s3c_onenand_remove(struct platform_device *pdev)
944 {
945 	struct mtd_info *mtd = platform_get_drvdata(pdev);
946 
947 	onenand_release(mtd);
948 }
949 
950 static int s3c_pm_ops_suspend(struct device *dev)
951 {
952 	struct mtd_info *mtd = dev_get_drvdata(dev);
953 	struct onenand_chip *this = mtd->priv;
954 
955 	this->wait(mtd, FL_PM_SUSPENDED);
956 	return 0;
957 }
958 
959 static  int s3c_pm_ops_resume(struct device *dev)
960 {
961 	struct mtd_info *mtd = dev_get_drvdata(dev);
962 	struct onenand_chip *this = mtd->priv;
963 
964 	this->unlock_all(mtd);
965 	return 0;
966 }
967 
968 static const struct dev_pm_ops s3c_pm_ops = {
969 	.suspend	= s3c_pm_ops_suspend,
970 	.resume		= s3c_pm_ops_resume,
971 };
972 
973 static const struct platform_device_id s3c_onenand_driver_ids[] = {
974 	{
975 		.name		= "s3c6400-onenand",
976 		.driver_data	= TYPE_S3C6400,
977 	}, {
978 		.name		= "s3c6410-onenand",
979 		.driver_data	= TYPE_S3C6410,
980 	}, {
981 		.name		= "s5pc110-onenand",
982 		.driver_data	= TYPE_S5PC110,
983 	}, { },
984 };
985 MODULE_DEVICE_TABLE(platform, s3c_onenand_driver_ids);
986 
987 static struct platform_driver s3c_onenand_driver = {
988 	.driver         = {
989 		.name	= "samsung-onenand",
990 		.pm	= &s3c_pm_ops,
991 	},
992 	.id_table	= s3c_onenand_driver_ids,
993 	.probe          = s3c_onenand_probe,
994 	.remove_new     = s3c_onenand_remove,
995 };
996 
997 module_platform_driver(s3c_onenand_driver);
998 
999 MODULE_LICENSE("GPL");
1000 MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
1001 MODULE_DESCRIPTION("Samsung OneNAND controller support");
1002