1 /* 2 * drivers/mtd/maps/intel_vr_nor.c 3 * 4 * An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel 5 * Vermilion Range chipset. 6 * 7 * The Vermilion Range Expansion Bus supports four chip selects, each of which 8 * has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device 9 * is a 256MiB memory region containing the address spaces for all four of the 10 * chip selects, with start addresses hardcoded on 64MiB boundaries. 11 * 12 * This map driver only supports NOR flash on chip select 0. The buswidth 13 * (either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing 14 * and Control Register for Chip Select 0 (EXP_TIMING_CS0). This driver does 15 * not modify the value in the EXP_TIMING_CS0 register except to enable writing 16 * and disable boot acceleration. The timing parameters in the register are 17 * assumed to have been properly initialized by the BIOS. The reset default 18 * timing parameters are maximally conservative (slow), so access to the flash 19 * will be slower than it should be if the BIOS has not initialized the timing 20 * parameters. 21 * 22 * Author: Andy Lowe <alowe@mvista.com> 23 * 24 * 2006 (c) MontaVista Software, Inc. This file is licensed under 25 * the terms of the GNU General Public License version 2. This program 26 * is licensed "as is" without any warranty of any kind, whether express 27 * or implied. 28 */ 29 30 #include <linux/module.h> 31 #include <linux/kernel.h> 32 #include <linux/slab.h> 33 #include <linux/pci.h> 34 #include <linux/init.h> 35 #include <linux/mtd/mtd.h> 36 #include <linux/mtd/map.h> 37 #include <linux/mtd/partitions.h> 38 #include <linux/mtd/cfi.h> 39 #include <linux/mtd/flashchip.h> 40 41 #define DRV_NAME "vr_nor" 42 43 struct vr_nor_mtd { 44 void __iomem *csr_base; 45 struct map_info map; 46 struct mtd_info *info; 47 int nr_parts; 48 struct pci_dev *dev; 49 }; 50 51 /* Expansion Bus Configuration and Status Registers are in BAR 0 */ 52 #define EXP_CSR_MBAR 0 53 /* Expansion Bus Memory Window is BAR 1 */ 54 #define EXP_WIN_MBAR 1 55 /* Maximum address space for Chip Select 0 is 64MiB */ 56 #define CS0_SIZE 0x04000000 57 /* Chip Select 0 is at offset 0 in the Memory Window */ 58 #define CS0_START 0x0 59 /* Chip Select 0 Timing Register is at offset 0 in CSR */ 60 #define EXP_TIMING_CS0 0x00 61 #define TIMING_CS_EN (1 << 31) /* Chip Select Enable */ 62 #define TIMING_BOOT_ACCEL_DIS (1 << 8) /* Boot Acceleration Disable */ 63 #define TIMING_WR_EN (1 << 1) /* Write Enable */ 64 #define TIMING_BYTE_EN (1 << 0) /* 8-bit vs 16-bit bus */ 65 #define TIMING_MASK 0x3FFF0000 66 67 static void __devexit vr_nor_destroy_partitions(struct vr_nor_mtd *p) 68 { 69 if (p->nr_parts > 0) { 70 #if defined(CONFIG_MTD_PARTITIONS) || defined(CONFIG_MTD_PARTITIONS_MODULE) 71 del_mtd_partitions(p->info); 72 #endif 73 } else 74 del_mtd_device(p->info); 75 } 76 77 static int __devinit vr_nor_init_partitions(struct vr_nor_mtd *p) 78 { 79 int err = 0; 80 #if defined(CONFIG_MTD_PARTITIONS) || defined(CONFIG_MTD_PARTITIONS_MODULE) 81 struct mtd_partition *parts; 82 static const char *part_probes[] = { "cmdlinepart", NULL }; 83 #endif 84 85 /* register the flash bank */ 86 #if defined(CONFIG_MTD_PARTITIONS) || defined(CONFIG_MTD_PARTITIONS_MODULE) 87 /* partition the flash bank */ 88 p->nr_parts = parse_mtd_partitions(p->info, part_probes, &parts, 0); 89 if (p->nr_parts > 0) 90 err = add_mtd_partitions(p->info, parts, p->nr_parts); 91 #endif 92 if (p->nr_parts <= 0) 93 err = add_mtd_device(p->info); 94 95 return err; 96 } 97 98 static void __devexit vr_nor_destroy_mtd_setup(struct vr_nor_mtd *p) 99 { 100 map_destroy(p->info); 101 } 102 103 static int __devinit vr_nor_mtd_setup(struct vr_nor_mtd *p) 104 { 105 static const char *probe_types[] = 106 { "cfi_probe", "jedec_probe", NULL }; 107 const char **type; 108 109 for (type = probe_types; !p->info && *type; type++) 110 p->info = do_map_probe(*type, &p->map); 111 if (!p->info) 112 return -ENODEV; 113 114 p->info->owner = THIS_MODULE; 115 116 return 0; 117 } 118 119 static void __devexit vr_nor_destroy_maps(struct vr_nor_mtd *p) 120 { 121 unsigned int exp_timing_cs0; 122 123 /* write-protect the flash bank */ 124 exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0); 125 exp_timing_cs0 &= ~TIMING_WR_EN; 126 writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0); 127 128 /* unmap the flash window */ 129 iounmap(p->map.virt); 130 131 /* unmap the csr window */ 132 iounmap(p->csr_base); 133 } 134 135 /* 136 * Initialize the map_info structure and map the flash. 137 * Returns 0 on success, nonzero otherwise. 138 */ 139 static int __devinit vr_nor_init_maps(struct vr_nor_mtd *p) 140 { 141 unsigned long csr_phys, csr_len; 142 unsigned long win_phys, win_len; 143 unsigned int exp_timing_cs0; 144 int err; 145 146 csr_phys = pci_resource_start(p->dev, EXP_CSR_MBAR); 147 csr_len = pci_resource_len(p->dev, EXP_CSR_MBAR); 148 win_phys = pci_resource_start(p->dev, EXP_WIN_MBAR); 149 win_len = pci_resource_len(p->dev, EXP_WIN_MBAR); 150 151 if (!csr_phys || !csr_len || !win_phys || !win_len) 152 return -ENODEV; 153 154 if (win_len < (CS0_START + CS0_SIZE)) 155 return -ENXIO; 156 157 p->csr_base = ioremap_nocache(csr_phys, csr_len); 158 if (!p->csr_base) 159 return -ENOMEM; 160 161 exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0); 162 if (!(exp_timing_cs0 & TIMING_CS_EN)) { 163 dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 " 164 "is disabled.\n"); 165 err = -ENODEV; 166 goto release; 167 } 168 if ((exp_timing_cs0 & TIMING_MASK) == TIMING_MASK) { 169 dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 " 170 "is configured for maximally slow access times.\n"); 171 } 172 p->map.name = DRV_NAME; 173 p->map.bankwidth = (exp_timing_cs0 & TIMING_BYTE_EN) ? 1 : 2; 174 p->map.phys = win_phys + CS0_START; 175 p->map.size = CS0_SIZE; 176 p->map.virt = ioremap_nocache(p->map.phys, p->map.size); 177 if (!p->map.virt) { 178 err = -ENOMEM; 179 goto release; 180 } 181 simple_map_init(&p->map); 182 183 /* Enable writes to flash bank */ 184 exp_timing_cs0 |= TIMING_BOOT_ACCEL_DIS | TIMING_WR_EN; 185 writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0); 186 187 return 0; 188 189 release: 190 iounmap(p->csr_base); 191 return err; 192 } 193 194 static struct pci_device_id vr_nor_pci_ids[] = { 195 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x500D)}, 196 {0,} 197 }; 198 199 static void __devexit vr_nor_pci_remove(struct pci_dev *dev) 200 { 201 struct vr_nor_mtd *p = pci_get_drvdata(dev); 202 203 pci_set_drvdata(dev, NULL); 204 vr_nor_destroy_partitions(p); 205 vr_nor_destroy_mtd_setup(p); 206 vr_nor_destroy_maps(p); 207 kfree(p); 208 pci_release_regions(dev); 209 pci_disable_device(dev); 210 } 211 212 static int __devinit 213 vr_nor_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 214 { 215 struct vr_nor_mtd *p = NULL; 216 unsigned int exp_timing_cs0; 217 int err; 218 219 err = pci_enable_device(dev); 220 if (err) 221 goto out; 222 223 err = pci_request_regions(dev, DRV_NAME); 224 if (err) 225 goto disable_dev; 226 227 p = kzalloc(sizeof(*p), GFP_KERNEL); 228 err = -ENOMEM; 229 if (!p) 230 goto release; 231 232 p->dev = dev; 233 234 err = vr_nor_init_maps(p); 235 if (err) 236 goto release; 237 238 err = vr_nor_mtd_setup(p); 239 if (err) 240 goto destroy_maps; 241 242 err = vr_nor_init_partitions(p); 243 if (err) 244 goto destroy_mtd_setup; 245 246 pci_set_drvdata(dev, p); 247 248 return 0; 249 250 destroy_mtd_setup: 251 map_destroy(p->info); 252 253 destroy_maps: 254 /* write-protect the flash bank */ 255 exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0); 256 exp_timing_cs0 &= ~TIMING_WR_EN; 257 writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0); 258 259 /* unmap the flash window */ 260 iounmap(p->map.virt); 261 262 /* unmap the csr window */ 263 iounmap(p->csr_base); 264 265 release: 266 kfree(p); 267 pci_release_regions(dev); 268 269 disable_dev: 270 pci_disable_device(dev); 271 272 out: 273 return err; 274 } 275 276 static struct pci_driver vr_nor_pci_driver = { 277 .name = DRV_NAME, 278 .probe = vr_nor_pci_probe, 279 .remove = __devexit_p(vr_nor_pci_remove), 280 .id_table = vr_nor_pci_ids, 281 }; 282 283 static int __init vr_nor_mtd_init(void) 284 { 285 return pci_register_driver(&vr_nor_pci_driver); 286 } 287 288 static void __exit vr_nor_mtd_exit(void) 289 { 290 pci_unregister_driver(&vr_nor_pci_driver); 291 } 292 293 module_init(vr_nor_mtd_init); 294 module_exit(vr_nor_mtd_exit); 295 296 MODULE_AUTHOR("Andy Lowe"); 297 MODULE_DESCRIPTION("MTD map driver for NOR flash on Intel Vermilion Range"); 298 MODULE_LICENSE("GPL"); 299 MODULE_DEVICE_TABLE(pci, vr_nor_pci_ids); 300