1 /* 2 * esb2rom.c 3 * 4 * Normal mappings of flash chips in physical memory 5 * through the Intel ESB2 Southbridge. 6 * 7 * This was derived from ichxrom.c in May 2006 by 8 * Lew Glendenning <lglendenning@lnxi.com> 9 * 10 * Eric Biederman, of course, was a major help in this effort. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/types.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <asm/io.h> 18 #include <linux/mtd/mtd.h> 19 #include <linux/mtd/map.h> 20 #include <linux/mtd/cfi.h> 21 #include <linux/mtd/flashchip.h> 22 #include <linux/pci.h> 23 #include <linux/pci_ids.h> 24 #include <linux/list.h> 25 26 #define MOD_NAME KBUILD_BASENAME 27 28 #define ADDRESS_NAME_LEN 18 29 30 #define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */ 31 32 #define BIOS_CNTL 0xDC 33 #define BIOS_LOCK_ENABLE 0x02 34 #define BIOS_WRITE_ENABLE 0x01 35 36 /* This became a 16-bit register, and EN2 has disappeared */ 37 #define FWH_DEC_EN1 0xD8 38 #define FWH_F8_EN 0x8000 39 #define FWH_F0_EN 0x4000 40 #define FWH_E8_EN 0x2000 41 #define FWH_E0_EN 0x1000 42 #define FWH_D8_EN 0x0800 43 #define FWH_D0_EN 0x0400 44 #define FWH_C8_EN 0x0200 45 #define FWH_C0_EN 0x0100 46 #define FWH_LEGACY_F_EN 0x0080 47 #define FWH_LEGACY_E_EN 0x0040 48 /* reserved 0x0020 and 0x0010 */ 49 #define FWH_70_EN 0x0008 50 #define FWH_60_EN 0x0004 51 #define FWH_50_EN 0x0002 52 #define FWH_40_EN 0x0001 53 54 /* these are 32-bit values */ 55 #define FWH_SEL1 0xD0 56 #define FWH_SEL2 0xD4 57 58 #define FWH_8MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 59 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ 60 FWH_70_EN | FWH_60_EN | FWH_50_EN | FWH_40_EN) 61 62 #define FWH_7MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 63 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ 64 FWH_70_EN | FWH_60_EN | FWH_50_EN) 65 66 #define FWH_6MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 67 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ 68 FWH_70_EN | FWH_60_EN) 69 70 #define FWH_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 71 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ 72 FWH_70_EN) 73 74 #define FWH_4MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 75 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN) 76 77 #define FWH_3_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 78 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN) 79 80 #define FWH_3MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 81 FWH_D8_EN | FWH_D0_EN) 82 83 #define FWH_2_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 84 FWH_D8_EN) 85 86 #define FWH_2MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN) 87 88 #define FWH_1_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN) 89 90 #define FWH_1MiB (FWH_F8_EN | FWH_F0_EN) 91 92 #define FWH_0_5MiB (FWH_F8_EN) 93 94 95 struct esb2rom_window { 96 void __iomem* virt; 97 unsigned long phys; 98 unsigned long size; 99 struct list_head maps; 100 struct resource rsrc; 101 struct pci_dev *pdev; 102 }; 103 104 struct esb2rom_map_info { 105 struct list_head list; 106 struct map_info map; 107 struct mtd_info *mtd; 108 struct resource rsrc; 109 char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN]; 110 }; 111 112 static struct esb2rom_window esb2rom_window = { 113 .maps = LIST_HEAD_INIT(esb2rom_window.maps), 114 }; 115 116 static void esb2rom_cleanup(struct esb2rom_window *window) 117 { 118 struct esb2rom_map_info *map, *scratch; 119 u8 byte; 120 121 /* Disable writes through the rom window */ 122 pci_read_config_byte(window->pdev, BIOS_CNTL, &byte); 123 pci_write_config_byte(window->pdev, BIOS_CNTL, 124 byte & ~BIOS_WRITE_ENABLE); 125 126 /* Free all of the mtd devices */ 127 list_for_each_entry_safe(map, scratch, &window->maps, list) { 128 if (map->rsrc.parent) 129 release_resource(&map->rsrc); 130 del_mtd_device(map->mtd); 131 map_destroy(map->mtd); 132 list_del(&map->list); 133 kfree(map); 134 } 135 if (window->rsrc.parent) 136 release_resource(&window->rsrc); 137 if (window->virt) { 138 iounmap(window->virt); 139 window->virt = NULL; 140 window->phys = 0; 141 window->size = 0; 142 } 143 pci_dev_put(window->pdev); 144 } 145 146 static int __devinit esb2rom_init_one(struct pci_dev *pdev, 147 const struct pci_device_id *ent) 148 { 149 static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; 150 struct esb2rom_window *window = &esb2rom_window; 151 struct esb2rom_map_info *map = NULL; 152 unsigned long map_top; 153 u8 byte; 154 u16 word; 155 156 /* For now I just handle the ecb2 and I assume there 157 * are not a lot of resources up at the top of the address 158 * space. It is possible to handle other devices in the 159 * top 16MiB but it is very painful. Also since 160 * you can only really attach a FWH to an ICHX there 161 * a number of simplifications you can make. 162 * 163 * Also you can page firmware hubs if an 8MiB window isn't enough 164 * but don't currently handle that case either. 165 */ 166 window->pdev = pci_dev_get(pdev); 167 168 /* RLG: experiment 2. Force the window registers to the widest values */ 169 170 /* 171 pci_read_config_word(pdev, FWH_DEC_EN1, &word); 172 printk(KERN_DEBUG "Original FWH_DEC_EN1 : %x\n", word); 173 pci_write_config_byte(pdev, FWH_DEC_EN1, 0xff); 174 pci_read_config_byte(pdev, FWH_DEC_EN1, &byte); 175 printk(KERN_DEBUG "New FWH_DEC_EN1 : %x\n", byte); 176 177 pci_read_config_byte(pdev, FWH_DEC_EN2, &byte); 178 printk(KERN_DEBUG "Original FWH_DEC_EN2 : %x\n", byte); 179 pci_write_config_byte(pdev, FWH_DEC_EN2, 0x0f); 180 pci_read_config_byte(pdev, FWH_DEC_EN2, &byte); 181 printk(KERN_DEBUG "New FWH_DEC_EN2 : %x\n", byte); 182 */ 183 184 /* Find a region continuous to the end of the ROM window */ 185 window->phys = 0; 186 pci_read_config_word(pdev, FWH_DEC_EN1, &word); 187 printk(KERN_DEBUG "pci_read_config_word : %x\n", word); 188 189 if ((word & FWH_8MiB) == FWH_8MiB) 190 window->phys = 0xff400000; 191 else if ((word & FWH_7MiB) == FWH_7MiB) 192 window->phys = 0xff500000; 193 else if ((word & FWH_6MiB) == FWH_6MiB) 194 window->phys = 0xff600000; 195 else if ((word & FWH_5MiB) == FWH_5MiB) 196 window->phys = 0xFF700000; 197 else if ((word & FWH_4MiB) == FWH_4MiB) 198 window->phys = 0xffc00000; 199 else if ((word & FWH_3_5MiB) == FWH_3_5MiB) 200 window->phys = 0xffc80000; 201 else if ((word & FWH_3MiB) == FWH_3MiB) 202 window->phys = 0xffd00000; 203 else if ((word & FWH_2_5MiB) == FWH_2_5MiB) 204 window->phys = 0xffd80000; 205 else if ((word & FWH_2MiB) == FWH_2MiB) 206 window->phys = 0xffe00000; 207 else if ((word & FWH_1_5MiB) == FWH_1_5MiB) 208 window->phys = 0xffe80000; 209 else if ((word & FWH_1MiB) == FWH_1MiB) 210 window->phys = 0xfff00000; 211 else if ((word & FWH_0_5MiB) == FWH_0_5MiB) 212 window->phys = 0xfff80000; 213 214 if (window->phys == 0) { 215 printk(KERN_ERR MOD_NAME ": Rom window is closed\n"); 216 goto out; 217 } 218 219 /* reserved 0x0020 and 0x0010 */ 220 window->phys -= 0x400000UL; 221 window->size = (0xffffffffUL - window->phys) + 1UL; 222 223 /* Enable writes through the rom window */ 224 pci_read_config_byte(pdev, BIOS_CNTL, &byte); 225 if (!(byte & BIOS_WRITE_ENABLE) && (byte & (BIOS_LOCK_ENABLE))) { 226 /* The BIOS will generate an error if I enable 227 * this device, so don't even try. 228 */ 229 printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n"); 230 goto out; 231 } 232 pci_write_config_byte(pdev, BIOS_CNTL, byte | BIOS_WRITE_ENABLE); 233 234 /* 235 * Try to reserve the window mem region. If this fails then 236 * it is likely due to the window being "reseved" by the BIOS. 237 */ 238 window->rsrc.name = MOD_NAME; 239 window->rsrc.start = window->phys; 240 window->rsrc.end = window->phys + window->size - 1; 241 window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 242 if (request_resource(&iomem_resource, &window->rsrc)) { 243 window->rsrc.parent = NULL; 244 printk(KERN_DEBUG MOD_NAME 245 ": %s(): Unable to register resource" 246 " 0x%.08llx-0x%.08llx - kernel bug?\n", 247 __func__, 248 (unsigned long long)window->rsrc.start, 249 (unsigned long long)window->rsrc.end); 250 } 251 252 /* Map the firmware hub into my address space. */ 253 window->virt = ioremap_nocache(window->phys, window->size); 254 if (!window->virt) { 255 printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n", 256 window->phys, window->size); 257 goto out; 258 } 259 260 /* Get the first address to look for an rom chip at */ 261 map_top = window->phys; 262 if ((window->phys & 0x3fffff) != 0) { 263 /* if not aligned on 4MiB, look 4MiB lower in address space */ 264 map_top = window->phys + 0x400000; 265 } 266 #if 1 267 /* The probe sequence run over the firmware hub lock 268 * registers sets them to 0x7 (no access). 269 * (Insane hardware design, but most copied Intel's.) 270 * ==> Probe at most the last 4M of the address space. 271 */ 272 if (map_top < 0xffc00000) 273 map_top = 0xffc00000; 274 #endif 275 /* Loop through and look for rom chips */ 276 while ((map_top - 1) < 0xffffffffUL) { 277 struct cfi_private *cfi; 278 unsigned long offset; 279 int i; 280 281 if (!map) 282 map = kmalloc(sizeof(*map), GFP_KERNEL); 283 if (!map) { 284 printk(KERN_ERR MOD_NAME ": kmalloc failed"); 285 goto out; 286 } 287 memset(map, 0, sizeof(*map)); 288 INIT_LIST_HEAD(&map->list); 289 map->map.name = map->map_name; 290 map->map.phys = map_top; 291 offset = map_top - window->phys; 292 map->map.virt = (void __iomem *) 293 (((unsigned long)(window->virt)) + offset); 294 map->map.size = 0xffffffffUL - map_top + 1UL; 295 /* Set the name of the map to the address I am trying */ 296 sprintf(map->map_name, "%s @%08Lx", 297 MOD_NAME, (unsigned long long)map->map.phys); 298 299 /* Firmware hubs only use vpp when being programmed 300 * in a factory setting. So in-place programming 301 * needs to use a different method. 302 */ 303 for(map->map.bankwidth = 32; map->map.bankwidth; 304 map->map.bankwidth >>= 1) { 305 char **probe_type; 306 /* Skip bankwidths that are not supported */ 307 if (!map_bankwidth_supported(map->map.bankwidth)) 308 continue; 309 310 /* Setup the map methods */ 311 simple_map_init(&map->map); 312 313 /* Try all of the probe methods */ 314 probe_type = rom_probe_types; 315 for(; *probe_type; probe_type++) { 316 map->mtd = do_map_probe(*probe_type, &map->map); 317 if (map->mtd) 318 goto found; 319 } 320 } 321 map_top += ROM_PROBE_STEP_SIZE; 322 continue; 323 found: 324 /* Trim the size if we are larger than the map */ 325 if (map->mtd->size > map->map.size) { 326 printk(KERN_WARNING MOD_NAME 327 " rom(%llu) larger than window(%lu). fixing...\n", 328 (unsigned long long)map->mtd->size, map->map.size); 329 map->mtd->size = map->map.size; 330 } 331 if (window->rsrc.parent) { 332 /* 333 * Registering the MTD device in iomem may not be possible 334 * if there is a BIOS "reserved" and BUSY range. If this 335 * fails then continue anyway. 336 */ 337 map->rsrc.name = map->map_name; 338 map->rsrc.start = map->map.phys; 339 map->rsrc.end = map->map.phys + map->mtd->size - 1; 340 map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 341 if (request_resource(&window->rsrc, &map->rsrc)) { 342 printk(KERN_ERR MOD_NAME 343 ": cannot reserve MTD resource\n"); 344 map->rsrc.parent = NULL; 345 } 346 } 347 348 /* Make the whole region visible in the map */ 349 map->map.virt = window->virt; 350 map->map.phys = window->phys; 351 cfi = map->map.fldrv_priv; 352 for(i = 0; i < cfi->numchips; i++) 353 cfi->chips[i].start += offset; 354 355 /* Now that the mtd devices is complete claim and export it */ 356 map->mtd->owner = THIS_MODULE; 357 if (add_mtd_device(map->mtd)) { 358 map_destroy(map->mtd); 359 map->mtd = NULL; 360 goto out; 361 } 362 363 /* Calculate the new value of map_top */ 364 map_top += map->mtd->size; 365 366 /* File away the map structure */ 367 list_add(&map->list, &window->maps); 368 map = NULL; 369 } 370 371 out: 372 /* Free any left over map structures */ 373 kfree(map); 374 375 /* See if I have any map structures */ 376 if (list_empty(&window->maps)) { 377 esb2rom_cleanup(window); 378 return -ENODEV; 379 } 380 return 0; 381 } 382 383 static void __devexit esb2rom_remove_one (struct pci_dev *pdev) 384 { 385 struct esb2rom_window *window = &esb2rom_window; 386 esb2rom_cleanup(window); 387 } 388 389 static struct pci_device_id esb2rom_pci_tbl[] __devinitdata = { 390 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, 391 PCI_ANY_ID, PCI_ANY_ID, }, 392 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, 393 PCI_ANY_ID, PCI_ANY_ID, }, 394 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, 395 PCI_ANY_ID, PCI_ANY_ID, }, 396 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, 397 PCI_ANY_ID, PCI_ANY_ID, }, 398 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, 399 PCI_ANY_ID, PCI_ANY_ID, }, 400 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, 401 PCI_ANY_ID, PCI_ANY_ID, }, 402 { 0, }, 403 }; 404 405 #if 0 406 MODULE_DEVICE_TABLE(pci, esb2rom_pci_tbl); 407 408 static struct pci_driver esb2rom_driver = { 409 .name = MOD_NAME, 410 .id_table = esb2rom_pci_tbl, 411 .probe = esb2rom_init_one, 412 .remove = esb2rom_remove_one, 413 }; 414 #endif 415 416 static int __init init_esb2rom(void) 417 { 418 struct pci_dev *pdev; 419 struct pci_device_id *id; 420 int retVal; 421 422 pdev = NULL; 423 for (id = esb2rom_pci_tbl; id->vendor; id++) { 424 printk(KERN_DEBUG "device id = %x\n", id->device); 425 pdev = pci_get_device(id->vendor, id->device, NULL); 426 if (pdev) { 427 printk(KERN_DEBUG "matched device = %x\n", id->device); 428 break; 429 } 430 } 431 if (pdev) { 432 printk(KERN_DEBUG "matched device id %x\n", id->device); 433 retVal = esb2rom_init_one(pdev, &esb2rom_pci_tbl[0]); 434 pci_dev_put(pdev); 435 printk(KERN_DEBUG "retVal = %d\n", retVal); 436 return retVal; 437 } 438 return -ENXIO; 439 #if 0 440 return pci_register_driver(&esb2rom_driver); 441 #endif 442 } 443 444 static void __exit cleanup_esb2rom(void) 445 { 446 esb2rom_remove_one(esb2rom_window.pdev); 447 } 448 449 module_init(init_esb2rom); 450 module_exit(cleanup_esb2rom); 451 452 MODULE_LICENSE("GPL"); 453 MODULE_AUTHOR("Lew Glendenning <lglendenning@lnxi.com>"); 454 MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ESB2 southbridge"); 455