1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * esb2rom.c 4 * 5 * Normal mappings of flash chips in physical memory 6 * through the Intel ESB2 Southbridge. 7 * 8 * This was derived from ichxrom.c in May 2006 by 9 * Lew Glendenning <lglendenning@lnxi.com> 10 * 11 * Eric Biederman, of course, was a major help in this effort. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/slab.h> 19 #include <asm/io.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/map.h> 22 #include <linux/mtd/cfi.h> 23 #include <linux/mtd/flashchip.h> 24 #include <linux/pci.h> 25 #include <linux/pci_ids.h> 26 #include <linux/list.h> 27 28 #define MOD_NAME KBUILD_BASENAME 29 30 #define ADDRESS_NAME_LEN 18 31 32 #define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */ 33 34 #define BIOS_CNTL 0xDC 35 #define BIOS_LOCK_ENABLE 0x02 36 #define BIOS_WRITE_ENABLE 0x01 37 38 /* This became a 16-bit register, and EN2 has disappeared */ 39 #define FWH_DEC_EN1 0xD8 40 #define FWH_F8_EN 0x8000 41 #define FWH_F0_EN 0x4000 42 #define FWH_E8_EN 0x2000 43 #define FWH_E0_EN 0x1000 44 #define FWH_D8_EN 0x0800 45 #define FWH_D0_EN 0x0400 46 #define FWH_C8_EN 0x0200 47 #define FWH_C0_EN 0x0100 48 #define FWH_LEGACY_F_EN 0x0080 49 #define FWH_LEGACY_E_EN 0x0040 50 /* reserved 0x0020 and 0x0010 */ 51 #define FWH_70_EN 0x0008 52 #define FWH_60_EN 0x0004 53 #define FWH_50_EN 0x0002 54 #define FWH_40_EN 0x0001 55 56 /* these are 32-bit values */ 57 #define FWH_SEL1 0xD0 58 #define FWH_SEL2 0xD4 59 60 #define FWH_8MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 61 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ 62 FWH_70_EN | FWH_60_EN | FWH_50_EN | FWH_40_EN) 63 64 #define FWH_7MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 65 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ 66 FWH_70_EN | FWH_60_EN | FWH_50_EN) 67 68 #define FWH_6MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 69 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ 70 FWH_70_EN | FWH_60_EN) 71 72 #define FWH_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 73 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN | \ 74 FWH_70_EN) 75 76 #define FWH_4MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 77 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN | FWH_C0_EN) 78 79 #define FWH_3_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 80 FWH_D8_EN | FWH_D0_EN | FWH_C8_EN) 81 82 #define FWH_3MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 83 FWH_D8_EN | FWH_D0_EN) 84 85 #define FWH_2_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN | \ 86 FWH_D8_EN) 87 88 #define FWH_2MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN | FWH_E0_EN) 89 90 #define FWH_1_5MiB (FWH_F8_EN | FWH_F0_EN | FWH_E8_EN) 91 92 #define FWH_1MiB (FWH_F8_EN | FWH_F0_EN) 93 94 #define FWH_0_5MiB (FWH_F8_EN) 95 96 97 struct esb2rom_window { 98 void __iomem* virt; 99 unsigned long phys; 100 unsigned long size; 101 struct list_head maps; 102 struct resource rsrc; 103 struct pci_dev *pdev; 104 }; 105 106 struct esb2rom_map_info { 107 struct list_head list; 108 struct map_info map; 109 struct mtd_info *mtd; 110 struct resource rsrc; 111 char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN]; 112 }; 113 114 static struct esb2rom_window esb2rom_window = { 115 .maps = LIST_HEAD_INIT(esb2rom_window.maps), 116 }; 117 118 static void esb2rom_cleanup(struct esb2rom_window *window) 119 { 120 struct esb2rom_map_info *map, *scratch; 121 u8 byte; 122 123 /* Disable writes through the rom window */ 124 pci_read_config_byte(window->pdev, BIOS_CNTL, &byte); 125 pci_write_config_byte(window->pdev, BIOS_CNTL, 126 byte & ~BIOS_WRITE_ENABLE); 127 128 /* Free all of the mtd devices */ 129 list_for_each_entry_safe(map, scratch, &window->maps, list) { 130 if (map->rsrc.parent) 131 release_resource(&map->rsrc); 132 mtd_device_unregister(map->mtd); 133 map_destroy(map->mtd); 134 list_del(&map->list); 135 kfree(map); 136 } 137 if (window->rsrc.parent) 138 release_resource(&window->rsrc); 139 if (window->virt) { 140 iounmap(window->virt); 141 window->virt = NULL; 142 window->phys = 0; 143 window->size = 0; 144 } 145 pci_dev_put(window->pdev); 146 } 147 148 static int __init esb2rom_init_one(struct pci_dev *pdev, 149 const struct pci_device_id *ent) 150 { 151 static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; 152 struct esb2rom_window *window = &esb2rom_window; 153 struct esb2rom_map_info *map = NULL; 154 unsigned long map_top; 155 u8 byte; 156 u16 word; 157 158 /* For now I just handle the ecb2 and I assume there 159 * are not a lot of resources up at the top of the address 160 * space. It is possible to handle other devices in the 161 * top 16MiB but it is very painful. Also since 162 * you can only really attach a FWH to an ICHX there 163 * a number of simplifications you can make. 164 * 165 * Also you can page firmware hubs if an 8MiB window isn't enough 166 * but don't currently handle that case either. 167 */ 168 window->pdev = pci_dev_get(pdev); 169 170 /* RLG: experiment 2. Force the window registers to the widest values */ 171 172 /* 173 pci_read_config_word(pdev, FWH_DEC_EN1, &word); 174 printk(KERN_DEBUG "Original FWH_DEC_EN1 : %x\n", word); 175 pci_write_config_byte(pdev, FWH_DEC_EN1, 0xff); 176 pci_read_config_byte(pdev, FWH_DEC_EN1, &byte); 177 printk(KERN_DEBUG "New FWH_DEC_EN1 : %x\n", byte); 178 179 pci_read_config_byte(pdev, FWH_DEC_EN2, &byte); 180 printk(KERN_DEBUG "Original FWH_DEC_EN2 : %x\n", byte); 181 pci_write_config_byte(pdev, FWH_DEC_EN2, 0x0f); 182 pci_read_config_byte(pdev, FWH_DEC_EN2, &byte); 183 printk(KERN_DEBUG "New FWH_DEC_EN2 : %x\n", byte); 184 */ 185 186 /* Find a region continuous to the end of the ROM window */ 187 window->phys = 0; 188 pci_read_config_word(pdev, FWH_DEC_EN1, &word); 189 printk(KERN_DEBUG "pci_read_config_word : %x\n", word); 190 191 if ((word & FWH_8MiB) == FWH_8MiB) 192 window->phys = 0xff400000; 193 else if ((word & FWH_7MiB) == FWH_7MiB) 194 window->phys = 0xff500000; 195 else if ((word & FWH_6MiB) == FWH_6MiB) 196 window->phys = 0xff600000; 197 else if ((word & FWH_5MiB) == FWH_5MiB) 198 window->phys = 0xFF700000; 199 else if ((word & FWH_4MiB) == FWH_4MiB) 200 window->phys = 0xffc00000; 201 else if ((word & FWH_3_5MiB) == FWH_3_5MiB) 202 window->phys = 0xffc80000; 203 else if ((word & FWH_3MiB) == FWH_3MiB) 204 window->phys = 0xffd00000; 205 else if ((word & FWH_2_5MiB) == FWH_2_5MiB) 206 window->phys = 0xffd80000; 207 else if ((word & FWH_2MiB) == FWH_2MiB) 208 window->phys = 0xffe00000; 209 else if ((word & FWH_1_5MiB) == FWH_1_5MiB) 210 window->phys = 0xffe80000; 211 else if ((word & FWH_1MiB) == FWH_1MiB) 212 window->phys = 0xfff00000; 213 else if ((word & FWH_0_5MiB) == FWH_0_5MiB) 214 window->phys = 0xfff80000; 215 216 if (window->phys == 0) { 217 printk(KERN_ERR MOD_NAME ": Rom window is closed\n"); 218 goto out; 219 } 220 221 /* reserved 0x0020 and 0x0010 */ 222 window->phys -= 0x400000UL; 223 window->size = (0xffffffffUL - window->phys) + 1UL; 224 225 /* Enable writes through the rom window */ 226 pci_read_config_byte(pdev, BIOS_CNTL, &byte); 227 if (!(byte & BIOS_WRITE_ENABLE) && (byte & (BIOS_LOCK_ENABLE))) { 228 /* The BIOS will generate an error if I enable 229 * this device, so don't even try. 230 */ 231 printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n"); 232 goto out; 233 } 234 pci_write_config_byte(pdev, BIOS_CNTL, byte | BIOS_WRITE_ENABLE); 235 236 /* 237 * Try to reserve the window mem region. If this fails then 238 * it is likely due to the window being "reserved" by the BIOS. 239 */ 240 window->rsrc.name = MOD_NAME; 241 window->rsrc.start = window->phys; 242 window->rsrc.end = window->phys + window->size - 1; 243 window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 244 if (request_resource(&iomem_resource, &window->rsrc)) { 245 window->rsrc.parent = NULL; 246 printk(KERN_DEBUG MOD_NAME ": " 247 "%s(): Unable to register resource %pR - kernel bug?\n", 248 __func__, &window->rsrc); 249 } 250 251 /* Map the firmware hub into my address space. */ 252 window->virt = ioremap_nocache(window->phys, window->size); 253 if (!window->virt) { 254 printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n", 255 window->phys, window->size); 256 goto out; 257 } 258 259 /* Get the first address to look for an rom chip at */ 260 map_top = window->phys; 261 if ((window->phys & 0x3fffff) != 0) { 262 /* if not aligned on 4MiB, look 4MiB lower in address space */ 263 map_top = window->phys + 0x400000; 264 } 265 #if 1 266 /* The probe sequence run over the firmware hub lock 267 * registers sets them to 0x7 (no access). 268 * (Insane hardware design, but most copied Intel's.) 269 * ==> Probe at most the last 4M of the address space. 270 */ 271 if (map_top < 0xffc00000) 272 map_top = 0xffc00000; 273 #endif 274 /* Loop through and look for rom chips */ 275 while ((map_top - 1) < 0xffffffffUL) { 276 struct cfi_private *cfi; 277 unsigned long offset; 278 int i; 279 280 if (!map) 281 map = kmalloc(sizeof(*map), GFP_KERNEL); 282 if (!map) { 283 printk(KERN_ERR MOD_NAME ": kmalloc failed"); 284 goto out; 285 } 286 memset(map, 0, sizeof(*map)); 287 INIT_LIST_HEAD(&map->list); 288 map->map.name = map->map_name; 289 map->map.phys = map_top; 290 offset = map_top - window->phys; 291 map->map.virt = (void __iomem *) 292 (((unsigned long)(window->virt)) + offset); 293 map->map.size = 0xffffffffUL - map_top + 1UL; 294 /* Set the name of the map to the address I am trying */ 295 sprintf(map->map_name, "%s @%08Lx", 296 MOD_NAME, (unsigned long long)map->map.phys); 297 298 /* Firmware hubs only use vpp when being programmed 299 * in a factory setting. So in-place programming 300 * needs to use a different method. 301 */ 302 for(map->map.bankwidth = 32; map->map.bankwidth; 303 map->map.bankwidth >>= 1) { 304 char **probe_type; 305 /* Skip bankwidths that are not supported */ 306 if (!map_bankwidth_supported(map->map.bankwidth)) 307 continue; 308 309 /* Setup the map methods */ 310 simple_map_init(&map->map); 311 312 /* Try all of the probe methods */ 313 probe_type = rom_probe_types; 314 for(; *probe_type; probe_type++) { 315 map->mtd = do_map_probe(*probe_type, &map->map); 316 if (map->mtd) 317 goto found; 318 } 319 } 320 map_top += ROM_PROBE_STEP_SIZE; 321 continue; 322 found: 323 /* Trim the size if we are larger than the map */ 324 if (map->mtd->size > map->map.size) { 325 printk(KERN_WARNING MOD_NAME 326 " rom(%llu) larger than window(%lu). fixing...\n", 327 (unsigned long long)map->mtd->size, map->map.size); 328 map->mtd->size = map->map.size; 329 } 330 if (window->rsrc.parent) { 331 /* 332 * Registering the MTD device in iomem may not be possible 333 * if there is a BIOS "reserved" and BUSY range. If this 334 * fails then continue anyway. 335 */ 336 map->rsrc.name = map->map_name; 337 map->rsrc.start = map->map.phys; 338 map->rsrc.end = map->map.phys + map->mtd->size - 1; 339 map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 340 if (request_resource(&window->rsrc, &map->rsrc)) { 341 printk(KERN_ERR MOD_NAME 342 ": cannot reserve MTD resource\n"); 343 map->rsrc.parent = NULL; 344 } 345 } 346 347 /* Make the whole region visible in the map */ 348 map->map.virt = window->virt; 349 map->map.phys = window->phys; 350 cfi = map->map.fldrv_priv; 351 for(i = 0; i < cfi->numchips; i++) 352 cfi->chips[i].start += offset; 353 354 /* Now that the mtd devices is complete claim and export it */ 355 map->mtd->owner = THIS_MODULE; 356 if (mtd_device_register(map->mtd, NULL, 0)) { 357 map_destroy(map->mtd); 358 map->mtd = NULL; 359 goto out; 360 } 361 362 /* Calculate the new value of map_top */ 363 map_top += map->mtd->size; 364 365 /* File away the map structure */ 366 list_add(&map->list, &window->maps); 367 map = NULL; 368 } 369 370 out: 371 /* Free any left over map structures */ 372 kfree(map); 373 374 /* See if I have any map structures */ 375 if (list_empty(&window->maps)) { 376 esb2rom_cleanup(window); 377 return -ENODEV; 378 } 379 return 0; 380 } 381 382 static void esb2rom_remove_one(struct pci_dev *pdev) 383 { 384 struct esb2rom_window *window = &esb2rom_window; 385 esb2rom_cleanup(window); 386 } 387 388 static const struct pci_device_id esb2rom_pci_tbl[] = { 389 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, 390 PCI_ANY_ID, PCI_ANY_ID, }, 391 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, 392 PCI_ANY_ID, PCI_ANY_ID, }, 393 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, 394 PCI_ANY_ID, PCI_ANY_ID, }, 395 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, 396 PCI_ANY_ID, PCI_ANY_ID, }, 397 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, 398 PCI_ANY_ID, PCI_ANY_ID, }, 399 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, 400 PCI_ANY_ID, PCI_ANY_ID, }, 401 { 0, }, 402 }; 403 404 #if 0 405 MODULE_DEVICE_TABLE(pci, esb2rom_pci_tbl); 406 407 static struct pci_driver esb2rom_driver = { 408 .name = MOD_NAME, 409 .id_table = esb2rom_pci_tbl, 410 .probe = esb2rom_init_one, 411 .remove = esb2rom_remove_one, 412 }; 413 #endif 414 415 static int __init init_esb2rom(void) 416 { 417 struct pci_dev *pdev; 418 const struct pci_device_id *id; 419 int retVal; 420 421 pdev = NULL; 422 for (id = esb2rom_pci_tbl; id->vendor; id++) { 423 printk(KERN_DEBUG "device id = %x\n", id->device); 424 pdev = pci_get_device(id->vendor, id->device, NULL); 425 if (pdev) { 426 printk(KERN_DEBUG "matched device = %x\n", id->device); 427 break; 428 } 429 } 430 if (pdev) { 431 printk(KERN_DEBUG "matched device id %x\n", id->device); 432 retVal = esb2rom_init_one(pdev, &esb2rom_pci_tbl[0]); 433 pci_dev_put(pdev); 434 printk(KERN_DEBUG "retVal = %d\n", retVal); 435 return retVal; 436 } 437 return -ENXIO; 438 #if 0 439 return pci_register_driver(&esb2rom_driver); 440 #endif 441 } 442 443 static void __exit cleanup_esb2rom(void) 444 { 445 esb2rom_remove_one(esb2rom_window.pdev); 446 } 447 448 module_init(init_esb2rom); 449 module_exit(cleanup_esb2rom); 450 451 MODULE_LICENSE("GPL"); 452 MODULE_AUTHOR("Lew Glendenning <lglendenning@lnxi.com>"); 453 MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ESB2 southbridge"); 454