1 /* 2 * ck804xrom.c 3 * 4 * Normal mappings of chips in physical memory 5 * 6 * Dave Olsen <dolsen@lnxi.com> 7 * Ryan Jackson <rjackson@lnxi.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/types.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <asm/io.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/map.h> 18 #include <linux/mtd/cfi.h> 19 #include <linux/mtd/flashchip.h> 20 #include <linux/pci.h> 21 #include <linux/pci_ids.h> 22 #include <linux/list.h> 23 24 25 #define MOD_NAME KBUILD_BASENAME 26 27 #define ADDRESS_NAME_LEN 18 28 29 #define ROM_PROBE_STEP_SIZE (64*1024) 30 31 #define DEV_CK804 1 32 #define DEV_MCP55 2 33 34 struct ck804xrom_window { 35 void __iomem *virt; 36 unsigned long phys; 37 unsigned long size; 38 struct list_head maps; 39 struct resource rsrc; 40 struct pci_dev *pdev; 41 }; 42 43 struct ck804xrom_map_info { 44 struct list_head list; 45 struct map_info map; 46 struct mtd_info *mtd; 47 struct resource rsrc; 48 char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN]; 49 }; 50 51 /* 52 * The following applies to ck804 only: 53 * The 2 bits controlling the window size are often set to allow reading 54 * the BIOS, but too small to allow writing, since the lock registers are 55 * 4MiB lower in the address space than the data. 56 * 57 * This is intended to prevent flashing the bios, perhaps accidentally. 58 * 59 * This parameter allows the normal driver to override the BIOS settings. 60 * 61 * The bits are 6 and 7. If both bits are set, it is a 5MiB window. 62 * If only the 7 Bit is set, it is a 4MiB window. Otherwise, a 63 * 64KiB window. 64 * 65 * The following applies to mcp55 only: 66 * The 15 bits controlling the window size are distributed as follows: 67 * byte @0x88: bit 0..7 68 * byte @0x8c: bit 8..15 69 * word @0x90: bit 16..30 70 * If all bits are enabled, we have a 16? MiB window 71 * Please set win_size_bits to 0x7fffffff if you actually want to do something 72 */ 73 static uint win_size_bits = 0; 74 module_param(win_size_bits, uint, 0); 75 MODULE_PARM_DESC(win_size_bits, "ROM window size bits override, normally set by BIOS."); 76 77 static struct ck804xrom_window ck804xrom_window = { 78 .maps = LIST_HEAD_INIT(ck804xrom_window.maps), 79 }; 80 81 static void ck804xrom_cleanup(struct ck804xrom_window *window) 82 { 83 struct ck804xrom_map_info *map, *scratch; 84 u8 byte; 85 86 if (window->pdev) { 87 /* Disable writes through the rom window */ 88 pci_read_config_byte(window->pdev, 0x6d, &byte); 89 pci_write_config_byte(window->pdev, 0x6d, byte & ~1); 90 } 91 92 /* Free all of the mtd devices */ 93 list_for_each_entry_safe(map, scratch, &window->maps, list) { 94 if (map->rsrc.parent) 95 release_resource(&map->rsrc); 96 97 mtd_device_unregister(map->mtd); 98 map_destroy(map->mtd); 99 list_del(&map->list); 100 kfree(map); 101 } 102 if (window->rsrc.parent) 103 release_resource(&window->rsrc); 104 105 if (window->virt) { 106 iounmap(window->virt); 107 window->virt = NULL; 108 window->phys = 0; 109 window->size = 0; 110 } 111 pci_dev_put(window->pdev); 112 } 113 114 115 static int __init ck804xrom_init_one(struct pci_dev *pdev, 116 const struct pci_device_id *ent) 117 { 118 static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; 119 u8 byte; 120 u16 word; 121 struct ck804xrom_window *window = &ck804xrom_window; 122 struct ck804xrom_map_info *map = NULL; 123 unsigned long map_top; 124 125 /* Remember the pci dev I find the window in */ 126 window->pdev = pci_dev_get(pdev); 127 128 switch (ent->driver_data) { 129 case DEV_CK804: 130 /* Enable the selected rom window. This is often incorrectly 131 * set up by the BIOS, and the 4MiB offset for the lock registers 132 * requires the full 5MiB of window space. 133 * 134 * This 'write, then read' approach leaves the bits for 135 * other uses of the hardware info. 136 */ 137 pci_read_config_byte(pdev, 0x88, &byte); 138 pci_write_config_byte(pdev, 0x88, byte | win_size_bits ); 139 140 /* Assume the rom window is properly setup, and find it's size */ 141 pci_read_config_byte(pdev, 0x88, &byte); 142 143 if ((byte & ((1<<7)|(1<<6))) == ((1<<7)|(1<<6))) 144 window->phys = 0xffb00000; /* 5MiB */ 145 else if ((byte & (1<<7)) == (1<<7)) 146 window->phys = 0xffc00000; /* 4MiB */ 147 else 148 window->phys = 0xffff0000; /* 64KiB */ 149 break; 150 151 case DEV_MCP55: 152 pci_read_config_byte(pdev, 0x88, &byte); 153 pci_write_config_byte(pdev, 0x88, byte | (win_size_bits & 0xff)); 154 155 pci_read_config_byte(pdev, 0x8c, &byte); 156 pci_write_config_byte(pdev, 0x8c, byte | ((win_size_bits & 0xff00) >> 8)); 157 158 pci_read_config_word(pdev, 0x90, &word); 159 pci_write_config_word(pdev, 0x90, word | ((win_size_bits & 0x7fff0000) >> 16)); 160 161 window->phys = 0xff000000; /* 16MiB, hardcoded for now */ 162 break; 163 } 164 165 window->size = 0xffffffffUL - window->phys + 1UL; 166 167 /* 168 * Try to reserve the window mem region. If this fails then 169 * it is likely due to a fragment of the window being 170 * "reserved" by the BIOS. In the case that the 171 * request_mem_region() fails then once the rom size is 172 * discovered we will try to reserve the unreserved fragment. 173 */ 174 window->rsrc.name = MOD_NAME; 175 window->rsrc.start = window->phys; 176 window->rsrc.end = window->phys + window->size - 1; 177 window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 178 if (request_resource(&iomem_resource, &window->rsrc)) { 179 window->rsrc.parent = NULL; 180 printk(KERN_ERR MOD_NAME 181 " %s(): Unable to register resource %pR - kernel bug?\n", 182 __func__, &window->rsrc); 183 } 184 185 186 /* Enable writes through the rom window */ 187 pci_read_config_byte(pdev, 0x6d, &byte); 188 pci_write_config_byte(pdev, 0x6d, byte | 1); 189 190 /* FIXME handle registers 0x80 - 0x8C the bios region locks */ 191 192 /* For write accesses caches are useless */ 193 window->virt = ioremap_nocache(window->phys, window->size); 194 if (!window->virt) { 195 printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n", 196 window->phys, window->size); 197 goto out; 198 } 199 200 /* Get the first address to look for a rom chip at */ 201 map_top = window->phys; 202 #if 1 203 /* The probe sequence run over the firmware hub lock 204 * registers sets them to 0x7 (no access). 205 * Probe at most the last 4MiB of the address space. 206 */ 207 if (map_top < 0xffc00000) 208 map_top = 0xffc00000; 209 #endif 210 /* Loop through and look for rom chips. Since we don't know the 211 * starting address for each chip, probe every ROM_PROBE_STEP_SIZE 212 * bytes from the starting address of the window. 213 */ 214 while((map_top - 1) < 0xffffffffUL) { 215 struct cfi_private *cfi; 216 unsigned long offset; 217 int i; 218 219 if (!map) 220 map = kmalloc(sizeof(*map), GFP_KERNEL); 221 222 if (!map) { 223 printk(KERN_ERR MOD_NAME ": kmalloc failed"); 224 goto out; 225 } 226 memset(map, 0, sizeof(*map)); 227 INIT_LIST_HEAD(&map->list); 228 map->map.name = map->map_name; 229 map->map.phys = map_top; 230 offset = map_top - window->phys; 231 map->map.virt = (void __iomem *) 232 (((unsigned long)(window->virt)) + offset); 233 map->map.size = 0xffffffffUL - map_top + 1UL; 234 /* Set the name of the map to the address I am trying */ 235 sprintf(map->map_name, "%s @%08Lx", 236 MOD_NAME, (unsigned long long)map->map.phys); 237 238 /* There is no generic VPP support */ 239 for(map->map.bankwidth = 32; map->map.bankwidth; 240 map->map.bankwidth >>= 1) 241 { 242 char **probe_type; 243 /* Skip bankwidths that are not supported */ 244 if (!map_bankwidth_supported(map->map.bankwidth)) 245 continue; 246 247 /* Setup the map methods */ 248 simple_map_init(&map->map); 249 250 /* Try all of the probe methods */ 251 probe_type = rom_probe_types; 252 for(; *probe_type; probe_type++) { 253 map->mtd = do_map_probe(*probe_type, &map->map); 254 if (map->mtd) 255 goto found; 256 } 257 } 258 map_top += ROM_PROBE_STEP_SIZE; 259 continue; 260 found: 261 /* Trim the size if we are larger than the map */ 262 if (map->mtd->size > map->map.size) { 263 printk(KERN_WARNING MOD_NAME 264 " rom(%llu) larger than window(%lu). fixing...\n", 265 (unsigned long long)map->mtd->size, map->map.size); 266 map->mtd->size = map->map.size; 267 } 268 if (window->rsrc.parent) { 269 /* 270 * Registering the MTD device in iomem may not be possible 271 * if there is a BIOS "reserved" and BUSY range. If this 272 * fails then continue anyway. 273 */ 274 map->rsrc.name = map->map_name; 275 map->rsrc.start = map->map.phys; 276 map->rsrc.end = map->map.phys + map->mtd->size - 1; 277 map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 278 if (request_resource(&window->rsrc, &map->rsrc)) { 279 printk(KERN_ERR MOD_NAME 280 ": cannot reserve MTD resource\n"); 281 map->rsrc.parent = NULL; 282 } 283 } 284 285 /* Make the whole region visible in the map */ 286 map->map.virt = window->virt; 287 map->map.phys = window->phys; 288 cfi = map->map.fldrv_priv; 289 for(i = 0; i < cfi->numchips; i++) 290 cfi->chips[i].start += offset; 291 292 /* Now that the mtd devices is complete claim and export it */ 293 map->mtd->owner = THIS_MODULE; 294 if (mtd_device_register(map->mtd, NULL, 0)) { 295 map_destroy(map->mtd); 296 map->mtd = NULL; 297 goto out; 298 } 299 300 301 /* Calculate the new value of map_top */ 302 map_top += map->mtd->size; 303 304 /* File away the map structure */ 305 list_add(&map->list, &window->maps); 306 map = NULL; 307 } 308 309 out: 310 /* Free any left over map structures */ 311 kfree(map); 312 313 /* See if I have any map structures */ 314 if (list_empty(&window->maps)) { 315 ck804xrom_cleanup(window); 316 return -ENODEV; 317 } 318 return 0; 319 } 320 321 322 static void ck804xrom_remove_one(struct pci_dev *pdev) 323 { 324 struct ck804xrom_window *window = &ck804xrom_window; 325 326 ck804xrom_cleanup(window); 327 } 328 329 static const struct pci_device_id ck804xrom_pci_tbl[] = { 330 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0051), .driver_data = DEV_CK804 }, 331 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0360), .driver_data = DEV_MCP55 }, 332 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0361), .driver_data = DEV_MCP55 }, 333 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0362), .driver_data = DEV_MCP55 }, 334 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0363), .driver_data = DEV_MCP55 }, 335 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0364), .driver_data = DEV_MCP55 }, 336 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0365), .driver_data = DEV_MCP55 }, 337 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0366), .driver_data = DEV_MCP55 }, 338 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0367), .driver_data = DEV_MCP55 }, 339 { 0, } 340 }; 341 342 #if 0 343 MODULE_DEVICE_TABLE(pci, ck804xrom_pci_tbl); 344 345 static struct pci_driver ck804xrom_driver = { 346 .name = MOD_NAME, 347 .id_table = ck804xrom_pci_tbl, 348 .probe = ck804xrom_init_one, 349 .remove = ck804xrom_remove_one, 350 }; 351 #endif 352 353 static int __init init_ck804xrom(void) 354 { 355 struct pci_dev *pdev; 356 const struct pci_device_id *id; 357 int retVal; 358 pdev = NULL; 359 360 for(id = ck804xrom_pci_tbl; id->vendor; id++) { 361 pdev = pci_get_device(id->vendor, id->device, NULL); 362 if (pdev) 363 break; 364 } 365 if (pdev) { 366 retVal = ck804xrom_init_one(pdev, id); 367 pci_dev_put(pdev); 368 return retVal; 369 } 370 return -ENXIO; 371 #if 0 372 return pci_register_driver(&ck804xrom_driver); 373 #endif 374 } 375 376 static void __exit cleanup_ck804xrom(void) 377 { 378 ck804xrom_remove_one(ck804xrom_window.pdev); 379 } 380 381 module_init(init_ck804xrom); 382 module_exit(cleanup_ck804xrom); 383 384 MODULE_LICENSE("GPL"); 385 MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>, Dave Olsen <dolsen@lnxi.com>"); 386 MODULE_DESCRIPTION("MTD map driver for BIOS chips on the Nvidia ck804 southbridge"); 387 388