1 /* 2 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller 3 * 4 * Author: Angus Clark <angus.clark@st.com> 5 * 6 * Copyright (C) 2010-2014 STMicroelectronics Limited 7 * 8 * JEDEC probe based on drivers/mtd/devices/m25p80.c 9 * 10 * This code is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 */ 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/regmap.h> 18 #include <linux/platform_device.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/partitions.h> 22 #include <linux/mtd/spi-nor.h> 23 #include <linux/sched.h> 24 #include <linux/delay.h> 25 #include <linux/io.h> 26 #include <linux/of.h> 27 28 #include "serial_flash_cmds.h" 29 30 /* 31 * FSM SPI Controller Registers 32 */ 33 #define SPI_CLOCKDIV 0x0010 34 #define SPI_MODESELECT 0x0018 35 #define SPI_CONFIGDATA 0x0020 36 #define SPI_STA_MODE_CHANGE 0x0028 37 #define SPI_FAST_SEQ_TRANSFER_SIZE 0x0100 38 #define SPI_FAST_SEQ_ADD1 0x0104 39 #define SPI_FAST_SEQ_ADD2 0x0108 40 #define SPI_FAST_SEQ_ADD_CFG 0x010c 41 #define SPI_FAST_SEQ_OPC1 0x0110 42 #define SPI_FAST_SEQ_OPC2 0x0114 43 #define SPI_FAST_SEQ_OPC3 0x0118 44 #define SPI_FAST_SEQ_OPC4 0x011c 45 #define SPI_FAST_SEQ_OPC5 0x0120 46 #define SPI_MODE_BITS 0x0124 47 #define SPI_DUMMY_BITS 0x0128 48 #define SPI_FAST_SEQ_FLASH_STA_DATA 0x012c 49 #define SPI_FAST_SEQ_1 0x0130 50 #define SPI_FAST_SEQ_2 0x0134 51 #define SPI_FAST_SEQ_3 0x0138 52 #define SPI_FAST_SEQ_4 0x013c 53 #define SPI_FAST_SEQ_CFG 0x0140 54 #define SPI_FAST_SEQ_STA 0x0144 55 #define SPI_QUAD_BOOT_SEQ_INIT_1 0x0148 56 #define SPI_QUAD_BOOT_SEQ_INIT_2 0x014c 57 #define SPI_QUAD_BOOT_READ_SEQ_1 0x0150 58 #define SPI_QUAD_BOOT_READ_SEQ_2 0x0154 59 #define SPI_PROGRAM_ERASE_TIME 0x0158 60 #define SPI_MULT_PAGE_REPEAT_SEQ_1 0x015c 61 #define SPI_MULT_PAGE_REPEAT_SEQ_2 0x0160 62 #define SPI_STATUS_WR_TIME_REG 0x0164 63 #define SPI_FAST_SEQ_DATA_REG 0x0300 64 65 /* 66 * Register: SPI_MODESELECT 67 */ 68 #define SPI_MODESELECT_CONTIG 0x01 69 #define SPI_MODESELECT_FASTREAD 0x02 70 #define SPI_MODESELECT_DUALIO 0x04 71 #define SPI_MODESELECT_FSM 0x08 72 #define SPI_MODESELECT_QUADBOOT 0x10 73 74 /* 75 * Register: SPI_CONFIGDATA 76 */ 77 #define SPI_CFG_DEVICE_ST 0x1 78 #define SPI_CFG_DEVICE_ATMEL 0x4 79 #define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0xfff) << 4) 80 #define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16) 81 #define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24) 82 83 #define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0x0AA) 84 #define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0xA0) 85 #define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0x00) 86 87 /* 88 * Register: SPI_FAST_SEQ_TRANSFER_SIZE 89 */ 90 #define TRANSFER_SIZE(x) ((x) * 8) 91 92 /* 93 * Register: SPI_FAST_SEQ_ADD_CFG 94 */ 95 #define ADR_CFG_CYCLES_ADD1(x) ((x) << 0) 96 #define ADR_CFG_PADS_1_ADD1 (0x0 << 6) 97 #define ADR_CFG_PADS_2_ADD1 (0x1 << 6) 98 #define ADR_CFG_PADS_4_ADD1 (0x3 << 6) 99 #define ADR_CFG_CSDEASSERT_ADD1 (1 << 8) 100 #define ADR_CFG_CYCLES_ADD2(x) ((x) << (0+16)) 101 #define ADR_CFG_PADS_1_ADD2 (0x0 << (6+16)) 102 #define ADR_CFG_PADS_2_ADD2 (0x1 << (6+16)) 103 #define ADR_CFG_PADS_4_ADD2 (0x3 << (6+16)) 104 #define ADR_CFG_CSDEASSERT_ADD2 (1 << (8+16)) 105 106 /* 107 * Register: SPI_FAST_SEQ_n 108 */ 109 #define SEQ_OPC_OPCODE(x) ((x) << 0) 110 #define SEQ_OPC_CYCLES(x) ((x) << 8) 111 #define SEQ_OPC_PADS_1 (0x0 << 14) 112 #define SEQ_OPC_PADS_2 (0x1 << 14) 113 #define SEQ_OPC_PADS_4 (0x3 << 14) 114 #define SEQ_OPC_CSDEASSERT (1 << 16) 115 116 /* 117 * Register: SPI_FAST_SEQ_CFG 118 */ 119 #define SEQ_CFG_STARTSEQ (1 << 0) 120 #define SEQ_CFG_SWRESET (1 << 5) 121 #define SEQ_CFG_CSDEASSERT (1 << 6) 122 #define SEQ_CFG_READNOTWRITE (1 << 7) 123 #define SEQ_CFG_ERASE (1 << 8) 124 #define SEQ_CFG_PADS_1 (0x0 << 16) 125 #define SEQ_CFG_PADS_2 (0x1 << 16) 126 #define SEQ_CFG_PADS_4 (0x3 << 16) 127 128 /* 129 * Register: SPI_MODE_BITS 130 */ 131 #define MODE_DATA(x) (x & 0xff) 132 #define MODE_CYCLES(x) ((x & 0x3f) << 16) 133 #define MODE_PADS_1 (0x0 << 22) 134 #define MODE_PADS_2 (0x1 << 22) 135 #define MODE_PADS_4 (0x3 << 22) 136 #define DUMMY_CSDEASSERT (1 << 24) 137 138 /* 139 * Register: SPI_DUMMY_BITS 140 */ 141 #define DUMMY_CYCLES(x) ((x & 0x3f) << 16) 142 #define DUMMY_PADS_1 (0x0 << 22) 143 #define DUMMY_PADS_2 (0x1 << 22) 144 #define DUMMY_PADS_4 (0x3 << 22) 145 #define DUMMY_CSDEASSERT (1 << 24) 146 147 /* 148 * Register: SPI_FAST_SEQ_FLASH_STA_DATA 149 */ 150 #define STA_DATA_BYTE1(x) ((x & 0xff) << 0) 151 #define STA_DATA_BYTE2(x) ((x & 0xff) << 8) 152 #define STA_PADS_1 (0x0 << 16) 153 #define STA_PADS_2 (0x1 << 16) 154 #define STA_PADS_4 (0x3 << 16) 155 #define STA_CSDEASSERT (0x1 << 20) 156 #define STA_RDNOTWR (0x1 << 21) 157 158 /* 159 * FSM SPI Instruction Opcodes 160 */ 161 #define STFSM_OPC_CMD 0x1 162 #define STFSM_OPC_ADD 0x2 163 #define STFSM_OPC_STA 0x3 164 #define STFSM_OPC_MODE 0x4 165 #define STFSM_OPC_DUMMY 0x5 166 #define STFSM_OPC_DATA 0x6 167 #define STFSM_OPC_WAIT 0x7 168 #define STFSM_OPC_JUMP 0x8 169 #define STFSM_OPC_GOTO 0x9 170 #define STFSM_OPC_STOP 0xF 171 172 /* 173 * FSM SPI Instructions (== opcode + operand). 174 */ 175 #define STFSM_INSTR(cmd, op) ((cmd) | ((op) << 4)) 176 177 #define STFSM_INST_CMD1 STFSM_INSTR(STFSM_OPC_CMD, 1) 178 #define STFSM_INST_CMD2 STFSM_INSTR(STFSM_OPC_CMD, 2) 179 #define STFSM_INST_CMD3 STFSM_INSTR(STFSM_OPC_CMD, 3) 180 #define STFSM_INST_CMD4 STFSM_INSTR(STFSM_OPC_CMD, 4) 181 #define STFSM_INST_CMD5 STFSM_INSTR(STFSM_OPC_CMD, 5) 182 #define STFSM_INST_ADD1 STFSM_INSTR(STFSM_OPC_ADD, 1) 183 #define STFSM_INST_ADD2 STFSM_INSTR(STFSM_OPC_ADD, 2) 184 185 #define STFSM_INST_DATA_WRITE STFSM_INSTR(STFSM_OPC_DATA, 1) 186 #define STFSM_INST_DATA_READ STFSM_INSTR(STFSM_OPC_DATA, 2) 187 188 #define STFSM_INST_STA_RD1 STFSM_INSTR(STFSM_OPC_STA, 0x1) 189 #define STFSM_INST_STA_WR1 STFSM_INSTR(STFSM_OPC_STA, 0x1) 190 #define STFSM_INST_STA_RD2 STFSM_INSTR(STFSM_OPC_STA, 0x2) 191 #define STFSM_INST_STA_WR1_2 STFSM_INSTR(STFSM_OPC_STA, 0x3) 192 193 #define STFSM_INST_MODE STFSM_INSTR(STFSM_OPC_MODE, 0) 194 #define STFSM_INST_DUMMY STFSM_INSTR(STFSM_OPC_DUMMY, 0) 195 #define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0) 196 #define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0) 197 198 #define STFSM_DEFAULT_EMI_FREQ 100000000UL /* 100 MHz */ 199 #define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */ 200 201 #define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */ 202 203 #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */ 204 205 /* S25FLxxxS commands */ 206 #define S25FL_CMD_WRITE4_1_1_4 0x34 207 #define S25FL_CMD_SE4 0xdc 208 #define S25FL_CMD_CLSR 0x30 209 #define S25FL_CMD_DYBWR 0xe1 210 #define S25FL_CMD_DYBRD 0xe0 211 #define S25FL_CMD_WRITE4 0x12 /* Note, opcode clashes with 212 * 'SPINOR_OP_WRITE_1_4_4' 213 * as found on N25Qxxx devices! */ 214 215 /* Status register */ 216 #define FLASH_STATUS_BUSY 0x01 217 #define FLASH_STATUS_WEL 0x02 218 #define FLASH_STATUS_BP0 0x04 219 #define FLASH_STATUS_BP1 0x08 220 #define FLASH_STATUS_BP2 0x10 221 #define FLASH_STATUS_SRWP0 0x80 222 #define FLASH_STATUS_TIMEOUT 0xff 223 /* S25FL Error Flags */ 224 #define S25FL_STATUS_E_ERR 0x20 225 #define S25FL_STATUS_P_ERR 0x40 226 227 #define N25Q_CMD_WRVCR 0x81 228 #define N25Q_CMD_RDVCR 0x85 229 #define N25Q_CMD_RDVECR 0x65 230 #define N25Q_CMD_RDNVCR 0xb5 231 #define N25Q_CMD_WRNVCR 0xb1 232 233 #define FLASH_PAGESIZE 256 /* In Bytes */ 234 #define FLASH_PAGESIZE_32 (FLASH_PAGESIZE / 4) /* In uint32_t */ 235 #define FLASH_MAX_BUSY_WAIT (300 * HZ) /* Maximum 'CHIPERASE' time */ 236 237 /* 238 * Flags to tweak operation of default read/write/erase routines 239 */ 240 #define CFG_READ_TOGGLE_32BIT_ADDR 0x00000001 241 #define CFG_WRITE_TOGGLE_32BIT_ADDR 0x00000002 242 #define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008 243 #define CFG_S25FL_CHECK_ERROR_FLAGS 0x00000010 244 245 struct stfsm_seq { 246 uint32_t data_size; 247 uint32_t addr1; 248 uint32_t addr2; 249 uint32_t addr_cfg; 250 uint32_t seq_opc[5]; 251 uint32_t mode; 252 uint32_t dummy; 253 uint32_t status; 254 uint8_t seq[16]; 255 uint32_t seq_cfg; 256 } __packed __aligned(4); 257 258 struct stfsm { 259 struct device *dev; 260 void __iomem *base; 261 struct resource *region; 262 struct mtd_info mtd; 263 struct mutex lock; 264 struct flash_info *info; 265 266 uint32_t configuration; 267 uint32_t fifo_dir_delay; 268 bool booted_from_spi; 269 bool reset_signal; 270 bool reset_por; 271 272 struct stfsm_seq stfsm_seq_read; 273 struct stfsm_seq stfsm_seq_write; 274 struct stfsm_seq stfsm_seq_en_32bit_addr; 275 }; 276 277 /* Parameters to configure a READ or WRITE FSM sequence */ 278 struct seq_rw_config { 279 uint32_t flags; /* flags to support config */ 280 uint8_t cmd; /* FLASH command */ 281 int write; /* Write Sequence */ 282 uint8_t addr_pads; /* No. of addr pads (MODE & DUMMY) */ 283 uint8_t data_pads; /* No. of data pads */ 284 uint8_t mode_data; /* MODE data */ 285 uint8_t mode_cycles; /* No. of MODE cycles */ 286 uint8_t dummy_cycles; /* No. of DUMMY cycles */ 287 }; 288 289 /* SPI Flash Device Table */ 290 struct flash_info { 291 char *name; 292 /* 293 * JEDEC id zero means "no ID" (most older chips); otherwise it has 294 * a high byte of zero plus three data bytes: the manufacturer id, 295 * then a two byte device id. 296 */ 297 u32 jedec_id; 298 u16 ext_id; 299 /* 300 * The size listed here is what works with SPINOR_OP_SE, which isn't 301 * necessarily called a "sector" by the vendor. 302 */ 303 unsigned sector_size; 304 u16 n_sectors; 305 u32 flags; 306 /* 307 * Note, where FAST_READ is supported, freq_max specifies the 308 * FAST_READ frequency, not the READ frequency. 309 */ 310 u32 max_freq; 311 int (*config)(struct stfsm *); 312 }; 313 314 static int stfsm_n25q_config(struct stfsm *fsm); 315 static int stfsm_mx25_config(struct stfsm *fsm); 316 static int stfsm_s25fl_config(struct stfsm *fsm); 317 static int stfsm_w25q_config(struct stfsm *fsm); 318 319 static struct flash_info flash_types[] = { 320 /* 321 * ST Microelectronics/Numonyx -- 322 * (newer production versions may have feature updates 323 * (eg faster operating frequency) 324 */ 325 #define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST) 326 { "m25p40", 0x202013, 0, 64 * 1024, 8, M25P_FLAG, 25, NULL }, 327 { "m25p80", 0x202014, 0, 64 * 1024, 16, M25P_FLAG, 25, NULL }, 328 { "m25p16", 0x202015, 0, 64 * 1024, 32, M25P_FLAG, 25, NULL }, 329 { "m25p32", 0x202016, 0, 64 * 1024, 64, M25P_FLAG, 50, NULL }, 330 { "m25p64", 0x202017, 0, 64 * 1024, 128, M25P_FLAG, 50, NULL }, 331 { "m25p128", 0x202018, 0, 256 * 1024, 64, M25P_FLAG, 50, NULL }, 332 333 #define M25PX_FLAG (FLASH_FLAG_READ_WRITE | \ 334 FLASH_FLAG_READ_FAST | \ 335 FLASH_FLAG_READ_1_1_2 | \ 336 FLASH_FLAG_WRITE_1_1_2) 337 { "m25px32", 0x207116, 0, 64 * 1024, 64, M25PX_FLAG, 75, NULL }, 338 { "m25px64", 0x207117, 0, 64 * 1024, 128, M25PX_FLAG, 75, NULL }, 339 340 /* Macronix MX25xxx 341 * - Support for 'FLASH_FLAG_WRITE_1_4_4' is omitted for devices 342 * where operating frequency must be reduced. 343 */ 344 #define MX25_FLAG (FLASH_FLAG_READ_WRITE | \ 345 FLASH_FLAG_READ_FAST | \ 346 FLASH_FLAG_READ_1_1_2 | \ 347 FLASH_FLAG_READ_1_2_2 | \ 348 FLASH_FLAG_READ_1_1_4 | \ 349 FLASH_FLAG_SE_4K | \ 350 FLASH_FLAG_SE_32K) 351 { "mx25l3255e", 0xc29e16, 0, 64 * 1024, 64, 352 (MX25_FLAG | FLASH_FLAG_WRITE_1_4_4), 86, 353 stfsm_mx25_config}, 354 { "mx25l25635e", 0xc22019, 0, 64*1024, 512, 355 (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, 356 stfsm_mx25_config }, 357 { "mx25l25655e", 0xc22619, 0, 64*1024, 512, 358 (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, 359 stfsm_mx25_config}, 360 361 #define N25Q_FLAG (FLASH_FLAG_READ_WRITE | \ 362 FLASH_FLAG_READ_FAST | \ 363 FLASH_FLAG_READ_1_1_2 | \ 364 FLASH_FLAG_READ_1_2_2 | \ 365 FLASH_FLAG_READ_1_1_4 | \ 366 FLASH_FLAG_READ_1_4_4 | \ 367 FLASH_FLAG_WRITE_1_1_2 | \ 368 FLASH_FLAG_WRITE_1_2_2 | \ 369 FLASH_FLAG_WRITE_1_1_4 | \ 370 FLASH_FLAG_WRITE_1_4_4) 371 { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, 372 stfsm_n25q_config }, 373 { "n25q256", 0x20ba19, 0, 64 * 1024, 512, 374 N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config }, 375 376 /* 377 * Spansion S25FLxxxP 378 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC) 379 */ 380 #define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE | \ 381 FLASH_FLAG_READ_1_1_2 | \ 382 FLASH_FLAG_READ_1_2_2 | \ 383 FLASH_FLAG_READ_1_1_4 | \ 384 FLASH_FLAG_READ_1_4_4 | \ 385 FLASH_FLAG_WRITE_1_1_4 | \ 386 FLASH_FLAG_READ_FAST) 387 { "s25fl032p", 0x010215, 0x4d00, 64 * 1024, 64, S25FLXXXP_FLAG, 80, 388 stfsm_s25fl_config}, 389 { "s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, S25FLXXXP_FLAG, 80, 390 stfsm_s25fl_config }, 391 { "s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, S25FLXXXP_FLAG, 80, 392 stfsm_s25fl_config }, 393 394 /* 395 * Spansion S25FLxxxS 396 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC) 397 * - RESET# signal supported by die but not bristled out on all 398 * package types. The package type is a function of board design, 399 * so this information is captured in the board's flags. 400 * - Supports 'DYB' sector protection. Depending on variant, sectors 401 * may default to locked state on power-on. 402 */ 403 #define S25FLXXXS_FLAG (S25FLXXXP_FLAG | \ 404 FLASH_FLAG_RESET | \ 405 FLASH_FLAG_DYB_LOCKING) 406 { "s25fl128s0", 0x012018, 0x0300, 256 * 1024, 64, S25FLXXXS_FLAG, 80, 407 stfsm_s25fl_config }, 408 { "s25fl128s1", 0x012018, 0x0301, 64 * 1024, 256, S25FLXXXS_FLAG, 80, 409 stfsm_s25fl_config }, 410 { "s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, 411 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config }, 412 { "s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, 413 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config }, 414 415 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 416 #define W25X_FLAG (FLASH_FLAG_READ_WRITE | \ 417 FLASH_FLAG_READ_FAST | \ 418 FLASH_FLAG_READ_1_1_2 | \ 419 FLASH_FLAG_WRITE_1_1_2) 420 { "w25x40", 0xef3013, 0, 64 * 1024, 8, W25X_FLAG, 75, NULL }, 421 { "w25x80", 0xef3014, 0, 64 * 1024, 16, W25X_FLAG, 75, NULL }, 422 { "w25x16", 0xef3015, 0, 64 * 1024, 32, W25X_FLAG, 75, NULL }, 423 { "w25x32", 0xef3016, 0, 64 * 1024, 64, W25X_FLAG, 75, NULL }, 424 { "w25x64", 0xef3017, 0, 64 * 1024, 128, W25X_FLAG, 75, NULL }, 425 426 /* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */ 427 #define W25Q_FLAG (FLASH_FLAG_READ_WRITE | \ 428 FLASH_FLAG_READ_FAST | \ 429 FLASH_FLAG_READ_1_1_2 | \ 430 FLASH_FLAG_READ_1_2_2 | \ 431 FLASH_FLAG_READ_1_1_4 | \ 432 FLASH_FLAG_READ_1_4_4 | \ 433 FLASH_FLAG_WRITE_1_1_4) 434 { "w25q80", 0xef4014, 0, 64 * 1024, 16, W25Q_FLAG, 80, 435 stfsm_w25q_config }, 436 { "w25q16", 0xef4015, 0, 64 * 1024, 32, W25Q_FLAG, 80, 437 stfsm_w25q_config }, 438 { "w25q32", 0xef4016, 0, 64 * 1024, 64, W25Q_FLAG, 80, 439 stfsm_w25q_config }, 440 { "w25q64", 0xef4017, 0, 64 * 1024, 128, W25Q_FLAG, 80, 441 stfsm_w25q_config }, 442 443 /* Sentinel */ 444 { NULL, 0x000000, 0, 0, 0, 0, 0, NULL }, 445 }; 446 447 /* 448 * FSM message sequence configurations: 449 * 450 * All configs are presented in order of preference 451 */ 452 453 /* Default READ configurations, in order of preference */ 454 static struct seq_rw_config default_read_configs[] = { 455 {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 2, 4}, 456 {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 4, 0}, 457 {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 4, 0}, 458 {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, 459 {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8}, 460 {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0}, 461 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 462 }; 463 464 /* Default WRITE configurations */ 465 static struct seq_rw_config default_write_configs[] = { 466 {FLASH_FLAG_WRITE_1_4_4, SPINOR_OP_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0}, 467 {FLASH_FLAG_WRITE_1_1_4, SPINOR_OP_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0}, 468 {FLASH_FLAG_WRITE_1_2_2, SPINOR_OP_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0}, 469 {FLASH_FLAG_WRITE_1_1_2, SPINOR_OP_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0}, 470 {FLASH_FLAG_READ_WRITE, SPINOR_OP_WRITE, 1, 1, 1, 0x00, 0, 0}, 471 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 472 }; 473 474 /* 475 * [N25Qxxx] Configuration 476 */ 477 #define N25Q_VCR_DUMMY_CYCLES(x) (((x) & 0xf) << 4) 478 #define N25Q_VCR_XIP_DISABLED ((uint8_t)0x1 << 3) 479 #define N25Q_VCR_WRAP_CONT 0x3 480 481 /* N25Q 3-byte Address READ configurations 482 * - 'FAST' variants configured for 8 dummy cycles. 483 * 484 * Note, the number of dummy cycles used for 'FAST' READ operations is 485 * configurable and would normally be tuned according to the READ command and 486 * operating frequency. However, this applies universally to all 'FAST' READ 487 * commands, including those used by the SPIBoot controller, and remains in 488 * force until the device is power-cycled. Since the SPIBoot controller is 489 * hard-wired to use 8 dummy cycles, we must configure the device to also use 8 490 * cycles. 491 */ 492 static struct seq_rw_config n25q_read3_configs[] = { 493 {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 0, 8}, 494 {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 0, 8}, 495 {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 0, 8}, 496 {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, 497 {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8}, 498 {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0}, 499 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 500 }; 501 502 /* N25Q 4-byte Address READ configurations 503 * - use special 4-byte address READ commands (reduces overheads, and 504 * reduces risk of hitting watchdog reset issues). 505 * - 'FAST' variants configured for 8 dummy cycles (see note above.) 506 */ 507 static struct seq_rw_config n25q_read4_configs[] = { 508 {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8}, 509 {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, 510 {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8}, 511 {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, 512 {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, 513 {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0}, 514 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 515 }; 516 517 /* 518 * [MX25xxx] Configuration 519 */ 520 #define MX25_STATUS_QE (0x1 << 6) 521 522 static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq) 523 { 524 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 525 SEQ_OPC_CYCLES(8) | 526 SEQ_OPC_OPCODE(SPINOR_OP_EN4B) | 527 SEQ_OPC_CSDEASSERT); 528 529 seq->seq[0] = STFSM_INST_CMD1; 530 seq->seq[1] = STFSM_INST_WAIT; 531 seq->seq[2] = STFSM_INST_STOP; 532 533 seq->seq_cfg = (SEQ_CFG_PADS_1 | 534 SEQ_CFG_ERASE | 535 SEQ_CFG_READNOTWRITE | 536 SEQ_CFG_CSDEASSERT | 537 SEQ_CFG_STARTSEQ); 538 539 return 0; 540 } 541 542 /* 543 * [S25FLxxx] Configuration 544 */ 545 #define STFSM_S25FL_CONFIG_QE (0x1 << 1) 546 547 /* 548 * S25FLxxxS devices provide three ways of supporting 32-bit addressing: Bank 549 * Register, Extended Address Modes, and a 32-bit address command set. The 550 * 32-bit address command set is used here, since it avoids any problems with 551 * entering a state that is incompatible with the SPIBoot Controller. 552 */ 553 static struct seq_rw_config stfsm_s25fl_read4_configs[] = { 554 {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4}, 555 {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, 556 {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0}, 557 {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, 558 {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, 559 {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0}, 560 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 561 }; 562 563 static struct seq_rw_config stfsm_s25fl_write4_configs[] = { 564 {FLASH_FLAG_WRITE_1_1_4, S25FL_CMD_WRITE4_1_1_4, 1, 1, 4, 0x00, 0, 0}, 565 {FLASH_FLAG_READ_WRITE, S25FL_CMD_WRITE4, 1, 1, 1, 0x00, 0, 0}, 566 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 567 }; 568 569 /* 570 * [W25Qxxx] Configuration 571 */ 572 #define W25Q_STATUS_QE (0x1 << 1) 573 574 static struct stfsm_seq stfsm_seq_read_jedec = { 575 .data_size = TRANSFER_SIZE(8), 576 .seq_opc[0] = (SEQ_OPC_PADS_1 | 577 SEQ_OPC_CYCLES(8) | 578 SEQ_OPC_OPCODE(SPINOR_OP_RDID)), 579 .seq = { 580 STFSM_INST_CMD1, 581 STFSM_INST_DATA_READ, 582 STFSM_INST_STOP, 583 }, 584 .seq_cfg = (SEQ_CFG_PADS_1 | 585 SEQ_CFG_READNOTWRITE | 586 SEQ_CFG_CSDEASSERT | 587 SEQ_CFG_STARTSEQ), 588 }; 589 590 static struct stfsm_seq stfsm_seq_read_status_fifo = { 591 .data_size = TRANSFER_SIZE(4), 592 .seq_opc[0] = (SEQ_OPC_PADS_1 | 593 SEQ_OPC_CYCLES(8) | 594 SEQ_OPC_OPCODE(SPINOR_OP_RDSR)), 595 .seq = { 596 STFSM_INST_CMD1, 597 STFSM_INST_DATA_READ, 598 STFSM_INST_STOP, 599 }, 600 .seq_cfg = (SEQ_CFG_PADS_1 | 601 SEQ_CFG_READNOTWRITE | 602 SEQ_CFG_CSDEASSERT | 603 SEQ_CFG_STARTSEQ), 604 }; 605 606 static struct stfsm_seq stfsm_seq_erase_sector = { 607 /* 'addr_cfg' configured during initialisation */ 608 .seq_opc = { 609 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 610 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), 611 612 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 613 SEQ_OPC_OPCODE(SPINOR_OP_SE)), 614 }, 615 .seq = { 616 STFSM_INST_CMD1, 617 STFSM_INST_CMD2, 618 STFSM_INST_ADD1, 619 STFSM_INST_ADD2, 620 STFSM_INST_STOP, 621 }, 622 .seq_cfg = (SEQ_CFG_PADS_1 | 623 SEQ_CFG_READNOTWRITE | 624 SEQ_CFG_CSDEASSERT | 625 SEQ_CFG_STARTSEQ), 626 }; 627 628 static struct stfsm_seq stfsm_seq_erase_chip = { 629 .seq_opc = { 630 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 631 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), 632 633 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 634 SEQ_OPC_OPCODE(SPINOR_OP_CHIP_ERASE) | SEQ_OPC_CSDEASSERT), 635 }, 636 .seq = { 637 STFSM_INST_CMD1, 638 STFSM_INST_CMD2, 639 STFSM_INST_WAIT, 640 STFSM_INST_STOP, 641 }, 642 .seq_cfg = (SEQ_CFG_PADS_1 | 643 SEQ_CFG_ERASE | 644 SEQ_CFG_READNOTWRITE | 645 SEQ_CFG_CSDEASSERT | 646 SEQ_CFG_STARTSEQ), 647 }; 648 649 static struct stfsm_seq stfsm_seq_write_status = { 650 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 651 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), 652 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 653 SEQ_OPC_OPCODE(SPINOR_OP_WRSR)), 654 .seq = { 655 STFSM_INST_CMD1, 656 STFSM_INST_CMD2, 657 STFSM_INST_STA_WR1, 658 STFSM_INST_STOP, 659 }, 660 .seq_cfg = (SEQ_CFG_PADS_1 | 661 SEQ_CFG_READNOTWRITE | 662 SEQ_CFG_CSDEASSERT | 663 SEQ_CFG_STARTSEQ), 664 }; 665 666 static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq) 667 { 668 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 669 SEQ_OPC_OPCODE(SPINOR_OP_EN4B)); 670 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 671 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | 672 SEQ_OPC_CSDEASSERT); 673 674 seq->seq[0] = STFSM_INST_CMD2; 675 seq->seq[1] = STFSM_INST_CMD1; 676 seq->seq[2] = STFSM_INST_WAIT; 677 seq->seq[3] = STFSM_INST_STOP; 678 679 seq->seq_cfg = (SEQ_CFG_PADS_1 | 680 SEQ_CFG_ERASE | 681 SEQ_CFG_READNOTWRITE | 682 SEQ_CFG_CSDEASSERT | 683 SEQ_CFG_STARTSEQ); 684 685 return 0; 686 } 687 688 static inline int stfsm_is_idle(struct stfsm *fsm) 689 { 690 return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10; 691 } 692 693 static inline uint32_t stfsm_fifo_available(struct stfsm *fsm) 694 { 695 return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f; 696 } 697 698 static void stfsm_clear_fifo(struct stfsm *fsm) 699 { 700 uint32_t avail; 701 702 for (;;) { 703 avail = stfsm_fifo_available(fsm); 704 if (!avail) 705 break; 706 707 while (avail) { 708 readl(fsm->base + SPI_FAST_SEQ_DATA_REG); 709 avail--; 710 } 711 } 712 } 713 714 static inline void stfsm_load_seq(struct stfsm *fsm, 715 const struct stfsm_seq *seq) 716 { 717 void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE; 718 const uint32_t *src = (const uint32_t *)seq; 719 int words = sizeof(*seq) / sizeof(*src); 720 721 BUG_ON(!stfsm_is_idle(fsm)); 722 723 while (words--) { 724 writel(*src, dst); 725 src++; 726 dst += 4; 727 } 728 } 729 730 static void stfsm_wait_seq(struct stfsm *fsm) 731 { 732 unsigned long deadline; 733 int timeout = 0; 734 735 deadline = jiffies + msecs_to_jiffies(STFSM_MAX_WAIT_SEQ_MS); 736 737 while (!timeout) { 738 if (time_after_eq(jiffies, deadline)) 739 timeout = 1; 740 741 if (stfsm_is_idle(fsm)) 742 return; 743 744 cond_resched(); 745 } 746 747 dev_err(fsm->dev, "timeout on sequence completion\n"); 748 } 749 750 static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, uint32_t size) 751 { 752 uint32_t remaining = size >> 2; 753 uint32_t avail; 754 uint32_t words; 755 756 dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size); 757 758 BUG_ON((((uintptr_t)buf) & 0x3) || (size & 0x3)); 759 760 while (remaining) { 761 for (;;) { 762 avail = stfsm_fifo_available(fsm); 763 if (avail) 764 break; 765 udelay(1); 766 } 767 words = min(avail, remaining); 768 remaining -= words; 769 770 readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words); 771 buf += words; 772 } 773 } 774 775 static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf, 776 uint32_t size) 777 { 778 uint32_t words = size >> 2; 779 780 dev_dbg(fsm->dev, "writing %d bytes to FIFO\n", size); 781 782 BUG_ON((((uintptr_t)buf) & 0x3) || (size & 0x3)); 783 784 writesl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words); 785 786 return size; 787 } 788 789 static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) 790 { 791 struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; 792 uint32_t cmd = enter ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; 793 794 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 795 SEQ_OPC_CYCLES(8) | 796 SEQ_OPC_OPCODE(cmd) | 797 SEQ_OPC_CSDEASSERT); 798 799 stfsm_load_seq(fsm, seq); 800 801 stfsm_wait_seq(fsm); 802 803 return 0; 804 } 805 806 static uint8_t stfsm_wait_busy(struct stfsm *fsm) 807 { 808 struct stfsm_seq *seq = &stfsm_seq_read_status_fifo; 809 unsigned long deadline; 810 uint32_t status; 811 int timeout = 0; 812 813 /* Use RDRS1 */ 814 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 815 SEQ_OPC_CYCLES(8) | 816 SEQ_OPC_OPCODE(SPINOR_OP_RDSR)); 817 818 /* Load read_status sequence */ 819 stfsm_load_seq(fsm, seq); 820 821 /* 822 * Repeat until busy bit is deasserted, or timeout, or error (S25FLxxxS) 823 */ 824 deadline = jiffies + FLASH_MAX_BUSY_WAIT; 825 while (!timeout) { 826 if (time_after_eq(jiffies, deadline)) 827 timeout = 1; 828 829 stfsm_wait_seq(fsm); 830 831 stfsm_read_fifo(fsm, &status, 4); 832 833 if ((status & FLASH_STATUS_BUSY) == 0) 834 return 0; 835 836 if ((fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) && 837 ((status & S25FL_STATUS_P_ERR) || 838 (status & S25FL_STATUS_E_ERR))) 839 return (uint8_t)(status & 0xff); 840 841 if (!timeout) 842 /* Restart */ 843 writel(seq->seq_cfg, fsm->base + SPI_FAST_SEQ_CFG); 844 845 cond_resched(); 846 } 847 848 dev_err(fsm->dev, "timeout on wait_busy\n"); 849 850 return FLASH_STATUS_TIMEOUT; 851 } 852 853 static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd, 854 uint8_t *data, int bytes) 855 { 856 struct stfsm_seq *seq = &stfsm_seq_read_status_fifo; 857 uint32_t tmp; 858 uint8_t *t = (uint8_t *)&tmp; 859 int i; 860 861 dev_dbg(fsm->dev, "read 'status' register [0x%02x], %d byte(s)\n", 862 cmd, bytes); 863 864 BUG_ON(bytes != 1 && bytes != 2); 865 866 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 867 SEQ_OPC_OPCODE(cmd)), 868 869 stfsm_load_seq(fsm, seq); 870 871 stfsm_read_fifo(fsm, &tmp, 4); 872 873 for (i = 0; i < bytes; i++) 874 data[i] = t[i]; 875 876 stfsm_wait_seq(fsm); 877 878 return 0; 879 } 880 881 static int stfsm_write_status(struct stfsm *fsm, uint8_t cmd, 882 uint16_t data, int bytes, int wait_busy) 883 { 884 struct stfsm_seq *seq = &stfsm_seq_write_status; 885 886 dev_dbg(fsm->dev, 887 "write 'status' register [0x%02x], %d byte(s), 0x%04x\n" 888 " %s wait-busy\n", cmd, bytes, data, wait_busy ? "with" : "no"); 889 890 BUG_ON(bytes != 1 && bytes != 2); 891 892 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 893 SEQ_OPC_OPCODE(cmd)); 894 895 seq->status = (uint32_t)data | STA_PADS_1 | STA_CSDEASSERT; 896 seq->seq[2] = (bytes == 1) ? STFSM_INST_STA_WR1 : STFSM_INST_STA_WR1_2; 897 898 stfsm_load_seq(fsm, seq); 899 900 stfsm_wait_seq(fsm); 901 902 if (wait_busy) 903 stfsm_wait_busy(fsm); 904 905 return 0; 906 } 907 908 /* 909 * SoC reset on 'boot-from-spi' systems 910 * 911 * Certain modes of operation cause the Flash device to enter a particular state 912 * for a period of time (e.g. 'Erase Sector', 'Quad Enable', and 'Enter 32-bit 913 * Addr' commands). On boot-from-spi systems, it is important to consider what 914 * happens if a warm reset occurs during this period. The SPIBoot controller 915 * assumes that Flash device is in its default reset state, 24-bit address mode, 916 * and ready to accept commands. This can be achieved using some form of 917 * on-board logic/controller to force a device POR in response to a SoC-level 918 * reset or by making use of the device reset signal if available (limited 919 * number of devices only). 920 * 921 * Failure to take such precautions can cause problems following a warm reset. 922 * For some operations (e.g. ERASE), there is little that can be done. For 923 * other modes of operation (e.g. 32-bit addressing), options are often 924 * available that can help minimise the window in which a reset could cause a 925 * problem. 926 * 927 */ 928 static bool stfsm_can_handle_soc_reset(struct stfsm *fsm) 929 { 930 /* Reset signal is available on the board and supported by the device */ 931 if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET) 932 return true; 933 934 /* Board-level logic forces a power-on-reset */ 935 if (fsm->reset_por) 936 return true; 937 938 /* Reset is not properly handled and may result in failure to reboot */ 939 return false; 940 } 941 942 /* Configure 'addr_cfg' according to addressing mode */ 943 static void stfsm_prepare_erasesec_seq(struct stfsm *fsm, 944 struct stfsm_seq *seq) 945 { 946 int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8; 947 948 seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(addr1_cycles) | 949 ADR_CFG_PADS_1_ADD1 | 950 ADR_CFG_CYCLES_ADD2(16) | 951 ADR_CFG_PADS_1_ADD2 | 952 ADR_CFG_CSDEASSERT_ADD2); 953 } 954 955 /* Search for preferred configuration based on available flags */ 956 static struct seq_rw_config * 957 stfsm_search_seq_rw_configs(struct stfsm *fsm, 958 struct seq_rw_config cfgs[]) 959 { 960 struct seq_rw_config *config; 961 int flags = fsm->info->flags; 962 963 for (config = cfgs; config->cmd != 0; config++) 964 if ((config->flags & flags) == config->flags) 965 return config; 966 967 return NULL; 968 } 969 970 /* Prepare a READ/WRITE sequence according to configuration parameters */ 971 static void stfsm_prepare_rw_seq(struct stfsm *fsm, 972 struct stfsm_seq *seq, 973 struct seq_rw_config *cfg) 974 { 975 int addr1_cycles, addr2_cycles; 976 int i = 0; 977 978 memset(seq, 0, sizeof(*seq)); 979 980 /* Add READ/WRITE OPC */ 981 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 | 982 SEQ_OPC_CYCLES(8) | 983 SEQ_OPC_OPCODE(cfg->cmd)); 984 985 /* Add WREN OPC for a WRITE sequence */ 986 if (cfg->write) 987 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 | 988 SEQ_OPC_CYCLES(8) | 989 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | 990 SEQ_OPC_CSDEASSERT); 991 992 /* Address configuration (24 or 32-bit addresses) */ 993 addr1_cycles = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8; 994 addr1_cycles /= cfg->addr_pads; 995 addr2_cycles = 16 / cfg->addr_pads; 996 seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 | /* ADD1 cycles */ 997 (cfg->addr_pads - 1) << 6 | /* ADD1 pads */ 998 (addr2_cycles & 0x3f) << 16 | /* ADD2 cycles */ 999 ((cfg->addr_pads - 1) << 22)); /* ADD2 pads */ 1000 1001 /* Data/Sequence configuration */ 1002 seq->seq_cfg = ((cfg->data_pads - 1) << 16 | 1003 SEQ_CFG_STARTSEQ | 1004 SEQ_CFG_CSDEASSERT); 1005 if (!cfg->write) 1006 seq->seq_cfg |= SEQ_CFG_READNOTWRITE; 1007 1008 /* Mode configuration (no. of pads taken from addr cfg) */ 1009 seq->mode = ((cfg->mode_data & 0xff) << 0 | /* data */ 1010 (cfg->mode_cycles & 0x3f) << 16 | /* cycles */ 1011 (cfg->addr_pads - 1) << 22); /* pads */ 1012 1013 /* Dummy configuration (no. of pads taken from addr cfg) */ 1014 seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 | /* cycles */ 1015 (cfg->addr_pads - 1) << 22); /* pads */ 1016 1017 1018 /* Instruction sequence */ 1019 i = 0; 1020 if (cfg->write) 1021 seq->seq[i++] = STFSM_INST_CMD2; 1022 1023 seq->seq[i++] = STFSM_INST_CMD1; 1024 1025 seq->seq[i++] = STFSM_INST_ADD1; 1026 seq->seq[i++] = STFSM_INST_ADD2; 1027 1028 if (cfg->mode_cycles) 1029 seq->seq[i++] = STFSM_INST_MODE; 1030 1031 if (cfg->dummy_cycles) 1032 seq->seq[i++] = STFSM_INST_DUMMY; 1033 1034 seq->seq[i++] = 1035 cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ; 1036 seq->seq[i++] = STFSM_INST_STOP; 1037 } 1038 1039 static int stfsm_search_prepare_rw_seq(struct stfsm *fsm, 1040 struct stfsm_seq *seq, 1041 struct seq_rw_config *cfgs) 1042 { 1043 struct seq_rw_config *config; 1044 1045 config = stfsm_search_seq_rw_configs(fsm, cfgs); 1046 if (!config) { 1047 dev_err(fsm->dev, "failed to find suitable config\n"); 1048 return -EINVAL; 1049 } 1050 1051 stfsm_prepare_rw_seq(fsm, seq, config); 1052 1053 return 0; 1054 } 1055 1056 /* Prepare a READ/WRITE/ERASE 'default' sequences */ 1057 static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm) 1058 { 1059 uint32_t flags = fsm->info->flags; 1060 int ret; 1061 1062 /* Configure 'READ' sequence */ 1063 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1064 default_read_configs); 1065 if (ret) { 1066 dev_err(fsm->dev, 1067 "failed to prep READ sequence with flags [0x%08x]\n", 1068 flags); 1069 return ret; 1070 } 1071 1072 /* Configure 'WRITE' sequence */ 1073 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, 1074 default_write_configs); 1075 if (ret) { 1076 dev_err(fsm->dev, 1077 "failed to prep WRITE sequence with flags [0x%08x]\n", 1078 flags); 1079 return ret; 1080 } 1081 1082 /* Configure 'ERASE_SECTOR' sequence */ 1083 stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); 1084 1085 return 0; 1086 } 1087 1088 static int stfsm_mx25_config(struct stfsm *fsm) 1089 { 1090 uint32_t flags = fsm->info->flags; 1091 uint32_t data_pads; 1092 uint8_t sta; 1093 int ret; 1094 bool soc_reset; 1095 1096 /* 1097 * Use default READ/WRITE sequences 1098 */ 1099 ret = stfsm_prepare_rwe_seqs_default(fsm); 1100 if (ret) 1101 return ret; 1102 1103 /* 1104 * Configure 32-bit Address Support 1105 */ 1106 if (flags & FLASH_FLAG_32BIT_ADDR) { 1107 /* Configure 'enter_32bitaddr' FSM sequence */ 1108 stfsm_mx25_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); 1109 1110 soc_reset = stfsm_can_handle_soc_reset(fsm); 1111 if (soc_reset || !fsm->booted_from_spi) 1112 /* If we can handle SoC resets, we enable 32-bit address 1113 * mode pervasively */ 1114 stfsm_enter_32bit_addr(fsm, 1); 1115 1116 else 1117 /* Else, enable/disable 32-bit addressing before/after 1118 * each operation */ 1119 fsm->configuration = (CFG_READ_TOGGLE_32BIT_ADDR | 1120 CFG_WRITE_TOGGLE_32BIT_ADDR | 1121 CFG_ERASESEC_TOGGLE_32BIT_ADDR); 1122 } 1123 1124 /* Check status of 'QE' bit, update if required. */ 1125 stfsm_read_status(fsm, SPINOR_OP_RDSR, &sta, 1); 1126 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; 1127 if (data_pads == 4) { 1128 if (!(sta & MX25_STATUS_QE)) { 1129 /* Set 'QE' */ 1130 sta |= MX25_STATUS_QE; 1131 1132 stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1); 1133 } 1134 } else { 1135 if (sta & MX25_STATUS_QE) { 1136 /* Clear 'QE' */ 1137 sta &= ~MX25_STATUS_QE; 1138 1139 stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1); 1140 } 1141 } 1142 1143 return 0; 1144 } 1145 1146 static int stfsm_n25q_config(struct stfsm *fsm) 1147 { 1148 uint32_t flags = fsm->info->flags; 1149 uint8_t vcr; 1150 int ret = 0; 1151 bool soc_reset; 1152 1153 /* Configure 'READ' sequence */ 1154 if (flags & FLASH_FLAG_32BIT_ADDR) 1155 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1156 n25q_read4_configs); 1157 else 1158 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1159 n25q_read3_configs); 1160 if (ret) { 1161 dev_err(fsm->dev, 1162 "failed to prepare READ sequence with flags [0x%08x]\n", 1163 flags); 1164 return ret; 1165 } 1166 1167 /* Configure 'WRITE' sequence (default configs) */ 1168 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, 1169 default_write_configs); 1170 if (ret) { 1171 dev_err(fsm->dev, 1172 "preparing WRITE sequence using flags [0x%08x] failed\n", 1173 flags); 1174 return ret; 1175 } 1176 1177 /* * Configure 'ERASE_SECTOR' sequence */ 1178 stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); 1179 1180 /* Configure 32-bit address support */ 1181 if (flags & FLASH_FLAG_32BIT_ADDR) { 1182 stfsm_n25q_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); 1183 1184 soc_reset = stfsm_can_handle_soc_reset(fsm); 1185 if (soc_reset || !fsm->booted_from_spi) { 1186 /* 1187 * If we can handle SoC resets, we enable 32-bit 1188 * address mode pervasively 1189 */ 1190 stfsm_enter_32bit_addr(fsm, 1); 1191 } else { 1192 /* 1193 * If not, enable/disable for WRITE and ERASE 1194 * operations (READ uses special commands) 1195 */ 1196 fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR | 1197 CFG_ERASESEC_TOGGLE_32BIT_ADDR); 1198 } 1199 } 1200 1201 /* 1202 * Configure device to use 8 dummy cycles 1203 */ 1204 vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED | 1205 N25Q_VCR_WRAP_CONT); 1206 stfsm_write_status(fsm, N25Q_CMD_WRVCR, vcr, 1, 0); 1207 1208 return 0; 1209 } 1210 1211 static void stfsm_s25fl_prepare_erasesec_seq_32(struct stfsm_seq *seq) 1212 { 1213 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | 1214 SEQ_OPC_CYCLES(8) | 1215 SEQ_OPC_OPCODE(S25FL_CMD_SE4)); 1216 1217 seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(16) | 1218 ADR_CFG_PADS_1_ADD1 | 1219 ADR_CFG_CYCLES_ADD2(16) | 1220 ADR_CFG_PADS_1_ADD2 | 1221 ADR_CFG_CSDEASSERT_ADD2); 1222 } 1223 1224 static void stfsm_s25fl_read_dyb(struct stfsm *fsm, uint32_t offs, uint8_t *dby) 1225 { 1226 uint32_t tmp; 1227 struct stfsm_seq seq = { 1228 .data_size = TRANSFER_SIZE(4), 1229 .seq_opc[0] = (SEQ_OPC_PADS_1 | 1230 SEQ_OPC_CYCLES(8) | 1231 SEQ_OPC_OPCODE(S25FL_CMD_DYBRD)), 1232 .addr_cfg = (ADR_CFG_CYCLES_ADD1(16) | 1233 ADR_CFG_PADS_1_ADD1 | 1234 ADR_CFG_CYCLES_ADD2(16) | 1235 ADR_CFG_PADS_1_ADD2), 1236 .addr1 = (offs >> 16) & 0xffff, 1237 .addr2 = offs & 0xffff, 1238 .seq = { 1239 STFSM_INST_CMD1, 1240 STFSM_INST_ADD1, 1241 STFSM_INST_ADD2, 1242 STFSM_INST_DATA_READ, 1243 STFSM_INST_STOP, 1244 }, 1245 .seq_cfg = (SEQ_CFG_PADS_1 | 1246 SEQ_CFG_READNOTWRITE | 1247 SEQ_CFG_CSDEASSERT | 1248 SEQ_CFG_STARTSEQ), 1249 }; 1250 1251 stfsm_load_seq(fsm, &seq); 1252 1253 stfsm_read_fifo(fsm, &tmp, 4); 1254 1255 *dby = (uint8_t)(tmp >> 24); 1256 1257 stfsm_wait_seq(fsm); 1258 } 1259 1260 static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby) 1261 { 1262 struct stfsm_seq seq = { 1263 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 1264 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | 1265 SEQ_OPC_CSDEASSERT), 1266 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 1267 SEQ_OPC_OPCODE(S25FL_CMD_DYBWR)), 1268 .addr_cfg = (ADR_CFG_CYCLES_ADD1(16) | 1269 ADR_CFG_PADS_1_ADD1 | 1270 ADR_CFG_CYCLES_ADD2(16) | 1271 ADR_CFG_PADS_1_ADD2), 1272 .status = (uint32_t)dby | STA_PADS_1 | STA_CSDEASSERT, 1273 .addr1 = (offs >> 16) & 0xffff, 1274 .addr2 = offs & 0xffff, 1275 .seq = { 1276 STFSM_INST_CMD1, 1277 STFSM_INST_CMD2, 1278 STFSM_INST_ADD1, 1279 STFSM_INST_ADD2, 1280 STFSM_INST_STA_WR1, 1281 STFSM_INST_STOP, 1282 }, 1283 .seq_cfg = (SEQ_CFG_PADS_1 | 1284 SEQ_CFG_READNOTWRITE | 1285 SEQ_CFG_CSDEASSERT | 1286 SEQ_CFG_STARTSEQ), 1287 }; 1288 1289 stfsm_load_seq(fsm, &seq); 1290 stfsm_wait_seq(fsm); 1291 1292 stfsm_wait_busy(fsm); 1293 } 1294 1295 static int stfsm_s25fl_clear_status_reg(struct stfsm *fsm) 1296 { 1297 struct stfsm_seq seq = { 1298 .seq_opc[0] = (SEQ_OPC_PADS_1 | 1299 SEQ_OPC_CYCLES(8) | 1300 SEQ_OPC_OPCODE(S25FL_CMD_CLSR) | 1301 SEQ_OPC_CSDEASSERT), 1302 .seq_opc[1] = (SEQ_OPC_PADS_1 | 1303 SEQ_OPC_CYCLES(8) | 1304 SEQ_OPC_OPCODE(SPINOR_OP_WRDI) | 1305 SEQ_OPC_CSDEASSERT), 1306 .seq = { 1307 STFSM_INST_CMD1, 1308 STFSM_INST_CMD2, 1309 STFSM_INST_WAIT, 1310 STFSM_INST_STOP, 1311 }, 1312 .seq_cfg = (SEQ_CFG_PADS_1 | 1313 SEQ_CFG_ERASE | 1314 SEQ_CFG_READNOTWRITE | 1315 SEQ_CFG_CSDEASSERT | 1316 SEQ_CFG_STARTSEQ), 1317 }; 1318 1319 stfsm_load_seq(fsm, &seq); 1320 1321 stfsm_wait_seq(fsm); 1322 1323 return 0; 1324 } 1325 1326 static int stfsm_s25fl_config(struct stfsm *fsm) 1327 { 1328 struct flash_info *info = fsm->info; 1329 uint32_t flags = info->flags; 1330 uint32_t data_pads; 1331 uint32_t offs; 1332 uint16_t sta_wr; 1333 uint8_t sr1, cr1, dyb; 1334 int update_sr = 0; 1335 int ret; 1336 1337 if (flags & FLASH_FLAG_32BIT_ADDR) { 1338 /* 1339 * Prepare Read/Write/Erase sequences according to S25FLxxx 1340 * 32-bit address command set 1341 */ 1342 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1343 stfsm_s25fl_read4_configs); 1344 if (ret) 1345 return ret; 1346 1347 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, 1348 stfsm_s25fl_write4_configs); 1349 if (ret) 1350 return ret; 1351 1352 stfsm_s25fl_prepare_erasesec_seq_32(&stfsm_seq_erase_sector); 1353 1354 } else { 1355 /* Use default configurations for 24-bit addressing */ 1356 ret = stfsm_prepare_rwe_seqs_default(fsm); 1357 if (ret) 1358 return ret; 1359 } 1360 1361 /* 1362 * For devices that support 'DYB' sector locking, check lock status and 1363 * unlock sectors if necessary (some variants power-on with sectors 1364 * locked by default) 1365 */ 1366 if (flags & FLASH_FLAG_DYB_LOCKING) { 1367 offs = 0; 1368 for (offs = 0; offs < info->sector_size * info->n_sectors;) { 1369 stfsm_s25fl_read_dyb(fsm, offs, &dyb); 1370 if (dyb == 0x00) 1371 stfsm_s25fl_write_dyb(fsm, offs, 0xff); 1372 1373 /* Handle bottom/top 4KiB parameter sectors */ 1374 if ((offs < info->sector_size * 2) || 1375 (offs >= (info->sector_size - info->n_sectors * 4))) 1376 offs += 0x1000; 1377 else 1378 offs += 0x10000; 1379 } 1380 } 1381 1382 /* Check status of 'QE' bit, update if required. */ 1383 stfsm_read_status(fsm, SPINOR_OP_RDSR2, &cr1, 1); 1384 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; 1385 if (data_pads == 4) { 1386 if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { 1387 /* Set 'QE' */ 1388 cr1 |= STFSM_S25FL_CONFIG_QE; 1389 1390 update_sr = 1; 1391 } 1392 } else { 1393 if (cr1 & STFSM_S25FL_CONFIG_QE) { 1394 /* Clear 'QE' */ 1395 cr1 &= ~STFSM_S25FL_CONFIG_QE; 1396 1397 update_sr = 1; 1398 } 1399 } 1400 if (update_sr) { 1401 stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); 1402 sta_wr = ((uint16_t)cr1 << 8) | sr1; 1403 stfsm_write_status(fsm, SPINOR_OP_WRSR, sta_wr, 2, 1); 1404 } 1405 1406 /* 1407 * S25FLxxx devices support Program and Error error flags. 1408 * Configure driver to check flags and clear if necessary. 1409 */ 1410 fsm->configuration |= CFG_S25FL_CHECK_ERROR_FLAGS; 1411 1412 return 0; 1413 } 1414 1415 static int stfsm_w25q_config(struct stfsm *fsm) 1416 { 1417 uint32_t data_pads; 1418 uint8_t sr1, sr2; 1419 uint16_t sr_wr; 1420 int update_sr = 0; 1421 int ret; 1422 1423 ret = stfsm_prepare_rwe_seqs_default(fsm); 1424 if (ret) 1425 return ret; 1426 1427 /* Check status of 'QE' bit, update if required. */ 1428 stfsm_read_status(fsm, SPINOR_OP_RDSR2, &sr2, 1); 1429 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; 1430 if (data_pads == 4) { 1431 if (!(sr2 & W25Q_STATUS_QE)) { 1432 /* Set 'QE' */ 1433 sr2 |= W25Q_STATUS_QE; 1434 update_sr = 1; 1435 } 1436 } else { 1437 if (sr2 & W25Q_STATUS_QE) { 1438 /* Clear 'QE' */ 1439 sr2 &= ~W25Q_STATUS_QE; 1440 update_sr = 1; 1441 } 1442 } 1443 if (update_sr) { 1444 /* Write status register */ 1445 stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); 1446 sr_wr = ((uint16_t)sr2 << 8) | sr1; 1447 stfsm_write_status(fsm, SPINOR_OP_WRSR, sr_wr, 2, 1); 1448 } 1449 1450 return 0; 1451 } 1452 1453 static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size, 1454 uint32_t offset) 1455 { 1456 struct stfsm_seq *seq = &fsm->stfsm_seq_read; 1457 uint32_t data_pads; 1458 uint32_t read_mask; 1459 uint32_t size_ub; 1460 uint32_t size_lb; 1461 uint32_t size_mop; 1462 uint32_t tmp[4]; 1463 uint32_t page_buf[FLASH_PAGESIZE_32]; 1464 uint8_t *p; 1465 1466 dev_dbg(fsm->dev, "reading %d bytes from 0x%08x\n", size, offset); 1467 1468 /* Enter 32-bit address mode, if required */ 1469 if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR) 1470 stfsm_enter_32bit_addr(fsm, 1); 1471 1472 /* Must read in multiples of 32 cycles (or 32*pads/8 Bytes) */ 1473 data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1; 1474 read_mask = (data_pads << 2) - 1; 1475 1476 /* Handle non-aligned buf */ 1477 p = ((uintptr_t)buf & 0x3) ? (uint8_t *)page_buf : buf; 1478 1479 /* Handle non-aligned size */ 1480 size_ub = (size + read_mask) & ~read_mask; 1481 size_lb = size & ~read_mask; 1482 size_mop = size & read_mask; 1483 1484 seq->data_size = TRANSFER_SIZE(size_ub); 1485 seq->addr1 = (offset >> 16) & 0xffff; 1486 seq->addr2 = offset & 0xffff; 1487 1488 stfsm_load_seq(fsm, seq); 1489 1490 if (size_lb) 1491 stfsm_read_fifo(fsm, (uint32_t *)p, size_lb); 1492 1493 if (size_mop) { 1494 stfsm_read_fifo(fsm, tmp, read_mask + 1); 1495 memcpy(p + size_lb, &tmp, size_mop); 1496 } 1497 1498 /* Handle non-aligned buf */ 1499 if ((uintptr_t)buf & 0x3) 1500 memcpy(buf, page_buf, size); 1501 1502 /* Wait for sequence to finish */ 1503 stfsm_wait_seq(fsm); 1504 1505 stfsm_clear_fifo(fsm); 1506 1507 /* Exit 32-bit address mode, if required */ 1508 if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR) 1509 stfsm_enter_32bit_addr(fsm, 0); 1510 1511 return 0; 1512 } 1513 1514 static int stfsm_write(struct stfsm *fsm, const uint8_t *buf, 1515 uint32_t size, uint32_t offset) 1516 { 1517 struct stfsm_seq *seq = &fsm->stfsm_seq_write; 1518 uint32_t data_pads; 1519 uint32_t write_mask; 1520 uint32_t size_ub; 1521 uint32_t size_lb; 1522 uint32_t size_mop; 1523 uint32_t tmp[4]; 1524 uint32_t page_buf[FLASH_PAGESIZE_32]; 1525 uint8_t *t = (uint8_t *)&tmp; 1526 const uint8_t *p; 1527 int ret; 1528 int i; 1529 1530 dev_dbg(fsm->dev, "writing %d bytes to 0x%08x\n", size, offset); 1531 1532 /* Enter 32-bit address mode, if required */ 1533 if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR) 1534 stfsm_enter_32bit_addr(fsm, 1); 1535 1536 /* Must write in multiples of 32 cycles (or 32*pads/8 bytes) */ 1537 data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1; 1538 write_mask = (data_pads << 2) - 1; 1539 1540 /* Handle non-aligned buf */ 1541 if ((uintptr_t)buf & 0x3) { 1542 memcpy(page_buf, buf, size); 1543 p = (uint8_t *)page_buf; 1544 } else { 1545 p = buf; 1546 } 1547 1548 /* Handle non-aligned size */ 1549 size_ub = (size + write_mask) & ~write_mask; 1550 size_lb = size & ~write_mask; 1551 size_mop = size & write_mask; 1552 1553 seq->data_size = TRANSFER_SIZE(size_ub); 1554 seq->addr1 = (offset >> 16) & 0xffff; 1555 seq->addr2 = offset & 0xffff; 1556 1557 /* Need to set FIFO to write mode, before writing data to FIFO (see 1558 * GNBvb79594) 1559 */ 1560 writel(0x00040000, fsm->base + SPI_FAST_SEQ_CFG); 1561 1562 /* 1563 * Before writing data to the FIFO, apply a small delay to allow a 1564 * potential change of FIFO direction to complete. 1565 */ 1566 if (fsm->fifo_dir_delay == 0) 1567 readl(fsm->base + SPI_FAST_SEQ_CFG); 1568 else 1569 udelay(fsm->fifo_dir_delay); 1570 1571 1572 /* Write data to FIFO, before starting sequence (see GNBvd79593) */ 1573 if (size_lb) { 1574 stfsm_write_fifo(fsm, (uint32_t *)p, size_lb); 1575 p += size_lb; 1576 } 1577 1578 /* Handle non-aligned size */ 1579 if (size_mop) { 1580 memset(t, 0xff, write_mask + 1); /* fill with 0xff's */ 1581 for (i = 0; i < size_mop; i++) 1582 t[i] = *p++; 1583 1584 stfsm_write_fifo(fsm, tmp, write_mask + 1); 1585 } 1586 1587 /* Start sequence */ 1588 stfsm_load_seq(fsm, seq); 1589 1590 /* Wait for sequence to finish */ 1591 stfsm_wait_seq(fsm); 1592 1593 /* Wait for completion */ 1594 ret = stfsm_wait_busy(fsm); 1595 if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) 1596 stfsm_s25fl_clear_status_reg(fsm); 1597 1598 /* Exit 32-bit address mode, if required */ 1599 if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR) 1600 stfsm_enter_32bit_addr(fsm, 0); 1601 1602 return 0; 1603 } 1604 1605 /* 1606 * Read an address range from the flash chip. The address range 1607 * may be any size provided it is within the physical boundaries. 1608 */ 1609 static int stfsm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, 1610 size_t *retlen, u_char *buf) 1611 { 1612 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent); 1613 uint32_t bytes; 1614 1615 dev_dbg(fsm->dev, "%s from 0x%08x, len %zd\n", 1616 __func__, (u32)from, len); 1617 1618 mutex_lock(&fsm->lock); 1619 1620 while (len > 0) { 1621 bytes = min_t(size_t, len, FLASH_PAGESIZE); 1622 1623 stfsm_read(fsm, buf, bytes, from); 1624 1625 buf += bytes; 1626 from += bytes; 1627 len -= bytes; 1628 1629 *retlen += bytes; 1630 } 1631 1632 mutex_unlock(&fsm->lock); 1633 1634 return 0; 1635 } 1636 1637 static int stfsm_erase_sector(struct stfsm *fsm, uint32_t offset) 1638 { 1639 struct stfsm_seq *seq = &stfsm_seq_erase_sector; 1640 int ret; 1641 1642 dev_dbg(fsm->dev, "erasing sector at 0x%08x\n", offset); 1643 1644 /* Enter 32-bit address mode, if required */ 1645 if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR) 1646 stfsm_enter_32bit_addr(fsm, 1); 1647 1648 seq->addr1 = (offset >> 16) & 0xffff; 1649 seq->addr2 = offset & 0xffff; 1650 1651 stfsm_load_seq(fsm, seq); 1652 1653 stfsm_wait_seq(fsm); 1654 1655 /* Wait for completion */ 1656 ret = stfsm_wait_busy(fsm); 1657 if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) 1658 stfsm_s25fl_clear_status_reg(fsm); 1659 1660 /* Exit 32-bit address mode, if required */ 1661 if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR) 1662 stfsm_enter_32bit_addr(fsm, 0); 1663 1664 return ret; 1665 } 1666 1667 static int stfsm_erase_chip(struct stfsm *fsm) 1668 { 1669 const struct stfsm_seq *seq = &stfsm_seq_erase_chip; 1670 1671 dev_dbg(fsm->dev, "erasing chip\n"); 1672 1673 stfsm_load_seq(fsm, seq); 1674 1675 stfsm_wait_seq(fsm); 1676 1677 return stfsm_wait_busy(fsm); 1678 } 1679 1680 /* 1681 * Write an address range to the flash chip. Data must be written in 1682 * FLASH_PAGESIZE chunks. The address range may be any size provided 1683 * it is within the physical boundaries. 1684 */ 1685 static int stfsm_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, 1686 size_t *retlen, const u_char *buf) 1687 { 1688 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent); 1689 1690 u32 page_offs; 1691 u32 bytes; 1692 uint8_t *b = (uint8_t *)buf; 1693 int ret = 0; 1694 1695 dev_dbg(fsm->dev, "%s to 0x%08x, len %zd\n", __func__, (u32)to, len); 1696 1697 /* Offset within page */ 1698 page_offs = to % FLASH_PAGESIZE; 1699 1700 mutex_lock(&fsm->lock); 1701 1702 while (len) { 1703 /* Write up to page boundary */ 1704 bytes = min_t(size_t, FLASH_PAGESIZE - page_offs, len); 1705 1706 ret = stfsm_write(fsm, b, bytes, to); 1707 if (ret) 1708 goto out1; 1709 1710 b += bytes; 1711 len -= bytes; 1712 to += bytes; 1713 1714 /* We are now page-aligned */ 1715 page_offs = 0; 1716 1717 *retlen += bytes; 1718 1719 } 1720 1721 out1: 1722 mutex_unlock(&fsm->lock); 1723 1724 return ret; 1725 } 1726 1727 /* 1728 * Erase an address range on the flash chip. The address range may extend 1729 * one or more erase sectors. Return an error is there is a problem erasing. 1730 */ 1731 static int stfsm_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) 1732 { 1733 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent); 1734 u32 addr, len; 1735 int ret; 1736 1737 dev_dbg(fsm->dev, "%s at 0x%llx, len %lld\n", __func__, 1738 (long long)instr->addr, (long long)instr->len); 1739 1740 addr = instr->addr; 1741 len = instr->len; 1742 1743 mutex_lock(&fsm->lock); 1744 1745 /* Whole-chip erase? */ 1746 if (len == mtd->size) { 1747 ret = stfsm_erase_chip(fsm); 1748 if (ret) 1749 goto out1; 1750 } else { 1751 while (len) { 1752 ret = stfsm_erase_sector(fsm, addr); 1753 if (ret) 1754 goto out1; 1755 1756 addr += mtd->erasesize; 1757 len -= mtd->erasesize; 1758 } 1759 } 1760 1761 mutex_unlock(&fsm->lock); 1762 1763 instr->state = MTD_ERASE_DONE; 1764 mtd_erase_callback(instr); 1765 1766 return 0; 1767 1768 out1: 1769 instr->state = MTD_ERASE_FAILED; 1770 mutex_unlock(&fsm->lock); 1771 1772 return ret; 1773 } 1774 1775 static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *jedec) 1776 { 1777 const struct stfsm_seq *seq = &stfsm_seq_read_jedec; 1778 uint32_t tmp[2]; 1779 1780 stfsm_load_seq(fsm, seq); 1781 1782 stfsm_read_fifo(fsm, tmp, 8); 1783 1784 memcpy(jedec, tmp, 5); 1785 1786 stfsm_wait_seq(fsm); 1787 } 1788 1789 static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm) 1790 { 1791 struct flash_info *info; 1792 u16 ext_jedec; 1793 u32 jedec; 1794 u8 id[5]; 1795 1796 stfsm_read_jedec(fsm, id); 1797 1798 jedec = id[0] << 16 | id[1] << 8 | id[2]; 1799 /* 1800 * JEDEC also defines an optional "extended device information" 1801 * string for after vendor-specific data, after the three bytes 1802 * we use here. Supporting some chips might require using it. 1803 */ 1804 ext_jedec = id[3] << 8 | id[4]; 1805 1806 dev_dbg(fsm->dev, "JEDEC = 0x%08x [%02x %02x %02x %02x %02x]\n", 1807 jedec, id[0], id[1], id[2], id[3], id[4]); 1808 1809 for (info = flash_types; info->name; info++) { 1810 if (info->jedec_id == jedec) { 1811 if (info->ext_id && info->ext_id != ext_jedec) 1812 continue; 1813 return info; 1814 } 1815 } 1816 dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec); 1817 1818 return NULL; 1819 } 1820 1821 static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode) 1822 { 1823 int ret, timeout = 10; 1824 1825 /* Wait for controller to accept mode change */ 1826 while (--timeout) { 1827 ret = readl(fsm->base + SPI_STA_MODE_CHANGE); 1828 if (ret & 0x1) 1829 break; 1830 udelay(1); 1831 } 1832 1833 if (!timeout) 1834 return -EBUSY; 1835 1836 writel(mode, fsm->base + SPI_MODESELECT); 1837 1838 return 0; 1839 } 1840 1841 static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq) 1842 { 1843 uint32_t emi_freq; 1844 uint32_t clk_div; 1845 1846 /* TODO: Make this dynamic */ 1847 emi_freq = STFSM_DEFAULT_EMI_FREQ; 1848 1849 /* 1850 * Calculate clk_div - values between 2 and 128 1851 * Multiple of 2, rounded up 1852 */ 1853 clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq); 1854 if (clk_div < 2) 1855 clk_div = 2; 1856 else if (clk_div > 128) 1857 clk_div = 128; 1858 1859 /* 1860 * Determine a suitable delay for the IP to complete a change of 1861 * direction of the FIFO. The required delay is related to the clock 1862 * divider used. The following heuristics are based on empirical tests, 1863 * using a 100MHz EMI clock. 1864 */ 1865 if (clk_div <= 4) 1866 fsm->fifo_dir_delay = 0; 1867 else if (clk_div <= 10) 1868 fsm->fifo_dir_delay = 1; 1869 else 1870 fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10); 1871 1872 dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n", 1873 emi_freq, spi_freq, clk_div); 1874 1875 writel(clk_div, fsm->base + SPI_CLOCKDIV); 1876 } 1877 1878 static int stfsm_init(struct stfsm *fsm) 1879 { 1880 int ret; 1881 1882 /* Perform a soft reset of the FSM controller */ 1883 writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG); 1884 udelay(1); 1885 writel(0, fsm->base + SPI_FAST_SEQ_CFG); 1886 1887 /* Set clock to 'safe' frequency initially */ 1888 stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ); 1889 1890 /* Switch to FSM */ 1891 ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM); 1892 if (ret) 1893 return ret; 1894 1895 /* Set timing parameters */ 1896 writel(SPI_CFG_DEVICE_ST | 1897 SPI_CFG_DEFAULT_MIN_CS_HIGH | 1898 SPI_CFG_DEFAULT_CS_SETUPHOLD | 1899 SPI_CFG_DEFAULT_DATA_HOLD, 1900 fsm->base + SPI_CONFIGDATA); 1901 writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG); 1902 1903 /* 1904 * Set the FSM 'WAIT' delay to the minimum workable value. Note, for 1905 * our purposes, the WAIT instruction is used purely to achieve 1906 * "sequence validity" rather than actually implement a delay. 1907 */ 1908 writel(0x00000001, fsm->base + SPI_PROGRAM_ERASE_TIME); 1909 1910 /* Clear FIFO, just in case */ 1911 stfsm_clear_fifo(fsm); 1912 1913 return 0; 1914 } 1915 1916 static void stfsm_fetch_platform_configs(struct platform_device *pdev) 1917 { 1918 struct stfsm *fsm = platform_get_drvdata(pdev); 1919 struct device_node *np = pdev->dev.of_node; 1920 struct regmap *regmap; 1921 uint32_t boot_device_reg; 1922 uint32_t boot_device_spi; 1923 uint32_t boot_device; /* Value we read from *boot_device_reg */ 1924 int ret; 1925 1926 /* Booting from SPI NOR Flash is the default */ 1927 fsm->booted_from_spi = true; 1928 1929 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1930 if (IS_ERR(regmap)) 1931 goto boot_device_fail; 1932 1933 fsm->reset_signal = of_property_read_bool(np, "st,reset-signal"); 1934 1935 fsm->reset_por = of_property_read_bool(np, "st,reset-por"); 1936 1937 /* Where in the syscon the boot device information lives */ 1938 ret = of_property_read_u32(np, "st,boot-device-reg", &boot_device_reg); 1939 if (ret) 1940 goto boot_device_fail; 1941 1942 /* Boot device value when booted from SPI NOR */ 1943 ret = of_property_read_u32(np, "st,boot-device-spi", &boot_device_spi); 1944 if (ret) 1945 goto boot_device_fail; 1946 1947 ret = regmap_read(regmap, boot_device_reg, &boot_device); 1948 if (ret) 1949 goto boot_device_fail; 1950 1951 if (boot_device != boot_device_spi) 1952 fsm->booted_from_spi = false; 1953 1954 return; 1955 1956 boot_device_fail: 1957 dev_warn(&pdev->dev, 1958 "failed to fetch boot device, assuming boot from SPI\n"); 1959 } 1960 1961 static int stfsm_probe(struct platform_device *pdev) 1962 { 1963 struct device_node *np = pdev->dev.of_node; 1964 struct mtd_part_parser_data ppdata; 1965 struct flash_info *info; 1966 struct resource *res; 1967 struct stfsm *fsm; 1968 int ret; 1969 1970 if (!np) { 1971 dev_err(&pdev->dev, "No DT found\n"); 1972 return -EINVAL; 1973 } 1974 ppdata.of_node = np; 1975 1976 fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL); 1977 if (!fsm) 1978 return -ENOMEM; 1979 1980 fsm->dev = &pdev->dev; 1981 1982 platform_set_drvdata(pdev, fsm); 1983 1984 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1985 if (!res) { 1986 dev_err(&pdev->dev, "Resource not found\n"); 1987 return -ENODEV; 1988 } 1989 1990 fsm->base = devm_ioremap_resource(&pdev->dev, res); 1991 if (IS_ERR(fsm->base)) { 1992 dev_err(&pdev->dev, 1993 "Failed to reserve memory region %pR\n", res); 1994 return PTR_ERR(fsm->base); 1995 } 1996 1997 mutex_init(&fsm->lock); 1998 1999 ret = stfsm_init(fsm); 2000 if (ret) { 2001 dev_err(&pdev->dev, "Failed to initialise FSM Controller\n"); 2002 return ret; 2003 } 2004 2005 stfsm_fetch_platform_configs(pdev); 2006 2007 /* Detect SPI FLASH device */ 2008 info = stfsm_jedec_probe(fsm); 2009 if (!info) 2010 return -ENODEV; 2011 fsm->info = info; 2012 2013 /* Use device size to determine address width */ 2014 if (info->sector_size * info->n_sectors > 0x1000000) 2015 info->flags |= FLASH_FLAG_32BIT_ADDR; 2016 2017 /* 2018 * Configure READ/WRITE/ERASE sequences according to platform and 2019 * device flags. 2020 */ 2021 if (info->config) { 2022 ret = info->config(fsm); 2023 if (ret) 2024 return ret; 2025 } else { 2026 ret = stfsm_prepare_rwe_seqs_default(fsm); 2027 if (ret) 2028 return ret; 2029 } 2030 2031 fsm->mtd.name = info->name; 2032 fsm->mtd.dev.parent = &pdev->dev; 2033 fsm->mtd.type = MTD_NORFLASH; 2034 fsm->mtd.writesize = 4; 2035 fsm->mtd.writebufsize = fsm->mtd.writesize; 2036 fsm->mtd.flags = MTD_CAP_NORFLASH; 2037 fsm->mtd.size = info->sector_size * info->n_sectors; 2038 fsm->mtd.erasesize = info->sector_size; 2039 2040 fsm->mtd._read = stfsm_mtd_read; 2041 fsm->mtd._write = stfsm_mtd_write; 2042 fsm->mtd._erase = stfsm_mtd_erase; 2043 2044 dev_info(&pdev->dev, 2045 "Found serial flash device: %s\n" 2046 " size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n", 2047 info->name, 2048 (long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20), 2049 fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10)); 2050 2051 return mtd_device_parse_register(&fsm->mtd, NULL, &ppdata, NULL, 0); 2052 } 2053 2054 static int stfsm_remove(struct platform_device *pdev) 2055 { 2056 struct stfsm *fsm = platform_get_drvdata(pdev); 2057 2058 return mtd_device_unregister(&fsm->mtd); 2059 } 2060 2061 static const struct of_device_id stfsm_match[] = { 2062 { .compatible = "st,spi-fsm", }, 2063 {}, 2064 }; 2065 MODULE_DEVICE_TABLE(of, stfsm_match); 2066 2067 static struct platform_driver stfsm_driver = { 2068 .probe = stfsm_probe, 2069 .remove = stfsm_remove, 2070 .driver = { 2071 .name = "st-spi-fsm", 2072 .of_match_table = stfsm_match, 2073 }, 2074 }; 2075 module_platform_driver(stfsm_driver); 2076 2077 MODULE_AUTHOR("Angus Clark <angus.clark@st.com>"); 2078 MODULE_DESCRIPTION("ST SPI FSM driver"); 2079 MODULE_LICENSE("GPL"); 2080