1 /* 2 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller 3 * 4 * Author: Angus Clark <angus.clark@st.com> 5 * 6 * Copyright (C) 2010-2014 STMicroelectronics Limited 7 * 8 * JEDEC probe based on drivers/mtd/devices/m25p80.c 9 * 10 * This code is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 */ 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/regmap.h> 18 #include <linux/platform_device.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/partitions.h> 22 #include <linux/sched.h> 23 #include <linux/delay.h> 24 #include <linux/io.h> 25 #include <linux/of.h> 26 27 #include "serial_flash_cmds.h" 28 29 /* 30 * FSM SPI Controller Registers 31 */ 32 #define SPI_CLOCKDIV 0x0010 33 #define SPI_MODESELECT 0x0018 34 #define SPI_CONFIGDATA 0x0020 35 #define SPI_STA_MODE_CHANGE 0x0028 36 #define SPI_FAST_SEQ_TRANSFER_SIZE 0x0100 37 #define SPI_FAST_SEQ_ADD1 0x0104 38 #define SPI_FAST_SEQ_ADD2 0x0108 39 #define SPI_FAST_SEQ_ADD_CFG 0x010c 40 #define SPI_FAST_SEQ_OPC1 0x0110 41 #define SPI_FAST_SEQ_OPC2 0x0114 42 #define SPI_FAST_SEQ_OPC3 0x0118 43 #define SPI_FAST_SEQ_OPC4 0x011c 44 #define SPI_FAST_SEQ_OPC5 0x0120 45 #define SPI_MODE_BITS 0x0124 46 #define SPI_DUMMY_BITS 0x0128 47 #define SPI_FAST_SEQ_FLASH_STA_DATA 0x012c 48 #define SPI_FAST_SEQ_1 0x0130 49 #define SPI_FAST_SEQ_2 0x0134 50 #define SPI_FAST_SEQ_3 0x0138 51 #define SPI_FAST_SEQ_4 0x013c 52 #define SPI_FAST_SEQ_CFG 0x0140 53 #define SPI_FAST_SEQ_STA 0x0144 54 #define SPI_QUAD_BOOT_SEQ_INIT_1 0x0148 55 #define SPI_QUAD_BOOT_SEQ_INIT_2 0x014c 56 #define SPI_QUAD_BOOT_READ_SEQ_1 0x0150 57 #define SPI_QUAD_BOOT_READ_SEQ_2 0x0154 58 #define SPI_PROGRAM_ERASE_TIME 0x0158 59 #define SPI_MULT_PAGE_REPEAT_SEQ_1 0x015c 60 #define SPI_MULT_PAGE_REPEAT_SEQ_2 0x0160 61 #define SPI_STATUS_WR_TIME_REG 0x0164 62 #define SPI_FAST_SEQ_DATA_REG 0x0300 63 64 /* 65 * Register: SPI_MODESELECT 66 */ 67 #define SPI_MODESELECT_CONTIG 0x01 68 #define SPI_MODESELECT_FASTREAD 0x02 69 #define SPI_MODESELECT_DUALIO 0x04 70 #define SPI_MODESELECT_FSM 0x08 71 #define SPI_MODESELECT_QUADBOOT 0x10 72 73 /* 74 * Register: SPI_CONFIGDATA 75 */ 76 #define SPI_CFG_DEVICE_ST 0x1 77 #define SPI_CFG_DEVICE_ATMEL 0x4 78 #define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0xfff) << 4) 79 #define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16) 80 #define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24) 81 82 #define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0x0AA) 83 #define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0xA0) 84 #define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0x00) 85 86 /* 87 * Register: SPI_FAST_SEQ_TRANSFER_SIZE 88 */ 89 #define TRANSFER_SIZE(x) ((x) * 8) 90 91 /* 92 * Register: SPI_FAST_SEQ_ADD_CFG 93 */ 94 #define ADR_CFG_CYCLES_ADD1(x) ((x) << 0) 95 #define ADR_CFG_PADS_1_ADD1 (0x0 << 6) 96 #define ADR_CFG_PADS_2_ADD1 (0x1 << 6) 97 #define ADR_CFG_PADS_4_ADD1 (0x3 << 6) 98 #define ADR_CFG_CSDEASSERT_ADD1 (1 << 8) 99 #define ADR_CFG_CYCLES_ADD2(x) ((x) << (0+16)) 100 #define ADR_CFG_PADS_1_ADD2 (0x0 << (6+16)) 101 #define ADR_CFG_PADS_2_ADD2 (0x1 << (6+16)) 102 #define ADR_CFG_PADS_4_ADD2 (0x3 << (6+16)) 103 #define ADR_CFG_CSDEASSERT_ADD2 (1 << (8+16)) 104 105 /* 106 * Register: SPI_FAST_SEQ_n 107 */ 108 #define SEQ_OPC_OPCODE(x) ((x) << 0) 109 #define SEQ_OPC_CYCLES(x) ((x) << 8) 110 #define SEQ_OPC_PADS_1 (0x0 << 14) 111 #define SEQ_OPC_PADS_2 (0x1 << 14) 112 #define SEQ_OPC_PADS_4 (0x3 << 14) 113 #define SEQ_OPC_CSDEASSERT (1 << 16) 114 115 /* 116 * Register: SPI_FAST_SEQ_CFG 117 */ 118 #define SEQ_CFG_STARTSEQ (1 << 0) 119 #define SEQ_CFG_SWRESET (1 << 5) 120 #define SEQ_CFG_CSDEASSERT (1 << 6) 121 #define SEQ_CFG_READNOTWRITE (1 << 7) 122 #define SEQ_CFG_ERASE (1 << 8) 123 #define SEQ_CFG_PADS_1 (0x0 << 16) 124 #define SEQ_CFG_PADS_2 (0x1 << 16) 125 #define SEQ_CFG_PADS_4 (0x3 << 16) 126 127 /* 128 * Register: SPI_MODE_BITS 129 */ 130 #define MODE_DATA(x) (x & 0xff) 131 #define MODE_CYCLES(x) ((x & 0x3f) << 16) 132 #define MODE_PADS_1 (0x0 << 22) 133 #define MODE_PADS_2 (0x1 << 22) 134 #define MODE_PADS_4 (0x3 << 22) 135 #define DUMMY_CSDEASSERT (1 << 24) 136 137 /* 138 * Register: SPI_DUMMY_BITS 139 */ 140 #define DUMMY_CYCLES(x) ((x & 0x3f) << 16) 141 #define DUMMY_PADS_1 (0x0 << 22) 142 #define DUMMY_PADS_2 (0x1 << 22) 143 #define DUMMY_PADS_4 (0x3 << 22) 144 #define DUMMY_CSDEASSERT (1 << 24) 145 146 /* 147 * Register: SPI_FAST_SEQ_FLASH_STA_DATA 148 */ 149 #define STA_DATA_BYTE1(x) ((x & 0xff) << 0) 150 #define STA_DATA_BYTE2(x) ((x & 0xff) << 8) 151 #define STA_PADS_1 (0x0 << 16) 152 #define STA_PADS_2 (0x1 << 16) 153 #define STA_PADS_4 (0x3 << 16) 154 #define STA_CSDEASSERT (0x1 << 20) 155 #define STA_RDNOTWR (0x1 << 21) 156 157 /* 158 * FSM SPI Instruction Opcodes 159 */ 160 #define STFSM_OPC_CMD 0x1 161 #define STFSM_OPC_ADD 0x2 162 #define STFSM_OPC_STA 0x3 163 #define STFSM_OPC_MODE 0x4 164 #define STFSM_OPC_DUMMY 0x5 165 #define STFSM_OPC_DATA 0x6 166 #define STFSM_OPC_WAIT 0x7 167 #define STFSM_OPC_JUMP 0x8 168 #define STFSM_OPC_GOTO 0x9 169 #define STFSM_OPC_STOP 0xF 170 171 /* 172 * FSM SPI Instructions (== opcode + operand). 173 */ 174 #define STFSM_INSTR(cmd, op) ((cmd) | ((op) << 4)) 175 176 #define STFSM_INST_CMD1 STFSM_INSTR(STFSM_OPC_CMD, 1) 177 #define STFSM_INST_CMD2 STFSM_INSTR(STFSM_OPC_CMD, 2) 178 #define STFSM_INST_CMD3 STFSM_INSTR(STFSM_OPC_CMD, 3) 179 #define STFSM_INST_CMD4 STFSM_INSTR(STFSM_OPC_CMD, 4) 180 #define STFSM_INST_CMD5 STFSM_INSTR(STFSM_OPC_CMD, 5) 181 #define STFSM_INST_ADD1 STFSM_INSTR(STFSM_OPC_ADD, 1) 182 #define STFSM_INST_ADD2 STFSM_INSTR(STFSM_OPC_ADD, 2) 183 184 #define STFSM_INST_DATA_WRITE STFSM_INSTR(STFSM_OPC_DATA, 1) 185 #define STFSM_INST_DATA_READ STFSM_INSTR(STFSM_OPC_DATA, 2) 186 187 #define STFSM_INST_STA_RD1 STFSM_INSTR(STFSM_OPC_STA, 0x1) 188 #define STFSM_INST_STA_WR1 STFSM_INSTR(STFSM_OPC_STA, 0x1) 189 #define STFSM_INST_STA_RD2 STFSM_INSTR(STFSM_OPC_STA, 0x2) 190 #define STFSM_INST_STA_WR1_2 STFSM_INSTR(STFSM_OPC_STA, 0x3) 191 192 #define STFSM_INST_MODE STFSM_INSTR(STFSM_OPC_MODE, 0) 193 #define STFSM_INST_DUMMY STFSM_INSTR(STFSM_OPC_DUMMY, 0) 194 #define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0) 195 #define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0) 196 197 #define STFSM_DEFAULT_EMI_FREQ 100000000UL /* 100 MHz */ 198 #define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */ 199 200 #define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */ 201 202 #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */ 203 204 /* Flash Commands */ 205 #define FLASH_CMD_WREN 0x06 206 #define FLASH_CMD_WRDI 0x04 207 #define FLASH_CMD_RDID 0x9f 208 #define FLASH_CMD_RDSR 0x05 209 #define FLASH_CMD_RDSR2 0x35 210 #define FLASH_CMD_WRSR 0x01 211 #define FLASH_CMD_SE_4K 0x20 212 #define FLASH_CMD_SE_32K 0x52 213 #define FLASH_CMD_SE 0xd8 214 #define FLASH_CMD_CHIPERASE 0xc7 215 #define FLASH_CMD_WRVCR 0x81 216 #define FLASH_CMD_RDVCR 0x85 217 218 #define FLASH_CMD_READ 0x03 /* READ */ 219 #define FLASH_CMD_READ_FAST 0x0b /* FAST READ */ 220 #define FLASH_CMD_READ_1_1_2 0x3b /* DUAL OUTPUT READ */ 221 #define FLASH_CMD_READ_1_2_2 0xbb /* DUAL I/O READ */ 222 #define FLASH_CMD_READ_1_1_4 0x6b /* QUAD OUTPUT READ */ 223 #define FLASH_CMD_READ_1_4_4 0xeb /* QUAD I/O READ */ 224 225 #define FLASH_CMD_WRITE 0x02 /* PAGE PROGRAM */ 226 #define FLASH_CMD_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */ 227 #define FLASH_CMD_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */ 228 #define FLASH_CMD_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */ 229 #define FLASH_CMD_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */ 230 231 #define FLASH_CMD_EN4B_ADDR 0xb7 /* Enter 4-byte address mode */ 232 #define FLASH_CMD_EX4B_ADDR 0xe9 /* Exit 4-byte address mode */ 233 234 /* READ commands with 32-bit addressing (N25Q256 and S25FLxxxS) */ 235 #define FLASH_CMD_READ4 0x13 236 #define FLASH_CMD_READ4_FAST 0x0c 237 #define FLASH_CMD_READ4_1_1_2 0x3c 238 #define FLASH_CMD_READ4_1_2_2 0xbc 239 #define FLASH_CMD_READ4_1_1_4 0x6c 240 #define FLASH_CMD_READ4_1_4_4 0xec 241 242 /* S25FLxxxS commands */ 243 #define S25FL_CMD_WRITE4_1_1_4 0x34 244 #define S25FL_CMD_SE4 0xdc 245 #define S25FL_CMD_CLSR 0x30 246 #define S25FL_CMD_DYBWR 0xe1 247 #define S25FL_CMD_DYBRD 0xe0 248 #define S25FL_CMD_WRITE4 0x12 /* Note, opcode clashes with 249 * 'FLASH_CMD_WRITE_1_4_4' 250 * as found on N25Qxxx devices! */ 251 252 /* Status register */ 253 #define FLASH_STATUS_BUSY 0x01 254 #define FLASH_STATUS_WEL 0x02 255 #define FLASH_STATUS_BP0 0x04 256 #define FLASH_STATUS_BP1 0x08 257 #define FLASH_STATUS_BP2 0x10 258 #define FLASH_STATUS_SRWP0 0x80 259 #define FLASH_STATUS_TIMEOUT 0xff 260 /* S25FL Error Flags */ 261 #define S25FL_STATUS_E_ERR 0x20 262 #define S25FL_STATUS_P_ERR 0x40 263 264 #define FLASH_PAGESIZE 256 /* In Bytes */ 265 #define FLASH_PAGESIZE_32 (FLASH_PAGESIZE / 4) /* In uint32_t */ 266 #define FLASH_MAX_BUSY_WAIT (300 * HZ) /* Maximum 'CHIPERASE' time */ 267 268 /* 269 * Flags to tweak operation of default read/write/erase routines 270 */ 271 #define CFG_READ_TOGGLE_32BIT_ADDR 0x00000001 272 #define CFG_WRITE_TOGGLE_32BIT_ADDR 0x00000002 273 #define CFG_WRITE_EX_32BIT_ADDR_DELAY 0x00000004 274 #define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008 275 #define CFG_S25FL_CHECK_ERROR_FLAGS 0x00000010 276 277 struct stfsm_seq { 278 uint32_t data_size; 279 uint32_t addr1; 280 uint32_t addr2; 281 uint32_t addr_cfg; 282 uint32_t seq_opc[5]; 283 uint32_t mode; 284 uint32_t dummy; 285 uint32_t status; 286 uint8_t seq[16]; 287 uint32_t seq_cfg; 288 } __packed __aligned(4); 289 290 struct stfsm { 291 struct device *dev; 292 void __iomem *base; 293 struct resource *region; 294 struct mtd_info mtd; 295 struct mutex lock; 296 struct flash_info *info; 297 298 uint32_t configuration; 299 uint32_t fifo_dir_delay; 300 bool booted_from_spi; 301 bool reset_signal; 302 bool reset_por; 303 304 struct stfsm_seq stfsm_seq_read; 305 struct stfsm_seq stfsm_seq_write; 306 struct stfsm_seq stfsm_seq_en_32bit_addr; 307 }; 308 309 /* Parameters to configure a READ or WRITE FSM sequence */ 310 struct seq_rw_config { 311 uint32_t flags; /* flags to support config */ 312 uint8_t cmd; /* FLASH command */ 313 int write; /* Write Sequence */ 314 uint8_t addr_pads; /* No. of addr pads (MODE & DUMMY) */ 315 uint8_t data_pads; /* No. of data pads */ 316 uint8_t mode_data; /* MODE data */ 317 uint8_t mode_cycles; /* No. of MODE cycles */ 318 uint8_t dummy_cycles; /* No. of DUMMY cycles */ 319 }; 320 321 /* SPI Flash Device Table */ 322 struct flash_info { 323 char *name; 324 /* 325 * JEDEC id zero means "no ID" (most older chips); otherwise it has 326 * a high byte of zero plus three data bytes: the manufacturer id, 327 * then a two byte device id. 328 */ 329 u32 jedec_id; 330 u16 ext_id; 331 /* 332 * The size listed here is what works with FLASH_CMD_SE, which isn't 333 * necessarily called a "sector" by the vendor. 334 */ 335 unsigned sector_size; 336 u16 n_sectors; 337 u32 flags; 338 /* 339 * Note, where FAST_READ is supported, freq_max specifies the 340 * FAST_READ frequency, not the READ frequency. 341 */ 342 u32 max_freq; 343 int (*config)(struct stfsm *); 344 }; 345 346 static int stfsm_n25q_config(struct stfsm *fsm); 347 static int stfsm_mx25_config(struct stfsm *fsm); 348 static int stfsm_s25fl_config(struct stfsm *fsm); 349 static int stfsm_w25q_config(struct stfsm *fsm); 350 351 static struct flash_info flash_types[] = { 352 /* 353 * ST Microelectronics/Numonyx -- 354 * (newer production versions may have feature updates 355 * (eg faster operating frequency) 356 */ 357 #define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST) 358 { "m25p40", 0x202013, 0, 64 * 1024, 8, M25P_FLAG, 25, NULL }, 359 { "m25p80", 0x202014, 0, 64 * 1024, 16, M25P_FLAG, 25, NULL }, 360 { "m25p16", 0x202015, 0, 64 * 1024, 32, M25P_FLAG, 25, NULL }, 361 { "m25p32", 0x202016, 0, 64 * 1024, 64, M25P_FLAG, 50, NULL }, 362 { "m25p64", 0x202017, 0, 64 * 1024, 128, M25P_FLAG, 50, NULL }, 363 { "m25p128", 0x202018, 0, 256 * 1024, 64, M25P_FLAG, 50, NULL }, 364 365 #define M25PX_FLAG (FLASH_FLAG_READ_WRITE | \ 366 FLASH_FLAG_READ_FAST | \ 367 FLASH_FLAG_READ_1_1_2 | \ 368 FLASH_FLAG_WRITE_1_1_2) 369 { "m25px32", 0x207116, 0, 64 * 1024, 64, M25PX_FLAG, 75, NULL }, 370 { "m25px64", 0x207117, 0, 64 * 1024, 128, M25PX_FLAG, 75, NULL }, 371 372 #define MX25_FLAG (FLASH_FLAG_READ_WRITE | \ 373 FLASH_FLAG_READ_FAST | \ 374 FLASH_FLAG_READ_1_1_2 | \ 375 FLASH_FLAG_READ_1_2_2 | \ 376 FLASH_FLAG_READ_1_1_4 | \ 377 FLASH_FLAG_READ_1_4_4 | \ 378 FLASH_FLAG_SE_4K | \ 379 FLASH_FLAG_SE_32K) 380 { "mx25l25635e", 0xc22019, 0, 64*1024, 512, 381 (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, 382 stfsm_mx25_config }, 383 384 #define N25Q_FLAG (FLASH_FLAG_READ_WRITE | \ 385 FLASH_FLAG_READ_FAST | \ 386 FLASH_FLAG_READ_1_1_2 | \ 387 FLASH_FLAG_READ_1_2_2 | \ 388 FLASH_FLAG_READ_1_1_4 | \ 389 FLASH_FLAG_READ_1_4_4 | \ 390 FLASH_FLAG_WRITE_1_1_2 | \ 391 FLASH_FLAG_WRITE_1_2_2 | \ 392 FLASH_FLAG_WRITE_1_1_4 | \ 393 FLASH_FLAG_WRITE_1_4_4) 394 { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, 395 stfsm_n25q_config }, 396 { "n25q256", 0x20ba19, 0, 64 * 1024, 512, 397 N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config }, 398 399 /* 400 * Spansion S25FLxxxP 401 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC) 402 */ 403 #define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE | \ 404 FLASH_FLAG_READ_1_1_2 | \ 405 FLASH_FLAG_READ_1_2_2 | \ 406 FLASH_FLAG_READ_1_1_4 | \ 407 FLASH_FLAG_READ_1_4_4 | \ 408 FLASH_FLAG_WRITE_1_1_4 | \ 409 FLASH_FLAG_READ_FAST) 410 { "s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, S25FLXXXP_FLAG, 80, 411 stfsm_s25fl_config }, 412 { "s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, S25FLXXXP_FLAG, 80, 413 stfsm_s25fl_config }, 414 415 /* 416 * Spansion S25FLxxxS 417 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC) 418 * - RESET# signal supported by die but not bristled out on all 419 * package types. The package type is a function of board design, 420 * so this information is captured in the board's flags. 421 * - Supports 'DYB' sector protection. Depending on variant, sectors 422 * may default to locked state on power-on. 423 */ 424 #define S25FLXXXS_FLAG (S25FLXXXP_FLAG | \ 425 FLASH_FLAG_RESET | \ 426 FLASH_FLAG_DYB_LOCKING) 427 { "s25fl128s0", 0x012018, 0x0300, 256 * 1024, 64, S25FLXXXS_FLAG, 80, 428 stfsm_s25fl_config }, 429 { "s25fl128s1", 0x012018, 0x0301, 64 * 1024, 256, S25FLXXXS_FLAG, 80, 430 stfsm_s25fl_config }, 431 { "s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, 432 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config }, 433 { "s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, 434 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config }, 435 436 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 437 #define W25X_FLAG (FLASH_FLAG_READ_WRITE | \ 438 FLASH_FLAG_READ_FAST | \ 439 FLASH_FLAG_READ_1_1_2 | \ 440 FLASH_FLAG_WRITE_1_1_2) 441 { "w25x40", 0xef3013, 0, 64 * 1024, 8, W25X_FLAG, 75, NULL }, 442 { "w25x80", 0xef3014, 0, 64 * 1024, 16, W25X_FLAG, 75, NULL }, 443 { "w25x16", 0xef3015, 0, 64 * 1024, 32, W25X_FLAG, 75, NULL }, 444 { "w25x32", 0xef3016, 0, 64 * 1024, 64, W25X_FLAG, 75, NULL }, 445 { "w25x64", 0xef3017, 0, 64 * 1024, 128, W25X_FLAG, 75, NULL }, 446 447 /* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */ 448 #define W25Q_FLAG (FLASH_FLAG_READ_WRITE | \ 449 FLASH_FLAG_READ_FAST | \ 450 FLASH_FLAG_READ_1_1_2 | \ 451 FLASH_FLAG_READ_1_2_2 | \ 452 FLASH_FLAG_READ_1_1_4 | \ 453 FLASH_FLAG_READ_1_4_4 | \ 454 FLASH_FLAG_WRITE_1_1_4) 455 { "w25q80", 0xef4014, 0, 64 * 1024, 16, W25Q_FLAG, 80, 456 stfsm_w25q_config }, 457 { "w25q16", 0xef4015, 0, 64 * 1024, 32, W25Q_FLAG, 80, 458 stfsm_w25q_config }, 459 { "w25q32", 0xef4016, 0, 64 * 1024, 64, W25Q_FLAG, 80, 460 stfsm_w25q_config }, 461 { "w25q64", 0xef4017, 0, 64 * 1024, 128, W25Q_FLAG, 80, 462 stfsm_w25q_config }, 463 464 /* Sentinel */ 465 { NULL, 0x000000, 0, 0, 0, 0, 0, NULL }, 466 }; 467 468 /* 469 * FSM message sequence configurations: 470 * 471 * All configs are presented in order of preference 472 */ 473 474 /* Default READ configurations, in order of preference */ 475 static struct seq_rw_config default_read_configs[] = { 476 {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 2, 4}, 477 {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 4, 0}, 478 {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 4, 0}, 479 {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, 480 {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8}, 481 {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0}, 482 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 483 }; 484 485 /* Default WRITE configurations */ 486 static struct seq_rw_config default_write_configs[] = { 487 {FLASH_FLAG_WRITE_1_4_4, FLASH_CMD_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0}, 488 {FLASH_FLAG_WRITE_1_1_4, FLASH_CMD_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0}, 489 {FLASH_FLAG_WRITE_1_2_2, FLASH_CMD_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0}, 490 {FLASH_FLAG_WRITE_1_1_2, FLASH_CMD_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0}, 491 {FLASH_FLAG_READ_WRITE, FLASH_CMD_WRITE, 1, 1, 1, 0x00, 0, 0}, 492 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 493 }; 494 495 /* 496 * [N25Qxxx] Configuration 497 */ 498 #define N25Q_VCR_DUMMY_CYCLES(x) (((x) & 0xf) << 4) 499 #define N25Q_VCR_XIP_DISABLED ((uint8_t)0x1 << 3) 500 #define N25Q_VCR_WRAP_CONT 0x3 501 502 /* N25Q 3-byte Address READ configurations 503 * - 'FAST' variants configured for 8 dummy cycles. 504 * 505 * Note, the number of dummy cycles used for 'FAST' READ operations is 506 * configurable and would normally be tuned according to the READ command and 507 * operating frequency. However, this applies universally to all 'FAST' READ 508 * commands, including those used by the SPIBoot controller, and remains in 509 * force until the device is power-cycled. Since the SPIBoot controller is 510 * hard-wired to use 8 dummy cycles, we must configure the device to also use 8 511 * cycles. 512 */ 513 static struct seq_rw_config n25q_read3_configs[] = { 514 {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 0, 8}, 515 {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 0, 8}, 516 {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 0, 8}, 517 {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, 518 {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8}, 519 {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0}, 520 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 521 }; 522 523 /* N25Q 4-byte Address READ configurations 524 * - use special 4-byte address READ commands (reduces overheads, and 525 * reduces risk of hitting watchdog reset issues). 526 * - 'FAST' variants configured for 8 dummy cycles (see note above.) 527 */ 528 static struct seq_rw_config n25q_read4_configs[] = { 529 {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8}, 530 {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, 531 {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8}, 532 {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, 533 {FLASH_FLAG_READ_FAST, FLASH_CMD_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, 534 {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ4, 0, 1, 1, 0x00, 0, 0}, 535 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 536 }; 537 538 /* 539 * [MX25xxx] Configuration 540 */ 541 #define MX25_STATUS_QE (0x1 << 6) 542 543 static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq) 544 { 545 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 546 SEQ_OPC_CYCLES(8) | 547 SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR) | 548 SEQ_OPC_CSDEASSERT); 549 550 seq->seq[0] = STFSM_INST_CMD1; 551 seq->seq[1] = STFSM_INST_WAIT; 552 seq->seq[2] = STFSM_INST_STOP; 553 554 seq->seq_cfg = (SEQ_CFG_PADS_1 | 555 SEQ_CFG_ERASE | 556 SEQ_CFG_READNOTWRITE | 557 SEQ_CFG_CSDEASSERT | 558 SEQ_CFG_STARTSEQ); 559 560 return 0; 561 } 562 563 /* 564 * [S25FLxxx] Configuration 565 */ 566 #define STFSM_S25FL_CONFIG_QE (0x1 << 1) 567 568 /* 569 * S25FLxxxS devices provide three ways of supporting 32-bit addressing: Bank 570 * Register, Extended Address Modes, and a 32-bit address command set. The 571 * 32-bit address command set is used here, since it avoids any problems with 572 * entering a state that is incompatible with the SPIBoot Controller. 573 */ 574 static struct seq_rw_config stfsm_s25fl_read4_configs[] = { 575 {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4}, 576 {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8}, 577 {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0}, 578 {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8}, 579 {FLASH_FLAG_READ_FAST, FLASH_CMD_READ4_FAST, 0, 1, 1, 0x00, 0, 8}, 580 {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ4, 0, 1, 1, 0x00, 0, 0}, 581 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 582 }; 583 584 static struct seq_rw_config stfsm_s25fl_write4_configs[] = { 585 {FLASH_FLAG_WRITE_1_1_4, S25FL_CMD_WRITE4_1_1_4, 1, 1, 4, 0x00, 0, 0}, 586 {FLASH_FLAG_READ_WRITE, S25FL_CMD_WRITE4, 1, 1, 1, 0x00, 0, 0}, 587 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 588 }; 589 590 /* 591 * [W25Qxxx] Configuration 592 */ 593 #define W25Q_STATUS_QE (0x1 << 9) 594 595 static struct stfsm_seq stfsm_seq_read_jedec = { 596 .data_size = TRANSFER_SIZE(8), 597 .seq_opc[0] = (SEQ_OPC_PADS_1 | 598 SEQ_OPC_CYCLES(8) | 599 SEQ_OPC_OPCODE(FLASH_CMD_RDID)), 600 .seq = { 601 STFSM_INST_CMD1, 602 STFSM_INST_DATA_READ, 603 STFSM_INST_STOP, 604 }, 605 .seq_cfg = (SEQ_CFG_PADS_1 | 606 SEQ_CFG_READNOTWRITE | 607 SEQ_CFG_CSDEASSERT | 608 SEQ_CFG_STARTSEQ), 609 }; 610 611 static struct stfsm_seq stfsm_seq_read_status_fifo = { 612 .data_size = TRANSFER_SIZE(4), 613 .seq_opc[0] = (SEQ_OPC_PADS_1 | 614 SEQ_OPC_CYCLES(8) | 615 SEQ_OPC_OPCODE(FLASH_CMD_RDSR)), 616 .seq = { 617 STFSM_INST_CMD1, 618 STFSM_INST_DATA_READ, 619 STFSM_INST_STOP, 620 }, 621 .seq_cfg = (SEQ_CFG_PADS_1 | 622 SEQ_CFG_READNOTWRITE | 623 SEQ_CFG_CSDEASSERT | 624 SEQ_CFG_STARTSEQ), 625 }; 626 627 static struct stfsm_seq stfsm_seq_erase_sector = { 628 /* 'addr_cfg' configured during initialisation */ 629 .seq_opc = { 630 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 631 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), 632 633 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 634 SEQ_OPC_OPCODE(FLASH_CMD_SE)), 635 }, 636 .seq = { 637 STFSM_INST_CMD1, 638 STFSM_INST_CMD2, 639 STFSM_INST_ADD1, 640 STFSM_INST_ADD2, 641 STFSM_INST_STOP, 642 }, 643 .seq_cfg = (SEQ_CFG_PADS_1 | 644 SEQ_CFG_READNOTWRITE | 645 SEQ_CFG_CSDEASSERT | 646 SEQ_CFG_STARTSEQ), 647 }; 648 649 static struct stfsm_seq stfsm_seq_erase_chip = { 650 .seq_opc = { 651 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 652 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), 653 654 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 655 SEQ_OPC_OPCODE(FLASH_CMD_CHIPERASE) | SEQ_OPC_CSDEASSERT), 656 }, 657 .seq = { 658 STFSM_INST_CMD1, 659 STFSM_INST_CMD2, 660 STFSM_INST_WAIT, 661 STFSM_INST_STOP, 662 }, 663 .seq_cfg = (SEQ_CFG_PADS_1 | 664 SEQ_CFG_ERASE | 665 SEQ_CFG_READNOTWRITE | 666 SEQ_CFG_CSDEASSERT | 667 SEQ_CFG_STARTSEQ), 668 }; 669 670 static struct stfsm_seq stfsm_seq_write_status = { 671 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 672 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), 673 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 674 SEQ_OPC_OPCODE(FLASH_CMD_WRSR)), 675 .seq = { 676 STFSM_INST_CMD1, 677 STFSM_INST_CMD2, 678 STFSM_INST_STA_WR1, 679 STFSM_INST_STOP, 680 }, 681 .seq_cfg = (SEQ_CFG_PADS_1 | 682 SEQ_CFG_READNOTWRITE | 683 SEQ_CFG_CSDEASSERT | 684 SEQ_CFG_STARTSEQ), 685 }; 686 687 static struct stfsm_seq stfsm_seq_wrvcr = { 688 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 689 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT), 690 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 691 SEQ_OPC_OPCODE(FLASH_CMD_WRVCR)), 692 .seq = { 693 STFSM_INST_CMD1, 694 STFSM_INST_CMD2, 695 STFSM_INST_STA_WR1, 696 STFSM_INST_STOP, 697 }, 698 .seq_cfg = (SEQ_CFG_PADS_1 | 699 SEQ_CFG_READNOTWRITE | 700 SEQ_CFG_CSDEASSERT | 701 SEQ_CFG_STARTSEQ), 702 }; 703 704 static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq) 705 { 706 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 707 SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR)); 708 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 709 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | 710 SEQ_OPC_CSDEASSERT); 711 712 seq->seq[0] = STFSM_INST_CMD2; 713 seq->seq[1] = STFSM_INST_CMD1; 714 seq->seq[2] = STFSM_INST_WAIT; 715 seq->seq[3] = STFSM_INST_STOP; 716 717 seq->seq_cfg = (SEQ_CFG_PADS_1 | 718 SEQ_CFG_ERASE | 719 SEQ_CFG_READNOTWRITE | 720 SEQ_CFG_CSDEASSERT | 721 SEQ_CFG_STARTSEQ); 722 723 return 0; 724 } 725 726 static inline int stfsm_is_idle(struct stfsm *fsm) 727 { 728 return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10; 729 } 730 731 static inline uint32_t stfsm_fifo_available(struct stfsm *fsm) 732 { 733 return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f; 734 } 735 736 static void stfsm_clear_fifo(struct stfsm *fsm) 737 { 738 uint32_t avail; 739 740 for (;;) { 741 avail = stfsm_fifo_available(fsm); 742 if (!avail) 743 break; 744 745 while (avail) { 746 readl(fsm->base + SPI_FAST_SEQ_DATA_REG); 747 avail--; 748 } 749 } 750 } 751 752 static inline void stfsm_load_seq(struct stfsm *fsm, 753 const struct stfsm_seq *seq) 754 { 755 void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE; 756 const uint32_t *src = (const uint32_t *)seq; 757 int words = sizeof(*seq) / sizeof(*src); 758 759 BUG_ON(!stfsm_is_idle(fsm)); 760 761 while (words--) { 762 writel(*src, dst); 763 src++; 764 dst += 4; 765 } 766 } 767 768 static void stfsm_wait_seq(struct stfsm *fsm) 769 { 770 unsigned long deadline; 771 int timeout = 0; 772 773 deadline = jiffies + msecs_to_jiffies(STFSM_MAX_WAIT_SEQ_MS); 774 775 while (!timeout) { 776 if (time_after_eq(jiffies, deadline)) 777 timeout = 1; 778 779 if (stfsm_is_idle(fsm)) 780 return; 781 782 cond_resched(); 783 } 784 785 dev_err(fsm->dev, "timeout on sequence completion\n"); 786 } 787 788 static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, uint32_t size) 789 { 790 uint32_t remaining = size >> 2; 791 uint32_t avail; 792 uint32_t words; 793 794 dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size); 795 796 BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3)); 797 798 while (remaining) { 799 for (;;) { 800 avail = stfsm_fifo_available(fsm); 801 if (avail) 802 break; 803 udelay(1); 804 } 805 words = min(avail, remaining); 806 remaining -= words; 807 808 readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words); 809 buf += words; 810 } 811 } 812 813 static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf, 814 uint32_t size) 815 { 816 uint32_t words = size >> 2; 817 818 dev_dbg(fsm->dev, "writing %d bytes to FIFO\n", size); 819 820 BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3)); 821 822 writesl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words); 823 824 return size; 825 } 826 827 static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) 828 { 829 struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; 830 uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR; 831 832 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 833 SEQ_OPC_CYCLES(8) | 834 SEQ_OPC_OPCODE(cmd) | 835 SEQ_OPC_CSDEASSERT); 836 837 stfsm_load_seq(fsm, seq); 838 839 stfsm_wait_seq(fsm); 840 841 return 0; 842 } 843 844 static uint8_t stfsm_wait_busy(struct stfsm *fsm) 845 { 846 struct stfsm_seq *seq = &stfsm_seq_read_status_fifo; 847 unsigned long deadline; 848 uint32_t status; 849 int timeout = 0; 850 851 /* Use RDRS1 */ 852 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 853 SEQ_OPC_CYCLES(8) | 854 SEQ_OPC_OPCODE(FLASH_CMD_RDSR)); 855 856 /* Load read_status sequence */ 857 stfsm_load_seq(fsm, seq); 858 859 /* 860 * Repeat until busy bit is deasserted, or timeout, or error (S25FLxxxS) 861 */ 862 deadline = jiffies + FLASH_MAX_BUSY_WAIT; 863 while (!timeout) { 864 if (time_after_eq(jiffies, deadline)) 865 timeout = 1; 866 867 stfsm_wait_seq(fsm); 868 869 stfsm_read_fifo(fsm, &status, 4); 870 871 if ((status & FLASH_STATUS_BUSY) == 0) 872 return 0; 873 874 if ((fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) && 875 ((status & S25FL_STATUS_P_ERR) || 876 (status & S25FL_STATUS_E_ERR))) 877 return (uint8_t)(status & 0xff); 878 879 if (!timeout) 880 /* Restart */ 881 writel(seq->seq_cfg, fsm->base + SPI_FAST_SEQ_CFG); 882 883 cond_resched(); 884 } 885 886 dev_err(fsm->dev, "timeout on wait_busy\n"); 887 888 return FLASH_STATUS_TIMEOUT; 889 } 890 891 static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd, 892 uint8_t *status) 893 { 894 struct stfsm_seq *seq = &stfsm_seq_read_status_fifo; 895 uint32_t tmp; 896 897 dev_dbg(fsm->dev, "reading STA[%s]\n", 898 (cmd == FLASH_CMD_RDSR) ? "1" : "2"); 899 900 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 901 SEQ_OPC_CYCLES(8) | 902 SEQ_OPC_OPCODE(cmd)), 903 904 stfsm_load_seq(fsm, seq); 905 906 stfsm_read_fifo(fsm, &tmp, 4); 907 908 *status = (uint8_t)(tmp >> 24); 909 910 stfsm_wait_seq(fsm); 911 912 return 0; 913 } 914 915 static int stfsm_write_status(struct stfsm *fsm, uint16_t status, 916 int sta_bytes) 917 { 918 struct stfsm_seq *seq = &stfsm_seq_write_status; 919 920 dev_dbg(fsm->dev, "writing STA[%s] 0x%04x\n", 921 (sta_bytes == 1) ? "1" : "1+2", status); 922 923 seq->status = (uint32_t)status | STA_PADS_1 | STA_CSDEASSERT; 924 seq->seq[2] = (sta_bytes == 1) ? 925 STFSM_INST_STA_WR1 : STFSM_INST_STA_WR1_2; 926 927 stfsm_load_seq(fsm, seq); 928 929 stfsm_wait_seq(fsm); 930 931 return 0; 932 }; 933 934 static int stfsm_wrvcr(struct stfsm *fsm, uint8_t data) 935 { 936 struct stfsm_seq *seq = &stfsm_seq_wrvcr; 937 938 dev_dbg(fsm->dev, "writing VCR 0x%02x\n", data); 939 940 seq->status = (STA_DATA_BYTE1(data) | STA_PADS_1 | STA_CSDEASSERT); 941 942 stfsm_load_seq(fsm, seq); 943 944 stfsm_wait_seq(fsm); 945 946 return 0; 947 } 948 949 /* 950 * SoC reset on 'boot-from-spi' systems 951 * 952 * Certain modes of operation cause the Flash device to enter a particular state 953 * for a period of time (e.g. 'Erase Sector', 'Quad Enable', and 'Enter 32-bit 954 * Addr' commands). On boot-from-spi systems, it is important to consider what 955 * happens if a warm reset occurs during this period. The SPIBoot controller 956 * assumes that Flash device is in its default reset state, 24-bit address mode, 957 * and ready to accept commands. This can be achieved using some form of 958 * on-board logic/controller to force a device POR in response to a SoC-level 959 * reset or by making use of the device reset signal if available (limited 960 * number of devices only). 961 * 962 * Failure to take such precautions can cause problems following a warm reset. 963 * For some operations (e.g. ERASE), there is little that can be done. For 964 * other modes of operation (e.g. 32-bit addressing), options are often 965 * available that can help minimise the window in which a reset could cause a 966 * problem. 967 * 968 */ 969 static bool stfsm_can_handle_soc_reset(struct stfsm *fsm) 970 { 971 /* Reset signal is available on the board and supported by the device */ 972 if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET) 973 return true; 974 975 /* Board-level logic forces a power-on-reset */ 976 if (fsm->reset_por) 977 return true; 978 979 /* Reset is not properly handled and may result in failure to reboot */ 980 return false; 981 } 982 983 /* Configure 'addr_cfg' according to addressing mode */ 984 static void stfsm_prepare_erasesec_seq(struct stfsm *fsm, 985 struct stfsm_seq *seq) 986 { 987 int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8; 988 989 seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(addr1_cycles) | 990 ADR_CFG_PADS_1_ADD1 | 991 ADR_CFG_CYCLES_ADD2(16) | 992 ADR_CFG_PADS_1_ADD2 | 993 ADR_CFG_CSDEASSERT_ADD2); 994 } 995 996 /* Search for preferred configuration based on available flags */ 997 static struct seq_rw_config * 998 stfsm_search_seq_rw_configs(struct stfsm *fsm, 999 struct seq_rw_config cfgs[]) 1000 { 1001 struct seq_rw_config *config; 1002 int flags = fsm->info->flags; 1003 1004 for (config = cfgs; config->cmd != 0; config++) 1005 if ((config->flags & flags) == config->flags) 1006 return config; 1007 1008 return NULL; 1009 } 1010 1011 /* Prepare a READ/WRITE sequence according to configuration parameters */ 1012 static void stfsm_prepare_rw_seq(struct stfsm *fsm, 1013 struct stfsm_seq *seq, 1014 struct seq_rw_config *cfg) 1015 { 1016 int addr1_cycles, addr2_cycles; 1017 int i = 0; 1018 1019 memset(seq, 0, sizeof(*seq)); 1020 1021 /* Add READ/WRITE OPC */ 1022 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 | 1023 SEQ_OPC_CYCLES(8) | 1024 SEQ_OPC_OPCODE(cfg->cmd)); 1025 1026 /* Add WREN OPC for a WRITE sequence */ 1027 if (cfg->write) 1028 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 | 1029 SEQ_OPC_CYCLES(8) | 1030 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | 1031 SEQ_OPC_CSDEASSERT); 1032 1033 /* Address configuration (24 or 32-bit addresses) */ 1034 addr1_cycles = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8; 1035 addr1_cycles /= cfg->addr_pads; 1036 addr2_cycles = 16 / cfg->addr_pads; 1037 seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 | /* ADD1 cycles */ 1038 (cfg->addr_pads - 1) << 6 | /* ADD1 pads */ 1039 (addr2_cycles & 0x3f) << 16 | /* ADD2 cycles */ 1040 ((cfg->addr_pads - 1) << 22)); /* ADD2 pads */ 1041 1042 /* Data/Sequence configuration */ 1043 seq->seq_cfg = ((cfg->data_pads - 1) << 16 | 1044 SEQ_CFG_STARTSEQ | 1045 SEQ_CFG_CSDEASSERT); 1046 if (!cfg->write) 1047 seq->seq_cfg |= SEQ_CFG_READNOTWRITE; 1048 1049 /* Mode configuration (no. of pads taken from addr cfg) */ 1050 seq->mode = ((cfg->mode_data & 0xff) << 0 | /* data */ 1051 (cfg->mode_cycles & 0x3f) << 16 | /* cycles */ 1052 (cfg->addr_pads - 1) << 22); /* pads */ 1053 1054 /* Dummy configuration (no. of pads taken from addr cfg) */ 1055 seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 | /* cycles */ 1056 (cfg->addr_pads - 1) << 22); /* pads */ 1057 1058 1059 /* Instruction sequence */ 1060 i = 0; 1061 if (cfg->write) 1062 seq->seq[i++] = STFSM_INST_CMD2; 1063 1064 seq->seq[i++] = STFSM_INST_CMD1; 1065 1066 seq->seq[i++] = STFSM_INST_ADD1; 1067 seq->seq[i++] = STFSM_INST_ADD2; 1068 1069 if (cfg->mode_cycles) 1070 seq->seq[i++] = STFSM_INST_MODE; 1071 1072 if (cfg->dummy_cycles) 1073 seq->seq[i++] = STFSM_INST_DUMMY; 1074 1075 seq->seq[i++] = 1076 cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ; 1077 seq->seq[i++] = STFSM_INST_STOP; 1078 } 1079 1080 static int stfsm_search_prepare_rw_seq(struct stfsm *fsm, 1081 struct stfsm_seq *seq, 1082 struct seq_rw_config *cfgs) 1083 { 1084 struct seq_rw_config *config; 1085 1086 config = stfsm_search_seq_rw_configs(fsm, cfgs); 1087 if (!config) { 1088 dev_err(fsm->dev, "failed to find suitable config\n"); 1089 return -EINVAL; 1090 } 1091 1092 stfsm_prepare_rw_seq(fsm, seq, config); 1093 1094 return 0; 1095 } 1096 1097 /* Prepare a READ/WRITE/ERASE 'default' sequences */ 1098 static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm) 1099 { 1100 uint32_t flags = fsm->info->flags; 1101 int ret; 1102 1103 /* Configure 'READ' sequence */ 1104 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1105 default_read_configs); 1106 if (ret) { 1107 dev_err(fsm->dev, 1108 "failed to prep READ sequence with flags [0x%08x]\n", 1109 flags); 1110 return ret; 1111 } 1112 1113 /* Configure 'WRITE' sequence */ 1114 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, 1115 default_write_configs); 1116 if (ret) { 1117 dev_err(fsm->dev, 1118 "failed to prep WRITE sequence with flags [0x%08x]\n", 1119 flags); 1120 return ret; 1121 } 1122 1123 /* Configure 'ERASE_SECTOR' sequence */ 1124 stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); 1125 1126 return 0; 1127 } 1128 1129 static int stfsm_mx25_config(struct stfsm *fsm) 1130 { 1131 uint32_t flags = fsm->info->flags; 1132 uint32_t data_pads; 1133 uint8_t sta; 1134 int ret; 1135 bool soc_reset; 1136 1137 /* 1138 * Use default READ/WRITE sequences 1139 */ 1140 ret = stfsm_prepare_rwe_seqs_default(fsm); 1141 if (ret) 1142 return ret; 1143 1144 /* 1145 * Configure 32-bit Address Support 1146 */ 1147 if (flags & FLASH_FLAG_32BIT_ADDR) { 1148 /* Configure 'enter_32bitaddr' FSM sequence */ 1149 stfsm_mx25_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); 1150 1151 soc_reset = stfsm_can_handle_soc_reset(fsm); 1152 if (soc_reset || !fsm->booted_from_spi) { 1153 /* If we can handle SoC resets, we enable 32-bit address 1154 * mode pervasively */ 1155 stfsm_enter_32bit_addr(fsm, 1); 1156 1157 } else { 1158 /* Else, enable/disable 32-bit addressing before/after 1159 * each operation */ 1160 fsm->configuration = (CFG_READ_TOGGLE_32BIT_ADDR | 1161 CFG_WRITE_TOGGLE_32BIT_ADDR | 1162 CFG_ERASESEC_TOGGLE_32BIT_ADDR); 1163 /* It seems a small delay is required after exiting 1164 * 32-bit mode following a write operation. The issue 1165 * is under investigation. 1166 */ 1167 fsm->configuration |= CFG_WRITE_EX_32BIT_ADDR_DELAY; 1168 } 1169 } 1170 1171 /* For QUAD mode, set 'QE' STATUS bit */ 1172 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; 1173 if (data_pads == 4) { 1174 stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta); 1175 sta |= MX25_STATUS_QE; 1176 stfsm_write_status(fsm, sta, 1); 1177 } 1178 1179 return 0; 1180 } 1181 1182 static int stfsm_n25q_config(struct stfsm *fsm) 1183 { 1184 uint32_t flags = fsm->info->flags; 1185 uint8_t vcr; 1186 int ret = 0; 1187 bool soc_reset; 1188 1189 /* Configure 'READ' sequence */ 1190 if (flags & FLASH_FLAG_32BIT_ADDR) 1191 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1192 n25q_read4_configs); 1193 else 1194 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1195 n25q_read3_configs); 1196 if (ret) { 1197 dev_err(fsm->dev, 1198 "failed to prepare READ sequence with flags [0x%08x]\n", 1199 flags); 1200 return ret; 1201 } 1202 1203 /* Configure 'WRITE' sequence (default configs) */ 1204 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, 1205 default_write_configs); 1206 if (ret) { 1207 dev_err(fsm->dev, 1208 "preparing WRITE sequence using flags [0x%08x] failed\n", 1209 flags); 1210 return ret; 1211 } 1212 1213 /* * Configure 'ERASE_SECTOR' sequence */ 1214 stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); 1215 1216 /* Configure 32-bit address support */ 1217 if (flags & FLASH_FLAG_32BIT_ADDR) { 1218 stfsm_n25q_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); 1219 1220 soc_reset = stfsm_can_handle_soc_reset(fsm); 1221 if (soc_reset || !fsm->booted_from_spi) { 1222 /* 1223 * If we can handle SoC resets, we enable 32-bit 1224 * address mode pervasively 1225 */ 1226 stfsm_enter_32bit_addr(fsm, 1); 1227 } else { 1228 /* 1229 * If not, enable/disable for WRITE and ERASE 1230 * operations (READ uses special commands) 1231 */ 1232 fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR | 1233 CFG_ERASESEC_TOGGLE_32BIT_ADDR); 1234 } 1235 } 1236 1237 /* 1238 * Configure device to use 8 dummy cycles 1239 */ 1240 vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED | 1241 N25Q_VCR_WRAP_CONT); 1242 stfsm_wrvcr(fsm, vcr); 1243 1244 return 0; 1245 } 1246 1247 static void stfsm_s25fl_prepare_erasesec_seq_32(struct stfsm_seq *seq) 1248 { 1249 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | 1250 SEQ_OPC_CYCLES(8) | 1251 SEQ_OPC_OPCODE(S25FL_CMD_SE4)); 1252 1253 seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(16) | 1254 ADR_CFG_PADS_1_ADD1 | 1255 ADR_CFG_CYCLES_ADD2(16) | 1256 ADR_CFG_PADS_1_ADD2 | 1257 ADR_CFG_CSDEASSERT_ADD2); 1258 } 1259 1260 static void stfsm_s25fl_read_dyb(struct stfsm *fsm, uint32_t offs, uint8_t *dby) 1261 { 1262 uint32_t tmp; 1263 struct stfsm_seq seq = { 1264 .data_size = TRANSFER_SIZE(4), 1265 .seq_opc[0] = (SEQ_OPC_PADS_1 | 1266 SEQ_OPC_CYCLES(8) | 1267 SEQ_OPC_OPCODE(S25FL_CMD_DYBRD)), 1268 .addr_cfg = (ADR_CFG_CYCLES_ADD1(16) | 1269 ADR_CFG_PADS_1_ADD1 | 1270 ADR_CFG_CYCLES_ADD2(16) | 1271 ADR_CFG_PADS_1_ADD2), 1272 .addr1 = (offs >> 16) & 0xffff, 1273 .addr2 = offs & 0xffff, 1274 .seq = { 1275 STFSM_INST_CMD1, 1276 STFSM_INST_ADD1, 1277 STFSM_INST_ADD2, 1278 STFSM_INST_DATA_READ, 1279 STFSM_INST_STOP, 1280 }, 1281 .seq_cfg = (SEQ_CFG_PADS_1 | 1282 SEQ_CFG_READNOTWRITE | 1283 SEQ_CFG_CSDEASSERT | 1284 SEQ_CFG_STARTSEQ), 1285 }; 1286 1287 stfsm_load_seq(fsm, &seq); 1288 1289 stfsm_read_fifo(fsm, &tmp, 4); 1290 1291 *dby = (uint8_t)(tmp >> 24); 1292 1293 stfsm_wait_seq(fsm); 1294 } 1295 1296 static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby) 1297 { 1298 struct stfsm_seq seq = { 1299 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 1300 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | 1301 SEQ_OPC_CSDEASSERT), 1302 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 1303 SEQ_OPC_OPCODE(S25FL_CMD_DYBWR)), 1304 .addr_cfg = (ADR_CFG_CYCLES_ADD1(16) | 1305 ADR_CFG_PADS_1_ADD1 | 1306 ADR_CFG_CYCLES_ADD2(16) | 1307 ADR_CFG_PADS_1_ADD2), 1308 .status = (uint32_t)dby | STA_PADS_1 | STA_CSDEASSERT, 1309 .addr1 = (offs >> 16) & 0xffff, 1310 .addr2 = offs & 0xffff, 1311 .seq = { 1312 STFSM_INST_CMD1, 1313 STFSM_INST_CMD2, 1314 STFSM_INST_ADD1, 1315 STFSM_INST_ADD2, 1316 STFSM_INST_STA_WR1, 1317 STFSM_INST_STOP, 1318 }, 1319 .seq_cfg = (SEQ_CFG_PADS_1 | 1320 SEQ_CFG_READNOTWRITE | 1321 SEQ_CFG_CSDEASSERT | 1322 SEQ_CFG_STARTSEQ), 1323 }; 1324 1325 stfsm_load_seq(fsm, &seq); 1326 stfsm_wait_seq(fsm); 1327 1328 stfsm_wait_busy(fsm); 1329 } 1330 1331 static int stfsm_s25fl_clear_status_reg(struct stfsm *fsm) 1332 { 1333 struct stfsm_seq seq = { 1334 .seq_opc[0] = (SEQ_OPC_PADS_1 | 1335 SEQ_OPC_CYCLES(8) | 1336 SEQ_OPC_OPCODE(S25FL_CMD_CLSR) | 1337 SEQ_OPC_CSDEASSERT), 1338 .seq_opc[1] = (SEQ_OPC_PADS_1 | 1339 SEQ_OPC_CYCLES(8) | 1340 SEQ_OPC_OPCODE(FLASH_CMD_WRDI) | 1341 SEQ_OPC_CSDEASSERT), 1342 .seq = { 1343 STFSM_INST_CMD1, 1344 STFSM_INST_CMD2, 1345 STFSM_INST_WAIT, 1346 STFSM_INST_STOP, 1347 }, 1348 .seq_cfg = (SEQ_CFG_PADS_1 | 1349 SEQ_CFG_ERASE | 1350 SEQ_CFG_READNOTWRITE | 1351 SEQ_CFG_CSDEASSERT | 1352 SEQ_CFG_STARTSEQ), 1353 }; 1354 1355 stfsm_load_seq(fsm, &seq); 1356 1357 stfsm_wait_seq(fsm); 1358 1359 return 0; 1360 } 1361 1362 static int stfsm_s25fl_config(struct stfsm *fsm) 1363 { 1364 struct flash_info *info = fsm->info; 1365 uint32_t flags = info->flags; 1366 uint32_t data_pads; 1367 uint32_t offs; 1368 uint16_t sta_wr; 1369 uint8_t sr1, cr1, dyb; 1370 int ret; 1371 1372 if (flags & FLASH_FLAG_32BIT_ADDR) { 1373 /* 1374 * Prepare Read/Write/Erase sequences according to S25FLxxx 1375 * 32-bit address command set 1376 */ 1377 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1378 stfsm_s25fl_read4_configs); 1379 if (ret) 1380 return ret; 1381 1382 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, 1383 stfsm_s25fl_write4_configs); 1384 if (ret) 1385 return ret; 1386 1387 stfsm_s25fl_prepare_erasesec_seq_32(&stfsm_seq_erase_sector); 1388 1389 } else { 1390 /* Use default configurations for 24-bit addressing */ 1391 ret = stfsm_prepare_rwe_seqs_default(fsm); 1392 if (ret) 1393 return ret; 1394 } 1395 1396 /* 1397 * For devices that support 'DYB' sector locking, check lock status and 1398 * unlock sectors if necessary (some variants power-on with sectors 1399 * locked by default) 1400 */ 1401 if (flags & FLASH_FLAG_DYB_LOCKING) { 1402 offs = 0; 1403 for (offs = 0; offs < info->sector_size * info->n_sectors;) { 1404 stfsm_s25fl_read_dyb(fsm, offs, &dyb); 1405 if (dyb == 0x00) 1406 stfsm_s25fl_write_dyb(fsm, offs, 0xff); 1407 1408 /* Handle bottom/top 4KiB parameter sectors */ 1409 if ((offs < info->sector_size * 2) || 1410 (offs >= (info->sector_size - info->n_sectors * 4))) 1411 offs += 0x1000; 1412 else 1413 offs += 0x10000; 1414 } 1415 } 1416 1417 /* Check status of 'QE' bit */ 1418 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; 1419 stfsm_read_status(fsm, FLASH_CMD_RDSR2, &cr1); 1420 if (data_pads == 4) { 1421 if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { 1422 /* Set 'QE' */ 1423 cr1 |= STFSM_S25FL_CONFIG_QE; 1424 1425 stfsm_read_status(fsm, FLASH_CMD_RDSR, &sr1); 1426 sta_wr = ((uint16_t)cr1 << 8) | sr1; 1427 1428 stfsm_write_status(fsm, sta_wr, 2); 1429 1430 stfsm_wait_busy(fsm); 1431 } 1432 } else { 1433 if ((cr1 & STFSM_S25FL_CONFIG_QE)) { 1434 /* Clear 'QE' */ 1435 cr1 &= ~STFSM_S25FL_CONFIG_QE; 1436 1437 stfsm_read_status(fsm, FLASH_CMD_RDSR, &sr1); 1438 sta_wr = ((uint16_t)cr1 << 8) | sr1; 1439 1440 stfsm_write_status(fsm, sta_wr, 2); 1441 1442 stfsm_wait_busy(fsm); 1443 } 1444 1445 } 1446 1447 /* 1448 * S25FLxxx devices support Program and Error error flags. 1449 * Configure driver to check flags and clear if necessary. 1450 */ 1451 fsm->configuration |= CFG_S25FL_CHECK_ERROR_FLAGS; 1452 1453 return 0; 1454 } 1455 1456 static int stfsm_w25q_config(struct stfsm *fsm) 1457 { 1458 uint32_t data_pads; 1459 uint16_t sta_wr; 1460 uint8_t sta1, sta2; 1461 int ret; 1462 1463 ret = stfsm_prepare_rwe_seqs_default(fsm); 1464 if (ret) 1465 return ret; 1466 1467 /* If using QUAD mode, set QE STATUS bit */ 1468 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; 1469 if (data_pads == 4) { 1470 stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta1); 1471 stfsm_read_status(fsm, FLASH_CMD_RDSR2, &sta2); 1472 1473 sta_wr = ((uint16_t)sta2 << 8) | sta1; 1474 1475 sta_wr |= W25Q_STATUS_QE; 1476 1477 stfsm_write_status(fsm, sta_wr, 2); 1478 1479 stfsm_wait_busy(fsm); 1480 } 1481 1482 return 0; 1483 } 1484 1485 static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size, 1486 uint32_t offset) 1487 { 1488 struct stfsm_seq *seq = &fsm->stfsm_seq_read; 1489 uint32_t data_pads; 1490 uint32_t read_mask; 1491 uint32_t size_ub; 1492 uint32_t size_lb; 1493 uint32_t size_mop; 1494 uint32_t tmp[4]; 1495 uint32_t page_buf[FLASH_PAGESIZE_32]; 1496 uint8_t *p; 1497 1498 dev_dbg(fsm->dev, "reading %d bytes from 0x%08x\n", size, offset); 1499 1500 /* Enter 32-bit address mode, if required */ 1501 if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR) 1502 stfsm_enter_32bit_addr(fsm, 1); 1503 1504 /* Must read in multiples of 32 cycles (or 32*pads/8 Bytes) */ 1505 data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1; 1506 read_mask = (data_pads << 2) - 1; 1507 1508 /* Handle non-aligned buf */ 1509 p = ((uint32_t)buf & 0x3) ? (uint8_t *)page_buf : buf; 1510 1511 /* Handle non-aligned size */ 1512 size_ub = (size + read_mask) & ~read_mask; 1513 size_lb = size & ~read_mask; 1514 size_mop = size & read_mask; 1515 1516 seq->data_size = TRANSFER_SIZE(size_ub); 1517 seq->addr1 = (offset >> 16) & 0xffff; 1518 seq->addr2 = offset & 0xffff; 1519 1520 stfsm_load_seq(fsm, seq); 1521 1522 if (size_lb) 1523 stfsm_read_fifo(fsm, (uint32_t *)p, size_lb); 1524 1525 if (size_mop) { 1526 stfsm_read_fifo(fsm, tmp, read_mask + 1); 1527 memcpy(p + size_lb, &tmp, size_mop); 1528 } 1529 1530 /* Handle non-aligned buf */ 1531 if ((uint32_t)buf & 0x3) 1532 memcpy(buf, page_buf, size); 1533 1534 /* Wait for sequence to finish */ 1535 stfsm_wait_seq(fsm); 1536 1537 stfsm_clear_fifo(fsm); 1538 1539 /* Exit 32-bit address mode, if required */ 1540 if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR) 1541 stfsm_enter_32bit_addr(fsm, 0); 1542 1543 return 0; 1544 } 1545 1546 static int stfsm_write(struct stfsm *fsm, const uint8_t *buf, 1547 uint32_t size, uint32_t offset) 1548 { 1549 struct stfsm_seq *seq = &fsm->stfsm_seq_write; 1550 uint32_t data_pads; 1551 uint32_t write_mask; 1552 uint32_t size_ub; 1553 uint32_t size_lb; 1554 uint32_t size_mop; 1555 uint32_t tmp[4]; 1556 uint32_t page_buf[FLASH_PAGESIZE_32]; 1557 uint8_t *t = (uint8_t *)&tmp; 1558 const uint8_t *p; 1559 int ret; 1560 int i; 1561 1562 dev_dbg(fsm->dev, "writing %d bytes to 0x%08x\n", size, offset); 1563 1564 /* Enter 32-bit address mode, if required */ 1565 if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR) 1566 stfsm_enter_32bit_addr(fsm, 1); 1567 1568 /* Must write in multiples of 32 cycles (or 32*pads/8 bytes) */ 1569 data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1; 1570 write_mask = (data_pads << 2) - 1; 1571 1572 /* Handle non-aligned buf */ 1573 if ((uint32_t)buf & 0x3) { 1574 memcpy(page_buf, buf, size); 1575 p = (uint8_t *)page_buf; 1576 } else { 1577 p = buf; 1578 } 1579 1580 /* Handle non-aligned size */ 1581 size_ub = (size + write_mask) & ~write_mask; 1582 size_lb = size & ~write_mask; 1583 size_mop = size & write_mask; 1584 1585 seq->data_size = TRANSFER_SIZE(size_ub); 1586 seq->addr1 = (offset >> 16) & 0xffff; 1587 seq->addr2 = offset & 0xffff; 1588 1589 /* Need to set FIFO to write mode, before writing data to FIFO (see 1590 * GNBvb79594) 1591 */ 1592 writel(0x00040000, fsm->base + SPI_FAST_SEQ_CFG); 1593 1594 /* 1595 * Before writing data to the FIFO, apply a small delay to allow a 1596 * potential change of FIFO direction to complete. 1597 */ 1598 if (fsm->fifo_dir_delay == 0) 1599 readl(fsm->base + SPI_FAST_SEQ_CFG); 1600 else 1601 udelay(fsm->fifo_dir_delay); 1602 1603 1604 /* Write data to FIFO, before starting sequence (see GNBvd79593) */ 1605 if (size_lb) { 1606 stfsm_write_fifo(fsm, (uint32_t *)p, size_lb); 1607 p += size_lb; 1608 } 1609 1610 /* Handle non-aligned size */ 1611 if (size_mop) { 1612 memset(t, 0xff, write_mask + 1); /* fill with 0xff's */ 1613 for (i = 0; i < size_mop; i++) 1614 t[i] = *p++; 1615 1616 stfsm_write_fifo(fsm, tmp, write_mask + 1); 1617 } 1618 1619 /* Start sequence */ 1620 stfsm_load_seq(fsm, seq); 1621 1622 /* Wait for sequence to finish */ 1623 stfsm_wait_seq(fsm); 1624 1625 /* Wait for completion */ 1626 ret = stfsm_wait_busy(fsm); 1627 if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) 1628 stfsm_s25fl_clear_status_reg(fsm); 1629 1630 /* Exit 32-bit address mode, if required */ 1631 if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR) { 1632 stfsm_enter_32bit_addr(fsm, 0); 1633 if (fsm->configuration & CFG_WRITE_EX_32BIT_ADDR_DELAY) 1634 udelay(1); 1635 } 1636 1637 return 0; 1638 } 1639 1640 /* 1641 * Read an address range from the flash chip. The address range 1642 * may be any size provided it is within the physical boundaries. 1643 */ 1644 static int stfsm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, 1645 size_t *retlen, u_char *buf) 1646 { 1647 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent); 1648 uint32_t bytes; 1649 1650 dev_dbg(fsm->dev, "%s from 0x%08x, len %zd\n", 1651 __func__, (u32)from, len); 1652 1653 mutex_lock(&fsm->lock); 1654 1655 while (len > 0) { 1656 bytes = min_t(size_t, len, FLASH_PAGESIZE); 1657 1658 stfsm_read(fsm, buf, bytes, from); 1659 1660 buf += bytes; 1661 from += bytes; 1662 len -= bytes; 1663 1664 *retlen += bytes; 1665 } 1666 1667 mutex_unlock(&fsm->lock); 1668 1669 return 0; 1670 } 1671 1672 static int stfsm_erase_sector(struct stfsm *fsm, uint32_t offset) 1673 { 1674 struct stfsm_seq *seq = &stfsm_seq_erase_sector; 1675 int ret; 1676 1677 dev_dbg(fsm->dev, "erasing sector at 0x%08x\n", offset); 1678 1679 /* Enter 32-bit address mode, if required */ 1680 if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR) 1681 stfsm_enter_32bit_addr(fsm, 1); 1682 1683 seq->addr1 = (offset >> 16) & 0xffff; 1684 seq->addr2 = offset & 0xffff; 1685 1686 stfsm_load_seq(fsm, seq); 1687 1688 stfsm_wait_seq(fsm); 1689 1690 /* Wait for completion */ 1691 ret = stfsm_wait_busy(fsm); 1692 if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) 1693 stfsm_s25fl_clear_status_reg(fsm); 1694 1695 /* Exit 32-bit address mode, if required */ 1696 if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR) 1697 stfsm_enter_32bit_addr(fsm, 0); 1698 1699 return ret; 1700 } 1701 1702 static int stfsm_erase_chip(struct stfsm *fsm) 1703 { 1704 const struct stfsm_seq *seq = &stfsm_seq_erase_chip; 1705 1706 dev_dbg(fsm->dev, "erasing chip\n"); 1707 1708 stfsm_load_seq(fsm, seq); 1709 1710 stfsm_wait_seq(fsm); 1711 1712 return stfsm_wait_busy(fsm); 1713 } 1714 1715 /* 1716 * Write an address range to the flash chip. Data must be written in 1717 * FLASH_PAGESIZE chunks. The address range may be any size provided 1718 * it is within the physical boundaries. 1719 */ 1720 static int stfsm_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, 1721 size_t *retlen, const u_char *buf) 1722 { 1723 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent); 1724 1725 u32 page_offs; 1726 u32 bytes; 1727 uint8_t *b = (uint8_t *)buf; 1728 int ret = 0; 1729 1730 dev_dbg(fsm->dev, "%s to 0x%08x, len %zd\n", __func__, (u32)to, len); 1731 1732 /* Offset within page */ 1733 page_offs = to % FLASH_PAGESIZE; 1734 1735 mutex_lock(&fsm->lock); 1736 1737 while (len) { 1738 /* Write up to page boundary */ 1739 bytes = min(FLASH_PAGESIZE - page_offs, len); 1740 1741 ret = stfsm_write(fsm, b, bytes, to); 1742 if (ret) 1743 goto out1; 1744 1745 b += bytes; 1746 len -= bytes; 1747 to += bytes; 1748 1749 /* We are now page-aligned */ 1750 page_offs = 0; 1751 1752 *retlen += bytes; 1753 1754 } 1755 1756 out1: 1757 mutex_unlock(&fsm->lock); 1758 1759 return ret; 1760 } 1761 1762 /* 1763 * Erase an address range on the flash chip. The address range may extend 1764 * one or more erase sectors. Return an error is there is a problem erasing. 1765 */ 1766 static int stfsm_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) 1767 { 1768 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent); 1769 u32 addr, len; 1770 int ret; 1771 1772 dev_dbg(fsm->dev, "%s at 0x%llx, len %lld\n", __func__, 1773 (long long)instr->addr, (long long)instr->len); 1774 1775 addr = instr->addr; 1776 len = instr->len; 1777 1778 mutex_lock(&fsm->lock); 1779 1780 /* Whole-chip erase? */ 1781 if (len == mtd->size) { 1782 ret = stfsm_erase_chip(fsm); 1783 if (ret) 1784 goto out1; 1785 } else { 1786 while (len) { 1787 ret = stfsm_erase_sector(fsm, addr); 1788 if (ret) 1789 goto out1; 1790 1791 addr += mtd->erasesize; 1792 len -= mtd->erasesize; 1793 } 1794 } 1795 1796 mutex_unlock(&fsm->lock); 1797 1798 instr->state = MTD_ERASE_DONE; 1799 mtd_erase_callback(instr); 1800 1801 return 0; 1802 1803 out1: 1804 instr->state = MTD_ERASE_FAILED; 1805 mutex_unlock(&fsm->lock); 1806 1807 return ret; 1808 } 1809 1810 static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *jedec) 1811 { 1812 const struct stfsm_seq *seq = &stfsm_seq_read_jedec; 1813 uint32_t tmp[2]; 1814 1815 stfsm_load_seq(fsm, seq); 1816 1817 stfsm_read_fifo(fsm, tmp, 8); 1818 1819 memcpy(jedec, tmp, 5); 1820 1821 stfsm_wait_seq(fsm); 1822 } 1823 1824 static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm) 1825 { 1826 struct flash_info *info; 1827 u16 ext_jedec; 1828 u32 jedec; 1829 u8 id[5]; 1830 1831 stfsm_read_jedec(fsm, id); 1832 1833 jedec = id[0] << 16 | id[1] << 8 | id[2]; 1834 /* 1835 * JEDEC also defines an optional "extended device information" 1836 * string for after vendor-specific data, after the three bytes 1837 * we use here. Supporting some chips might require using it. 1838 */ 1839 ext_jedec = id[3] << 8 | id[4]; 1840 1841 dev_dbg(fsm->dev, "JEDEC = 0x%08x [%02x %02x %02x %02x %02x]\n", 1842 jedec, id[0], id[1], id[2], id[3], id[4]); 1843 1844 for (info = flash_types; info->name; info++) { 1845 if (info->jedec_id == jedec) { 1846 if (info->ext_id && info->ext_id != ext_jedec) 1847 continue; 1848 return info; 1849 } 1850 } 1851 dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec); 1852 1853 return NULL; 1854 } 1855 1856 static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode) 1857 { 1858 int ret, timeout = 10; 1859 1860 /* Wait for controller to accept mode change */ 1861 while (--timeout) { 1862 ret = readl(fsm->base + SPI_STA_MODE_CHANGE); 1863 if (ret & 0x1) 1864 break; 1865 udelay(1); 1866 } 1867 1868 if (!timeout) 1869 return -EBUSY; 1870 1871 writel(mode, fsm->base + SPI_MODESELECT); 1872 1873 return 0; 1874 } 1875 1876 static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq) 1877 { 1878 uint32_t emi_freq; 1879 uint32_t clk_div; 1880 1881 /* TODO: Make this dynamic */ 1882 emi_freq = STFSM_DEFAULT_EMI_FREQ; 1883 1884 /* 1885 * Calculate clk_div - values between 2 and 128 1886 * Multiple of 2, rounded up 1887 */ 1888 clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq); 1889 if (clk_div < 2) 1890 clk_div = 2; 1891 else if (clk_div > 128) 1892 clk_div = 128; 1893 1894 /* 1895 * Determine a suitable delay for the IP to complete a change of 1896 * direction of the FIFO. The required delay is related to the clock 1897 * divider used. The following heuristics are based on empirical tests, 1898 * using a 100MHz EMI clock. 1899 */ 1900 if (clk_div <= 4) 1901 fsm->fifo_dir_delay = 0; 1902 else if (clk_div <= 10) 1903 fsm->fifo_dir_delay = 1; 1904 else 1905 fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10); 1906 1907 dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n", 1908 emi_freq, spi_freq, clk_div); 1909 1910 writel(clk_div, fsm->base + SPI_CLOCKDIV); 1911 } 1912 1913 static int stfsm_init(struct stfsm *fsm) 1914 { 1915 int ret; 1916 1917 /* Perform a soft reset of the FSM controller */ 1918 writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG); 1919 udelay(1); 1920 writel(0, fsm->base + SPI_FAST_SEQ_CFG); 1921 1922 /* Set clock to 'safe' frequency initially */ 1923 stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ); 1924 1925 /* Switch to FSM */ 1926 ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM); 1927 if (ret) 1928 return ret; 1929 1930 /* Set timing parameters */ 1931 writel(SPI_CFG_DEVICE_ST | 1932 SPI_CFG_DEFAULT_MIN_CS_HIGH | 1933 SPI_CFG_DEFAULT_CS_SETUPHOLD | 1934 SPI_CFG_DEFAULT_DATA_HOLD, 1935 fsm->base + SPI_CONFIGDATA); 1936 writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG); 1937 1938 /* Clear FIFO, just in case */ 1939 stfsm_clear_fifo(fsm); 1940 1941 return 0; 1942 } 1943 1944 static void stfsm_fetch_platform_configs(struct platform_device *pdev) 1945 { 1946 struct stfsm *fsm = platform_get_drvdata(pdev); 1947 struct device_node *np = pdev->dev.of_node; 1948 struct regmap *regmap; 1949 uint32_t boot_device_reg; 1950 uint32_t boot_device_spi; 1951 uint32_t boot_device; /* Value we read from *boot_device_reg */ 1952 int ret; 1953 1954 /* Booting from SPI NOR Flash is the default */ 1955 fsm->booted_from_spi = true; 1956 1957 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1958 if (IS_ERR(regmap)) 1959 goto boot_device_fail; 1960 1961 fsm->reset_signal = of_property_read_bool(np, "st,reset-signal"); 1962 1963 fsm->reset_por = of_property_read_bool(np, "st,reset-por"); 1964 1965 /* Where in the syscon the boot device information lives */ 1966 ret = of_property_read_u32(np, "st,boot-device-reg", &boot_device_reg); 1967 if (ret) 1968 goto boot_device_fail; 1969 1970 /* Boot device value when booted from SPI NOR */ 1971 ret = of_property_read_u32(np, "st,boot-device-spi", &boot_device_spi); 1972 if (ret) 1973 goto boot_device_fail; 1974 1975 ret = regmap_read(regmap, boot_device_reg, &boot_device); 1976 if (ret) 1977 goto boot_device_fail; 1978 1979 if (boot_device != boot_device_spi) 1980 fsm->booted_from_spi = false; 1981 1982 return; 1983 1984 boot_device_fail: 1985 dev_warn(&pdev->dev, 1986 "failed to fetch boot device, assuming boot from SPI\n"); 1987 } 1988 1989 static int stfsm_probe(struct platform_device *pdev) 1990 { 1991 struct device_node *np = pdev->dev.of_node; 1992 struct mtd_part_parser_data ppdata; 1993 struct flash_info *info; 1994 struct resource *res; 1995 struct stfsm *fsm; 1996 int ret; 1997 1998 if (!np) { 1999 dev_err(&pdev->dev, "No DT found\n"); 2000 return -EINVAL; 2001 } 2002 ppdata.of_node = np; 2003 2004 fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL); 2005 if (!fsm) 2006 return -ENOMEM; 2007 2008 fsm->dev = &pdev->dev; 2009 2010 platform_set_drvdata(pdev, fsm); 2011 2012 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2013 if (!res) { 2014 dev_err(&pdev->dev, "Resource not found\n"); 2015 return -ENODEV; 2016 } 2017 2018 fsm->base = devm_ioremap_resource(&pdev->dev, res); 2019 if (IS_ERR(fsm->base)) { 2020 dev_err(&pdev->dev, 2021 "Failed to reserve memory region %pR\n", res); 2022 return PTR_ERR(fsm->base); 2023 } 2024 2025 mutex_init(&fsm->lock); 2026 2027 ret = stfsm_init(fsm); 2028 if (ret) { 2029 dev_err(&pdev->dev, "Failed to initialise FSM Controller\n"); 2030 return ret; 2031 } 2032 2033 stfsm_fetch_platform_configs(pdev); 2034 2035 /* Detect SPI FLASH device */ 2036 info = stfsm_jedec_probe(fsm); 2037 if (!info) 2038 return -ENODEV; 2039 fsm->info = info; 2040 2041 /* Use device size to determine address width */ 2042 if (info->sector_size * info->n_sectors > 0x1000000) 2043 info->flags |= FLASH_FLAG_32BIT_ADDR; 2044 2045 /* 2046 * Configure READ/WRITE/ERASE sequences according to platform and 2047 * device flags. 2048 */ 2049 if (info->config) { 2050 ret = info->config(fsm); 2051 if (ret) 2052 return ret; 2053 } else { 2054 ret = stfsm_prepare_rwe_seqs_default(fsm); 2055 if (ret) 2056 return ret; 2057 } 2058 2059 fsm->mtd.name = info->name; 2060 fsm->mtd.dev.parent = &pdev->dev; 2061 fsm->mtd.type = MTD_NORFLASH; 2062 fsm->mtd.writesize = 4; 2063 fsm->mtd.writebufsize = fsm->mtd.writesize; 2064 fsm->mtd.flags = MTD_CAP_NORFLASH; 2065 fsm->mtd.size = info->sector_size * info->n_sectors; 2066 fsm->mtd.erasesize = info->sector_size; 2067 2068 fsm->mtd._read = stfsm_mtd_read; 2069 fsm->mtd._write = stfsm_mtd_write; 2070 fsm->mtd._erase = stfsm_mtd_erase; 2071 2072 dev_info(&pdev->dev, 2073 "Found serial flash device: %s\n" 2074 " size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n", 2075 info->name, 2076 (long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20), 2077 fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10)); 2078 2079 return mtd_device_parse_register(&fsm->mtd, NULL, &ppdata, NULL, 0); 2080 } 2081 2082 static int stfsm_remove(struct platform_device *pdev) 2083 { 2084 struct stfsm *fsm = platform_get_drvdata(pdev); 2085 2086 return mtd_device_unregister(&fsm->mtd); 2087 } 2088 2089 static struct of_device_id stfsm_match[] = { 2090 { .compatible = "st,spi-fsm", }, 2091 {}, 2092 }; 2093 MODULE_DEVICE_TABLE(of, stfsm_match); 2094 2095 static struct platform_driver stfsm_driver = { 2096 .probe = stfsm_probe, 2097 .remove = stfsm_remove, 2098 .driver = { 2099 .name = "st-spi-fsm", 2100 .owner = THIS_MODULE, 2101 .of_match_table = stfsm_match, 2102 }, 2103 }; 2104 module_platform_driver(stfsm_driver); 2105 2106 MODULE_AUTHOR("Angus Clark <angus.clark@st.com>"); 2107 MODULE_DESCRIPTION("ST SPI FSM driver"); 2108 MODULE_LICENSE("GPL"); 2109