1 /* 2 Common Flash Interface probe code. 3 (C) 2000 Red Hat. GPL'd. 4 $Id: jedec_probe.c,v 1.66 2005/11/07 11:14:23 gleixner Exp $ 5 See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5) 6 for the standard this probe goes back to. 7 8 Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 9 */ 10 11 #include <linux/module.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/kernel.h> 15 #include <asm/io.h> 16 #include <asm/byteorder.h> 17 #include <linux/errno.h> 18 #include <linux/slab.h> 19 #include <linux/interrupt.h> 20 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/map.h> 23 #include <linux/mtd/cfi.h> 24 #include <linux/mtd/gen_probe.h> 25 26 /* Manufacturers */ 27 #define MANUFACTURER_AMD 0x0001 28 #define MANUFACTURER_ATMEL 0x001f 29 #define MANUFACTURER_FUJITSU 0x0004 30 #define MANUFACTURER_HYUNDAI 0x00AD 31 #define MANUFACTURER_INTEL 0x0089 32 #define MANUFACTURER_MACRONIX 0x00C2 33 #define MANUFACTURER_NEC 0x0010 34 #define MANUFACTURER_PMC 0x009D 35 #define MANUFACTURER_SHARP 0x00b0 36 #define MANUFACTURER_SST 0x00BF 37 #define MANUFACTURER_ST 0x0020 38 #define MANUFACTURER_TOSHIBA 0x0098 39 #define MANUFACTURER_WINBOND 0x00da 40 41 42 /* AMD */ 43 #define AM29DL800BB 0x22C8 44 #define AM29DL800BT 0x224A 45 46 #define AM29F800BB 0x2258 47 #define AM29F800BT 0x22D6 48 #define AM29LV400BB 0x22BA 49 #define AM29LV400BT 0x22B9 50 #define AM29LV800BB 0x225B 51 #define AM29LV800BT 0x22DA 52 #define AM29LV160DT 0x22C4 53 #define AM29LV160DB 0x2249 54 #define AM29F017D 0x003D 55 #define AM29F016D 0x00AD 56 #define AM29F080 0x00D5 57 #define AM29F040 0x00A4 58 #define AM29LV040B 0x004F 59 #define AM29F032B 0x0041 60 #define AM29F002T 0x00B0 61 62 /* Atmel */ 63 #define AT49BV512 0x0003 64 #define AT29LV512 0x003d 65 #define AT49BV16X 0x00C0 66 #define AT49BV16XT 0x00C2 67 #define AT49BV32X 0x00C8 68 #define AT49BV32XT 0x00C9 69 70 /* Fujitsu */ 71 #define MBM29F040C 0x00A4 72 #define MBM29F800BA 0x2258 73 #define MBM29LV650UE 0x22D7 74 #define MBM29LV320TE 0x22F6 75 #define MBM29LV320BE 0x22F9 76 #define MBM29LV160TE 0x22C4 77 #define MBM29LV160BE 0x2249 78 #define MBM29LV800BA 0x225B 79 #define MBM29LV800TA 0x22DA 80 #define MBM29LV400TC 0x22B9 81 #define MBM29LV400BC 0x22BA 82 83 /* Hyundai */ 84 #define HY29F002T 0x00B0 85 86 /* Intel */ 87 #define I28F004B3T 0x00d4 88 #define I28F004B3B 0x00d5 89 #define I28F400B3T 0x8894 90 #define I28F400B3B 0x8895 91 #define I28F008S5 0x00a6 92 #define I28F016S5 0x00a0 93 #define I28F008SA 0x00a2 94 #define I28F008B3T 0x00d2 95 #define I28F008B3B 0x00d3 96 #define I28F800B3T 0x8892 97 #define I28F800B3B 0x8893 98 #define I28F016S3 0x00aa 99 #define I28F016B3T 0x00d0 100 #define I28F016B3B 0x00d1 101 #define I28F160B3T 0x8890 102 #define I28F160B3B 0x8891 103 #define I28F320B3T 0x8896 104 #define I28F320B3B 0x8897 105 #define I28F640B3T 0x8898 106 #define I28F640B3B 0x8899 107 #define I82802AB 0x00ad 108 #define I82802AC 0x00ac 109 110 /* Macronix */ 111 #define MX29LV040C 0x004F 112 #define MX29LV160T 0x22C4 113 #define MX29LV160B 0x2249 114 #define MX29F040 0x00A4 115 #define MX29F016 0x00AD 116 #define MX29F002T 0x00B0 117 #define MX29F004T 0x0045 118 #define MX29F004B 0x0046 119 120 /* NEC */ 121 #define UPD29F064115 0x221C 122 123 /* PMC */ 124 #define PM49FL002 0x006D 125 #define PM49FL004 0x006E 126 #define PM49FL008 0x006A 127 128 /* Sharp */ 129 #define LH28F640BF 0x00b0 130 131 /* ST - www.st.com */ 132 #define M29F800AB 0x0058 133 #define M29W800DT 0x00D7 134 #define M29W800DB 0x005B 135 #define M29W160DT 0x22C4 136 #define M29W160DB 0x2249 137 #define M29W040B 0x00E3 138 #define M50FW040 0x002C 139 #define M50FW080 0x002D 140 #define M50FW016 0x002E 141 #define M50LPW080 0x002F 142 143 /* SST */ 144 #define SST29EE020 0x0010 145 #define SST29LE020 0x0012 146 #define SST29EE512 0x005d 147 #define SST29LE512 0x003d 148 #define SST39LF800 0x2781 149 #define SST39LF160 0x2782 150 #define SST39VF1601 0x234b 151 #define SST39LF512 0x00D4 152 #define SST39LF010 0x00D5 153 #define SST39LF020 0x00D6 154 #define SST39LF040 0x00D7 155 #define SST39SF010A 0x00B5 156 #define SST39SF020A 0x00B6 157 #define SST49LF004B 0x0060 158 #define SST49LF040B 0x0050 159 #define SST49LF008A 0x005a 160 #define SST49LF030A 0x001C 161 #define SST49LF040A 0x0051 162 #define SST49LF080A 0x005B 163 164 /* Toshiba */ 165 #define TC58FVT160 0x00C2 166 #define TC58FVB160 0x0043 167 #define TC58FVT321 0x009A 168 #define TC58FVB321 0x009C 169 #define TC58FVT641 0x0093 170 #define TC58FVB641 0x0095 171 172 /* Winbond */ 173 #define W49V002A 0x00b0 174 175 176 /* 177 * Unlock address sets for AMD command sets. 178 * Intel command sets use the MTD_UADDR_UNNECESSARY. 179 * Each identifier, except MTD_UADDR_UNNECESSARY, and 180 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. 181 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure 182 * initialization need not require initializing all of the 183 * unlock addresses for all bit widths. 184 */ 185 enum uaddr { 186 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ 187 MTD_UADDR_0x0555_0x02AA, 188 MTD_UADDR_0x0555_0x0AAA, 189 MTD_UADDR_0x5555_0x2AAA, 190 MTD_UADDR_0x0AAA_0x0555, 191 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ 192 MTD_UADDR_UNNECESSARY, /* Does not require any address */ 193 }; 194 195 196 struct unlock_addr { 197 uint32_t addr1; 198 uint32_t addr2; 199 }; 200 201 202 /* 203 * I don't like the fact that the first entry in unlock_addrs[] 204 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, 205 * should not be used. The problem is that structures with 206 * initializers have extra fields initialized to 0. It is _very_ 207 * desireable to have the unlock address entries for unsupported 208 * data widths automatically initialized - that means that 209 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here 210 * must go unused. 211 */ 212 static const struct unlock_addr unlock_addrs[] = { 213 [MTD_UADDR_NOT_SUPPORTED] = { 214 .addr1 = 0xffff, 215 .addr2 = 0xffff 216 }, 217 218 [MTD_UADDR_0x0555_0x02AA] = { 219 .addr1 = 0x0555, 220 .addr2 = 0x02aa 221 }, 222 223 [MTD_UADDR_0x0555_0x0AAA] = { 224 .addr1 = 0x0555, 225 .addr2 = 0x0aaa 226 }, 227 228 [MTD_UADDR_0x5555_0x2AAA] = { 229 .addr1 = 0x5555, 230 .addr2 = 0x2aaa 231 }, 232 233 [MTD_UADDR_0x0AAA_0x0555] = { 234 .addr1 = 0x0AAA, 235 .addr2 = 0x0555 236 }, 237 238 [MTD_UADDR_DONT_CARE] = { 239 .addr1 = 0x0000, /* Doesn't matter which address */ 240 .addr2 = 0x0000 /* is used - must be last entry */ 241 }, 242 243 [MTD_UADDR_UNNECESSARY] = { 244 .addr1 = 0x0000, 245 .addr2 = 0x0000 246 } 247 }; 248 249 struct amd_flash_info { 250 const char *name; 251 const uint16_t mfr_id; 252 const uint16_t dev_id; 253 const uint8_t dev_size; 254 const uint8_t nr_regions; 255 const uint16_t cmd_set; 256 const uint32_t regions[6]; 257 const uint8_t devtypes; /* Bitmask for x8, x16 etc. */ 258 const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */ 259 }; 260 261 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) 262 263 #define SIZE_64KiB 16 264 #define SIZE_128KiB 17 265 #define SIZE_256KiB 18 266 #define SIZE_512KiB 19 267 #define SIZE_1MiB 20 268 #define SIZE_2MiB 21 269 #define SIZE_4MiB 22 270 #define SIZE_8MiB 23 271 272 273 /* 274 * Please keep this list ordered by manufacturer! 275 * Fortunately, the list isn't searched often and so a 276 * slow, linear search isn't so bad. 277 */ 278 static const struct amd_flash_info jedec_table[] = { 279 { 280 .mfr_id = MANUFACTURER_AMD, 281 .dev_id = AM29F032B, 282 .name = "AMD AM29F032B", 283 .uaddr = MTD_UADDR_0x0555_0x02AA, 284 .devtypes = CFI_DEVICETYPE_X8, 285 .dev_size = SIZE_4MiB, 286 .cmd_set = P_ID_AMD_STD, 287 .nr_regions = 1, 288 .regions = { 289 ERASEINFO(0x10000,64) 290 } 291 }, { 292 .mfr_id = MANUFACTURER_AMD, 293 .dev_id = AM29LV160DT, 294 .name = "AMD AM29LV160DT", 295 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 296 .uaddr = MTD_UADDR_0x0AAA_0x0555, 297 .dev_size = SIZE_2MiB, 298 .cmd_set = P_ID_AMD_STD, 299 .nr_regions = 4, 300 .regions = { 301 ERASEINFO(0x10000,31), 302 ERASEINFO(0x08000,1), 303 ERASEINFO(0x02000,2), 304 ERASEINFO(0x04000,1) 305 } 306 }, { 307 .mfr_id = MANUFACTURER_AMD, 308 .dev_id = AM29LV160DB, 309 .name = "AMD AM29LV160DB", 310 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 311 .uaddr = MTD_UADDR_0x0AAA_0x0555, 312 .dev_size = SIZE_2MiB, 313 .cmd_set = P_ID_AMD_STD, 314 .nr_regions = 4, 315 .regions = { 316 ERASEINFO(0x04000,1), 317 ERASEINFO(0x02000,2), 318 ERASEINFO(0x08000,1), 319 ERASEINFO(0x10000,31) 320 } 321 }, { 322 .mfr_id = MANUFACTURER_AMD, 323 .dev_id = AM29LV400BB, 324 .name = "AMD AM29LV400BB", 325 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 326 .uaddr = MTD_UADDR_0x0AAA_0x0555, 327 .dev_size = SIZE_512KiB, 328 .cmd_set = P_ID_AMD_STD, 329 .nr_regions = 4, 330 .regions = { 331 ERASEINFO(0x04000,1), 332 ERASEINFO(0x02000,2), 333 ERASEINFO(0x08000,1), 334 ERASEINFO(0x10000,7) 335 } 336 }, { 337 .mfr_id = MANUFACTURER_AMD, 338 .dev_id = AM29LV400BT, 339 .name = "AMD AM29LV400BT", 340 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 341 .uaddr = MTD_UADDR_0x0AAA_0x0555, 342 .dev_size = SIZE_512KiB, 343 .cmd_set = P_ID_AMD_STD, 344 .nr_regions = 4, 345 .regions = { 346 ERASEINFO(0x10000,7), 347 ERASEINFO(0x08000,1), 348 ERASEINFO(0x02000,2), 349 ERASEINFO(0x04000,1) 350 } 351 }, { 352 .mfr_id = MANUFACTURER_AMD, 353 .dev_id = AM29LV800BB, 354 .name = "AMD AM29LV800BB", 355 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 356 .uaddr = MTD_UADDR_0x0AAA_0x0555, 357 .dev_size = SIZE_1MiB, 358 .cmd_set = P_ID_AMD_STD, 359 .nr_regions = 4, 360 .regions = { 361 ERASEINFO(0x04000,1), 362 ERASEINFO(0x02000,2), 363 ERASEINFO(0x08000,1), 364 ERASEINFO(0x10000,15), 365 } 366 }, { 367 /* add DL */ 368 .mfr_id = MANUFACTURER_AMD, 369 .dev_id = AM29DL800BB, 370 .name = "AMD AM29DL800BB", 371 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 372 .uaddr = MTD_UADDR_0x0AAA_0x0555, 373 .dev_size = SIZE_1MiB, 374 .cmd_set = P_ID_AMD_STD, 375 .nr_regions = 6, 376 .regions = { 377 ERASEINFO(0x04000,1), 378 ERASEINFO(0x08000,1), 379 ERASEINFO(0x02000,4), 380 ERASEINFO(0x08000,1), 381 ERASEINFO(0x04000,1), 382 ERASEINFO(0x10000,14) 383 } 384 }, { 385 .mfr_id = MANUFACTURER_AMD, 386 .dev_id = AM29DL800BT, 387 .name = "AMD AM29DL800BT", 388 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 389 .uaddr = MTD_UADDR_0x0AAA_0x0555, 390 .dev_size = SIZE_1MiB, 391 .cmd_set = P_ID_AMD_STD, 392 .nr_regions = 6, 393 .regions = { 394 ERASEINFO(0x10000,14), 395 ERASEINFO(0x04000,1), 396 ERASEINFO(0x08000,1), 397 ERASEINFO(0x02000,4), 398 ERASEINFO(0x08000,1), 399 ERASEINFO(0x04000,1) 400 } 401 }, { 402 .mfr_id = MANUFACTURER_AMD, 403 .dev_id = AM29F800BB, 404 .name = "AMD AM29F800BB", 405 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 406 .uaddr = MTD_UADDR_0x0AAA_0x0555, 407 .dev_size = SIZE_1MiB, 408 .cmd_set = P_ID_AMD_STD, 409 .nr_regions = 4, 410 .regions = { 411 ERASEINFO(0x04000,1), 412 ERASEINFO(0x02000,2), 413 ERASEINFO(0x08000,1), 414 ERASEINFO(0x10000,15), 415 } 416 }, { 417 .mfr_id = MANUFACTURER_AMD, 418 .dev_id = AM29LV800BT, 419 .name = "AMD AM29LV800BT", 420 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 421 .uaddr = MTD_UADDR_0x0AAA_0x0555, 422 .dev_size = SIZE_1MiB, 423 .cmd_set = P_ID_AMD_STD, 424 .nr_regions = 4, 425 .regions = { 426 ERASEINFO(0x10000,15), 427 ERASEINFO(0x08000,1), 428 ERASEINFO(0x02000,2), 429 ERASEINFO(0x04000,1) 430 } 431 }, { 432 .mfr_id = MANUFACTURER_AMD, 433 .dev_id = AM29F800BT, 434 .name = "AMD AM29F800BT", 435 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 436 .uaddr = MTD_UADDR_0x0AAA_0x0555, 437 .dev_size = SIZE_1MiB, 438 .cmd_set = P_ID_AMD_STD, 439 .nr_regions = 4, 440 .regions = { 441 ERASEINFO(0x10000,15), 442 ERASEINFO(0x08000,1), 443 ERASEINFO(0x02000,2), 444 ERASEINFO(0x04000,1) 445 } 446 }, { 447 .mfr_id = MANUFACTURER_AMD, 448 .dev_id = AM29F017D, 449 .name = "AMD AM29F017D", 450 .devtypes = CFI_DEVICETYPE_X8, 451 .uaddr = MTD_UADDR_DONT_CARE, 452 .dev_size = SIZE_2MiB, 453 .cmd_set = P_ID_AMD_STD, 454 .nr_regions = 1, 455 .regions = { 456 ERASEINFO(0x10000,32), 457 } 458 }, { 459 .mfr_id = MANUFACTURER_AMD, 460 .dev_id = AM29F016D, 461 .name = "AMD AM29F016D", 462 .devtypes = CFI_DEVICETYPE_X8, 463 .uaddr = MTD_UADDR_0x0555_0x02AA, 464 .dev_size = SIZE_2MiB, 465 .cmd_set = P_ID_AMD_STD, 466 .nr_regions = 1, 467 .regions = { 468 ERASEINFO(0x10000,32), 469 } 470 }, { 471 .mfr_id = MANUFACTURER_AMD, 472 .dev_id = AM29F080, 473 .name = "AMD AM29F080", 474 .devtypes = CFI_DEVICETYPE_X8, 475 .uaddr = MTD_UADDR_0x0555_0x02AA, 476 .dev_size = SIZE_1MiB, 477 .cmd_set = P_ID_AMD_STD, 478 .nr_regions = 1, 479 .regions = { 480 ERASEINFO(0x10000,16), 481 } 482 }, { 483 .mfr_id = MANUFACTURER_AMD, 484 .dev_id = AM29F040, 485 .name = "AMD AM29F040", 486 .devtypes = CFI_DEVICETYPE_X8, 487 .uaddr = MTD_UADDR_0x0555_0x02AA, 488 .dev_size = SIZE_512KiB, 489 .cmd_set = P_ID_AMD_STD, 490 .nr_regions = 1, 491 .regions = { 492 ERASEINFO(0x10000,8), 493 } 494 }, { 495 .mfr_id = MANUFACTURER_AMD, 496 .dev_id = AM29LV040B, 497 .name = "AMD AM29LV040B", 498 .devtypes = CFI_DEVICETYPE_X8, 499 .uaddr = MTD_UADDR_0x0555_0x02AA, 500 .dev_size = SIZE_512KiB, 501 .cmd_set = P_ID_AMD_STD, 502 .nr_regions = 1, 503 .regions = { 504 ERASEINFO(0x10000,8), 505 } 506 }, { 507 .mfr_id = MANUFACTURER_AMD, 508 .dev_id = AM29F002T, 509 .name = "AMD AM29F002T", 510 .devtypes = CFI_DEVICETYPE_X8, 511 .uaddr = MTD_UADDR_0x0555_0x02AA, 512 .dev_size = SIZE_256KiB, 513 .cmd_set = P_ID_AMD_STD, 514 .nr_regions = 4, 515 .regions = { 516 ERASEINFO(0x10000,3), 517 ERASEINFO(0x08000,1), 518 ERASEINFO(0x02000,2), 519 ERASEINFO(0x04000,1), 520 } 521 }, { 522 .mfr_id = MANUFACTURER_ATMEL, 523 .dev_id = AT49BV512, 524 .name = "Atmel AT49BV512", 525 .devtypes = CFI_DEVICETYPE_X8, 526 .uaddr = MTD_UADDR_0x5555_0x2AAA, 527 .dev_size = SIZE_64KiB, 528 .cmd_set = P_ID_AMD_STD, 529 .nr_regions = 1, 530 .regions = { 531 ERASEINFO(0x10000,1) 532 } 533 }, { 534 .mfr_id = MANUFACTURER_ATMEL, 535 .dev_id = AT29LV512, 536 .name = "Atmel AT29LV512", 537 .devtypes = CFI_DEVICETYPE_X8, 538 .uaddr = MTD_UADDR_0x5555_0x2AAA, 539 .dev_size = SIZE_64KiB, 540 .cmd_set = P_ID_AMD_STD, 541 .nr_regions = 1, 542 .regions = { 543 ERASEINFO(0x80,256), 544 ERASEINFO(0x80,256) 545 } 546 }, { 547 .mfr_id = MANUFACTURER_ATMEL, 548 .dev_id = AT49BV16X, 549 .name = "Atmel AT49BV16X", 550 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 551 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 552 .dev_size = SIZE_2MiB, 553 .cmd_set = P_ID_AMD_STD, 554 .nr_regions = 2, 555 .regions = { 556 ERASEINFO(0x02000,8), 557 ERASEINFO(0x10000,31) 558 } 559 }, { 560 .mfr_id = MANUFACTURER_ATMEL, 561 .dev_id = AT49BV16XT, 562 .name = "Atmel AT49BV16XT", 563 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 564 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 565 .dev_size = SIZE_2MiB, 566 .cmd_set = P_ID_AMD_STD, 567 .nr_regions = 2, 568 .regions = { 569 ERASEINFO(0x10000,31), 570 ERASEINFO(0x02000,8) 571 } 572 }, { 573 .mfr_id = MANUFACTURER_ATMEL, 574 .dev_id = AT49BV32X, 575 .name = "Atmel AT49BV32X", 576 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 577 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 578 .dev_size = SIZE_4MiB, 579 .cmd_set = P_ID_AMD_STD, 580 .nr_regions = 2, 581 .regions = { 582 ERASEINFO(0x02000,8), 583 ERASEINFO(0x10000,63) 584 } 585 }, { 586 .mfr_id = MANUFACTURER_ATMEL, 587 .dev_id = AT49BV32XT, 588 .name = "Atmel AT49BV32XT", 589 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 590 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 591 .dev_size = SIZE_4MiB, 592 .cmd_set = P_ID_AMD_STD, 593 .nr_regions = 2, 594 .regions = { 595 ERASEINFO(0x10000,63), 596 ERASEINFO(0x02000,8) 597 } 598 }, { 599 .mfr_id = MANUFACTURER_FUJITSU, 600 .dev_id = MBM29F040C, 601 .name = "Fujitsu MBM29F040C", 602 .devtypes = CFI_DEVICETYPE_X8, 603 .uaddr = MTD_UADDR_0x0AAA_0x0555, 604 .dev_size = SIZE_512KiB, 605 .cmd_set = P_ID_AMD_STD, 606 .nr_regions = 1, 607 .regions = { 608 ERASEINFO(0x10000,8) 609 } 610 }, { 611 .mfr_id = MANUFACTURER_FUJITSU, 612 .dev_id = MBM29F800BA, 613 .name = "Fujitsu MBM29F800BA", 614 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 615 .uaddr = MTD_UADDR_0x0AAA_0x0555, 616 .dev_size = SIZE_1MiB, 617 .cmd_set = P_ID_AMD_STD, 618 .nr_regions = 4, 619 .regions = { 620 ERASEINFO(0x04000,1), 621 ERASEINFO(0x02000,2), 622 ERASEINFO(0x08000,1), 623 ERASEINFO(0x10000,15), 624 } 625 }, { 626 .mfr_id = MANUFACTURER_FUJITSU, 627 .dev_id = MBM29LV650UE, 628 .name = "Fujitsu MBM29LV650UE", 629 .devtypes = CFI_DEVICETYPE_X8, 630 .uaddr = MTD_UADDR_DONT_CARE, 631 .dev_size = SIZE_8MiB, 632 .cmd_set = P_ID_AMD_STD, 633 .nr_regions = 1, 634 .regions = { 635 ERASEINFO(0x10000,128) 636 } 637 }, { 638 .mfr_id = MANUFACTURER_FUJITSU, 639 .dev_id = MBM29LV320TE, 640 .name = "Fujitsu MBM29LV320TE", 641 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 642 .uaddr = MTD_UADDR_0x0AAA_0x0555, 643 .dev_size = SIZE_4MiB, 644 .cmd_set = P_ID_AMD_STD, 645 .nr_regions = 2, 646 .regions = { 647 ERASEINFO(0x10000,63), 648 ERASEINFO(0x02000,8) 649 } 650 }, { 651 .mfr_id = MANUFACTURER_FUJITSU, 652 .dev_id = MBM29LV320BE, 653 .name = "Fujitsu MBM29LV320BE", 654 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 655 .uaddr = MTD_UADDR_0x0AAA_0x0555, 656 .dev_size = SIZE_4MiB, 657 .cmd_set = P_ID_AMD_STD, 658 .nr_regions = 2, 659 .regions = { 660 ERASEINFO(0x02000,8), 661 ERASEINFO(0x10000,63) 662 } 663 }, { 664 .mfr_id = MANUFACTURER_FUJITSU, 665 .dev_id = MBM29LV160TE, 666 .name = "Fujitsu MBM29LV160TE", 667 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 668 .uaddr = MTD_UADDR_0x0AAA_0x0555, 669 .dev_size = SIZE_2MiB, 670 .cmd_set = P_ID_AMD_STD, 671 .nr_regions = 4, 672 .regions = { 673 ERASEINFO(0x10000,31), 674 ERASEINFO(0x08000,1), 675 ERASEINFO(0x02000,2), 676 ERASEINFO(0x04000,1) 677 } 678 }, { 679 .mfr_id = MANUFACTURER_FUJITSU, 680 .dev_id = MBM29LV160BE, 681 .name = "Fujitsu MBM29LV160BE", 682 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 683 .uaddr = MTD_UADDR_0x0AAA_0x0555, 684 .dev_size = SIZE_2MiB, 685 .cmd_set = P_ID_AMD_STD, 686 .nr_regions = 4, 687 .regions = { 688 ERASEINFO(0x04000,1), 689 ERASEINFO(0x02000,2), 690 ERASEINFO(0x08000,1), 691 ERASEINFO(0x10000,31) 692 } 693 }, { 694 .mfr_id = MANUFACTURER_FUJITSU, 695 .dev_id = MBM29LV800BA, 696 .name = "Fujitsu MBM29LV800BA", 697 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 698 .uaddr = MTD_UADDR_0x0AAA_0x0555, 699 .dev_size = SIZE_1MiB, 700 .cmd_set = P_ID_AMD_STD, 701 .nr_regions = 4, 702 .regions = { 703 ERASEINFO(0x04000,1), 704 ERASEINFO(0x02000,2), 705 ERASEINFO(0x08000,1), 706 ERASEINFO(0x10000,15) 707 } 708 }, { 709 .mfr_id = MANUFACTURER_FUJITSU, 710 .dev_id = MBM29LV800TA, 711 .name = "Fujitsu MBM29LV800TA", 712 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 713 .uaddr = MTD_UADDR_0x0AAA_0x0555, 714 .dev_size = SIZE_1MiB, 715 .cmd_set = P_ID_AMD_STD, 716 .nr_regions = 4, 717 .regions = { 718 ERASEINFO(0x10000,15), 719 ERASEINFO(0x08000,1), 720 ERASEINFO(0x02000,2), 721 ERASEINFO(0x04000,1) 722 } 723 }, { 724 .mfr_id = MANUFACTURER_FUJITSU, 725 .dev_id = MBM29LV400BC, 726 .name = "Fujitsu MBM29LV400BC", 727 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 728 .uaddr = MTD_UADDR_0x0AAA_0x0555, 729 .dev_size = SIZE_512KiB, 730 .cmd_set = P_ID_AMD_STD, 731 .nr_regions = 4, 732 .regions = { 733 ERASEINFO(0x04000,1), 734 ERASEINFO(0x02000,2), 735 ERASEINFO(0x08000,1), 736 ERASEINFO(0x10000,7) 737 } 738 }, { 739 .mfr_id = MANUFACTURER_FUJITSU, 740 .dev_id = MBM29LV400TC, 741 .name = "Fujitsu MBM29LV400TC", 742 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 743 .uaddr = MTD_UADDR_0x0AAA_0x0555, 744 .dev_size = SIZE_512KiB, 745 .cmd_set = P_ID_AMD_STD, 746 .nr_regions = 4, 747 .regions = { 748 ERASEINFO(0x10000,7), 749 ERASEINFO(0x08000,1), 750 ERASEINFO(0x02000,2), 751 ERASEINFO(0x04000,1) 752 } 753 }, { 754 .mfr_id = MANUFACTURER_HYUNDAI, 755 .dev_id = HY29F002T, 756 .name = "Hyundai HY29F002T", 757 .devtypes = CFI_DEVICETYPE_X8, 758 .uaddr = MTD_UADDR_0x0555_0x02AA, 759 .dev_size = SIZE_256KiB, 760 .cmd_set = P_ID_AMD_STD, 761 .nr_regions = 4, 762 .regions = { 763 ERASEINFO(0x10000,3), 764 ERASEINFO(0x08000,1), 765 ERASEINFO(0x02000,2), 766 ERASEINFO(0x04000,1), 767 } 768 }, { 769 .mfr_id = MANUFACTURER_INTEL, 770 .dev_id = I28F004B3B, 771 .name = "Intel 28F004B3B", 772 .devtypes = CFI_DEVICETYPE_X8, 773 .uaddr = MTD_UADDR_UNNECESSARY, 774 .dev_size = SIZE_512KiB, 775 .cmd_set = P_ID_INTEL_STD, 776 .nr_regions = 2, 777 .regions = { 778 ERASEINFO(0x02000, 8), 779 ERASEINFO(0x10000, 7), 780 } 781 }, { 782 .mfr_id = MANUFACTURER_INTEL, 783 .dev_id = I28F004B3T, 784 .name = "Intel 28F004B3T", 785 .devtypes = CFI_DEVICETYPE_X8, 786 .uaddr = MTD_UADDR_UNNECESSARY, 787 .dev_size = SIZE_512KiB, 788 .cmd_set = P_ID_INTEL_STD, 789 .nr_regions = 2, 790 .regions = { 791 ERASEINFO(0x10000, 7), 792 ERASEINFO(0x02000, 8), 793 } 794 }, { 795 .mfr_id = MANUFACTURER_INTEL, 796 .dev_id = I28F400B3B, 797 .name = "Intel 28F400B3B", 798 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 799 .uaddr = MTD_UADDR_UNNECESSARY, 800 .dev_size = SIZE_512KiB, 801 .cmd_set = P_ID_INTEL_STD, 802 .nr_regions = 2, 803 .regions = { 804 ERASEINFO(0x02000, 8), 805 ERASEINFO(0x10000, 7), 806 } 807 }, { 808 .mfr_id = MANUFACTURER_INTEL, 809 .dev_id = I28F400B3T, 810 .name = "Intel 28F400B3T", 811 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 812 .uaddr = MTD_UADDR_UNNECESSARY, 813 .dev_size = SIZE_512KiB, 814 .cmd_set = P_ID_INTEL_STD, 815 .nr_regions = 2, 816 .regions = { 817 ERASEINFO(0x10000, 7), 818 ERASEINFO(0x02000, 8), 819 } 820 }, { 821 .mfr_id = MANUFACTURER_INTEL, 822 .dev_id = I28F008B3B, 823 .name = "Intel 28F008B3B", 824 .devtypes = CFI_DEVICETYPE_X8, 825 .uaddr = MTD_UADDR_UNNECESSARY, 826 .dev_size = SIZE_1MiB, 827 .cmd_set = P_ID_INTEL_STD, 828 .nr_regions = 2, 829 .regions = { 830 ERASEINFO(0x02000, 8), 831 ERASEINFO(0x10000, 15), 832 } 833 }, { 834 .mfr_id = MANUFACTURER_INTEL, 835 .dev_id = I28F008B3T, 836 .name = "Intel 28F008B3T", 837 .devtypes = CFI_DEVICETYPE_X8, 838 .uaddr = MTD_UADDR_UNNECESSARY, 839 .dev_size = SIZE_1MiB, 840 .cmd_set = P_ID_INTEL_STD, 841 .nr_regions = 2, 842 .regions = { 843 ERASEINFO(0x10000, 15), 844 ERASEINFO(0x02000, 8), 845 } 846 }, { 847 .mfr_id = MANUFACTURER_INTEL, 848 .dev_id = I28F008S5, 849 .name = "Intel 28F008S5", 850 .devtypes = CFI_DEVICETYPE_X8, 851 .uaddr = MTD_UADDR_UNNECESSARY, 852 .dev_size = SIZE_1MiB, 853 .cmd_set = P_ID_INTEL_EXT, 854 .nr_regions = 1, 855 .regions = { 856 ERASEINFO(0x10000,16), 857 } 858 }, { 859 .mfr_id = MANUFACTURER_INTEL, 860 .dev_id = I28F016S5, 861 .name = "Intel 28F016S5", 862 .devtypes = CFI_DEVICETYPE_X8, 863 .uaddr = MTD_UADDR_UNNECESSARY, 864 .dev_size = SIZE_2MiB, 865 .cmd_set = P_ID_INTEL_EXT, 866 .nr_regions = 1, 867 .regions = { 868 ERASEINFO(0x10000,32), 869 } 870 }, { 871 .mfr_id = MANUFACTURER_INTEL, 872 .dev_id = I28F008SA, 873 .name = "Intel 28F008SA", 874 .devtypes = CFI_DEVICETYPE_X8, 875 .uaddr = MTD_UADDR_UNNECESSARY, 876 .dev_size = SIZE_1MiB, 877 .cmd_set = P_ID_INTEL_STD, 878 .nr_regions = 1, 879 .regions = { 880 ERASEINFO(0x10000, 16), 881 } 882 }, { 883 .mfr_id = MANUFACTURER_INTEL, 884 .dev_id = I28F800B3B, 885 .name = "Intel 28F800B3B", 886 .devtypes = CFI_DEVICETYPE_X16, 887 .uaddr = MTD_UADDR_UNNECESSARY, 888 .dev_size = SIZE_1MiB, 889 .cmd_set = P_ID_INTEL_STD, 890 .nr_regions = 2, 891 .regions = { 892 ERASEINFO(0x02000, 8), 893 ERASEINFO(0x10000, 15), 894 } 895 }, { 896 .mfr_id = MANUFACTURER_INTEL, 897 .dev_id = I28F800B3T, 898 .name = "Intel 28F800B3T", 899 .devtypes = CFI_DEVICETYPE_X16, 900 .uaddr = MTD_UADDR_UNNECESSARY, 901 .dev_size = SIZE_1MiB, 902 .cmd_set = P_ID_INTEL_STD, 903 .nr_regions = 2, 904 .regions = { 905 ERASEINFO(0x10000, 15), 906 ERASEINFO(0x02000, 8), 907 } 908 }, { 909 .mfr_id = MANUFACTURER_INTEL, 910 .dev_id = I28F016B3B, 911 .name = "Intel 28F016B3B", 912 .devtypes = CFI_DEVICETYPE_X8, 913 .uaddr = MTD_UADDR_UNNECESSARY, 914 .dev_size = SIZE_2MiB, 915 .cmd_set = P_ID_INTEL_STD, 916 .nr_regions = 2, 917 .regions = { 918 ERASEINFO(0x02000, 8), 919 ERASEINFO(0x10000, 31), 920 } 921 }, { 922 .mfr_id = MANUFACTURER_INTEL, 923 .dev_id = I28F016S3, 924 .name = "Intel I28F016S3", 925 .devtypes = CFI_DEVICETYPE_X8, 926 .uaddr = MTD_UADDR_UNNECESSARY, 927 .dev_size = SIZE_2MiB, 928 .cmd_set = P_ID_INTEL_STD, 929 .nr_regions = 1, 930 .regions = { 931 ERASEINFO(0x10000, 32), 932 } 933 }, { 934 .mfr_id = MANUFACTURER_INTEL, 935 .dev_id = I28F016B3T, 936 .name = "Intel 28F016B3T", 937 .devtypes = CFI_DEVICETYPE_X8, 938 .uaddr = MTD_UADDR_UNNECESSARY, 939 .dev_size = SIZE_2MiB, 940 .cmd_set = P_ID_INTEL_STD, 941 .nr_regions = 2, 942 .regions = { 943 ERASEINFO(0x10000, 31), 944 ERASEINFO(0x02000, 8), 945 } 946 }, { 947 .mfr_id = MANUFACTURER_INTEL, 948 .dev_id = I28F160B3B, 949 .name = "Intel 28F160B3B", 950 .devtypes = CFI_DEVICETYPE_X16, 951 .uaddr = MTD_UADDR_UNNECESSARY, 952 .dev_size = SIZE_2MiB, 953 .cmd_set = P_ID_INTEL_STD, 954 .nr_regions = 2, 955 .regions = { 956 ERASEINFO(0x02000, 8), 957 ERASEINFO(0x10000, 31), 958 } 959 }, { 960 .mfr_id = MANUFACTURER_INTEL, 961 .dev_id = I28F160B3T, 962 .name = "Intel 28F160B3T", 963 .devtypes = CFI_DEVICETYPE_X16, 964 .uaddr = MTD_UADDR_UNNECESSARY, 965 .dev_size = SIZE_2MiB, 966 .cmd_set = P_ID_INTEL_STD, 967 .nr_regions = 2, 968 .regions = { 969 ERASEINFO(0x10000, 31), 970 ERASEINFO(0x02000, 8), 971 } 972 }, { 973 .mfr_id = MANUFACTURER_INTEL, 974 .dev_id = I28F320B3B, 975 .name = "Intel 28F320B3B", 976 .devtypes = CFI_DEVICETYPE_X16, 977 .uaddr = MTD_UADDR_UNNECESSARY, 978 .dev_size = SIZE_4MiB, 979 .cmd_set = P_ID_INTEL_STD, 980 .nr_regions = 2, 981 .regions = { 982 ERASEINFO(0x02000, 8), 983 ERASEINFO(0x10000, 63), 984 } 985 }, { 986 .mfr_id = MANUFACTURER_INTEL, 987 .dev_id = I28F320B3T, 988 .name = "Intel 28F320B3T", 989 .devtypes = CFI_DEVICETYPE_X16, 990 .uaddr = MTD_UADDR_UNNECESSARY, 991 .dev_size = SIZE_4MiB, 992 .cmd_set = P_ID_INTEL_STD, 993 .nr_regions = 2, 994 .regions = { 995 ERASEINFO(0x10000, 63), 996 ERASEINFO(0x02000, 8), 997 } 998 }, { 999 .mfr_id = MANUFACTURER_INTEL, 1000 .dev_id = I28F640B3B, 1001 .name = "Intel 28F640B3B", 1002 .devtypes = CFI_DEVICETYPE_X16, 1003 .uaddr = MTD_UADDR_UNNECESSARY, 1004 .dev_size = SIZE_8MiB, 1005 .cmd_set = P_ID_INTEL_STD, 1006 .nr_regions = 2, 1007 .regions = { 1008 ERASEINFO(0x02000, 8), 1009 ERASEINFO(0x10000, 127), 1010 } 1011 }, { 1012 .mfr_id = MANUFACTURER_INTEL, 1013 .dev_id = I28F640B3T, 1014 .name = "Intel 28F640B3T", 1015 .devtypes = CFI_DEVICETYPE_X16, 1016 .uaddr = MTD_UADDR_UNNECESSARY, 1017 .dev_size = SIZE_8MiB, 1018 .cmd_set = P_ID_INTEL_STD, 1019 .nr_regions = 2, 1020 .regions = { 1021 ERASEINFO(0x10000, 127), 1022 ERASEINFO(0x02000, 8), 1023 } 1024 }, { 1025 .mfr_id = MANUFACTURER_INTEL, 1026 .dev_id = I82802AB, 1027 .name = "Intel 82802AB", 1028 .devtypes = CFI_DEVICETYPE_X8, 1029 .uaddr = MTD_UADDR_UNNECESSARY, 1030 .dev_size = SIZE_512KiB, 1031 .cmd_set = P_ID_INTEL_EXT, 1032 .nr_regions = 1, 1033 .regions = { 1034 ERASEINFO(0x10000,8), 1035 } 1036 }, { 1037 .mfr_id = MANUFACTURER_INTEL, 1038 .dev_id = I82802AC, 1039 .name = "Intel 82802AC", 1040 .devtypes = CFI_DEVICETYPE_X8, 1041 .uaddr = MTD_UADDR_UNNECESSARY, 1042 .dev_size = SIZE_1MiB, 1043 .cmd_set = P_ID_INTEL_EXT, 1044 .nr_regions = 1, 1045 .regions = { 1046 ERASEINFO(0x10000,16), 1047 } 1048 }, { 1049 .mfr_id = MANUFACTURER_MACRONIX, 1050 .dev_id = MX29LV040C, 1051 .name = "Macronix MX29LV040C", 1052 .devtypes = CFI_DEVICETYPE_X8, 1053 .uaddr = MTD_UADDR_0x0555_0x02AA, 1054 .dev_size = SIZE_512KiB, 1055 .cmd_set = P_ID_AMD_STD, 1056 .nr_regions = 1, 1057 .regions = { 1058 ERASEINFO(0x10000,8), 1059 } 1060 }, { 1061 .mfr_id = MANUFACTURER_MACRONIX, 1062 .dev_id = MX29LV160T, 1063 .name = "MXIC MX29LV160T", 1064 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1065 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1066 .dev_size = SIZE_2MiB, 1067 .cmd_set = P_ID_AMD_STD, 1068 .nr_regions = 4, 1069 .regions = { 1070 ERASEINFO(0x10000,31), 1071 ERASEINFO(0x08000,1), 1072 ERASEINFO(0x02000,2), 1073 ERASEINFO(0x04000,1) 1074 } 1075 }, { 1076 .mfr_id = MANUFACTURER_NEC, 1077 .dev_id = UPD29F064115, 1078 .name = "NEC uPD29F064115", 1079 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1080 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1081 .dev_size = SIZE_8MiB, 1082 .cmd_set = P_ID_AMD_STD, 1083 .nr_regions = 3, 1084 .regions = { 1085 ERASEINFO(0x2000,8), 1086 ERASEINFO(0x10000,126), 1087 ERASEINFO(0x2000,8), 1088 } 1089 }, { 1090 .mfr_id = MANUFACTURER_MACRONIX, 1091 .dev_id = MX29LV160B, 1092 .name = "MXIC MX29LV160B", 1093 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1094 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1095 .dev_size = SIZE_2MiB, 1096 .cmd_set = P_ID_AMD_STD, 1097 .nr_regions = 4, 1098 .regions = { 1099 ERASEINFO(0x04000,1), 1100 ERASEINFO(0x02000,2), 1101 ERASEINFO(0x08000,1), 1102 ERASEINFO(0x10000,31) 1103 } 1104 }, { 1105 .mfr_id = MANUFACTURER_MACRONIX, 1106 .dev_id = MX29F040, 1107 .name = "Macronix MX29F040", 1108 .devtypes = CFI_DEVICETYPE_X8, 1109 .uaddr = MTD_UADDR_0x0555_0x02AA, 1110 .dev_size = SIZE_512KiB, 1111 .cmd_set = P_ID_AMD_STD, 1112 .nr_regions = 1, 1113 .regions = { 1114 ERASEINFO(0x10000,8), 1115 } 1116 }, { 1117 .mfr_id = MANUFACTURER_MACRONIX, 1118 .dev_id = MX29F016, 1119 .name = "Macronix MX29F016", 1120 .devtypes = CFI_DEVICETYPE_X8, 1121 .uaddr = MTD_UADDR_0x0555_0x02AA, 1122 .dev_size = SIZE_2MiB, 1123 .cmd_set = P_ID_AMD_STD, 1124 .nr_regions = 1, 1125 .regions = { 1126 ERASEINFO(0x10000,32), 1127 } 1128 }, { 1129 .mfr_id = MANUFACTURER_MACRONIX, 1130 .dev_id = MX29F004T, 1131 .name = "Macronix MX29F004T", 1132 .devtypes = CFI_DEVICETYPE_X8, 1133 .uaddr = MTD_UADDR_0x0555_0x02AA, 1134 .dev_size = SIZE_512KiB, 1135 .cmd_set = P_ID_AMD_STD, 1136 .nr_regions = 4, 1137 .regions = { 1138 ERASEINFO(0x10000,7), 1139 ERASEINFO(0x08000,1), 1140 ERASEINFO(0x02000,2), 1141 ERASEINFO(0x04000,1), 1142 } 1143 }, { 1144 .mfr_id = MANUFACTURER_MACRONIX, 1145 .dev_id = MX29F004B, 1146 .name = "Macronix MX29F004B", 1147 .devtypes = CFI_DEVICETYPE_X8, 1148 .uaddr = MTD_UADDR_0x0555_0x02AA, 1149 .dev_size = SIZE_512KiB, 1150 .cmd_set = P_ID_AMD_STD, 1151 .nr_regions = 4, 1152 .regions = { 1153 ERASEINFO(0x04000,1), 1154 ERASEINFO(0x02000,2), 1155 ERASEINFO(0x08000,1), 1156 ERASEINFO(0x10000,7), 1157 } 1158 }, { 1159 .mfr_id = MANUFACTURER_MACRONIX, 1160 .dev_id = MX29F002T, 1161 .name = "Macronix MX29F002T", 1162 .devtypes = CFI_DEVICETYPE_X8, 1163 .uaddr = MTD_UADDR_0x0555_0x02AA, 1164 .dev_size = SIZE_256KiB, 1165 .cmd_set = P_ID_AMD_STD, 1166 .nr_regions = 4, 1167 .regions = { 1168 ERASEINFO(0x10000,3), 1169 ERASEINFO(0x08000,1), 1170 ERASEINFO(0x02000,2), 1171 ERASEINFO(0x04000,1), 1172 } 1173 }, { 1174 .mfr_id = MANUFACTURER_PMC, 1175 .dev_id = PM49FL002, 1176 .name = "PMC Pm49FL002", 1177 .devtypes = CFI_DEVICETYPE_X8, 1178 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1179 .dev_size = SIZE_256KiB, 1180 .cmd_set = P_ID_AMD_STD, 1181 .nr_regions = 1, 1182 .regions = { 1183 ERASEINFO( 0x01000, 64 ) 1184 } 1185 }, { 1186 .mfr_id = MANUFACTURER_PMC, 1187 .dev_id = PM49FL004, 1188 .name = "PMC Pm49FL004", 1189 .devtypes = CFI_DEVICETYPE_X8, 1190 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1191 .dev_size = SIZE_512KiB, 1192 .cmd_set = P_ID_AMD_STD, 1193 .nr_regions = 1, 1194 .regions = { 1195 ERASEINFO( 0x01000, 128 ) 1196 } 1197 }, { 1198 .mfr_id = MANUFACTURER_PMC, 1199 .dev_id = PM49FL008, 1200 .name = "PMC Pm49FL008", 1201 .devtypes = CFI_DEVICETYPE_X8, 1202 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1203 .dev_size = SIZE_1MiB, 1204 .cmd_set = P_ID_AMD_STD, 1205 .nr_regions = 1, 1206 .regions = { 1207 ERASEINFO( 0x01000, 256 ) 1208 } 1209 }, { 1210 .mfr_id = MANUFACTURER_SHARP, 1211 .dev_id = LH28F640BF, 1212 .name = "LH28F640BF", 1213 .devtypes = CFI_DEVICETYPE_X8, 1214 .uaddr = MTD_UADDR_UNNECESSARY, 1215 .dev_size = SIZE_4MiB, 1216 .cmd_set = P_ID_INTEL_STD, 1217 .nr_regions = 1, 1218 .regions = { 1219 ERASEINFO(0x40000,16), 1220 } 1221 }, { 1222 .mfr_id = MANUFACTURER_SST, 1223 .dev_id = SST39LF512, 1224 .name = "SST 39LF512", 1225 .devtypes = CFI_DEVICETYPE_X8, 1226 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1227 .dev_size = SIZE_64KiB, 1228 .cmd_set = P_ID_AMD_STD, 1229 .nr_regions = 1, 1230 .regions = { 1231 ERASEINFO(0x01000,16), 1232 } 1233 }, { 1234 .mfr_id = MANUFACTURER_SST, 1235 .dev_id = SST39LF010, 1236 .name = "SST 39LF010", 1237 .devtypes = CFI_DEVICETYPE_X8, 1238 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1239 .dev_size = SIZE_128KiB, 1240 .cmd_set = P_ID_AMD_STD, 1241 .nr_regions = 1, 1242 .regions = { 1243 ERASEINFO(0x01000,32), 1244 } 1245 }, { 1246 .mfr_id = MANUFACTURER_SST, 1247 .dev_id = SST29EE020, 1248 .name = "SST 29EE020", 1249 .devtypes = CFI_DEVICETYPE_X8, 1250 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1251 .dev_size = SIZE_256KiB, 1252 .cmd_set = P_ID_SST_PAGE, 1253 .nr_regions = 1, 1254 .regions = {ERASEINFO(0x01000,64), 1255 } 1256 }, { 1257 .mfr_id = MANUFACTURER_SST, 1258 .dev_id = SST29LE020, 1259 .name = "SST 29LE020", 1260 .devtypes = CFI_DEVICETYPE_X8, 1261 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1262 .dev_size = SIZE_256KiB, 1263 .cmd_set = P_ID_SST_PAGE, 1264 .nr_regions = 1, 1265 .regions = {ERASEINFO(0x01000,64), 1266 } 1267 }, { 1268 .mfr_id = MANUFACTURER_SST, 1269 .dev_id = SST39LF020, 1270 .name = "SST 39LF020", 1271 .devtypes = CFI_DEVICETYPE_X8, 1272 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1273 .dev_size = SIZE_256KiB, 1274 .cmd_set = P_ID_AMD_STD, 1275 .nr_regions = 1, 1276 .regions = { 1277 ERASEINFO(0x01000,64), 1278 } 1279 }, { 1280 .mfr_id = MANUFACTURER_SST, 1281 .dev_id = SST39LF040, 1282 .name = "SST 39LF040", 1283 .devtypes = CFI_DEVICETYPE_X8, 1284 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1285 .dev_size = SIZE_512KiB, 1286 .cmd_set = P_ID_AMD_STD, 1287 .nr_regions = 1, 1288 .regions = { 1289 ERASEINFO(0x01000,128), 1290 } 1291 }, { 1292 .mfr_id = MANUFACTURER_SST, 1293 .dev_id = SST39SF010A, 1294 .name = "SST 39SF010A", 1295 .devtypes = CFI_DEVICETYPE_X8, 1296 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1297 .dev_size = SIZE_128KiB, 1298 .cmd_set = P_ID_AMD_STD, 1299 .nr_regions = 1, 1300 .regions = { 1301 ERASEINFO(0x01000,32), 1302 } 1303 }, { 1304 .mfr_id = MANUFACTURER_SST, 1305 .dev_id = SST39SF020A, 1306 .name = "SST 39SF020A", 1307 .devtypes = CFI_DEVICETYPE_X8, 1308 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1309 .dev_size = SIZE_256KiB, 1310 .cmd_set = P_ID_AMD_STD, 1311 .nr_regions = 1, 1312 .regions = { 1313 ERASEINFO(0x01000,64), 1314 } 1315 }, { 1316 .mfr_id = MANUFACTURER_SST, 1317 .dev_id = SST49LF040B, 1318 .name = "SST 49LF040B", 1319 .devtypes = CFI_DEVICETYPE_X8, 1320 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1321 .dev_size = SIZE_512KiB, 1322 .cmd_set = P_ID_AMD_STD, 1323 .nr_regions = 1, 1324 .regions = { 1325 ERASEINFO(0x01000,128), 1326 } 1327 }, { 1328 1329 .mfr_id = MANUFACTURER_SST, 1330 .dev_id = SST49LF004B, 1331 .name = "SST 49LF004B", 1332 .devtypes = CFI_DEVICETYPE_X8, 1333 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1334 .dev_size = SIZE_512KiB, 1335 .cmd_set = P_ID_AMD_STD, 1336 .nr_regions = 1, 1337 .regions = { 1338 ERASEINFO(0x01000,128), 1339 } 1340 }, { 1341 .mfr_id = MANUFACTURER_SST, 1342 .dev_id = SST49LF008A, 1343 .name = "SST 49LF008A", 1344 .devtypes = CFI_DEVICETYPE_X8, 1345 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1346 .dev_size = SIZE_1MiB, 1347 .cmd_set = P_ID_AMD_STD, 1348 .nr_regions = 1, 1349 .regions = { 1350 ERASEINFO(0x01000,256), 1351 } 1352 }, { 1353 .mfr_id = MANUFACTURER_SST, 1354 .dev_id = SST49LF030A, 1355 .name = "SST 49LF030A", 1356 .devtypes = CFI_DEVICETYPE_X8, 1357 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1358 .dev_size = SIZE_512KiB, 1359 .cmd_set = P_ID_AMD_STD, 1360 .nr_regions = 1, 1361 .regions = { 1362 ERASEINFO(0x01000,96), 1363 } 1364 }, { 1365 .mfr_id = MANUFACTURER_SST, 1366 .dev_id = SST49LF040A, 1367 .name = "SST 49LF040A", 1368 .devtypes = CFI_DEVICETYPE_X8, 1369 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1370 .dev_size = SIZE_512KiB, 1371 .cmd_set = P_ID_AMD_STD, 1372 .nr_regions = 1, 1373 .regions = { 1374 ERASEINFO(0x01000,128), 1375 } 1376 }, { 1377 .mfr_id = MANUFACTURER_SST, 1378 .dev_id = SST49LF080A, 1379 .name = "SST 49LF080A", 1380 .devtypes = CFI_DEVICETYPE_X8, 1381 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1382 .dev_size = SIZE_1MiB, 1383 .cmd_set = P_ID_AMD_STD, 1384 .nr_regions = 1, 1385 .regions = { 1386 ERASEINFO(0x01000,256), 1387 } 1388 }, { 1389 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1390 .dev_id = SST39LF160, 1391 .name = "SST 39LF160", 1392 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1393 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1394 .dev_size = SIZE_2MiB, 1395 .cmd_set = P_ID_AMD_STD, 1396 .nr_regions = 2, 1397 .regions = { 1398 ERASEINFO(0x1000,256), 1399 ERASEINFO(0x1000,256) 1400 } 1401 }, { 1402 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1403 .dev_id = SST39VF1601, 1404 .name = "SST 39VF1601", 1405 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1406 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1407 .dev_size = SIZE_2MiB, 1408 .cmd_set = P_ID_AMD_STD, 1409 .nr_regions = 2, 1410 .regions = { 1411 ERASEINFO(0x1000,256), 1412 ERASEINFO(0x1000,256) 1413 } 1414 }, { 1415 .mfr_id = MANUFACTURER_ST, 1416 .dev_id = M29F800AB, 1417 .name = "ST M29F800AB", 1418 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1419 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1420 .dev_size = SIZE_1MiB, 1421 .cmd_set = P_ID_AMD_STD, 1422 .nr_regions = 4, 1423 .regions = { 1424 ERASEINFO(0x04000,1), 1425 ERASEINFO(0x02000,2), 1426 ERASEINFO(0x08000,1), 1427 ERASEINFO(0x10000,15), 1428 } 1429 }, { 1430 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1431 .dev_id = M29W800DT, 1432 .name = "ST M29W800DT", 1433 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1434 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1435 .dev_size = SIZE_1MiB, 1436 .cmd_set = P_ID_AMD_STD, 1437 .nr_regions = 4, 1438 .regions = { 1439 ERASEINFO(0x10000,15), 1440 ERASEINFO(0x08000,1), 1441 ERASEINFO(0x02000,2), 1442 ERASEINFO(0x04000,1) 1443 } 1444 }, { 1445 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1446 .dev_id = M29W800DB, 1447 .name = "ST M29W800DB", 1448 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1449 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1450 .dev_size = SIZE_1MiB, 1451 .cmd_set = P_ID_AMD_STD, 1452 .nr_regions = 4, 1453 .regions = { 1454 ERASEINFO(0x04000,1), 1455 ERASEINFO(0x02000,2), 1456 ERASEINFO(0x08000,1), 1457 ERASEINFO(0x10000,15) 1458 } 1459 }, { 1460 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1461 .dev_id = M29W160DT, 1462 .name = "ST M29W160DT", 1463 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1464 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1465 .dev_size = SIZE_2MiB, 1466 .cmd_set = P_ID_AMD_STD, 1467 .nr_regions = 4, 1468 .regions = { 1469 ERASEINFO(0x10000,31), 1470 ERASEINFO(0x08000,1), 1471 ERASEINFO(0x02000,2), 1472 ERASEINFO(0x04000,1) 1473 } 1474 }, { 1475 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1476 .dev_id = M29W160DB, 1477 .name = "ST M29W160DB", 1478 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1479 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1480 .dev_size = SIZE_2MiB, 1481 .cmd_set = P_ID_AMD_STD, 1482 .nr_regions = 4, 1483 .regions = { 1484 ERASEINFO(0x04000,1), 1485 ERASEINFO(0x02000,2), 1486 ERASEINFO(0x08000,1), 1487 ERASEINFO(0x10000,31) 1488 } 1489 }, { 1490 .mfr_id = MANUFACTURER_ST, 1491 .dev_id = M29W040B, 1492 .name = "ST M29W040B", 1493 .devtypes = CFI_DEVICETYPE_X8, 1494 .uaddr = MTD_UADDR_0x0555_0x02AA, 1495 .dev_size = SIZE_512KiB, 1496 .cmd_set = P_ID_AMD_STD, 1497 .nr_regions = 1, 1498 .regions = { 1499 ERASEINFO(0x10000,8), 1500 } 1501 }, { 1502 .mfr_id = MANUFACTURER_ST, 1503 .dev_id = M50FW040, 1504 .name = "ST M50FW040", 1505 .devtypes = CFI_DEVICETYPE_X8, 1506 .uaddr = MTD_UADDR_UNNECESSARY, 1507 .dev_size = SIZE_512KiB, 1508 .cmd_set = P_ID_INTEL_EXT, 1509 .nr_regions = 1, 1510 .regions = { 1511 ERASEINFO(0x10000,8), 1512 } 1513 }, { 1514 .mfr_id = MANUFACTURER_ST, 1515 .dev_id = M50FW080, 1516 .name = "ST M50FW080", 1517 .devtypes = CFI_DEVICETYPE_X8, 1518 .uaddr = MTD_UADDR_UNNECESSARY, 1519 .dev_size = SIZE_1MiB, 1520 .cmd_set = P_ID_INTEL_EXT, 1521 .nr_regions = 1, 1522 .regions = { 1523 ERASEINFO(0x10000,16), 1524 } 1525 }, { 1526 .mfr_id = MANUFACTURER_ST, 1527 .dev_id = M50FW016, 1528 .name = "ST M50FW016", 1529 .devtypes = CFI_DEVICETYPE_X8, 1530 .uaddr = MTD_UADDR_UNNECESSARY, 1531 .dev_size = SIZE_2MiB, 1532 .cmd_set = P_ID_INTEL_EXT, 1533 .nr_regions = 1, 1534 .regions = { 1535 ERASEINFO(0x10000,32), 1536 } 1537 }, { 1538 .mfr_id = MANUFACTURER_ST, 1539 .dev_id = M50LPW080, 1540 .name = "ST M50LPW080", 1541 .devtypes = CFI_DEVICETYPE_X8, 1542 .uaddr = MTD_UADDR_UNNECESSARY, 1543 .dev_size = SIZE_1MiB, 1544 .cmd_set = P_ID_INTEL_EXT, 1545 .nr_regions = 1, 1546 .regions = { 1547 ERASEINFO(0x10000,16), 1548 } 1549 }, { 1550 .mfr_id = MANUFACTURER_TOSHIBA, 1551 .dev_id = TC58FVT160, 1552 .name = "Toshiba TC58FVT160", 1553 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1554 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1555 .dev_size = SIZE_2MiB, 1556 .cmd_set = P_ID_AMD_STD, 1557 .nr_regions = 4, 1558 .regions = { 1559 ERASEINFO(0x10000,31), 1560 ERASEINFO(0x08000,1), 1561 ERASEINFO(0x02000,2), 1562 ERASEINFO(0x04000,1) 1563 } 1564 }, { 1565 .mfr_id = MANUFACTURER_TOSHIBA, 1566 .dev_id = TC58FVB160, 1567 .name = "Toshiba TC58FVB160", 1568 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1569 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1570 .dev_size = SIZE_2MiB, 1571 .cmd_set = P_ID_AMD_STD, 1572 .nr_regions = 4, 1573 .regions = { 1574 ERASEINFO(0x04000,1), 1575 ERASEINFO(0x02000,2), 1576 ERASEINFO(0x08000,1), 1577 ERASEINFO(0x10000,31) 1578 } 1579 }, { 1580 .mfr_id = MANUFACTURER_TOSHIBA, 1581 .dev_id = TC58FVB321, 1582 .name = "Toshiba TC58FVB321", 1583 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1584 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1585 .dev_size = SIZE_4MiB, 1586 .cmd_set = P_ID_AMD_STD, 1587 .nr_regions = 2, 1588 .regions = { 1589 ERASEINFO(0x02000,8), 1590 ERASEINFO(0x10000,63) 1591 } 1592 }, { 1593 .mfr_id = MANUFACTURER_TOSHIBA, 1594 .dev_id = TC58FVT321, 1595 .name = "Toshiba TC58FVT321", 1596 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1597 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1598 .dev_size = SIZE_4MiB, 1599 .cmd_set = P_ID_AMD_STD, 1600 .nr_regions = 2, 1601 .regions = { 1602 ERASEINFO(0x10000,63), 1603 ERASEINFO(0x02000,8) 1604 } 1605 }, { 1606 .mfr_id = MANUFACTURER_TOSHIBA, 1607 .dev_id = TC58FVB641, 1608 .name = "Toshiba TC58FVB641", 1609 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1610 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1611 .dev_size = SIZE_8MiB, 1612 .cmd_set = P_ID_AMD_STD, 1613 .nr_regions = 2, 1614 .regions = { 1615 ERASEINFO(0x02000,8), 1616 ERASEINFO(0x10000,127) 1617 } 1618 }, { 1619 .mfr_id = MANUFACTURER_TOSHIBA, 1620 .dev_id = TC58FVT641, 1621 .name = "Toshiba TC58FVT641", 1622 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1623 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1624 .dev_size = SIZE_8MiB, 1625 .cmd_set = P_ID_AMD_STD, 1626 .nr_regions = 2, 1627 .regions = { 1628 ERASEINFO(0x10000,127), 1629 ERASEINFO(0x02000,8) 1630 } 1631 }, { 1632 .mfr_id = MANUFACTURER_WINBOND, 1633 .dev_id = W49V002A, 1634 .name = "Winbond W49V002A", 1635 .devtypes = CFI_DEVICETYPE_X8, 1636 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1637 .dev_size = SIZE_256KiB, 1638 .cmd_set = P_ID_AMD_STD, 1639 .nr_regions = 4, 1640 .regions = { 1641 ERASEINFO(0x10000, 3), 1642 ERASEINFO(0x08000, 1), 1643 ERASEINFO(0x02000, 2), 1644 ERASEINFO(0x04000, 1), 1645 } 1646 } 1647 }; 1648 1649 static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, 1650 struct cfi_private *cfi) 1651 { 1652 map_word result; 1653 unsigned long mask; 1654 u32 ofs = cfi_build_cmd_addr(0, cfi_interleave(cfi), cfi->device_type); 1655 mask = (1 << (cfi->device_type * 8)) -1; 1656 result = map_read(map, base + ofs); 1657 return result.x[0] & mask; 1658 } 1659 1660 static inline u32 jedec_read_id(struct map_info *map, uint32_t base, 1661 struct cfi_private *cfi) 1662 { 1663 map_word result; 1664 unsigned long mask; 1665 u32 ofs = cfi_build_cmd_addr(1, cfi_interleave(cfi), cfi->device_type); 1666 mask = (1 << (cfi->device_type * 8)) -1; 1667 result = map_read(map, base + ofs); 1668 return result.x[0] & mask; 1669 } 1670 1671 static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi) 1672 { 1673 /* Reset */ 1674 1675 /* after checking the datasheets for SST, MACRONIX and ATMEL 1676 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset 1677 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at 1678 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips 1679 * as they will ignore the writes and dont care what address 1680 * the F0 is written to */ 1681 if (cfi->addr_unlock1) { 1682 DEBUG( MTD_DEBUG_LEVEL3, 1683 "reset unlock called %x %x \n", 1684 cfi->addr_unlock1,cfi->addr_unlock2); 1685 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1686 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1687 } 1688 1689 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1690 /* Some misdesigned Intel chips do not respond for 0xF0 for a reset, 1691 * so ensure we're in read mode. Send both the Intel and the AMD command 1692 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so 1693 * this should be safe. 1694 */ 1695 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); 1696 /* FIXME - should have reset delay before continuing */ 1697 } 1698 1699 1700 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index) 1701 { 1702 int i,num_erase_regions; 1703 uint8_t uaddr; 1704 1705 if (! (jedec_table[index].devtypes & p_cfi->device_type)) { 1706 DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n", 1707 jedec_table[index].name, 4 * (1<<p_cfi->device_type)); 1708 return 0; 1709 } 1710 1711 printk(KERN_INFO "Found: %s\n",jedec_table[index].name); 1712 1713 num_erase_regions = jedec_table[index].nr_regions; 1714 1715 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); 1716 if (!p_cfi->cfiq) { 1717 //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name); 1718 return 0; 1719 } 1720 1721 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident)); 1722 1723 p_cfi->cfiq->P_ID = jedec_table[index].cmd_set; 1724 p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions; 1725 p_cfi->cfiq->DevSize = jedec_table[index].dev_size; 1726 p_cfi->cfi_mode = CFI_MODE_JEDEC; 1727 1728 for (i=0; i<num_erase_regions; i++){ 1729 p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i]; 1730 } 1731 p_cfi->cmdset_priv = NULL; 1732 1733 /* This may be redundant for some cases, but it doesn't hurt */ 1734 p_cfi->mfr = jedec_table[index].mfr_id; 1735 p_cfi->id = jedec_table[index].dev_id; 1736 1737 uaddr = jedec_table[index].uaddr; 1738 1739 /* The table has unlock addresses in _bytes_, and we try not to let 1740 our brains explode when we see the datasheets talking about address 1741 lines numbered from A-1 to A18. The CFI table has unlock addresses 1742 in device-words according to the mode the device is connected in */ 1743 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type; 1744 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type; 1745 1746 return 1; /* ok */ 1747 } 1748 1749 1750 /* 1751 * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing 1752 * the mapped address, unlock addresses, and proper chip ID. This function 1753 * attempts to minimize errors. It is doubtfull that this probe will ever 1754 * be perfect - consequently there should be some module parameters that 1755 * could be manually specified to force the chip info. 1756 */ 1757 static inline int jedec_match( uint32_t base, 1758 struct map_info *map, 1759 struct cfi_private *cfi, 1760 const struct amd_flash_info *finfo ) 1761 { 1762 int rc = 0; /* failure until all tests pass */ 1763 u32 mfr, id; 1764 uint8_t uaddr; 1765 1766 /* 1767 * The IDs must match. For X16 and X32 devices operating in 1768 * a lower width ( X8 or X16 ), the device ID's are usually just 1769 * the lower byte(s) of the larger device ID for wider mode. If 1770 * a part is found that doesn't fit this assumption (device id for 1771 * smaller width mode is completely unrealated to full-width mode) 1772 * then the jedec_table[] will have to be augmented with the IDs 1773 * for different widths. 1774 */ 1775 switch (cfi->device_type) { 1776 case CFI_DEVICETYPE_X8: 1777 mfr = (uint8_t)finfo->mfr_id; 1778 id = (uint8_t)finfo->dev_id; 1779 1780 /* bjd: it seems that if we do this, we can end up 1781 * detecting 16bit flashes as an 8bit device, even though 1782 * there aren't. 1783 */ 1784 if (finfo->dev_id > 0xff) { 1785 DEBUG( MTD_DEBUG_LEVEL3, "%s(): ID is not 8bit\n", 1786 __func__); 1787 goto match_done; 1788 } 1789 break; 1790 case CFI_DEVICETYPE_X16: 1791 mfr = (uint16_t)finfo->mfr_id; 1792 id = (uint16_t)finfo->dev_id; 1793 break; 1794 case CFI_DEVICETYPE_X32: 1795 mfr = (uint16_t)finfo->mfr_id; 1796 id = (uint32_t)finfo->dev_id; 1797 break; 1798 default: 1799 printk(KERN_WARNING 1800 "MTD %s(): Unsupported device type %d\n", 1801 __func__, cfi->device_type); 1802 goto match_done; 1803 } 1804 if ( cfi->mfr != mfr || cfi->id != id ) { 1805 goto match_done; 1806 } 1807 1808 /* the part size must fit in the memory window */ 1809 DEBUG( MTD_DEBUG_LEVEL3, 1810 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n", 1811 __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) ); 1812 if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) { 1813 DEBUG( MTD_DEBUG_LEVEL3, 1814 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n", 1815 __func__, finfo->mfr_id, finfo->dev_id, 1816 1 << finfo->dev_size ); 1817 goto match_done; 1818 } 1819 1820 if (! (finfo->devtypes & cfi->device_type)) 1821 goto match_done; 1822 1823 uaddr = finfo->uaddr; 1824 1825 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n", 1826 __func__, cfi->addr_unlock1, cfi->addr_unlock2 ); 1827 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr 1828 && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 || 1829 unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) { 1830 DEBUG( MTD_DEBUG_LEVEL3, 1831 "MTD %s(): 0x%.4x 0x%.4x did not match\n", 1832 __func__, 1833 unlock_addrs[uaddr].addr1, 1834 unlock_addrs[uaddr].addr2); 1835 goto match_done; 1836 } 1837 1838 /* 1839 * Make sure the ID's dissappear when the device is taken out of 1840 * ID mode. The only time this should fail when it should succeed 1841 * is when the ID's are written as data to the same 1842 * addresses. For this rare and unfortunate case the chip 1843 * cannot be probed correctly. 1844 * FIXME - write a driver that takes all of the chip info as 1845 * module parameters, doesn't probe but forces a load. 1846 */ 1847 DEBUG( MTD_DEBUG_LEVEL3, 1848 "MTD %s(): check ID's disappear when not in ID mode\n", 1849 __func__ ); 1850 jedec_reset( base, map, cfi ); 1851 mfr = jedec_read_mfr( map, base, cfi ); 1852 id = jedec_read_id( map, base, cfi ); 1853 if ( mfr == cfi->mfr && id == cfi->id ) { 1854 DEBUG( MTD_DEBUG_LEVEL3, 1855 "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n" 1856 "You might need to manually specify JEDEC parameters.\n", 1857 __func__, cfi->mfr, cfi->id ); 1858 goto match_done; 1859 } 1860 1861 /* all tests passed - mark as success */ 1862 rc = 1; 1863 1864 /* 1865 * Put the device back in ID mode - only need to do this if we 1866 * were truly frobbing a real device. 1867 */ 1868 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ ); 1869 if (cfi->addr_unlock1) { 1870 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1871 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1872 } 1873 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1874 /* FIXME - should have a delay before continuing */ 1875 1876 match_done: 1877 return rc; 1878 } 1879 1880 1881 static int jedec_probe_chip(struct map_info *map, __u32 base, 1882 unsigned long *chip_map, struct cfi_private *cfi) 1883 { 1884 int i; 1885 enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED; 1886 u32 probe_offset1, probe_offset2; 1887 1888 retry: 1889 if (!cfi->numchips) { 1890 uaddr_idx++; 1891 1892 if (MTD_UADDR_UNNECESSARY == uaddr_idx) 1893 return 0; 1894 1895 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type; 1896 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type; 1897 } 1898 1899 /* Make certain we aren't probing past the end of map */ 1900 if (base >= map->size) { 1901 printk(KERN_NOTICE 1902 "Probe at base(0x%08x) past the end of the map(0x%08lx)\n", 1903 base, map->size -1); 1904 return 0; 1905 1906 } 1907 /* Ensure the unlock addresses we try stay inside the map */ 1908 probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, cfi_interleave(cfi), cfi->device_type); 1909 probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, cfi_interleave(cfi), cfi->device_type); 1910 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || 1911 ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) 1912 goto retry; 1913 1914 /* Reset */ 1915 jedec_reset(base, map, cfi); 1916 1917 /* Autoselect Mode */ 1918 if(cfi->addr_unlock1) { 1919 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1920 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1921 } 1922 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1923 /* FIXME - should have a delay before continuing */ 1924 1925 if (!cfi->numchips) { 1926 /* This is the first time we're called. Set up the CFI 1927 stuff accordingly and return */ 1928 1929 cfi->mfr = jedec_read_mfr(map, base, cfi); 1930 cfi->id = jedec_read_id(map, base, cfi); 1931 DEBUG(MTD_DEBUG_LEVEL3, 1932 "Search for id:(%02x %02x) interleave(%d) type(%d)\n", 1933 cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type); 1934 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { 1935 if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) { 1936 DEBUG( MTD_DEBUG_LEVEL3, 1937 "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n", 1938 __func__, cfi->mfr, cfi->id, 1939 cfi->addr_unlock1, cfi->addr_unlock2 ); 1940 if (!cfi_jedec_setup(cfi, i)) 1941 return 0; 1942 goto ok_out; 1943 } 1944 } 1945 goto retry; 1946 } else { 1947 uint16_t mfr; 1948 uint16_t id; 1949 1950 /* Make sure it is a chip of the same manufacturer and id */ 1951 mfr = jedec_read_mfr(map, base, cfi); 1952 id = jedec_read_id(map, base, cfi); 1953 1954 if ((mfr != cfi->mfr) || (id != cfi->id)) { 1955 printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n", 1956 map->name, mfr, id, base); 1957 jedec_reset(base, map, cfi); 1958 return 0; 1959 } 1960 } 1961 1962 /* Check each previous chip locations to see if it's an alias */ 1963 for (i=0; i < (base >> cfi->chipshift); i++) { 1964 unsigned long start; 1965 if(!test_bit(i, chip_map)) { 1966 continue; /* Skip location; no valid chip at this address */ 1967 } 1968 start = i << cfi->chipshift; 1969 if (jedec_read_mfr(map, start, cfi) == cfi->mfr && 1970 jedec_read_id(map, start, cfi) == cfi->id) { 1971 /* Eep. This chip also looks like it's in autoselect mode. 1972 Is it an alias for the new one? */ 1973 jedec_reset(start, map, cfi); 1974 1975 /* If the device IDs go away, it's an alias */ 1976 if (jedec_read_mfr(map, base, cfi) != cfi->mfr || 1977 jedec_read_id(map, base, cfi) != cfi->id) { 1978 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 1979 map->name, base, start); 1980 return 0; 1981 } 1982 1983 /* Yes, it's actually got the device IDs as data. Most 1984 * unfortunate. Stick the new chip in read mode 1985 * too and if it's the same, assume it's an alias. */ 1986 /* FIXME: Use other modes to do a proper check */ 1987 jedec_reset(base, map, cfi); 1988 if (jedec_read_mfr(map, base, cfi) == cfi->mfr && 1989 jedec_read_id(map, base, cfi) == cfi->id) { 1990 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 1991 map->name, base, start); 1992 return 0; 1993 } 1994 } 1995 } 1996 1997 /* OK, if we got to here, then none of the previous chips appear to 1998 be aliases for the current one. */ 1999 set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ 2000 cfi->numchips++; 2001 2002 ok_out: 2003 /* Put it back into Read Mode */ 2004 jedec_reset(base, map, cfi); 2005 2006 printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", 2007 map->name, cfi_interleave(cfi), cfi->device_type*8, base, 2008 map->bankwidth*8); 2009 2010 return 1; 2011 } 2012 2013 static struct chip_probe jedec_chip_probe = { 2014 .name = "JEDEC", 2015 .probe_chip = jedec_probe_chip 2016 }; 2017 2018 static struct mtd_info *jedec_probe(struct map_info *map) 2019 { 2020 /* 2021 * Just use the generic probe stuff to call our CFI-specific 2022 * chip_probe routine in all the possible permutations, etc. 2023 */ 2024 return mtd_do_chip_probe(map, &jedec_chip_probe); 2025 } 2026 2027 static struct mtd_chip_driver jedec_chipdrv = { 2028 .probe = jedec_probe, 2029 .name = "jedec_probe", 2030 .module = THIS_MODULE 2031 }; 2032 2033 static int __init jedec_probe_init(void) 2034 { 2035 register_mtd_chip_driver(&jedec_chipdrv); 2036 return 0; 2037 } 2038 2039 static void __exit jedec_probe_exit(void) 2040 { 2041 unregister_mtd_chip_driver(&jedec_chipdrv); 2042 } 2043 2044 module_init(jedec_probe_init); 2045 module_exit(jedec_probe_exit); 2046 2047 MODULE_LICENSE("GPL"); 2048 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al."); 2049 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips"); 2050