1 /* 2 Common Flash Interface probe code. 3 (C) 2000 Red Hat. GPL'd. 4 See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5) 5 for the standard this probe goes back to. 6 7 Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 8 */ 9 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/kernel.h> 14 #include <asm/io.h> 15 #include <asm/byteorder.h> 16 #include <linux/errno.h> 17 #include <linux/slab.h> 18 #include <linux/interrupt.h> 19 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/map.h> 22 #include <linux/mtd/cfi.h> 23 #include <linux/mtd/gen_probe.h> 24 25 /* Manufacturers */ 26 #define MANUFACTURER_AMD 0x0001 27 #define MANUFACTURER_ATMEL 0x001f 28 #define MANUFACTURER_EON 0x001c 29 #define MANUFACTURER_FUJITSU 0x0004 30 #define MANUFACTURER_HYUNDAI 0x00AD 31 #define MANUFACTURER_INTEL 0x0089 32 #define MANUFACTURER_MACRONIX 0x00C2 33 #define MANUFACTURER_NEC 0x0010 34 #define MANUFACTURER_PMC 0x009D 35 #define MANUFACTURER_SHARP 0x00b0 36 #define MANUFACTURER_SST 0x00BF 37 #define MANUFACTURER_ST 0x0020 38 #define MANUFACTURER_TOSHIBA 0x0098 39 #define MANUFACTURER_WINBOND 0x00da 40 #define CONTINUATION_CODE 0x007f 41 42 43 /* AMD */ 44 #define AM29DL800BB 0x22CB 45 #define AM29DL800BT 0x224A 46 47 #define AM29F800BB 0x2258 48 #define AM29F800BT 0x22D6 49 #define AM29LV400BB 0x22BA 50 #define AM29LV400BT 0x22B9 51 #define AM29LV800BB 0x225B 52 #define AM29LV800BT 0x22DA 53 #define AM29LV160DT 0x22C4 54 #define AM29LV160DB 0x2249 55 #define AM29F017D 0x003D 56 #define AM29F016D 0x00AD 57 #define AM29F080 0x00D5 58 #define AM29F040 0x00A4 59 #define AM29LV040B 0x004F 60 #define AM29F032B 0x0041 61 #define AM29F002T 0x00B0 62 #define AM29SL800DB 0x226B 63 #define AM29SL800DT 0x22EA 64 65 /* Atmel */ 66 #define AT49BV512 0x0003 67 #define AT29LV512 0x003d 68 #define AT49BV16X 0x00C0 69 #define AT49BV16XT 0x00C2 70 #define AT49BV32X 0x00C8 71 #define AT49BV32XT 0x00C9 72 73 /* Eon */ 74 #define EN29SL800BB 0x226B 75 #define EN29SL800BT 0x22EA 76 77 /* Fujitsu */ 78 #define MBM29F040C 0x00A4 79 #define MBM29F800BA 0x2258 80 #define MBM29LV650UE 0x22D7 81 #define MBM29LV320TE 0x22F6 82 #define MBM29LV320BE 0x22F9 83 #define MBM29LV160TE 0x22C4 84 #define MBM29LV160BE 0x2249 85 #define MBM29LV800BA 0x225B 86 #define MBM29LV800TA 0x22DA 87 #define MBM29LV400TC 0x22B9 88 #define MBM29LV400BC 0x22BA 89 90 /* Hyundai */ 91 #define HY29F002T 0x00B0 92 93 /* Intel */ 94 #define I28F004B3T 0x00d4 95 #define I28F004B3B 0x00d5 96 #define I28F400B3T 0x8894 97 #define I28F400B3B 0x8895 98 #define I28F008S5 0x00a6 99 #define I28F016S5 0x00a0 100 #define I28F008SA 0x00a2 101 #define I28F008B3T 0x00d2 102 #define I28F008B3B 0x00d3 103 #define I28F800B3T 0x8892 104 #define I28F800B3B 0x8893 105 #define I28F016S3 0x00aa 106 #define I28F016B3T 0x00d0 107 #define I28F016B3B 0x00d1 108 #define I28F160B3T 0x8890 109 #define I28F160B3B 0x8891 110 #define I28F320B3T 0x8896 111 #define I28F320B3B 0x8897 112 #define I28F640B3T 0x8898 113 #define I28F640B3B 0x8899 114 #define I82802AB 0x00ad 115 #define I82802AC 0x00ac 116 117 /* Macronix */ 118 #define MX29LV040C 0x004F 119 #define MX29LV160T 0x22C4 120 #define MX29LV160B 0x2249 121 #define MX29F040 0x00A4 122 #define MX29F016 0x00AD 123 #define MX29F002T 0x00B0 124 #define MX29F004T 0x0045 125 #define MX29F004B 0x0046 126 127 /* NEC */ 128 #define UPD29F064115 0x221C 129 130 /* PMC */ 131 #define PM49FL002 0x006D 132 #define PM49FL004 0x006E 133 #define PM49FL008 0x006A 134 135 /* Sharp */ 136 #define LH28F640BF 0x00b0 137 138 /* ST - www.st.com */ 139 #define M29F800AB 0x0058 140 #define M29W800DT 0x00D7 141 #define M29W800DB 0x005B 142 #define M29W400DT 0x00EE 143 #define M29W400DB 0x00EF 144 #define M29W160DT 0x22C4 145 #define M29W160DB 0x2249 146 #define M29W040B 0x00E3 147 #define M50FW040 0x002C 148 #define M50FW080 0x002D 149 #define M50FW016 0x002E 150 #define M50LPW080 0x002F 151 #define M50FLW080A 0x0080 152 #define M50FLW080B 0x0081 153 154 /* SST */ 155 #define SST29EE020 0x0010 156 #define SST29LE020 0x0012 157 #define SST29EE512 0x005d 158 #define SST29LE512 0x003d 159 #define SST39LF800 0x2781 160 #define SST39LF160 0x2782 161 #define SST39VF1601 0x234b 162 #define SST39VF3201 0x235b 163 #define SST39LF512 0x00D4 164 #define SST39LF010 0x00D5 165 #define SST39LF020 0x00D6 166 #define SST39LF040 0x00D7 167 #define SST39SF010A 0x00B5 168 #define SST39SF020A 0x00B6 169 #define SST49LF004B 0x0060 170 #define SST49LF040B 0x0050 171 #define SST49LF008A 0x005a 172 #define SST49LF030A 0x001C 173 #define SST49LF040A 0x0051 174 #define SST49LF080A 0x005B 175 #define SST36VF3203 0x7354 176 177 /* Toshiba */ 178 #define TC58FVT160 0x00C2 179 #define TC58FVB160 0x0043 180 #define TC58FVT321 0x009A 181 #define TC58FVB321 0x009C 182 #define TC58FVT641 0x0093 183 #define TC58FVB641 0x0095 184 185 /* Winbond */ 186 #define W49V002A 0x00b0 187 188 189 /* 190 * Unlock address sets for AMD command sets. 191 * Intel command sets use the MTD_UADDR_UNNECESSARY. 192 * Each identifier, except MTD_UADDR_UNNECESSARY, and 193 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. 194 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure 195 * initialization need not require initializing all of the 196 * unlock addresses for all bit widths. 197 */ 198 enum uaddr { 199 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ 200 MTD_UADDR_0x0555_0x02AA, 201 MTD_UADDR_0x0555_0x0AAA, 202 MTD_UADDR_0x5555_0x2AAA, 203 MTD_UADDR_0x0AAA_0x0555, 204 MTD_UADDR_0xAAAA_0x5555, 205 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ 206 MTD_UADDR_UNNECESSARY, /* Does not require any address */ 207 }; 208 209 210 struct unlock_addr { 211 uint32_t addr1; 212 uint32_t addr2; 213 }; 214 215 216 /* 217 * I don't like the fact that the first entry in unlock_addrs[] 218 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, 219 * should not be used. The problem is that structures with 220 * initializers have extra fields initialized to 0. It is _very_ 221 * desireable to have the unlock address entries for unsupported 222 * data widths automatically initialized - that means that 223 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here 224 * must go unused. 225 */ 226 static const struct unlock_addr unlock_addrs[] = { 227 [MTD_UADDR_NOT_SUPPORTED] = { 228 .addr1 = 0xffff, 229 .addr2 = 0xffff 230 }, 231 232 [MTD_UADDR_0x0555_0x02AA] = { 233 .addr1 = 0x0555, 234 .addr2 = 0x02aa 235 }, 236 237 [MTD_UADDR_0x0555_0x0AAA] = { 238 .addr1 = 0x0555, 239 .addr2 = 0x0aaa 240 }, 241 242 [MTD_UADDR_0x5555_0x2AAA] = { 243 .addr1 = 0x5555, 244 .addr2 = 0x2aaa 245 }, 246 247 [MTD_UADDR_0x0AAA_0x0555] = { 248 .addr1 = 0x0AAA, 249 .addr2 = 0x0555 250 }, 251 252 [MTD_UADDR_0xAAAA_0x5555] = { 253 .addr1 = 0xaaaa, 254 .addr2 = 0x5555 255 }, 256 257 [MTD_UADDR_DONT_CARE] = { 258 .addr1 = 0x0000, /* Doesn't matter which address */ 259 .addr2 = 0x0000 /* is used - must be last entry */ 260 }, 261 262 [MTD_UADDR_UNNECESSARY] = { 263 .addr1 = 0x0000, 264 .addr2 = 0x0000 265 } 266 }; 267 268 struct amd_flash_info { 269 const char *name; 270 const uint16_t mfr_id; 271 const uint16_t dev_id; 272 const uint8_t dev_size; 273 const uint8_t nr_regions; 274 const uint16_t cmd_set; 275 const uint32_t regions[6]; 276 const uint8_t devtypes; /* Bitmask for x8, x16 etc. */ 277 const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */ 278 }; 279 280 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) 281 282 #define SIZE_64KiB 16 283 #define SIZE_128KiB 17 284 #define SIZE_256KiB 18 285 #define SIZE_512KiB 19 286 #define SIZE_1MiB 20 287 #define SIZE_2MiB 21 288 #define SIZE_4MiB 22 289 #define SIZE_8MiB 23 290 291 292 /* 293 * Please keep this list ordered by manufacturer! 294 * Fortunately, the list isn't searched often and so a 295 * slow, linear search isn't so bad. 296 */ 297 static const struct amd_flash_info jedec_table[] = { 298 { 299 .mfr_id = MANUFACTURER_AMD, 300 .dev_id = AM29F032B, 301 .name = "AMD AM29F032B", 302 .uaddr = MTD_UADDR_0x0555_0x02AA, 303 .devtypes = CFI_DEVICETYPE_X8, 304 .dev_size = SIZE_4MiB, 305 .cmd_set = P_ID_AMD_STD, 306 .nr_regions = 1, 307 .regions = { 308 ERASEINFO(0x10000,64) 309 } 310 }, { 311 .mfr_id = MANUFACTURER_AMD, 312 .dev_id = AM29LV160DT, 313 .name = "AMD AM29LV160DT", 314 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 315 .uaddr = MTD_UADDR_0x0AAA_0x0555, 316 .dev_size = SIZE_2MiB, 317 .cmd_set = P_ID_AMD_STD, 318 .nr_regions = 4, 319 .regions = { 320 ERASEINFO(0x10000,31), 321 ERASEINFO(0x08000,1), 322 ERASEINFO(0x02000,2), 323 ERASEINFO(0x04000,1) 324 } 325 }, { 326 .mfr_id = MANUFACTURER_AMD, 327 .dev_id = AM29LV160DB, 328 .name = "AMD AM29LV160DB", 329 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 330 .uaddr = MTD_UADDR_0x0AAA_0x0555, 331 .dev_size = SIZE_2MiB, 332 .cmd_set = P_ID_AMD_STD, 333 .nr_regions = 4, 334 .regions = { 335 ERASEINFO(0x04000,1), 336 ERASEINFO(0x02000,2), 337 ERASEINFO(0x08000,1), 338 ERASEINFO(0x10000,31) 339 } 340 }, { 341 .mfr_id = MANUFACTURER_AMD, 342 .dev_id = AM29LV400BB, 343 .name = "AMD AM29LV400BB", 344 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 345 .uaddr = MTD_UADDR_0x0AAA_0x0555, 346 .dev_size = SIZE_512KiB, 347 .cmd_set = P_ID_AMD_STD, 348 .nr_regions = 4, 349 .regions = { 350 ERASEINFO(0x04000,1), 351 ERASEINFO(0x02000,2), 352 ERASEINFO(0x08000,1), 353 ERASEINFO(0x10000,7) 354 } 355 }, { 356 .mfr_id = MANUFACTURER_AMD, 357 .dev_id = AM29LV400BT, 358 .name = "AMD AM29LV400BT", 359 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 360 .uaddr = MTD_UADDR_0x0AAA_0x0555, 361 .dev_size = SIZE_512KiB, 362 .cmd_set = P_ID_AMD_STD, 363 .nr_regions = 4, 364 .regions = { 365 ERASEINFO(0x10000,7), 366 ERASEINFO(0x08000,1), 367 ERASEINFO(0x02000,2), 368 ERASEINFO(0x04000,1) 369 } 370 }, { 371 .mfr_id = MANUFACTURER_AMD, 372 .dev_id = AM29LV800BB, 373 .name = "AMD AM29LV800BB", 374 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 375 .uaddr = MTD_UADDR_0x0AAA_0x0555, 376 .dev_size = SIZE_1MiB, 377 .cmd_set = P_ID_AMD_STD, 378 .nr_regions = 4, 379 .regions = { 380 ERASEINFO(0x04000,1), 381 ERASEINFO(0x02000,2), 382 ERASEINFO(0x08000,1), 383 ERASEINFO(0x10000,15), 384 } 385 }, { 386 /* add DL */ 387 .mfr_id = MANUFACTURER_AMD, 388 .dev_id = AM29DL800BB, 389 .name = "AMD AM29DL800BB", 390 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 391 .uaddr = MTD_UADDR_0x0AAA_0x0555, 392 .dev_size = SIZE_1MiB, 393 .cmd_set = P_ID_AMD_STD, 394 .nr_regions = 6, 395 .regions = { 396 ERASEINFO(0x04000,1), 397 ERASEINFO(0x08000,1), 398 ERASEINFO(0x02000,4), 399 ERASEINFO(0x08000,1), 400 ERASEINFO(0x04000,1), 401 ERASEINFO(0x10000,14) 402 } 403 }, { 404 .mfr_id = MANUFACTURER_AMD, 405 .dev_id = AM29DL800BT, 406 .name = "AMD AM29DL800BT", 407 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 408 .uaddr = MTD_UADDR_0x0AAA_0x0555, 409 .dev_size = SIZE_1MiB, 410 .cmd_set = P_ID_AMD_STD, 411 .nr_regions = 6, 412 .regions = { 413 ERASEINFO(0x10000,14), 414 ERASEINFO(0x04000,1), 415 ERASEINFO(0x08000,1), 416 ERASEINFO(0x02000,4), 417 ERASEINFO(0x08000,1), 418 ERASEINFO(0x04000,1) 419 } 420 }, { 421 .mfr_id = MANUFACTURER_AMD, 422 .dev_id = AM29F800BB, 423 .name = "AMD AM29F800BB", 424 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 425 .uaddr = MTD_UADDR_0x0AAA_0x0555, 426 .dev_size = SIZE_1MiB, 427 .cmd_set = P_ID_AMD_STD, 428 .nr_regions = 4, 429 .regions = { 430 ERASEINFO(0x04000,1), 431 ERASEINFO(0x02000,2), 432 ERASEINFO(0x08000,1), 433 ERASEINFO(0x10000,15), 434 } 435 }, { 436 .mfr_id = MANUFACTURER_AMD, 437 .dev_id = AM29LV800BT, 438 .name = "AMD AM29LV800BT", 439 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 440 .uaddr = MTD_UADDR_0x0AAA_0x0555, 441 .dev_size = SIZE_1MiB, 442 .cmd_set = P_ID_AMD_STD, 443 .nr_regions = 4, 444 .regions = { 445 ERASEINFO(0x10000,15), 446 ERASEINFO(0x08000,1), 447 ERASEINFO(0x02000,2), 448 ERASEINFO(0x04000,1) 449 } 450 }, { 451 .mfr_id = MANUFACTURER_AMD, 452 .dev_id = AM29F800BT, 453 .name = "AMD AM29F800BT", 454 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 455 .uaddr = MTD_UADDR_0x0AAA_0x0555, 456 .dev_size = SIZE_1MiB, 457 .cmd_set = P_ID_AMD_STD, 458 .nr_regions = 4, 459 .regions = { 460 ERASEINFO(0x10000,15), 461 ERASEINFO(0x08000,1), 462 ERASEINFO(0x02000,2), 463 ERASEINFO(0x04000,1) 464 } 465 }, { 466 .mfr_id = MANUFACTURER_AMD, 467 .dev_id = AM29F017D, 468 .name = "AMD AM29F017D", 469 .devtypes = CFI_DEVICETYPE_X8, 470 .uaddr = MTD_UADDR_DONT_CARE, 471 .dev_size = SIZE_2MiB, 472 .cmd_set = P_ID_AMD_STD, 473 .nr_regions = 1, 474 .regions = { 475 ERASEINFO(0x10000,32), 476 } 477 }, { 478 .mfr_id = MANUFACTURER_AMD, 479 .dev_id = AM29F016D, 480 .name = "AMD AM29F016D", 481 .devtypes = CFI_DEVICETYPE_X8, 482 .uaddr = MTD_UADDR_0x0555_0x02AA, 483 .dev_size = SIZE_2MiB, 484 .cmd_set = P_ID_AMD_STD, 485 .nr_regions = 1, 486 .regions = { 487 ERASEINFO(0x10000,32), 488 } 489 }, { 490 .mfr_id = MANUFACTURER_AMD, 491 .dev_id = AM29F080, 492 .name = "AMD AM29F080", 493 .devtypes = CFI_DEVICETYPE_X8, 494 .uaddr = MTD_UADDR_0x0555_0x02AA, 495 .dev_size = SIZE_1MiB, 496 .cmd_set = P_ID_AMD_STD, 497 .nr_regions = 1, 498 .regions = { 499 ERASEINFO(0x10000,16), 500 } 501 }, { 502 .mfr_id = MANUFACTURER_AMD, 503 .dev_id = AM29F040, 504 .name = "AMD AM29F040", 505 .devtypes = CFI_DEVICETYPE_X8, 506 .uaddr = MTD_UADDR_0x0555_0x02AA, 507 .dev_size = SIZE_512KiB, 508 .cmd_set = P_ID_AMD_STD, 509 .nr_regions = 1, 510 .regions = { 511 ERASEINFO(0x10000,8), 512 } 513 }, { 514 .mfr_id = MANUFACTURER_AMD, 515 .dev_id = AM29LV040B, 516 .name = "AMD AM29LV040B", 517 .devtypes = CFI_DEVICETYPE_X8, 518 .uaddr = MTD_UADDR_0x0555_0x02AA, 519 .dev_size = SIZE_512KiB, 520 .cmd_set = P_ID_AMD_STD, 521 .nr_regions = 1, 522 .regions = { 523 ERASEINFO(0x10000,8), 524 } 525 }, { 526 .mfr_id = MANUFACTURER_AMD, 527 .dev_id = AM29F002T, 528 .name = "AMD AM29F002T", 529 .devtypes = CFI_DEVICETYPE_X8, 530 .uaddr = MTD_UADDR_0x0555_0x02AA, 531 .dev_size = SIZE_256KiB, 532 .cmd_set = P_ID_AMD_STD, 533 .nr_regions = 4, 534 .regions = { 535 ERASEINFO(0x10000,3), 536 ERASEINFO(0x08000,1), 537 ERASEINFO(0x02000,2), 538 ERASEINFO(0x04000,1), 539 } 540 }, { 541 .mfr_id = MANUFACTURER_AMD, 542 .dev_id = AM29SL800DT, 543 .name = "AMD AM29SL800DT", 544 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 545 .uaddr = MTD_UADDR_0x0AAA_0x0555, 546 .dev_size = SIZE_1MiB, 547 .cmd_set = P_ID_AMD_STD, 548 .nr_regions = 4, 549 .regions = { 550 ERASEINFO(0x10000,15), 551 ERASEINFO(0x08000,1), 552 ERASEINFO(0x02000,2), 553 ERASEINFO(0x04000,1), 554 } 555 }, { 556 .mfr_id = MANUFACTURER_AMD, 557 .dev_id = AM29SL800DB, 558 .name = "AMD AM29SL800DB", 559 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 560 .uaddr = MTD_UADDR_0x0AAA_0x0555, 561 .dev_size = SIZE_1MiB, 562 .cmd_set = P_ID_AMD_STD, 563 .nr_regions = 4, 564 .regions = { 565 ERASEINFO(0x04000,1), 566 ERASEINFO(0x02000,2), 567 ERASEINFO(0x08000,1), 568 ERASEINFO(0x10000,15), 569 } 570 }, { 571 .mfr_id = MANUFACTURER_ATMEL, 572 .dev_id = AT49BV512, 573 .name = "Atmel AT49BV512", 574 .devtypes = CFI_DEVICETYPE_X8, 575 .uaddr = MTD_UADDR_0x5555_0x2AAA, 576 .dev_size = SIZE_64KiB, 577 .cmd_set = P_ID_AMD_STD, 578 .nr_regions = 1, 579 .regions = { 580 ERASEINFO(0x10000,1) 581 } 582 }, { 583 .mfr_id = MANUFACTURER_ATMEL, 584 .dev_id = AT29LV512, 585 .name = "Atmel AT29LV512", 586 .devtypes = CFI_DEVICETYPE_X8, 587 .uaddr = MTD_UADDR_0x5555_0x2AAA, 588 .dev_size = SIZE_64KiB, 589 .cmd_set = P_ID_AMD_STD, 590 .nr_regions = 1, 591 .regions = { 592 ERASEINFO(0x80,256), 593 ERASEINFO(0x80,256) 594 } 595 }, { 596 .mfr_id = MANUFACTURER_ATMEL, 597 .dev_id = AT49BV16X, 598 .name = "Atmel AT49BV16X", 599 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 600 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 601 .dev_size = SIZE_2MiB, 602 .cmd_set = P_ID_AMD_STD, 603 .nr_regions = 2, 604 .regions = { 605 ERASEINFO(0x02000,8), 606 ERASEINFO(0x10000,31) 607 } 608 }, { 609 .mfr_id = MANUFACTURER_ATMEL, 610 .dev_id = AT49BV16XT, 611 .name = "Atmel AT49BV16XT", 612 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 613 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 614 .dev_size = SIZE_2MiB, 615 .cmd_set = P_ID_AMD_STD, 616 .nr_regions = 2, 617 .regions = { 618 ERASEINFO(0x10000,31), 619 ERASEINFO(0x02000,8) 620 } 621 }, { 622 .mfr_id = MANUFACTURER_ATMEL, 623 .dev_id = AT49BV32X, 624 .name = "Atmel AT49BV32X", 625 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 626 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 627 .dev_size = SIZE_4MiB, 628 .cmd_set = P_ID_AMD_STD, 629 .nr_regions = 2, 630 .regions = { 631 ERASEINFO(0x02000,8), 632 ERASEINFO(0x10000,63) 633 } 634 }, { 635 .mfr_id = MANUFACTURER_ATMEL, 636 .dev_id = AT49BV32XT, 637 .name = "Atmel AT49BV32XT", 638 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 639 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 640 .dev_size = SIZE_4MiB, 641 .cmd_set = P_ID_AMD_STD, 642 .nr_regions = 2, 643 .regions = { 644 ERASEINFO(0x10000,63), 645 ERASEINFO(0x02000,8) 646 } 647 }, { 648 .mfr_id = MANUFACTURER_EON, 649 .dev_id = EN29SL800BT, 650 .name = "Eon EN29SL800BT", 651 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 652 .uaddr = MTD_UADDR_0x0AAA_0x0555, 653 .dev_size = SIZE_1MiB, 654 .cmd_set = P_ID_AMD_STD, 655 .nr_regions = 4, 656 .regions = { 657 ERASEINFO(0x10000,15), 658 ERASEINFO(0x08000,1), 659 ERASEINFO(0x02000,2), 660 ERASEINFO(0x04000,1), 661 } 662 }, { 663 .mfr_id = MANUFACTURER_EON, 664 .dev_id = EN29SL800BB, 665 .name = "Eon EN29SL800BB", 666 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 667 .uaddr = MTD_UADDR_0x0AAA_0x0555, 668 .dev_size = SIZE_1MiB, 669 .cmd_set = P_ID_AMD_STD, 670 .nr_regions = 4, 671 .regions = { 672 ERASEINFO(0x04000,1), 673 ERASEINFO(0x02000,2), 674 ERASEINFO(0x08000,1), 675 ERASEINFO(0x10000,15), 676 } 677 }, { 678 .mfr_id = MANUFACTURER_FUJITSU, 679 .dev_id = MBM29F040C, 680 .name = "Fujitsu MBM29F040C", 681 .devtypes = CFI_DEVICETYPE_X8, 682 .uaddr = MTD_UADDR_0x0AAA_0x0555, 683 .dev_size = SIZE_512KiB, 684 .cmd_set = P_ID_AMD_STD, 685 .nr_regions = 1, 686 .regions = { 687 ERASEINFO(0x10000,8) 688 } 689 }, { 690 .mfr_id = MANUFACTURER_FUJITSU, 691 .dev_id = MBM29F800BA, 692 .name = "Fujitsu MBM29F800BA", 693 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 694 .uaddr = MTD_UADDR_0x0AAA_0x0555, 695 .dev_size = SIZE_1MiB, 696 .cmd_set = P_ID_AMD_STD, 697 .nr_regions = 4, 698 .regions = { 699 ERASEINFO(0x04000,1), 700 ERASEINFO(0x02000,2), 701 ERASEINFO(0x08000,1), 702 ERASEINFO(0x10000,15), 703 } 704 }, { 705 .mfr_id = MANUFACTURER_FUJITSU, 706 .dev_id = MBM29LV650UE, 707 .name = "Fujitsu MBM29LV650UE", 708 .devtypes = CFI_DEVICETYPE_X8, 709 .uaddr = MTD_UADDR_DONT_CARE, 710 .dev_size = SIZE_8MiB, 711 .cmd_set = P_ID_AMD_STD, 712 .nr_regions = 1, 713 .regions = { 714 ERASEINFO(0x10000,128) 715 } 716 }, { 717 .mfr_id = MANUFACTURER_FUJITSU, 718 .dev_id = MBM29LV320TE, 719 .name = "Fujitsu MBM29LV320TE", 720 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 721 .uaddr = MTD_UADDR_0x0AAA_0x0555, 722 .dev_size = SIZE_4MiB, 723 .cmd_set = P_ID_AMD_STD, 724 .nr_regions = 2, 725 .regions = { 726 ERASEINFO(0x10000,63), 727 ERASEINFO(0x02000,8) 728 } 729 }, { 730 .mfr_id = MANUFACTURER_FUJITSU, 731 .dev_id = MBM29LV320BE, 732 .name = "Fujitsu MBM29LV320BE", 733 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 734 .uaddr = MTD_UADDR_0x0AAA_0x0555, 735 .dev_size = SIZE_4MiB, 736 .cmd_set = P_ID_AMD_STD, 737 .nr_regions = 2, 738 .regions = { 739 ERASEINFO(0x02000,8), 740 ERASEINFO(0x10000,63) 741 } 742 }, { 743 .mfr_id = MANUFACTURER_FUJITSU, 744 .dev_id = MBM29LV160TE, 745 .name = "Fujitsu MBM29LV160TE", 746 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 747 .uaddr = MTD_UADDR_0x0AAA_0x0555, 748 .dev_size = SIZE_2MiB, 749 .cmd_set = P_ID_AMD_STD, 750 .nr_regions = 4, 751 .regions = { 752 ERASEINFO(0x10000,31), 753 ERASEINFO(0x08000,1), 754 ERASEINFO(0x02000,2), 755 ERASEINFO(0x04000,1) 756 } 757 }, { 758 .mfr_id = MANUFACTURER_FUJITSU, 759 .dev_id = MBM29LV160BE, 760 .name = "Fujitsu MBM29LV160BE", 761 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 762 .uaddr = MTD_UADDR_0x0AAA_0x0555, 763 .dev_size = SIZE_2MiB, 764 .cmd_set = P_ID_AMD_STD, 765 .nr_regions = 4, 766 .regions = { 767 ERASEINFO(0x04000,1), 768 ERASEINFO(0x02000,2), 769 ERASEINFO(0x08000,1), 770 ERASEINFO(0x10000,31) 771 } 772 }, { 773 .mfr_id = MANUFACTURER_FUJITSU, 774 .dev_id = MBM29LV800BA, 775 .name = "Fujitsu MBM29LV800BA", 776 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 777 .uaddr = MTD_UADDR_0x0AAA_0x0555, 778 .dev_size = SIZE_1MiB, 779 .cmd_set = P_ID_AMD_STD, 780 .nr_regions = 4, 781 .regions = { 782 ERASEINFO(0x04000,1), 783 ERASEINFO(0x02000,2), 784 ERASEINFO(0x08000,1), 785 ERASEINFO(0x10000,15) 786 } 787 }, { 788 .mfr_id = MANUFACTURER_FUJITSU, 789 .dev_id = MBM29LV800TA, 790 .name = "Fujitsu MBM29LV800TA", 791 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 792 .uaddr = MTD_UADDR_0x0AAA_0x0555, 793 .dev_size = SIZE_1MiB, 794 .cmd_set = P_ID_AMD_STD, 795 .nr_regions = 4, 796 .regions = { 797 ERASEINFO(0x10000,15), 798 ERASEINFO(0x08000,1), 799 ERASEINFO(0x02000,2), 800 ERASEINFO(0x04000,1) 801 } 802 }, { 803 .mfr_id = MANUFACTURER_FUJITSU, 804 .dev_id = MBM29LV400BC, 805 .name = "Fujitsu MBM29LV400BC", 806 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 807 .uaddr = MTD_UADDR_0x0AAA_0x0555, 808 .dev_size = SIZE_512KiB, 809 .cmd_set = P_ID_AMD_STD, 810 .nr_regions = 4, 811 .regions = { 812 ERASEINFO(0x04000,1), 813 ERASEINFO(0x02000,2), 814 ERASEINFO(0x08000,1), 815 ERASEINFO(0x10000,7) 816 } 817 }, { 818 .mfr_id = MANUFACTURER_FUJITSU, 819 .dev_id = MBM29LV400TC, 820 .name = "Fujitsu MBM29LV400TC", 821 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 822 .uaddr = MTD_UADDR_0x0AAA_0x0555, 823 .dev_size = SIZE_512KiB, 824 .cmd_set = P_ID_AMD_STD, 825 .nr_regions = 4, 826 .regions = { 827 ERASEINFO(0x10000,7), 828 ERASEINFO(0x08000,1), 829 ERASEINFO(0x02000,2), 830 ERASEINFO(0x04000,1) 831 } 832 }, { 833 .mfr_id = MANUFACTURER_HYUNDAI, 834 .dev_id = HY29F002T, 835 .name = "Hyundai HY29F002T", 836 .devtypes = CFI_DEVICETYPE_X8, 837 .uaddr = MTD_UADDR_0x0555_0x02AA, 838 .dev_size = SIZE_256KiB, 839 .cmd_set = P_ID_AMD_STD, 840 .nr_regions = 4, 841 .regions = { 842 ERASEINFO(0x10000,3), 843 ERASEINFO(0x08000,1), 844 ERASEINFO(0x02000,2), 845 ERASEINFO(0x04000,1), 846 } 847 }, { 848 .mfr_id = MANUFACTURER_INTEL, 849 .dev_id = I28F004B3B, 850 .name = "Intel 28F004B3B", 851 .devtypes = CFI_DEVICETYPE_X8, 852 .uaddr = MTD_UADDR_UNNECESSARY, 853 .dev_size = SIZE_512KiB, 854 .cmd_set = P_ID_INTEL_STD, 855 .nr_regions = 2, 856 .regions = { 857 ERASEINFO(0x02000, 8), 858 ERASEINFO(0x10000, 7), 859 } 860 }, { 861 .mfr_id = MANUFACTURER_INTEL, 862 .dev_id = I28F004B3T, 863 .name = "Intel 28F004B3T", 864 .devtypes = CFI_DEVICETYPE_X8, 865 .uaddr = MTD_UADDR_UNNECESSARY, 866 .dev_size = SIZE_512KiB, 867 .cmd_set = P_ID_INTEL_STD, 868 .nr_regions = 2, 869 .regions = { 870 ERASEINFO(0x10000, 7), 871 ERASEINFO(0x02000, 8), 872 } 873 }, { 874 .mfr_id = MANUFACTURER_INTEL, 875 .dev_id = I28F400B3B, 876 .name = "Intel 28F400B3B", 877 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 878 .uaddr = MTD_UADDR_UNNECESSARY, 879 .dev_size = SIZE_512KiB, 880 .cmd_set = P_ID_INTEL_STD, 881 .nr_regions = 2, 882 .regions = { 883 ERASEINFO(0x02000, 8), 884 ERASEINFO(0x10000, 7), 885 } 886 }, { 887 .mfr_id = MANUFACTURER_INTEL, 888 .dev_id = I28F400B3T, 889 .name = "Intel 28F400B3T", 890 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 891 .uaddr = MTD_UADDR_UNNECESSARY, 892 .dev_size = SIZE_512KiB, 893 .cmd_set = P_ID_INTEL_STD, 894 .nr_regions = 2, 895 .regions = { 896 ERASEINFO(0x10000, 7), 897 ERASEINFO(0x02000, 8), 898 } 899 }, { 900 .mfr_id = MANUFACTURER_INTEL, 901 .dev_id = I28F008B3B, 902 .name = "Intel 28F008B3B", 903 .devtypes = CFI_DEVICETYPE_X8, 904 .uaddr = MTD_UADDR_UNNECESSARY, 905 .dev_size = SIZE_1MiB, 906 .cmd_set = P_ID_INTEL_STD, 907 .nr_regions = 2, 908 .regions = { 909 ERASEINFO(0x02000, 8), 910 ERASEINFO(0x10000, 15), 911 } 912 }, { 913 .mfr_id = MANUFACTURER_INTEL, 914 .dev_id = I28F008B3T, 915 .name = "Intel 28F008B3T", 916 .devtypes = CFI_DEVICETYPE_X8, 917 .uaddr = MTD_UADDR_UNNECESSARY, 918 .dev_size = SIZE_1MiB, 919 .cmd_set = P_ID_INTEL_STD, 920 .nr_regions = 2, 921 .regions = { 922 ERASEINFO(0x10000, 15), 923 ERASEINFO(0x02000, 8), 924 } 925 }, { 926 .mfr_id = MANUFACTURER_INTEL, 927 .dev_id = I28F008S5, 928 .name = "Intel 28F008S5", 929 .devtypes = CFI_DEVICETYPE_X8, 930 .uaddr = MTD_UADDR_UNNECESSARY, 931 .dev_size = SIZE_1MiB, 932 .cmd_set = P_ID_INTEL_EXT, 933 .nr_regions = 1, 934 .regions = { 935 ERASEINFO(0x10000,16), 936 } 937 }, { 938 .mfr_id = MANUFACTURER_INTEL, 939 .dev_id = I28F016S5, 940 .name = "Intel 28F016S5", 941 .devtypes = CFI_DEVICETYPE_X8, 942 .uaddr = MTD_UADDR_UNNECESSARY, 943 .dev_size = SIZE_2MiB, 944 .cmd_set = P_ID_INTEL_EXT, 945 .nr_regions = 1, 946 .regions = { 947 ERASEINFO(0x10000,32), 948 } 949 }, { 950 .mfr_id = MANUFACTURER_INTEL, 951 .dev_id = I28F008SA, 952 .name = "Intel 28F008SA", 953 .devtypes = CFI_DEVICETYPE_X8, 954 .uaddr = MTD_UADDR_UNNECESSARY, 955 .dev_size = SIZE_1MiB, 956 .cmd_set = P_ID_INTEL_STD, 957 .nr_regions = 1, 958 .regions = { 959 ERASEINFO(0x10000, 16), 960 } 961 }, { 962 .mfr_id = MANUFACTURER_INTEL, 963 .dev_id = I28F800B3B, 964 .name = "Intel 28F800B3B", 965 .devtypes = CFI_DEVICETYPE_X16, 966 .uaddr = MTD_UADDR_UNNECESSARY, 967 .dev_size = SIZE_1MiB, 968 .cmd_set = P_ID_INTEL_STD, 969 .nr_regions = 2, 970 .regions = { 971 ERASEINFO(0x02000, 8), 972 ERASEINFO(0x10000, 15), 973 } 974 }, { 975 .mfr_id = MANUFACTURER_INTEL, 976 .dev_id = I28F800B3T, 977 .name = "Intel 28F800B3T", 978 .devtypes = CFI_DEVICETYPE_X16, 979 .uaddr = MTD_UADDR_UNNECESSARY, 980 .dev_size = SIZE_1MiB, 981 .cmd_set = P_ID_INTEL_STD, 982 .nr_regions = 2, 983 .regions = { 984 ERASEINFO(0x10000, 15), 985 ERASEINFO(0x02000, 8), 986 } 987 }, { 988 .mfr_id = MANUFACTURER_INTEL, 989 .dev_id = I28F016B3B, 990 .name = "Intel 28F016B3B", 991 .devtypes = CFI_DEVICETYPE_X8, 992 .uaddr = MTD_UADDR_UNNECESSARY, 993 .dev_size = SIZE_2MiB, 994 .cmd_set = P_ID_INTEL_STD, 995 .nr_regions = 2, 996 .regions = { 997 ERASEINFO(0x02000, 8), 998 ERASEINFO(0x10000, 31), 999 } 1000 }, { 1001 .mfr_id = MANUFACTURER_INTEL, 1002 .dev_id = I28F016S3, 1003 .name = "Intel I28F016S3", 1004 .devtypes = CFI_DEVICETYPE_X8, 1005 .uaddr = MTD_UADDR_UNNECESSARY, 1006 .dev_size = SIZE_2MiB, 1007 .cmd_set = P_ID_INTEL_STD, 1008 .nr_regions = 1, 1009 .regions = { 1010 ERASEINFO(0x10000, 32), 1011 } 1012 }, { 1013 .mfr_id = MANUFACTURER_INTEL, 1014 .dev_id = I28F016B3T, 1015 .name = "Intel 28F016B3T", 1016 .devtypes = CFI_DEVICETYPE_X8, 1017 .uaddr = MTD_UADDR_UNNECESSARY, 1018 .dev_size = SIZE_2MiB, 1019 .cmd_set = P_ID_INTEL_STD, 1020 .nr_regions = 2, 1021 .regions = { 1022 ERASEINFO(0x10000, 31), 1023 ERASEINFO(0x02000, 8), 1024 } 1025 }, { 1026 .mfr_id = MANUFACTURER_INTEL, 1027 .dev_id = I28F160B3B, 1028 .name = "Intel 28F160B3B", 1029 .devtypes = CFI_DEVICETYPE_X16, 1030 .uaddr = MTD_UADDR_UNNECESSARY, 1031 .dev_size = SIZE_2MiB, 1032 .cmd_set = P_ID_INTEL_STD, 1033 .nr_regions = 2, 1034 .regions = { 1035 ERASEINFO(0x02000, 8), 1036 ERASEINFO(0x10000, 31), 1037 } 1038 }, { 1039 .mfr_id = MANUFACTURER_INTEL, 1040 .dev_id = I28F160B3T, 1041 .name = "Intel 28F160B3T", 1042 .devtypes = CFI_DEVICETYPE_X16, 1043 .uaddr = MTD_UADDR_UNNECESSARY, 1044 .dev_size = SIZE_2MiB, 1045 .cmd_set = P_ID_INTEL_STD, 1046 .nr_regions = 2, 1047 .regions = { 1048 ERASEINFO(0x10000, 31), 1049 ERASEINFO(0x02000, 8), 1050 } 1051 }, { 1052 .mfr_id = MANUFACTURER_INTEL, 1053 .dev_id = I28F320B3B, 1054 .name = "Intel 28F320B3B", 1055 .devtypes = CFI_DEVICETYPE_X16, 1056 .uaddr = MTD_UADDR_UNNECESSARY, 1057 .dev_size = SIZE_4MiB, 1058 .cmd_set = P_ID_INTEL_STD, 1059 .nr_regions = 2, 1060 .regions = { 1061 ERASEINFO(0x02000, 8), 1062 ERASEINFO(0x10000, 63), 1063 } 1064 }, { 1065 .mfr_id = MANUFACTURER_INTEL, 1066 .dev_id = I28F320B3T, 1067 .name = "Intel 28F320B3T", 1068 .devtypes = CFI_DEVICETYPE_X16, 1069 .uaddr = MTD_UADDR_UNNECESSARY, 1070 .dev_size = SIZE_4MiB, 1071 .cmd_set = P_ID_INTEL_STD, 1072 .nr_regions = 2, 1073 .regions = { 1074 ERASEINFO(0x10000, 63), 1075 ERASEINFO(0x02000, 8), 1076 } 1077 }, { 1078 .mfr_id = MANUFACTURER_INTEL, 1079 .dev_id = I28F640B3B, 1080 .name = "Intel 28F640B3B", 1081 .devtypes = CFI_DEVICETYPE_X16, 1082 .uaddr = MTD_UADDR_UNNECESSARY, 1083 .dev_size = SIZE_8MiB, 1084 .cmd_set = P_ID_INTEL_STD, 1085 .nr_regions = 2, 1086 .regions = { 1087 ERASEINFO(0x02000, 8), 1088 ERASEINFO(0x10000, 127), 1089 } 1090 }, { 1091 .mfr_id = MANUFACTURER_INTEL, 1092 .dev_id = I28F640B3T, 1093 .name = "Intel 28F640B3T", 1094 .devtypes = CFI_DEVICETYPE_X16, 1095 .uaddr = MTD_UADDR_UNNECESSARY, 1096 .dev_size = SIZE_8MiB, 1097 .cmd_set = P_ID_INTEL_STD, 1098 .nr_regions = 2, 1099 .regions = { 1100 ERASEINFO(0x10000, 127), 1101 ERASEINFO(0x02000, 8), 1102 } 1103 }, { 1104 .mfr_id = MANUFACTURER_INTEL, 1105 .dev_id = I82802AB, 1106 .name = "Intel 82802AB", 1107 .devtypes = CFI_DEVICETYPE_X8, 1108 .uaddr = MTD_UADDR_UNNECESSARY, 1109 .dev_size = SIZE_512KiB, 1110 .cmd_set = P_ID_INTEL_EXT, 1111 .nr_regions = 1, 1112 .regions = { 1113 ERASEINFO(0x10000,8), 1114 } 1115 }, { 1116 .mfr_id = MANUFACTURER_INTEL, 1117 .dev_id = I82802AC, 1118 .name = "Intel 82802AC", 1119 .devtypes = CFI_DEVICETYPE_X8, 1120 .uaddr = MTD_UADDR_UNNECESSARY, 1121 .dev_size = SIZE_1MiB, 1122 .cmd_set = P_ID_INTEL_EXT, 1123 .nr_regions = 1, 1124 .regions = { 1125 ERASEINFO(0x10000,16), 1126 } 1127 }, { 1128 .mfr_id = MANUFACTURER_MACRONIX, 1129 .dev_id = MX29LV040C, 1130 .name = "Macronix MX29LV040C", 1131 .devtypes = CFI_DEVICETYPE_X8, 1132 .uaddr = MTD_UADDR_0x0555_0x02AA, 1133 .dev_size = SIZE_512KiB, 1134 .cmd_set = P_ID_AMD_STD, 1135 .nr_regions = 1, 1136 .regions = { 1137 ERASEINFO(0x10000,8), 1138 } 1139 }, { 1140 .mfr_id = MANUFACTURER_MACRONIX, 1141 .dev_id = MX29LV160T, 1142 .name = "MXIC MX29LV160T", 1143 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1144 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1145 .dev_size = SIZE_2MiB, 1146 .cmd_set = P_ID_AMD_STD, 1147 .nr_regions = 4, 1148 .regions = { 1149 ERASEINFO(0x10000,31), 1150 ERASEINFO(0x08000,1), 1151 ERASEINFO(0x02000,2), 1152 ERASEINFO(0x04000,1) 1153 } 1154 }, { 1155 .mfr_id = MANUFACTURER_NEC, 1156 .dev_id = UPD29F064115, 1157 .name = "NEC uPD29F064115", 1158 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1159 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1160 .dev_size = SIZE_8MiB, 1161 .cmd_set = P_ID_AMD_STD, 1162 .nr_regions = 3, 1163 .regions = { 1164 ERASEINFO(0x2000,8), 1165 ERASEINFO(0x10000,126), 1166 ERASEINFO(0x2000,8), 1167 } 1168 }, { 1169 .mfr_id = MANUFACTURER_MACRONIX, 1170 .dev_id = MX29LV160B, 1171 .name = "MXIC MX29LV160B", 1172 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1173 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1174 .dev_size = SIZE_2MiB, 1175 .cmd_set = P_ID_AMD_STD, 1176 .nr_regions = 4, 1177 .regions = { 1178 ERASEINFO(0x04000,1), 1179 ERASEINFO(0x02000,2), 1180 ERASEINFO(0x08000,1), 1181 ERASEINFO(0x10000,31) 1182 } 1183 }, { 1184 .mfr_id = MANUFACTURER_MACRONIX, 1185 .dev_id = MX29F040, 1186 .name = "Macronix MX29F040", 1187 .devtypes = CFI_DEVICETYPE_X8, 1188 .uaddr = MTD_UADDR_0x0555_0x02AA, 1189 .dev_size = SIZE_512KiB, 1190 .cmd_set = P_ID_AMD_STD, 1191 .nr_regions = 1, 1192 .regions = { 1193 ERASEINFO(0x10000,8), 1194 } 1195 }, { 1196 .mfr_id = MANUFACTURER_MACRONIX, 1197 .dev_id = MX29F016, 1198 .name = "Macronix MX29F016", 1199 .devtypes = CFI_DEVICETYPE_X8, 1200 .uaddr = MTD_UADDR_0x0555_0x02AA, 1201 .dev_size = SIZE_2MiB, 1202 .cmd_set = P_ID_AMD_STD, 1203 .nr_regions = 1, 1204 .regions = { 1205 ERASEINFO(0x10000,32), 1206 } 1207 }, { 1208 .mfr_id = MANUFACTURER_MACRONIX, 1209 .dev_id = MX29F004T, 1210 .name = "Macronix MX29F004T", 1211 .devtypes = CFI_DEVICETYPE_X8, 1212 .uaddr = MTD_UADDR_0x0555_0x02AA, 1213 .dev_size = SIZE_512KiB, 1214 .cmd_set = P_ID_AMD_STD, 1215 .nr_regions = 4, 1216 .regions = { 1217 ERASEINFO(0x10000,7), 1218 ERASEINFO(0x08000,1), 1219 ERASEINFO(0x02000,2), 1220 ERASEINFO(0x04000,1), 1221 } 1222 }, { 1223 .mfr_id = MANUFACTURER_MACRONIX, 1224 .dev_id = MX29F004B, 1225 .name = "Macronix MX29F004B", 1226 .devtypes = CFI_DEVICETYPE_X8, 1227 .uaddr = MTD_UADDR_0x0555_0x02AA, 1228 .dev_size = SIZE_512KiB, 1229 .cmd_set = P_ID_AMD_STD, 1230 .nr_regions = 4, 1231 .regions = { 1232 ERASEINFO(0x04000,1), 1233 ERASEINFO(0x02000,2), 1234 ERASEINFO(0x08000,1), 1235 ERASEINFO(0x10000,7), 1236 } 1237 }, { 1238 .mfr_id = MANUFACTURER_MACRONIX, 1239 .dev_id = MX29F002T, 1240 .name = "Macronix MX29F002T", 1241 .devtypes = CFI_DEVICETYPE_X8, 1242 .uaddr = MTD_UADDR_0x0555_0x02AA, 1243 .dev_size = SIZE_256KiB, 1244 .cmd_set = P_ID_AMD_STD, 1245 .nr_regions = 4, 1246 .regions = { 1247 ERASEINFO(0x10000,3), 1248 ERASEINFO(0x08000,1), 1249 ERASEINFO(0x02000,2), 1250 ERASEINFO(0x04000,1), 1251 } 1252 }, { 1253 .mfr_id = MANUFACTURER_PMC, 1254 .dev_id = PM49FL002, 1255 .name = "PMC Pm49FL002", 1256 .devtypes = CFI_DEVICETYPE_X8, 1257 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1258 .dev_size = SIZE_256KiB, 1259 .cmd_set = P_ID_AMD_STD, 1260 .nr_regions = 1, 1261 .regions = { 1262 ERASEINFO( 0x01000, 64 ) 1263 } 1264 }, { 1265 .mfr_id = MANUFACTURER_PMC, 1266 .dev_id = PM49FL004, 1267 .name = "PMC Pm49FL004", 1268 .devtypes = CFI_DEVICETYPE_X8, 1269 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1270 .dev_size = SIZE_512KiB, 1271 .cmd_set = P_ID_AMD_STD, 1272 .nr_regions = 1, 1273 .regions = { 1274 ERASEINFO( 0x01000, 128 ) 1275 } 1276 }, { 1277 .mfr_id = MANUFACTURER_PMC, 1278 .dev_id = PM49FL008, 1279 .name = "PMC Pm49FL008", 1280 .devtypes = CFI_DEVICETYPE_X8, 1281 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1282 .dev_size = SIZE_1MiB, 1283 .cmd_set = P_ID_AMD_STD, 1284 .nr_regions = 1, 1285 .regions = { 1286 ERASEINFO( 0x01000, 256 ) 1287 } 1288 }, { 1289 .mfr_id = MANUFACTURER_SHARP, 1290 .dev_id = LH28F640BF, 1291 .name = "LH28F640BF", 1292 .devtypes = CFI_DEVICETYPE_X8, 1293 .uaddr = MTD_UADDR_UNNECESSARY, 1294 .dev_size = SIZE_4MiB, 1295 .cmd_set = P_ID_INTEL_STD, 1296 .nr_regions = 1, 1297 .regions = { 1298 ERASEINFO(0x40000,16), 1299 } 1300 }, { 1301 .mfr_id = MANUFACTURER_SST, 1302 .dev_id = SST39LF512, 1303 .name = "SST 39LF512", 1304 .devtypes = CFI_DEVICETYPE_X8, 1305 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1306 .dev_size = SIZE_64KiB, 1307 .cmd_set = P_ID_AMD_STD, 1308 .nr_regions = 1, 1309 .regions = { 1310 ERASEINFO(0x01000,16), 1311 } 1312 }, { 1313 .mfr_id = MANUFACTURER_SST, 1314 .dev_id = SST39LF010, 1315 .name = "SST 39LF010", 1316 .devtypes = CFI_DEVICETYPE_X8, 1317 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1318 .dev_size = SIZE_128KiB, 1319 .cmd_set = P_ID_AMD_STD, 1320 .nr_regions = 1, 1321 .regions = { 1322 ERASEINFO(0x01000,32), 1323 } 1324 }, { 1325 .mfr_id = MANUFACTURER_SST, 1326 .dev_id = SST29EE020, 1327 .name = "SST 29EE020", 1328 .devtypes = CFI_DEVICETYPE_X8, 1329 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1330 .dev_size = SIZE_256KiB, 1331 .cmd_set = P_ID_SST_PAGE, 1332 .nr_regions = 1, 1333 .regions = {ERASEINFO(0x01000,64), 1334 } 1335 }, { 1336 .mfr_id = MANUFACTURER_SST, 1337 .dev_id = SST29LE020, 1338 .name = "SST 29LE020", 1339 .devtypes = CFI_DEVICETYPE_X8, 1340 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1341 .dev_size = SIZE_256KiB, 1342 .cmd_set = P_ID_SST_PAGE, 1343 .nr_regions = 1, 1344 .regions = {ERASEINFO(0x01000,64), 1345 } 1346 }, { 1347 .mfr_id = MANUFACTURER_SST, 1348 .dev_id = SST39LF020, 1349 .name = "SST 39LF020", 1350 .devtypes = CFI_DEVICETYPE_X8, 1351 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1352 .dev_size = SIZE_256KiB, 1353 .cmd_set = P_ID_AMD_STD, 1354 .nr_regions = 1, 1355 .regions = { 1356 ERASEINFO(0x01000,64), 1357 } 1358 }, { 1359 .mfr_id = MANUFACTURER_SST, 1360 .dev_id = SST39LF040, 1361 .name = "SST 39LF040", 1362 .devtypes = CFI_DEVICETYPE_X8, 1363 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1364 .dev_size = SIZE_512KiB, 1365 .cmd_set = P_ID_AMD_STD, 1366 .nr_regions = 1, 1367 .regions = { 1368 ERASEINFO(0x01000,128), 1369 } 1370 }, { 1371 .mfr_id = MANUFACTURER_SST, 1372 .dev_id = SST39SF010A, 1373 .name = "SST 39SF010A", 1374 .devtypes = CFI_DEVICETYPE_X8, 1375 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1376 .dev_size = SIZE_128KiB, 1377 .cmd_set = P_ID_AMD_STD, 1378 .nr_regions = 1, 1379 .regions = { 1380 ERASEINFO(0x01000,32), 1381 } 1382 }, { 1383 .mfr_id = MANUFACTURER_SST, 1384 .dev_id = SST39SF020A, 1385 .name = "SST 39SF020A", 1386 .devtypes = CFI_DEVICETYPE_X8, 1387 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1388 .dev_size = SIZE_256KiB, 1389 .cmd_set = P_ID_AMD_STD, 1390 .nr_regions = 1, 1391 .regions = { 1392 ERASEINFO(0x01000,64), 1393 } 1394 }, { 1395 .mfr_id = MANUFACTURER_SST, 1396 .dev_id = SST49LF040B, 1397 .name = "SST 49LF040B", 1398 .devtypes = CFI_DEVICETYPE_X8, 1399 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1400 .dev_size = SIZE_512KiB, 1401 .cmd_set = P_ID_AMD_STD, 1402 .nr_regions = 1, 1403 .regions = { 1404 ERASEINFO(0x01000,128), 1405 } 1406 }, { 1407 1408 .mfr_id = MANUFACTURER_SST, 1409 .dev_id = SST49LF004B, 1410 .name = "SST 49LF004B", 1411 .devtypes = CFI_DEVICETYPE_X8, 1412 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1413 .dev_size = SIZE_512KiB, 1414 .cmd_set = P_ID_AMD_STD, 1415 .nr_regions = 1, 1416 .regions = { 1417 ERASEINFO(0x01000,128), 1418 } 1419 }, { 1420 .mfr_id = MANUFACTURER_SST, 1421 .dev_id = SST49LF008A, 1422 .name = "SST 49LF008A", 1423 .devtypes = CFI_DEVICETYPE_X8, 1424 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1425 .dev_size = SIZE_1MiB, 1426 .cmd_set = P_ID_AMD_STD, 1427 .nr_regions = 1, 1428 .regions = { 1429 ERASEINFO(0x01000,256), 1430 } 1431 }, { 1432 .mfr_id = MANUFACTURER_SST, 1433 .dev_id = SST49LF030A, 1434 .name = "SST 49LF030A", 1435 .devtypes = CFI_DEVICETYPE_X8, 1436 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1437 .dev_size = SIZE_512KiB, 1438 .cmd_set = P_ID_AMD_STD, 1439 .nr_regions = 1, 1440 .regions = { 1441 ERASEINFO(0x01000,96), 1442 } 1443 }, { 1444 .mfr_id = MANUFACTURER_SST, 1445 .dev_id = SST49LF040A, 1446 .name = "SST 49LF040A", 1447 .devtypes = CFI_DEVICETYPE_X8, 1448 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1449 .dev_size = SIZE_512KiB, 1450 .cmd_set = P_ID_AMD_STD, 1451 .nr_regions = 1, 1452 .regions = { 1453 ERASEINFO(0x01000,128), 1454 } 1455 }, { 1456 .mfr_id = MANUFACTURER_SST, 1457 .dev_id = SST49LF080A, 1458 .name = "SST 49LF080A", 1459 .devtypes = CFI_DEVICETYPE_X8, 1460 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1461 .dev_size = SIZE_1MiB, 1462 .cmd_set = P_ID_AMD_STD, 1463 .nr_regions = 1, 1464 .regions = { 1465 ERASEINFO(0x01000,256), 1466 } 1467 }, { 1468 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1469 .dev_id = SST39LF160, 1470 .name = "SST 39LF160", 1471 .devtypes = CFI_DEVICETYPE_X16, 1472 .uaddr = MTD_UADDR_0xAAAA_0x5555, 1473 .dev_size = SIZE_2MiB, 1474 .cmd_set = P_ID_AMD_STD, 1475 .nr_regions = 2, 1476 .regions = { 1477 ERASEINFO(0x1000,256), 1478 ERASEINFO(0x1000,256) 1479 } 1480 }, { 1481 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1482 .dev_id = SST39VF1601, 1483 .name = "SST 39VF1601", 1484 .devtypes = CFI_DEVICETYPE_X16, 1485 .uaddr = MTD_UADDR_0xAAAA_0x5555, 1486 .dev_size = SIZE_2MiB, 1487 .cmd_set = P_ID_AMD_STD, 1488 .nr_regions = 2, 1489 .regions = { 1490 ERASEINFO(0x1000,256), 1491 ERASEINFO(0x1000,256) 1492 } 1493 }, { 1494 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1495 .dev_id = SST39VF3201, 1496 .name = "SST 39VF3201", 1497 .devtypes = CFI_DEVICETYPE_X16, 1498 .uaddr = MTD_UADDR_0xAAAA_0x5555, 1499 .dev_size = SIZE_4MiB, 1500 .cmd_set = P_ID_AMD_STD, 1501 .nr_regions = 4, 1502 .regions = { 1503 ERASEINFO(0x1000,256), 1504 ERASEINFO(0x1000,256), 1505 ERASEINFO(0x1000,256), 1506 ERASEINFO(0x1000,256) 1507 } 1508 }, { 1509 .mfr_id = MANUFACTURER_SST, 1510 .dev_id = SST36VF3203, 1511 .name = "SST 36VF3203", 1512 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1513 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1514 .dev_size = SIZE_4MiB, 1515 .cmd_set = P_ID_AMD_STD, 1516 .nr_regions = 1, 1517 .regions = { 1518 ERASEINFO(0x10000,64), 1519 } 1520 }, { 1521 .mfr_id = MANUFACTURER_ST, 1522 .dev_id = M29F800AB, 1523 .name = "ST M29F800AB", 1524 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1525 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1526 .dev_size = SIZE_1MiB, 1527 .cmd_set = P_ID_AMD_STD, 1528 .nr_regions = 4, 1529 .regions = { 1530 ERASEINFO(0x04000,1), 1531 ERASEINFO(0x02000,2), 1532 ERASEINFO(0x08000,1), 1533 ERASEINFO(0x10000,15), 1534 } 1535 }, { 1536 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1537 .dev_id = M29W800DT, 1538 .name = "ST M29W800DT", 1539 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1540 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1541 .dev_size = SIZE_1MiB, 1542 .cmd_set = P_ID_AMD_STD, 1543 .nr_regions = 4, 1544 .regions = { 1545 ERASEINFO(0x10000,15), 1546 ERASEINFO(0x08000,1), 1547 ERASEINFO(0x02000,2), 1548 ERASEINFO(0x04000,1) 1549 } 1550 }, { 1551 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1552 .dev_id = M29W800DB, 1553 .name = "ST M29W800DB", 1554 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1555 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1556 .dev_size = SIZE_1MiB, 1557 .cmd_set = P_ID_AMD_STD, 1558 .nr_regions = 4, 1559 .regions = { 1560 ERASEINFO(0x04000,1), 1561 ERASEINFO(0x02000,2), 1562 ERASEINFO(0x08000,1), 1563 ERASEINFO(0x10000,15) 1564 } 1565 }, { 1566 .mfr_id = MANUFACTURER_ST, 1567 .dev_id = M29W400DT, 1568 .name = "ST M29W400DT", 1569 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1570 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1571 .dev_size = SIZE_512KiB, 1572 .cmd_set = P_ID_AMD_STD, 1573 .nr_regions = 4, 1574 .regions = { 1575 ERASEINFO(0x04000,7), 1576 ERASEINFO(0x02000,1), 1577 ERASEINFO(0x08000,2), 1578 ERASEINFO(0x10000,1) 1579 } 1580 }, { 1581 .mfr_id = MANUFACTURER_ST, 1582 .dev_id = M29W400DB, 1583 .name = "ST M29W400DB", 1584 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1585 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1586 .dev_size = SIZE_512KiB, 1587 .cmd_set = P_ID_AMD_STD, 1588 .nr_regions = 4, 1589 .regions = { 1590 ERASEINFO(0x04000,1), 1591 ERASEINFO(0x02000,2), 1592 ERASEINFO(0x08000,1), 1593 ERASEINFO(0x10000,7) 1594 } 1595 }, { 1596 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1597 .dev_id = M29W160DT, 1598 .name = "ST M29W160DT", 1599 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1600 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1601 .dev_size = SIZE_2MiB, 1602 .cmd_set = P_ID_AMD_STD, 1603 .nr_regions = 4, 1604 .regions = { 1605 ERASEINFO(0x10000,31), 1606 ERASEINFO(0x08000,1), 1607 ERASEINFO(0x02000,2), 1608 ERASEINFO(0x04000,1) 1609 } 1610 }, { 1611 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1612 .dev_id = M29W160DB, 1613 .name = "ST M29W160DB", 1614 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1615 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1616 .dev_size = SIZE_2MiB, 1617 .cmd_set = P_ID_AMD_STD, 1618 .nr_regions = 4, 1619 .regions = { 1620 ERASEINFO(0x04000,1), 1621 ERASEINFO(0x02000,2), 1622 ERASEINFO(0x08000,1), 1623 ERASEINFO(0x10000,31) 1624 } 1625 }, { 1626 .mfr_id = MANUFACTURER_ST, 1627 .dev_id = M29W040B, 1628 .name = "ST M29W040B", 1629 .devtypes = CFI_DEVICETYPE_X8, 1630 .uaddr = MTD_UADDR_0x0555_0x02AA, 1631 .dev_size = SIZE_512KiB, 1632 .cmd_set = P_ID_AMD_STD, 1633 .nr_regions = 1, 1634 .regions = { 1635 ERASEINFO(0x10000,8), 1636 } 1637 }, { 1638 .mfr_id = MANUFACTURER_ST, 1639 .dev_id = M50FW040, 1640 .name = "ST M50FW040", 1641 .devtypes = CFI_DEVICETYPE_X8, 1642 .uaddr = MTD_UADDR_UNNECESSARY, 1643 .dev_size = SIZE_512KiB, 1644 .cmd_set = P_ID_INTEL_EXT, 1645 .nr_regions = 1, 1646 .regions = { 1647 ERASEINFO(0x10000,8), 1648 } 1649 }, { 1650 .mfr_id = MANUFACTURER_ST, 1651 .dev_id = M50FW080, 1652 .name = "ST M50FW080", 1653 .devtypes = CFI_DEVICETYPE_X8, 1654 .uaddr = MTD_UADDR_UNNECESSARY, 1655 .dev_size = SIZE_1MiB, 1656 .cmd_set = P_ID_INTEL_EXT, 1657 .nr_regions = 1, 1658 .regions = { 1659 ERASEINFO(0x10000,16), 1660 } 1661 }, { 1662 .mfr_id = MANUFACTURER_ST, 1663 .dev_id = M50FW016, 1664 .name = "ST M50FW016", 1665 .devtypes = CFI_DEVICETYPE_X8, 1666 .uaddr = MTD_UADDR_UNNECESSARY, 1667 .dev_size = SIZE_2MiB, 1668 .cmd_set = P_ID_INTEL_EXT, 1669 .nr_regions = 1, 1670 .regions = { 1671 ERASEINFO(0x10000,32), 1672 } 1673 }, { 1674 .mfr_id = MANUFACTURER_ST, 1675 .dev_id = M50LPW080, 1676 .name = "ST M50LPW080", 1677 .devtypes = CFI_DEVICETYPE_X8, 1678 .uaddr = MTD_UADDR_UNNECESSARY, 1679 .dev_size = SIZE_1MiB, 1680 .cmd_set = P_ID_INTEL_EXT, 1681 .nr_regions = 1, 1682 .regions = { 1683 ERASEINFO(0x10000,16), 1684 }, 1685 }, { 1686 .mfr_id = MANUFACTURER_ST, 1687 .dev_id = M50FLW080A, 1688 .name = "ST M50FLW080A", 1689 .devtypes = CFI_DEVICETYPE_X8, 1690 .uaddr = MTD_UADDR_UNNECESSARY, 1691 .dev_size = SIZE_1MiB, 1692 .cmd_set = P_ID_INTEL_EXT, 1693 .nr_regions = 4, 1694 .regions = { 1695 ERASEINFO(0x1000,16), 1696 ERASEINFO(0x10000,13), 1697 ERASEINFO(0x1000,16), 1698 ERASEINFO(0x1000,16), 1699 } 1700 }, { 1701 .mfr_id = MANUFACTURER_ST, 1702 .dev_id = M50FLW080B, 1703 .name = "ST M50FLW080B", 1704 .devtypes = CFI_DEVICETYPE_X8, 1705 .uaddr = MTD_UADDR_UNNECESSARY, 1706 .dev_size = SIZE_1MiB, 1707 .cmd_set = P_ID_INTEL_EXT, 1708 .nr_regions = 4, 1709 .regions = { 1710 ERASEINFO(0x1000,16), 1711 ERASEINFO(0x1000,16), 1712 ERASEINFO(0x10000,13), 1713 ERASEINFO(0x1000,16), 1714 } 1715 }, { 1716 .mfr_id = MANUFACTURER_TOSHIBA, 1717 .dev_id = TC58FVT160, 1718 .name = "Toshiba TC58FVT160", 1719 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1720 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1721 .dev_size = SIZE_2MiB, 1722 .cmd_set = P_ID_AMD_STD, 1723 .nr_regions = 4, 1724 .regions = { 1725 ERASEINFO(0x10000,31), 1726 ERASEINFO(0x08000,1), 1727 ERASEINFO(0x02000,2), 1728 ERASEINFO(0x04000,1) 1729 } 1730 }, { 1731 .mfr_id = MANUFACTURER_TOSHIBA, 1732 .dev_id = TC58FVB160, 1733 .name = "Toshiba TC58FVB160", 1734 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1735 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1736 .dev_size = SIZE_2MiB, 1737 .cmd_set = P_ID_AMD_STD, 1738 .nr_regions = 4, 1739 .regions = { 1740 ERASEINFO(0x04000,1), 1741 ERASEINFO(0x02000,2), 1742 ERASEINFO(0x08000,1), 1743 ERASEINFO(0x10000,31) 1744 } 1745 }, { 1746 .mfr_id = MANUFACTURER_TOSHIBA, 1747 .dev_id = TC58FVB321, 1748 .name = "Toshiba TC58FVB321", 1749 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1750 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1751 .dev_size = SIZE_4MiB, 1752 .cmd_set = P_ID_AMD_STD, 1753 .nr_regions = 2, 1754 .regions = { 1755 ERASEINFO(0x02000,8), 1756 ERASEINFO(0x10000,63) 1757 } 1758 }, { 1759 .mfr_id = MANUFACTURER_TOSHIBA, 1760 .dev_id = TC58FVT321, 1761 .name = "Toshiba TC58FVT321", 1762 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1763 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1764 .dev_size = SIZE_4MiB, 1765 .cmd_set = P_ID_AMD_STD, 1766 .nr_regions = 2, 1767 .regions = { 1768 ERASEINFO(0x10000,63), 1769 ERASEINFO(0x02000,8) 1770 } 1771 }, { 1772 .mfr_id = MANUFACTURER_TOSHIBA, 1773 .dev_id = TC58FVB641, 1774 .name = "Toshiba TC58FVB641", 1775 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1776 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1777 .dev_size = SIZE_8MiB, 1778 .cmd_set = P_ID_AMD_STD, 1779 .nr_regions = 2, 1780 .regions = { 1781 ERASEINFO(0x02000,8), 1782 ERASEINFO(0x10000,127) 1783 } 1784 }, { 1785 .mfr_id = MANUFACTURER_TOSHIBA, 1786 .dev_id = TC58FVT641, 1787 .name = "Toshiba TC58FVT641", 1788 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1789 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1790 .dev_size = SIZE_8MiB, 1791 .cmd_set = P_ID_AMD_STD, 1792 .nr_regions = 2, 1793 .regions = { 1794 ERASEINFO(0x10000,127), 1795 ERASEINFO(0x02000,8) 1796 } 1797 }, { 1798 .mfr_id = MANUFACTURER_WINBOND, 1799 .dev_id = W49V002A, 1800 .name = "Winbond W49V002A", 1801 .devtypes = CFI_DEVICETYPE_X8, 1802 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1803 .dev_size = SIZE_256KiB, 1804 .cmd_set = P_ID_AMD_STD, 1805 .nr_regions = 4, 1806 .regions = { 1807 ERASEINFO(0x10000, 3), 1808 ERASEINFO(0x08000, 1), 1809 ERASEINFO(0x02000, 2), 1810 ERASEINFO(0x04000, 1), 1811 } 1812 } 1813 }; 1814 1815 static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, 1816 struct cfi_private *cfi) 1817 { 1818 map_word result; 1819 unsigned long mask; 1820 int bank = 0; 1821 1822 /* According to JEDEC "Standard Manufacturer's Identification Code" 1823 * (http://www.jedec.org/download/search/jep106W.pdf) 1824 * several first banks can contain 0x7f instead of actual ID 1825 */ 1826 do { 1827 uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi); 1828 mask = (1 << (cfi->device_type * 8)) - 1; 1829 result = map_read(map, base + ofs); 1830 bank++; 1831 } while ((result.x[0] & mask) == CONTINUATION_CODE); 1832 1833 return result.x[0] & mask; 1834 } 1835 1836 static inline u32 jedec_read_id(struct map_info *map, uint32_t base, 1837 struct cfi_private *cfi) 1838 { 1839 map_word result; 1840 unsigned long mask; 1841 u32 ofs = cfi_build_cmd_addr(1, map, cfi); 1842 mask = (1 << (cfi->device_type * 8)) -1; 1843 result = map_read(map, base + ofs); 1844 return result.x[0] & mask; 1845 } 1846 1847 static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi) 1848 { 1849 /* Reset */ 1850 1851 /* after checking the datasheets for SST, MACRONIX and ATMEL 1852 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset 1853 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at 1854 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips 1855 * as they will ignore the writes and dont care what address 1856 * the F0 is written to */ 1857 if (cfi->addr_unlock1) { 1858 DEBUG( MTD_DEBUG_LEVEL3, 1859 "reset unlock called %x %x \n", 1860 cfi->addr_unlock1,cfi->addr_unlock2); 1861 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1862 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1863 } 1864 1865 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1866 /* Some misdesigned Intel chips do not respond for 0xF0 for a reset, 1867 * so ensure we're in read mode. Send both the Intel and the AMD command 1868 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so 1869 * this should be safe. 1870 */ 1871 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); 1872 /* FIXME - should have reset delay before continuing */ 1873 } 1874 1875 1876 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index) 1877 { 1878 int i,num_erase_regions; 1879 uint8_t uaddr; 1880 1881 if (! (jedec_table[index].devtypes & p_cfi->device_type)) { 1882 DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n", 1883 jedec_table[index].name, 4 * (1<<p_cfi->device_type)); 1884 return 0; 1885 } 1886 1887 printk(KERN_INFO "Found: %s\n",jedec_table[index].name); 1888 1889 num_erase_regions = jedec_table[index].nr_regions; 1890 1891 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); 1892 if (!p_cfi->cfiq) { 1893 //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name); 1894 return 0; 1895 } 1896 1897 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident)); 1898 1899 p_cfi->cfiq->P_ID = jedec_table[index].cmd_set; 1900 p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions; 1901 p_cfi->cfiq->DevSize = jedec_table[index].dev_size; 1902 p_cfi->cfi_mode = CFI_MODE_JEDEC; 1903 1904 for (i=0; i<num_erase_regions; i++){ 1905 p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i]; 1906 } 1907 p_cfi->cmdset_priv = NULL; 1908 1909 /* This may be redundant for some cases, but it doesn't hurt */ 1910 p_cfi->mfr = jedec_table[index].mfr_id; 1911 p_cfi->id = jedec_table[index].dev_id; 1912 1913 uaddr = jedec_table[index].uaddr; 1914 1915 /* The table has unlock addresses in _bytes_, and we try not to let 1916 our brains explode when we see the datasheets talking about address 1917 lines numbered from A-1 to A18. The CFI table has unlock addresses 1918 in device-words according to the mode the device is connected in */ 1919 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type; 1920 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type; 1921 1922 return 1; /* ok */ 1923 } 1924 1925 1926 /* 1927 * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing 1928 * the mapped address, unlock addresses, and proper chip ID. This function 1929 * attempts to minimize errors. It is doubtfull that this probe will ever 1930 * be perfect - consequently there should be some module parameters that 1931 * could be manually specified to force the chip info. 1932 */ 1933 static inline int jedec_match( uint32_t base, 1934 struct map_info *map, 1935 struct cfi_private *cfi, 1936 const struct amd_flash_info *finfo ) 1937 { 1938 int rc = 0; /* failure until all tests pass */ 1939 u32 mfr, id; 1940 uint8_t uaddr; 1941 1942 /* 1943 * The IDs must match. For X16 and X32 devices operating in 1944 * a lower width ( X8 or X16 ), the device ID's are usually just 1945 * the lower byte(s) of the larger device ID for wider mode. If 1946 * a part is found that doesn't fit this assumption (device id for 1947 * smaller width mode is completely unrealated to full-width mode) 1948 * then the jedec_table[] will have to be augmented with the IDs 1949 * for different widths. 1950 */ 1951 switch (cfi->device_type) { 1952 case CFI_DEVICETYPE_X8: 1953 mfr = (uint8_t)finfo->mfr_id; 1954 id = (uint8_t)finfo->dev_id; 1955 1956 /* bjd: it seems that if we do this, we can end up 1957 * detecting 16bit flashes as an 8bit device, even though 1958 * there aren't. 1959 */ 1960 if (finfo->dev_id > 0xff) { 1961 DEBUG( MTD_DEBUG_LEVEL3, "%s(): ID is not 8bit\n", 1962 __func__); 1963 goto match_done; 1964 } 1965 break; 1966 case CFI_DEVICETYPE_X16: 1967 mfr = (uint16_t)finfo->mfr_id; 1968 id = (uint16_t)finfo->dev_id; 1969 break; 1970 case CFI_DEVICETYPE_X32: 1971 mfr = (uint16_t)finfo->mfr_id; 1972 id = (uint32_t)finfo->dev_id; 1973 break; 1974 default: 1975 printk(KERN_WARNING 1976 "MTD %s(): Unsupported device type %d\n", 1977 __func__, cfi->device_type); 1978 goto match_done; 1979 } 1980 if ( cfi->mfr != mfr || cfi->id != id ) { 1981 goto match_done; 1982 } 1983 1984 /* the part size must fit in the memory window */ 1985 DEBUG( MTD_DEBUG_LEVEL3, 1986 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n", 1987 __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) ); 1988 if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) { 1989 DEBUG( MTD_DEBUG_LEVEL3, 1990 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n", 1991 __func__, finfo->mfr_id, finfo->dev_id, 1992 1 << finfo->dev_size ); 1993 goto match_done; 1994 } 1995 1996 if (! (finfo->devtypes & cfi->device_type)) 1997 goto match_done; 1998 1999 uaddr = finfo->uaddr; 2000 2001 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n", 2002 __func__, cfi->addr_unlock1, cfi->addr_unlock2 ); 2003 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr 2004 && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 || 2005 unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) { 2006 DEBUG( MTD_DEBUG_LEVEL3, 2007 "MTD %s(): 0x%.4x 0x%.4x did not match\n", 2008 __func__, 2009 unlock_addrs[uaddr].addr1, 2010 unlock_addrs[uaddr].addr2); 2011 goto match_done; 2012 } 2013 2014 /* 2015 * Make sure the ID's dissappear when the device is taken out of 2016 * ID mode. The only time this should fail when it should succeed 2017 * is when the ID's are written as data to the same 2018 * addresses. For this rare and unfortunate case the chip 2019 * cannot be probed correctly. 2020 * FIXME - write a driver that takes all of the chip info as 2021 * module parameters, doesn't probe but forces a load. 2022 */ 2023 DEBUG( MTD_DEBUG_LEVEL3, 2024 "MTD %s(): check ID's disappear when not in ID mode\n", 2025 __func__ ); 2026 jedec_reset( base, map, cfi ); 2027 mfr = jedec_read_mfr( map, base, cfi ); 2028 id = jedec_read_id( map, base, cfi ); 2029 if ( mfr == cfi->mfr && id == cfi->id ) { 2030 DEBUG( MTD_DEBUG_LEVEL3, 2031 "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n" 2032 "You might need to manually specify JEDEC parameters.\n", 2033 __func__, cfi->mfr, cfi->id ); 2034 goto match_done; 2035 } 2036 2037 /* all tests passed - mark as success */ 2038 rc = 1; 2039 2040 /* 2041 * Put the device back in ID mode - only need to do this if we 2042 * were truly frobbing a real device. 2043 */ 2044 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ ); 2045 if (cfi->addr_unlock1) { 2046 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2047 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 2048 } 2049 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2050 /* FIXME - should have a delay before continuing */ 2051 2052 match_done: 2053 return rc; 2054 } 2055 2056 2057 static int jedec_probe_chip(struct map_info *map, __u32 base, 2058 unsigned long *chip_map, struct cfi_private *cfi) 2059 { 2060 int i; 2061 enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED; 2062 u32 probe_offset1, probe_offset2; 2063 2064 retry: 2065 if (!cfi->numchips) { 2066 uaddr_idx++; 2067 2068 if (MTD_UADDR_UNNECESSARY == uaddr_idx) 2069 return 0; 2070 2071 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type; 2072 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type; 2073 } 2074 2075 /* Make certain we aren't probing past the end of map */ 2076 if (base >= map->size) { 2077 printk(KERN_NOTICE 2078 "Probe at base(0x%08x) past the end of the map(0x%08lx)\n", 2079 base, map->size -1); 2080 return 0; 2081 2082 } 2083 /* Ensure the unlock addresses we try stay inside the map */ 2084 probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi); 2085 probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi); 2086 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || 2087 ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) 2088 goto retry; 2089 2090 /* Reset */ 2091 jedec_reset(base, map, cfi); 2092 2093 /* Autoselect Mode */ 2094 if(cfi->addr_unlock1) { 2095 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2096 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 2097 } 2098 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2099 /* FIXME - should have a delay before continuing */ 2100 2101 if (!cfi->numchips) { 2102 /* This is the first time we're called. Set up the CFI 2103 stuff accordingly and return */ 2104 2105 cfi->mfr = jedec_read_mfr(map, base, cfi); 2106 cfi->id = jedec_read_id(map, base, cfi); 2107 DEBUG(MTD_DEBUG_LEVEL3, 2108 "Search for id:(%02x %02x) interleave(%d) type(%d)\n", 2109 cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type); 2110 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { 2111 if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) { 2112 DEBUG( MTD_DEBUG_LEVEL3, 2113 "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n", 2114 __func__, cfi->mfr, cfi->id, 2115 cfi->addr_unlock1, cfi->addr_unlock2 ); 2116 if (!cfi_jedec_setup(cfi, i)) 2117 return 0; 2118 goto ok_out; 2119 } 2120 } 2121 goto retry; 2122 } else { 2123 uint16_t mfr; 2124 uint16_t id; 2125 2126 /* Make sure it is a chip of the same manufacturer and id */ 2127 mfr = jedec_read_mfr(map, base, cfi); 2128 id = jedec_read_id(map, base, cfi); 2129 2130 if ((mfr != cfi->mfr) || (id != cfi->id)) { 2131 printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n", 2132 map->name, mfr, id, base); 2133 jedec_reset(base, map, cfi); 2134 return 0; 2135 } 2136 } 2137 2138 /* Check each previous chip locations to see if it's an alias */ 2139 for (i=0; i < (base >> cfi->chipshift); i++) { 2140 unsigned long start; 2141 if(!test_bit(i, chip_map)) { 2142 continue; /* Skip location; no valid chip at this address */ 2143 } 2144 start = i << cfi->chipshift; 2145 if (jedec_read_mfr(map, start, cfi) == cfi->mfr && 2146 jedec_read_id(map, start, cfi) == cfi->id) { 2147 /* Eep. This chip also looks like it's in autoselect mode. 2148 Is it an alias for the new one? */ 2149 jedec_reset(start, map, cfi); 2150 2151 /* If the device IDs go away, it's an alias */ 2152 if (jedec_read_mfr(map, base, cfi) != cfi->mfr || 2153 jedec_read_id(map, base, cfi) != cfi->id) { 2154 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 2155 map->name, base, start); 2156 return 0; 2157 } 2158 2159 /* Yes, it's actually got the device IDs as data. Most 2160 * unfortunate. Stick the new chip in read mode 2161 * too and if it's the same, assume it's an alias. */ 2162 /* FIXME: Use other modes to do a proper check */ 2163 jedec_reset(base, map, cfi); 2164 if (jedec_read_mfr(map, base, cfi) == cfi->mfr && 2165 jedec_read_id(map, base, cfi) == cfi->id) { 2166 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 2167 map->name, base, start); 2168 return 0; 2169 } 2170 } 2171 } 2172 2173 /* OK, if we got to here, then none of the previous chips appear to 2174 be aliases for the current one. */ 2175 set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ 2176 cfi->numchips++; 2177 2178 ok_out: 2179 /* Put it back into Read Mode */ 2180 jedec_reset(base, map, cfi); 2181 2182 printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", 2183 map->name, cfi_interleave(cfi), cfi->device_type*8, base, 2184 map->bankwidth*8); 2185 2186 return 1; 2187 } 2188 2189 static struct chip_probe jedec_chip_probe = { 2190 .name = "JEDEC", 2191 .probe_chip = jedec_probe_chip 2192 }; 2193 2194 static struct mtd_info *jedec_probe(struct map_info *map) 2195 { 2196 /* 2197 * Just use the generic probe stuff to call our CFI-specific 2198 * chip_probe routine in all the possible permutations, etc. 2199 */ 2200 return mtd_do_chip_probe(map, &jedec_chip_probe); 2201 } 2202 2203 static struct mtd_chip_driver jedec_chipdrv = { 2204 .probe = jedec_probe, 2205 .name = "jedec_probe", 2206 .module = THIS_MODULE 2207 }; 2208 2209 static int __init jedec_probe_init(void) 2210 { 2211 register_mtd_chip_driver(&jedec_chipdrv); 2212 return 0; 2213 } 2214 2215 static void __exit jedec_probe_exit(void) 2216 { 2217 unregister_mtd_chip_driver(&jedec_chipdrv); 2218 } 2219 2220 module_init(jedec_probe_init); 2221 module_exit(jedec_probe_exit); 2222 2223 MODULE_LICENSE("GPL"); 2224 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al."); 2225 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips"); 2226