1 /* 2 Common Flash Interface probe code. 3 (C) 2000 Red Hat. GPL'd. 4 See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5) 5 for the standard this probe goes back to. 6 7 Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 8 */ 9 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/kernel.h> 14 #include <asm/io.h> 15 #include <asm/byteorder.h> 16 #include <linux/errno.h> 17 #include <linux/slab.h> 18 #include <linux/interrupt.h> 19 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/map.h> 22 #include <linux/mtd/cfi.h> 23 #include <linux/mtd/gen_probe.h> 24 25 /* Manufacturers */ 26 #define MANUFACTURER_AMD 0x0001 27 #define MANUFACTURER_ATMEL 0x001f 28 #define MANUFACTURER_EON 0x001c 29 #define MANUFACTURER_FUJITSU 0x0004 30 #define MANUFACTURER_HYUNDAI 0x00AD 31 #define MANUFACTURER_INTEL 0x0089 32 #define MANUFACTURER_MACRONIX 0x00C2 33 #define MANUFACTURER_NEC 0x0010 34 #define MANUFACTURER_PMC 0x009D 35 #define MANUFACTURER_SHARP 0x00b0 36 #define MANUFACTURER_SST 0x00BF 37 #define MANUFACTURER_ST 0x0020 38 #define MANUFACTURER_TOSHIBA 0x0098 39 #define MANUFACTURER_WINBOND 0x00da 40 #define CONTINUATION_CODE 0x007f 41 42 43 /* AMD */ 44 #define AM29DL800BB 0x22CB 45 #define AM29DL800BT 0x224A 46 47 #define AM29F800BB 0x2258 48 #define AM29F800BT 0x22D6 49 #define AM29LV400BB 0x22BA 50 #define AM29LV400BT 0x22B9 51 #define AM29LV800BB 0x225B 52 #define AM29LV800BT 0x22DA 53 #define AM29LV160DT 0x22C4 54 #define AM29LV160DB 0x2249 55 #define AM29F017D 0x003D 56 #define AM29F016D 0x00AD 57 #define AM29F080 0x00D5 58 #define AM29F040 0x00A4 59 #define AM29LV040B 0x004F 60 #define AM29F032B 0x0041 61 #define AM29F002T 0x00B0 62 #define AM29SL800DB 0x226B 63 #define AM29SL800DT 0x22EA 64 65 /* Atmel */ 66 #define AT49BV512 0x0003 67 #define AT29LV512 0x003d 68 #define AT49BV16X 0x00C0 69 #define AT49BV16XT 0x00C2 70 #define AT49BV32X 0x00C8 71 #define AT49BV32XT 0x00C9 72 73 /* Eon */ 74 #define EN29SL800BB 0x226B 75 #define EN29SL800BT 0x22EA 76 77 /* Fujitsu */ 78 #define MBM29F040C 0x00A4 79 #define MBM29F800BA 0x2258 80 #define MBM29LV650UE 0x22D7 81 #define MBM29LV320TE 0x22F6 82 #define MBM29LV320BE 0x22F9 83 #define MBM29LV160TE 0x22C4 84 #define MBM29LV160BE 0x2249 85 #define MBM29LV800BA 0x225B 86 #define MBM29LV800TA 0x22DA 87 #define MBM29LV400TC 0x22B9 88 #define MBM29LV400BC 0x22BA 89 90 /* Hyundai */ 91 #define HY29F002T 0x00B0 92 93 /* Intel */ 94 #define I28F004B3T 0x00d4 95 #define I28F004B3B 0x00d5 96 #define I28F400B3T 0x8894 97 #define I28F400B3B 0x8895 98 #define I28F008S5 0x00a6 99 #define I28F016S5 0x00a0 100 #define I28F008SA 0x00a2 101 #define I28F008B3T 0x00d2 102 #define I28F008B3B 0x00d3 103 #define I28F800B3T 0x8892 104 #define I28F800B3B 0x8893 105 #define I28F016S3 0x00aa 106 #define I28F016B3T 0x00d0 107 #define I28F016B3B 0x00d1 108 #define I28F160B3T 0x8890 109 #define I28F160B3B 0x8891 110 #define I28F320B3T 0x8896 111 #define I28F320B3B 0x8897 112 #define I28F640B3T 0x8898 113 #define I28F640B3B 0x8899 114 #define I82802AB 0x00ad 115 #define I82802AC 0x00ac 116 117 /* Macronix */ 118 #define MX29LV040C 0x004F 119 #define MX29LV160T 0x22C4 120 #define MX29LV160B 0x2249 121 #define MX29F040 0x00A4 122 #define MX29F016 0x00AD 123 #define MX29F002T 0x00B0 124 #define MX29F004T 0x0045 125 #define MX29F004B 0x0046 126 127 /* NEC */ 128 #define UPD29F064115 0x221C 129 130 /* PMC */ 131 #define PM49FL002 0x006D 132 #define PM49FL004 0x006E 133 #define PM49FL008 0x006A 134 135 /* Sharp */ 136 #define LH28F640BF 0x00b0 137 138 /* ST - www.st.com */ 139 #define M29F800AB 0x0058 140 #define M29W800DT 0x00D7 141 #define M29W800DB 0x005B 142 #define M29W400DT 0x00EE 143 #define M29W400DB 0x00EF 144 #define M29W160DT 0x22C4 145 #define M29W160DB 0x2249 146 #define M29W040B 0x00E3 147 #define M50FW040 0x002C 148 #define M50FW080 0x002D 149 #define M50FW016 0x002E 150 #define M50LPW080 0x002F 151 #define M50FLW080A 0x0080 152 #define M50FLW080B 0x0081 153 154 /* SST */ 155 #define SST29EE020 0x0010 156 #define SST29LE020 0x0012 157 #define SST29EE512 0x005d 158 #define SST29LE512 0x003d 159 #define SST39LF800 0x2781 160 #define SST39LF160 0x2782 161 #define SST39VF1601 0x234b 162 #define SST39VF3201 0x235b 163 #define SST39LF512 0x00D4 164 #define SST39LF010 0x00D5 165 #define SST39LF020 0x00D6 166 #define SST39LF040 0x00D7 167 #define SST39SF010A 0x00B5 168 #define SST39SF020A 0x00B6 169 #define SST39SF040 0x00B7 170 #define SST49LF004B 0x0060 171 #define SST49LF040B 0x0050 172 #define SST49LF008A 0x005a 173 #define SST49LF030A 0x001C 174 #define SST49LF040A 0x0051 175 #define SST49LF080A 0x005B 176 #define SST36VF3203 0x7354 177 178 /* Toshiba */ 179 #define TC58FVT160 0x00C2 180 #define TC58FVB160 0x0043 181 #define TC58FVT321 0x009A 182 #define TC58FVB321 0x009C 183 #define TC58FVT641 0x0093 184 #define TC58FVB641 0x0095 185 186 /* Winbond */ 187 #define W49V002A 0x00b0 188 189 190 /* 191 * Unlock address sets for AMD command sets. 192 * Intel command sets use the MTD_UADDR_UNNECESSARY. 193 * Each identifier, except MTD_UADDR_UNNECESSARY, and 194 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. 195 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure 196 * initialization need not require initializing all of the 197 * unlock addresses for all bit widths. 198 */ 199 enum uaddr { 200 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ 201 MTD_UADDR_0x0555_0x02AA, 202 MTD_UADDR_0x0555_0x0AAA, 203 MTD_UADDR_0x5555_0x2AAA, 204 MTD_UADDR_0x0AAA_0x0555, 205 MTD_UADDR_0xAAAA_0x5555, 206 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ 207 MTD_UADDR_UNNECESSARY, /* Does not require any address */ 208 }; 209 210 211 struct unlock_addr { 212 uint32_t addr1; 213 uint32_t addr2; 214 }; 215 216 217 /* 218 * I don't like the fact that the first entry in unlock_addrs[] 219 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, 220 * should not be used. The problem is that structures with 221 * initializers have extra fields initialized to 0. It is _very_ 222 * desireable to have the unlock address entries for unsupported 223 * data widths automatically initialized - that means that 224 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here 225 * must go unused. 226 */ 227 static const struct unlock_addr unlock_addrs[] = { 228 [MTD_UADDR_NOT_SUPPORTED] = { 229 .addr1 = 0xffff, 230 .addr2 = 0xffff 231 }, 232 233 [MTD_UADDR_0x0555_0x02AA] = { 234 .addr1 = 0x0555, 235 .addr2 = 0x02aa 236 }, 237 238 [MTD_UADDR_0x0555_0x0AAA] = { 239 .addr1 = 0x0555, 240 .addr2 = 0x0aaa 241 }, 242 243 [MTD_UADDR_0x5555_0x2AAA] = { 244 .addr1 = 0x5555, 245 .addr2 = 0x2aaa 246 }, 247 248 [MTD_UADDR_0x0AAA_0x0555] = { 249 .addr1 = 0x0AAA, 250 .addr2 = 0x0555 251 }, 252 253 [MTD_UADDR_0xAAAA_0x5555] = { 254 .addr1 = 0xaaaa, 255 .addr2 = 0x5555 256 }, 257 258 [MTD_UADDR_DONT_CARE] = { 259 .addr1 = 0x0000, /* Doesn't matter which address */ 260 .addr2 = 0x0000 /* is used - must be last entry */ 261 }, 262 263 [MTD_UADDR_UNNECESSARY] = { 264 .addr1 = 0x0000, 265 .addr2 = 0x0000 266 } 267 }; 268 269 struct amd_flash_info { 270 const char *name; 271 const uint16_t mfr_id; 272 const uint16_t dev_id; 273 const uint8_t dev_size; 274 const uint8_t nr_regions; 275 const uint16_t cmd_set; 276 const uint32_t regions[6]; 277 const uint8_t devtypes; /* Bitmask for x8, x16 etc. */ 278 const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */ 279 }; 280 281 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) 282 283 #define SIZE_64KiB 16 284 #define SIZE_128KiB 17 285 #define SIZE_256KiB 18 286 #define SIZE_512KiB 19 287 #define SIZE_1MiB 20 288 #define SIZE_2MiB 21 289 #define SIZE_4MiB 22 290 #define SIZE_8MiB 23 291 292 293 /* 294 * Please keep this list ordered by manufacturer! 295 * Fortunately, the list isn't searched often and so a 296 * slow, linear search isn't so bad. 297 */ 298 static const struct amd_flash_info jedec_table[] = { 299 { 300 .mfr_id = MANUFACTURER_AMD, 301 .dev_id = AM29F032B, 302 .name = "AMD AM29F032B", 303 .uaddr = MTD_UADDR_0x0555_0x02AA, 304 .devtypes = CFI_DEVICETYPE_X8, 305 .dev_size = SIZE_4MiB, 306 .cmd_set = P_ID_AMD_STD, 307 .nr_regions = 1, 308 .regions = { 309 ERASEINFO(0x10000,64) 310 } 311 }, { 312 .mfr_id = MANUFACTURER_AMD, 313 .dev_id = AM29LV160DT, 314 .name = "AMD AM29LV160DT", 315 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 316 .uaddr = MTD_UADDR_0x0AAA_0x0555, 317 .dev_size = SIZE_2MiB, 318 .cmd_set = P_ID_AMD_STD, 319 .nr_regions = 4, 320 .regions = { 321 ERASEINFO(0x10000,31), 322 ERASEINFO(0x08000,1), 323 ERASEINFO(0x02000,2), 324 ERASEINFO(0x04000,1) 325 } 326 }, { 327 .mfr_id = MANUFACTURER_AMD, 328 .dev_id = AM29LV160DB, 329 .name = "AMD AM29LV160DB", 330 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 331 .uaddr = MTD_UADDR_0x0AAA_0x0555, 332 .dev_size = SIZE_2MiB, 333 .cmd_set = P_ID_AMD_STD, 334 .nr_regions = 4, 335 .regions = { 336 ERASEINFO(0x04000,1), 337 ERASEINFO(0x02000,2), 338 ERASEINFO(0x08000,1), 339 ERASEINFO(0x10000,31) 340 } 341 }, { 342 .mfr_id = MANUFACTURER_AMD, 343 .dev_id = AM29LV400BB, 344 .name = "AMD AM29LV400BB", 345 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 346 .uaddr = MTD_UADDR_0x0AAA_0x0555, 347 .dev_size = SIZE_512KiB, 348 .cmd_set = P_ID_AMD_STD, 349 .nr_regions = 4, 350 .regions = { 351 ERASEINFO(0x04000,1), 352 ERASEINFO(0x02000,2), 353 ERASEINFO(0x08000,1), 354 ERASEINFO(0x10000,7) 355 } 356 }, { 357 .mfr_id = MANUFACTURER_AMD, 358 .dev_id = AM29LV400BT, 359 .name = "AMD AM29LV400BT", 360 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 361 .uaddr = MTD_UADDR_0x0AAA_0x0555, 362 .dev_size = SIZE_512KiB, 363 .cmd_set = P_ID_AMD_STD, 364 .nr_regions = 4, 365 .regions = { 366 ERASEINFO(0x10000,7), 367 ERASEINFO(0x08000,1), 368 ERASEINFO(0x02000,2), 369 ERASEINFO(0x04000,1) 370 } 371 }, { 372 .mfr_id = MANUFACTURER_AMD, 373 .dev_id = AM29LV800BB, 374 .name = "AMD AM29LV800BB", 375 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 376 .uaddr = MTD_UADDR_0x0AAA_0x0555, 377 .dev_size = SIZE_1MiB, 378 .cmd_set = P_ID_AMD_STD, 379 .nr_regions = 4, 380 .regions = { 381 ERASEINFO(0x04000,1), 382 ERASEINFO(0x02000,2), 383 ERASEINFO(0x08000,1), 384 ERASEINFO(0x10000,15), 385 } 386 }, { 387 /* add DL */ 388 .mfr_id = MANUFACTURER_AMD, 389 .dev_id = AM29DL800BB, 390 .name = "AMD AM29DL800BB", 391 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 392 .uaddr = MTD_UADDR_0x0AAA_0x0555, 393 .dev_size = SIZE_1MiB, 394 .cmd_set = P_ID_AMD_STD, 395 .nr_regions = 6, 396 .regions = { 397 ERASEINFO(0x04000,1), 398 ERASEINFO(0x08000,1), 399 ERASEINFO(0x02000,4), 400 ERASEINFO(0x08000,1), 401 ERASEINFO(0x04000,1), 402 ERASEINFO(0x10000,14) 403 } 404 }, { 405 .mfr_id = MANUFACTURER_AMD, 406 .dev_id = AM29DL800BT, 407 .name = "AMD AM29DL800BT", 408 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 409 .uaddr = MTD_UADDR_0x0AAA_0x0555, 410 .dev_size = SIZE_1MiB, 411 .cmd_set = P_ID_AMD_STD, 412 .nr_regions = 6, 413 .regions = { 414 ERASEINFO(0x10000,14), 415 ERASEINFO(0x04000,1), 416 ERASEINFO(0x08000,1), 417 ERASEINFO(0x02000,4), 418 ERASEINFO(0x08000,1), 419 ERASEINFO(0x04000,1) 420 } 421 }, { 422 .mfr_id = MANUFACTURER_AMD, 423 .dev_id = AM29F800BB, 424 .name = "AMD AM29F800BB", 425 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 426 .uaddr = MTD_UADDR_0x0AAA_0x0555, 427 .dev_size = SIZE_1MiB, 428 .cmd_set = P_ID_AMD_STD, 429 .nr_regions = 4, 430 .regions = { 431 ERASEINFO(0x04000,1), 432 ERASEINFO(0x02000,2), 433 ERASEINFO(0x08000,1), 434 ERASEINFO(0x10000,15), 435 } 436 }, { 437 .mfr_id = MANUFACTURER_AMD, 438 .dev_id = AM29LV800BT, 439 .name = "AMD AM29LV800BT", 440 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 441 .uaddr = MTD_UADDR_0x0AAA_0x0555, 442 .dev_size = SIZE_1MiB, 443 .cmd_set = P_ID_AMD_STD, 444 .nr_regions = 4, 445 .regions = { 446 ERASEINFO(0x10000,15), 447 ERASEINFO(0x08000,1), 448 ERASEINFO(0x02000,2), 449 ERASEINFO(0x04000,1) 450 } 451 }, { 452 .mfr_id = MANUFACTURER_AMD, 453 .dev_id = AM29F800BT, 454 .name = "AMD AM29F800BT", 455 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 456 .uaddr = MTD_UADDR_0x0AAA_0x0555, 457 .dev_size = SIZE_1MiB, 458 .cmd_set = P_ID_AMD_STD, 459 .nr_regions = 4, 460 .regions = { 461 ERASEINFO(0x10000,15), 462 ERASEINFO(0x08000,1), 463 ERASEINFO(0x02000,2), 464 ERASEINFO(0x04000,1) 465 } 466 }, { 467 .mfr_id = MANUFACTURER_AMD, 468 .dev_id = AM29F017D, 469 .name = "AMD AM29F017D", 470 .devtypes = CFI_DEVICETYPE_X8, 471 .uaddr = MTD_UADDR_DONT_CARE, 472 .dev_size = SIZE_2MiB, 473 .cmd_set = P_ID_AMD_STD, 474 .nr_regions = 1, 475 .regions = { 476 ERASEINFO(0x10000,32), 477 } 478 }, { 479 .mfr_id = MANUFACTURER_AMD, 480 .dev_id = AM29F016D, 481 .name = "AMD AM29F016D", 482 .devtypes = CFI_DEVICETYPE_X8, 483 .uaddr = MTD_UADDR_0x0555_0x02AA, 484 .dev_size = SIZE_2MiB, 485 .cmd_set = P_ID_AMD_STD, 486 .nr_regions = 1, 487 .regions = { 488 ERASEINFO(0x10000,32), 489 } 490 }, { 491 .mfr_id = MANUFACTURER_AMD, 492 .dev_id = AM29F080, 493 .name = "AMD AM29F080", 494 .devtypes = CFI_DEVICETYPE_X8, 495 .uaddr = MTD_UADDR_0x0555_0x02AA, 496 .dev_size = SIZE_1MiB, 497 .cmd_set = P_ID_AMD_STD, 498 .nr_regions = 1, 499 .regions = { 500 ERASEINFO(0x10000,16), 501 } 502 }, { 503 .mfr_id = MANUFACTURER_AMD, 504 .dev_id = AM29F040, 505 .name = "AMD AM29F040", 506 .devtypes = CFI_DEVICETYPE_X8, 507 .uaddr = MTD_UADDR_0x0555_0x02AA, 508 .dev_size = SIZE_512KiB, 509 .cmd_set = P_ID_AMD_STD, 510 .nr_regions = 1, 511 .regions = { 512 ERASEINFO(0x10000,8), 513 } 514 }, { 515 .mfr_id = MANUFACTURER_AMD, 516 .dev_id = AM29LV040B, 517 .name = "AMD AM29LV040B", 518 .devtypes = CFI_DEVICETYPE_X8, 519 .uaddr = MTD_UADDR_0x0555_0x02AA, 520 .dev_size = SIZE_512KiB, 521 .cmd_set = P_ID_AMD_STD, 522 .nr_regions = 1, 523 .regions = { 524 ERASEINFO(0x10000,8), 525 } 526 }, { 527 .mfr_id = MANUFACTURER_AMD, 528 .dev_id = AM29F002T, 529 .name = "AMD AM29F002T", 530 .devtypes = CFI_DEVICETYPE_X8, 531 .uaddr = MTD_UADDR_0x0555_0x02AA, 532 .dev_size = SIZE_256KiB, 533 .cmd_set = P_ID_AMD_STD, 534 .nr_regions = 4, 535 .regions = { 536 ERASEINFO(0x10000,3), 537 ERASEINFO(0x08000,1), 538 ERASEINFO(0x02000,2), 539 ERASEINFO(0x04000,1), 540 } 541 }, { 542 .mfr_id = MANUFACTURER_AMD, 543 .dev_id = AM29SL800DT, 544 .name = "AMD AM29SL800DT", 545 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 546 .uaddr = MTD_UADDR_0x0AAA_0x0555, 547 .dev_size = SIZE_1MiB, 548 .cmd_set = P_ID_AMD_STD, 549 .nr_regions = 4, 550 .regions = { 551 ERASEINFO(0x10000,15), 552 ERASEINFO(0x08000,1), 553 ERASEINFO(0x02000,2), 554 ERASEINFO(0x04000,1), 555 } 556 }, { 557 .mfr_id = MANUFACTURER_AMD, 558 .dev_id = AM29SL800DB, 559 .name = "AMD AM29SL800DB", 560 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 561 .uaddr = MTD_UADDR_0x0AAA_0x0555, 562 .dev_size = SIZE_1MiB, 563 .cmd_set = P_ID_AMD_STD, 564 .nr_regions = 4, 565 .regions = { 566 ERASEINFO(0x04000,1), 567 ERASEINFO(0x02000,2), 568 ERASEINFO(0x08000,1), 569 ERASEINFO(0x10000,15), 570 } 571 }, { 572 .mfr_id = MANUFACTURER_ATMEL, 573 .dev_id = AT49BV512, 574 .name = "Atmel AT49BV512", 575 .devtypes = CFI_DEVICETYPE_X8, 576 .uaddr = MTD_UADDR_0x5555_0x2AAA, 577 .dev_size = SIZE_64KiB, 578 .cmd_set = P_ID_AMD_STD, 579 .nr_regions = 1, 580 .regions = { 581 ERASEINFO(0x10000,1) 582 } 583 }, { 584 .mfr_id = MANUFACTURER_ATMEL, 585 .dev_id = AT29LV512, 586 .name = "Atmel AT29LV512", 587 .devtypes = CFI_DEVICETYPE_X8, 588 .uaddr = MTD_UADDR_0x5555_0x2AAA, 589 .dev_size = SIZE_64KiB, 590 .cmd_set = P_ID_AMD_STD, 591 .nr_regions = 1, 592 .regions = { 593 ERASEINFO(0x80,256), 594 ERASEINFO(0x80,256) 595 } 596 }, { 597 .mfr_id = MANUFACTURER_ATMEL, 598 .dev_id = AT49BV16X, 599 .name = "Atmel AT49BV16X", 600 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 601 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 602 .dev_size = SIZE_2MiB, 603 .cmd_set = P_ID_AMD_STD, 604 .nr_regions = 2, 605 .regions = { 606 ERASEINFO(0x02000,8), 607 ERASEINFO(0x10000,31) 608 } 609 }, { 610 .mfr_id = MANUFACTURER_ATMEL, 611 .dev_id = AT49BV16XT, 612 .name = "Atmel AT49BV16XT", 613 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 614 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 615 .dev_size = SIZE_2MiB, 616 .cmd_set = P_ID_AMD_STD, 617 .nr_regions = 2, 618 .regions = { 619 ERASEINFO(0x10000,31), 620 ERASEINFO(0x02000,8) 621 } 622 }, { 623 .mfr_id = MANUFACTURER_ATMEL, 624 .dev_id = AT49BV32X, 625 .name = "Atmel AT49BV32X", 626 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 627 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 628 .dev_size = SIZE_4MiB, 629 .cmd_set = P_ID_AMD_STD, 630 .nr_regions = 2, 631 .regions = { 632 ERASEINFO(0x02000,8), 633 ERASEINFO(0x10000,63) 634 } 635 }, { 636 .mfr_id = MANUFACTURER_ATMEL, 637 .dev_id = AT49BV32XT, 638 .name = "Atmel AT49BV32XT", 639 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 640 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 641 .dev_size = SIZE_4MiB, 642 .cmd_set = P_ID_AMD_STD, 643 .nr_regions = 2, 644 .regions = { 645 ERASEINFO(0x10000,63), 646 ERASEINFO(0x02000,8) 647 } 648 }, { 649 .mfr_id = MANUFACTURER_EON, 650 .dev_id = EN29SL800BT, 651 .name = "Eon EN29SL800BT", 652 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 653 .uaddr = MTD_UADDR_0x0AAA_0x0555, 654 .dev_size = SIZE_1MiB, 655 .cmd_set = P_ID_AMD_STD, 656 .nr_regions = 4, 657 .regions = { 658 ERASEINFO(0x10000,15), 659 ERASEINFO(0x08000,1), 660 ERASEINFO(0x02000,2), 661 ERASEINFO(0x04000,1), 662 } 663 }, { 664 .mfr_id = MANUFACTURER_EON, 665 .dev_id = EN29SL800BB, 666 .name = "Eon EN29SL800BB", 667 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 668 .uaddr = MTD_UADDR_0x0AAA_0x0555, 669 .dev_size = SIZE_1MiB, 670 .cmd_set = P_ID_AMD_STD, 671 .nr_regions = 4, 672 .regions = { 673 ERASEINFO(0x04000,1), 674 ERASEINFO(0x02000,2), 675 ERASEINFO(0x08000,1), 676 ERASEINFO(0x10000,15), 677 } 678 }, { 679 .mfr_id = MANUFACTURER_FUJITSU, 680 .dev_id = MBM29F040C, 681 .name = "Fujitsu MBM29F040C", 682 .devtypes = CFI_DEVICETYPE_X8, 683 .uaddr = MTD_UADDR_0x0AAA_0x0555, 684 .dev_size = SIZE_512KiB, 685 .cmd_set = P_ID_AMD_STD, 686 .nr_regions = 1, 687 .regions = { 688 ERASEINFO(0x10000,8) 689 } 690 }, { 691 .mfr_id = MANUFACTURER_FUJITSU, 692 .dev_id = MBM29F800BA, 693 .name = "Fujitsu MBM29F800BA", 694 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 695 .uaddr = MTD_UADDR_0x0AAA_0x0555, 696 .dev_size = SIZE_1MiB, 697 .cmd_set = P_ID_AMD_STD, 698 .nr_regions = 4, 699 .regions = { 700 ERASEINFO(0x04000,1), 701 ERASEINFO(0x02000,2), 702 ERASEINFO(0x08000,1), 703 ERASEINFO(0x10000,15), 704 } 705 }, { 706 .mfr_id = MANUFACTURER_FUJITSU, 707 .dev_id = MBM29LV650UE, 708 .name = "Fujitsu MBM29LV650UE", 709 .devtypes = CFI_DEVICETYPE_X8, 710 .uaddr = MTD_UADDR_DONT_CARE, 711 .dev_size = SIZE_8MiB, 712 .cmd_set = P_ID_AMD_STD, 713 .nr_regions = 1, 714 .regions = { 715 ERASEINFO(0x10000,128) 716 } 717 }, { 718 .mfr_id = MANUFACTURER_FUJITSU, 719 .dev_id = MBM29LV320TE, 720 .name = "Fujitsu MBM29LV320TE", 721 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 722 .uaddr = MTD_UADDR_0x0AAA_0x0555, 723 .dev_size = SIZE_4MiB, 724 .cmd_set = P_ID_AMD_STD, 725 .nr_regions = 2, 726 .regions = { 727 ERASEINFO(0x10000,63), 728 ERASEINFO(0x02000,8) 729 } 730 }, { 731 .mfr_id = MANUFACTURER_FUJITSU, 732 .dev_id = MBM29LV320BE, 733 .name = "Fujitsu MBM29LV320BE", 734 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 735 .uaddr = MTD_UADDR_0x0AAA_0x0555, 736 .dev_size = SIZE_4MiB, 737 .cmd_set = P_ID_AMD_STD, 738 .nr_regions = 2, 739 .regions = { 740 ERASEINFO(0x02000,8), 741 ERASEINFO(0x10000,63) 742 } 743 }, { 744 .mfr_id = MANUFACTURER_FUJITSU, 745 .dev_id = MBM29LV160TE, 746 .name = "Fujitsu MBM29LV160TE", 747 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 748 .uaddr = MTD_UADDR_0x0AAA_0x0555, 749 .dev_size = SIZE_2MiB, 750 .cmd_set = P_ID_AMD_STD, 751 .nr_regions = 4, 752 .regions = { 753 ERASEINFO(0x10000,31), 754 ERASEINFO(0x08000,1), 755 ERASEINFO(0x02000,2), 756 ERASEINFO(0x04000,1) 757 } 758 }, { 759 .mfr_id = MANUFACTURER_FUJITSU, 760 .dev_id = MBM29LV160BE, 761 .name = "Fujitsu MBM29LV160BE", 762 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 763 .uaddr = MTD_UADDR_0x0AAA_0x0555, 764 .dev_size = SIZE_2MiB, 765 .cmd_set = P_ID_AMD_STD, 766 .nr_regions = 4, 767 .regions = { 768 ERASEINFO(0x04000,1), 769 ERASEINFO(0x02000,2), 770 ERASEINFO(0x08000,1), 771 ERASEINFO(0x10000,31) 772 } 773 }, { 774 .mfr_id = MANUFACTURER_FUJITSU, 775 .dev_id = MBM29LV800BA, 776 .name = "Fujitsu MBM29LV800BA", 777 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 778 .uaddr = MTD_UADDR_0x0AAA_0x0555, 779 .dev_size = SIZE_1MiB, 780 .cmd_set = P_ID_AMD_STD, 781 .nr_regions = 4, 782 .regions = { 783 ERASEINFO(0x04000,1), 784 ERASEINFO(0x02000,2), 785 ERASEINFO(0x08000,1), 786 ERASEINFO(0x10000,15) 787 } 788 }, { 789 .mfr_id = MANUFACTURER_FUJITSU, 790 .dev_id = MBM29LV800TA, 791 .name = "Fujitsu MBM29LV800TA", 792 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 793 .uaddr = MTD_UADDR_0x0AAA_0x0555, 794 .dev_size = SIZE_1MiB, 795 .cmd_set = P_ID_AMD_STD, 796 .nr_regions = 4, 797 .regions = { 798 ERASEINFO(0x10000,15), 799 ERASEINFO(0x08000,1), 800 ERASEINFO(0x02000,2), 801 ERASEINFO(0x04000,1) 802 } 803 }, { 804 .mfr_id = MANUFACTURER_FUJITSU, 805 .dev_id = MBM29LV400BC, 806 .name = "Fujitsu MBM29LV400BC", 807 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 808 .uaddr = MTD_UADDR_0x0AAA_0x0555, 809 .dev_size = SIZE_512KiB, 810 .cmd_set = P_ID_AMD_STD, 811 .nr_regions = 4, 812 .regions = { 813 ERASEINFO(0x04000,1), 814 ERASEINFO(0x02000,2), 815 ERASEINFO(0x08000,1), 816 ERASEINFO(0x10000,7) 817 } 818 }, { 819 .mfr_id = MANUFACTURER_FUJITSU, 820 .dev_id = MBM29LV400TC, 821 .name = "Fujitsu MBM29LV400TC", 822 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 823 .uaddr = MTD_UADDR_0x0AAA_0x0555, 824 .dev_size = SIZE_512KiB, 825 .cmd_set = P_ID_AMD_STD, 826 .nr_regions = 4, 827 .regions = { 828 ERASEINFO(0x10000,7), 829 ERASEINFO(0x08000,1), 830 ERASEINFO(0x02000,2), 831 ERASEINFO(0x04000,1) 832 } 833 }, { 834 .mfr_id = MANUFACTURER_HYUNDAI, 835 .dev_id = HY29F002T, 836 .name = "Hyundai HY29F002T", 837 .devtypes = CFI_DEVICETYPE_X8, 838 .uaddr = MTD_UADDR_0x0555_0x02AA, 839 .dev_size = SIZE_256KiB, 840 .cmd_set = P_ID_AMD_STD, 841 .nr_regions = 4, 842 .regions = { 843 ERASEINFO(0x10000,3), 844 ERASEINFO(0x08000,1), 845 ERASEINFO(0x02000,2), 846 ERASEINFO(0x04000,1), 847 } 848 }, { 849 .mfr_id = MANUFACTURER_INTEL, 850 .dev_id = I28F004B3B, 851 .name = "Intel 28F004B3B", 852 .devtypes = CFI_DEVICETYPE_X8, 853 .uaddr = MTD_UADDR_UNNECESSARY, 854 .dev_size = SIZE_512KiB, 855 .cmd_set = P_ID_INTEL_STD, 856 .nr_regions = 2, 857 .regions = { 858 ERASEINFO(0x02000, 8), 859 ERASEINFO(0x10000, 7), 860 } 861 }, { 862 .mfr_id = MANUFACTURER_INTEL, 863 .dev_id = I28F004B3T, 864 .name = "Intel 28F004B3T", 865 .devtypes = CFI_DEVICETYPE_X8, 866 .uaddr = MTD_UADDR_UNNECESSARY, 867 .dev_size = SIZE_512KiB, 868 .cmd_set = P_ID_INTEL_STD, 869 .nr_regions = 2, 870 .regions = { 871 ERASEINFO(0x10000, 7), 872 ERASEINFO(0x02000, 8), 873 } 874 }, { 875 .mfr_id = MANUFACTURER_INTEL, 876 .dev_id = I28F400B3B, 877 .name = "Intel 28F400B3B", 878 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 879 .uaddr = MTD_UADDR_UNNECESSARY, 880 .dev_size = SIZE_512KiB, 881 .cmd_set = P_ID_INTEL_STD, 882 .nr_regions = 2, 883 .regions = { 884 ERASEINFO(0x02000, 8), 885 ERASEINFO(0x10000, 7), 886 } 887 }, { 888 .mfr_id = MANUFACTURER_INTEL, 889 .dev_id = I28F400B3T, 890 .name = "Intel 28F400B3T", 891 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 892 .uaddr = MTD_UADDR_UNNECESSARY, 893 .dev_size = SIZE_512KiB, 894 .cmd_set = P_ID_INTEL_STD, 895 .nr_regions = 2, 896 .regions = { 897 ERASEINFO(0x10000, 7), 898 ERASEINFO(0x02000, 8), 899 } 900 }, { 901 .mfr_id = MANUFACTURER_INTEL, 902 .dev_id = I28F008B3B, 903 .name = "Intel 28F008B3B", 904 .devtypes = CFI_DEVICETYPE_X8, 905 .uaddr = MTD_UADDR_UNNECESSARY, 906 .dev_size = SIZE_1MiB, 907 .cmd_set = P_ID_INTEL_STD, 908 .nr_regions = 2, 909 .regions = { 910 ERASEINFO(0x02000, 8), 911 ERASEINFO(0x10000, 15), 912 } 913 }, { 914 .mfr_id = MANUFACTURER_INTEL, 915 .dev_id = I28F008B3T, 916 .name = "Intel 28F008B3T", 917 .devtypes = CFI_DEVICETYPE_X8, 918 .uaddr = MTD_UADDR_UNNECESSARY, 919 .dev_size = SIZE_1MiB, 920 .cmd_set = P_ID_INTEL_STD, 921 .nr_regions = 2, 922 .regions = { 923 ERASEINFO(0x10000, 15), 924 ERASEINFO(0x02000, 8), 925 } 926 }, { 927 .mfr_id = MANUFACTURER_INTEL, 928 .dev_id = I28F008S5, 929 .name = "Intel 28F008S5", 930 .devtypes = CFI_DEVICETYPE_X8, 931 .uaddr = MTD_UADDR_UNNECESSARY, 932 .dev_size = SIZE_1MiB, 933 .cmd_set = P_ID_INTEL_EXT, 934 .nr_regions = 1, 935 .regions = { 936 ERASEINFO(0x10000,16), 937 } 938 }, { 939 .mfr_id = MANUFACTURER_INTEL, 940 .dev_id = I28F016S5, 941 .name = "Intel 28F016S5", 942 .devtypes = CFI_DEVICETYPE_X8, 943 .uaddr = MTD_UADDR_UNNECESSARY, 944 .dev_size = SIZE_2MiB, 945 .cmd_set = P_ID_INTEL_EXT, 946 .nr_regions = 1, 947 .regions = { 948 ERASEINFO(0x10000,32), 949 } 950 }, { 951 .mfr_id = MANUFACTURER_INTEL, 952 .dev_id = I28F008SA, 953 .name = "Intel 28F008SA", 954 .devtypes = CFI_DEVICETYPE_X8, 955 .uaddr = MTD_UADDR_UNNECESSARY, 956 .dev_size = SIZE_1MiB, 957 .cmd_set = P_ID_INTEL_STD, 958 .nr_regions = 1, 959 .regions = { 960 ERASEINFO(0x10000, 16), 961 } 962 }, { 963 .mfr_id = MANUFACTURER_INTEL, 964 .dev_id = I28F800B3B, 965 .name = "Intel 28F800B3B", 966 .devtypes = CFI_DEVICETYPE_X16, 967 .uaddr = MTD_UADDR_UNNECESSARY, 968 .dev_size = SIZE_1MiB, 969 .cmd_set = P_ID_INTEL_STD, 970 .nr_regions = 2, 971 .regions = { 972 ERASEINFO(0x02000, 8), 973 ERASEINFO(0x10000, 15), 974 } 975 }, { 976 .mfr_id = MANUFACTURER_INTEL, 977 .dev_id = I28F800B3T, 978 .name = "Intel 28F800B3T", 979 .devtypes = CFI_DEVICETYPE_X16, 980 .uaddr = MTD_UADDR_UNNECESSARY, 981 .dev_size = SIZE_1MiB, 982 .cmd_set = P_ID_INTEL_STD, 983 .nr_regions = 2, 984 .regions = { 985 ERASEINFO(0x10000, 15), 986 ERASEINFO(0x02000, 8), 987 } 988 }, { 989 .mfr_id = MANUFACTURER_INTEL, 990 .dev_id = I28F016B3B, 991 .name = "Intel 28F016B3B", 992 .devtypes = CFI_DEVICETYPE_X8, 993 .uaddr = MTD_UADDR_UNNECESSARY, 994 .dev_size = SIZE_2MiB, 995 .cmd_set = P_ID_INTEL_STD, 996 .nr_regions = 2, 997 .regions = { 998 ERASEINFO(0x02000, 8), 999 ERASEINFO(0x10000, 31), 1000 } 1001 }, { 1002 .mfr_id = MANUFACTURER_INTEL, 1003 .dev_id = I28F016S3, 1004 .name = "Intel I28F016S3", 1005 .devtypes = CFI_DEVICETYPE_X8, 1006 .uaddr = MTD_UADDR_UNNECESSARY, 1007 .dev_size = SIZE_2MiB, 1008 .cmd_set = P_ID_INTEL_STD, 1009 .nr_regions = 1, 1010 .regions = { 1011 ERASEINFO(0x10000, 32), 1012 } 1013 }, { 1014 .mfr_id = MANUFACTURER_INTEL, 1015 .dev_id = I28F016B3T, 1016 .name = "Intel 28F016B3T", 1017 .devtypes = CFI_DEVICETYPE_X8, 1018 .uaddr = MTD_UADDR_UNNECESSARY, 1019 .dev_size = SIZE_2MiB, 1020 .cmd_set = P_ID_INTEL_STD, 1021 .nr_regions = 2, 1022 .regions = { 1023 ERASEINFO(0x10000, 31), 1024 ERASEINFO(0x02000, 8), 1025 } 1026 }, { 1027 .mfr_id = MANUFACTURER_INTEL, 1028 .dev_id = I28F160B3B, 1029 .name = "Intel 28F160B3B", 1030 .devtypes = CFI_DEVICETYPE_X16, 1031 .uaddr = MTD_UADDR_UNNECESSARY, 1032 .dev_size = SIZE_2MiB, 1033 .cmd_set = P_ID_INTEL_STD, 1034 .nr_regions = 2, 1035 .regions = { 1036 ERASEINFO(0x02000, 8), 1037 ERASEINFO(0x10000, 31), 1038 } 1039 }, { 1040 .mfr_id = MANUFACTURER_INTEL, 1041 .dev_id = I28F160B3T, 1042 .name = "Intel 28F160B3T", 1043 .devtypes = CFI_DEVICETYPE_X16, 1044 .uaddr = MTD_UADDR_UNNECESSARY, 1045 .dev_size = SIZE_2MiB, 1046 .cmd_set = P_ID_INTEL_STD, 1047 .nr_regions = 2, 1048 .regions = { 1049 ERASEINFO(0x10000, 31), 1050 ERASEINFO(0x02000, 8), 1051 } 1052 }, { 1053 .mfr_id = MANUFACTURER_INTEL, 1054 .dev_id = I28F320B3B, 1055 .name = "Intel 28F320B3B", 1056 .devtypes = CFI_DEVICETYPE_X16, 1057 .uaddr = MTD_UADDR_UNNECESSARY, 1058 .dev_size = SIZE_4MiB, 1059 .cmd_set = P_ID_INTEL_STD, 1060 .nr_regions = 2, 1061 .regions = { 1062 ERASEINFO(0x02000, 8), 1063 ERASEINFO(0x10000, 63), 1064 } 1065 }, { 1066 .mfr_id = MANUFACTURER_INTEL, 1067 .dev_id = I28F320B3T, 1068 .name = "Intel 28F320B3T", 1069 .devtypes = CFI_DEVICETYPE_X16, 1070 .uaddr = MTD_UADDR_UNNECESSARY, 1071 .dev_size = SIZE_4MiB, 1072 .cmd_set = P_ID_INTEL_STD, 1073 .nr_regions = 2, 1074 .regions = { 1075 ERASEINFO(0x10000, 63), 1076 ERASEINFO(0x02000, 8), 1077 } 1078 }, { 1079 .mfr_id = MANUFACTURER_INTEL, 1080 .dev_id = I28F640B3B, 1081 .name = "Intel 28F640B3B", 1082 .devtypes = CFI_DEVICETYPE_X16, 1083 .uaddr = MTD_UADDR_UNNECESSARY, 1084 .dev_size = SIZE_8MiB, 1085 .cmd_set = P_ID_INTEL_STD, 1086 .nr_regions = 2, 1087 .regions = { 1088 ERASEINFO(0x02000, 8), 1089 ERASEINFO(0x10000, 127), 1090 } 1091 }, { 1092 .mfr_id = MANUFACTURER_INTEL, 1093 .dev_id = I28F640B3T, 1094 .name = "Intel 28F640B3T", 1095 .devtypes = CFI_DEVICETYPE_X16, 1096 .uaddr = MTD_UADDR_UNNECESSARY, 1097 .dev_size = SIZE_8MiB, 1098 .cmd_set = P_ID_INTEL_STD, 1099 .nr_regions = 2, 1100 .regions = { 1101 ERASEINFO(0x10000, 127), 1102 ERASEINFO(0x02000, 8), 1103 } 1104 }, { 1105 .mfr_id = MANUFACTURER_INTEL, 1106 .dev_id = I82802AB, 1107 .name = "Intel 82802AB", 1108 .devtypes = CFI_DEVICETYPE_X8, 1109 .uaddr = MTD_UADDR_UNNECESSARY, 1110 .dev_size = SIZE_512KiB, 1111 .cmd_set = P_ID_INTEL_EXT, 1112 .nr_regions = 1, 1113 .regions = { 1114 ERASEINFO(0x10000,8), 1115 } 1116 }, { 1117 .mfr_id = MANUFACTURER_INTEL, 1118 .dev_id = I82802AC, 1119 .name = "Intel 82802AC", 1120 .devtypes = CFI_DEVICETYPE_X8, 1121 .uaddr = MTD_UADDR_UNNECESSARY, 1122 .dev_size = SIZE_1MiB, 1123 .cmd_set = P_ID_INTEL_EXT, 1124 .nr_regions = 1, 1125 .regions = { 1126 ERASEINFO(0x10000,16), 1127 } 1128 }, { 1129 .mfr_id = MANUFACTURER_MACRONIX, 1130 .dev_id = MX29LV040C, 1131 .name = "Macronix MX29LV040C", 1132 .devtypes = CFI_DEVICETYPE_X8, 1133 .uaddr = MTD_UADDR_0x0555_0x02AA, 1134 .dev_size = SIZE_512KiB, 1135 .cmd_set = P_ID_AMD_STD, 1136 .nr_regions = 1, 1137 .regions = { 1138 ERASEINFO(0x10000,8), 1139 } 1140 }, { 1141 .mfr_id = MANUFACTURER_MACRONIX, 1142 .dev_id = MX29LV160T, 1143 .name = "MXIC MX29LV160T", 1144 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1145 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1146 .dev_size = SIZE_2MiB, 1147 .cmd_set = P_ID_AMD_STD, 1148 .nr_regions = 4, 1149 .regions = { 1150 ERASEINFO(0x10000,31), 1151 ERASEINFO(0x08000,1), 1152 ERASEINFO(0x02000,2), 1153 ERASEINFO(0x04000,1) 1154 } 1155 }, { 1156 .mfr_id = MANUFACTURER_NEC, 1157 .dev_id = UPD29F064115, 1158 .name = "NEC uPD29F064115", 1159 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1160 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1161 .dev_size = SIZE_8MiB, 1162 .cmd_set = P_ID_AMD_STD, 1163 .nr_regions = 3, 1164 .regions = { 1165 ERASEINFO(0x2000,8), 1166 ERASEINFO(0x10000,126), 1167 ERASEINFO(0x2000,8), 1168 } 1169 }, { 1170 .mfr_id = MANUFACTURER_MACRONIX, 1171 .dev_id = MX29LV160B, 1172 .name = "MXIC MX29LV160B", 1173 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1174 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1175 .dev_size = SIZE_2MiB, 1176 .cmd_set = P_ID_AMD_STD, 1177 .nr_regions = 4, 1178 .regions = { 1179 ERASEINFO(0x04000,1), 1180 ERASEINFO(0x02000,2), 1181 ERASEINFO(0x08000,1), 1182 ERASEINFO(0x10000,31) 1183 } 1184 }, { 1185 .mfr_id = MANUFACTURER_MACRONIX, 1186 .dev_id = MX29F040, 1187 .name = "Macronix MX29F040", 1188 .devtypes = CFI_DEVICETYPE_X8, 1189 .uaddr = MTD_UADDR_0x0555_0x02AA, 1190 .dev_size = SIZE_512KiB, 1191 .cmd_set = P_ID_AMD_STD, 1192 .nr_regions = 1, 1193 .regions = { 1194 ERASEINFO(0x10000,8), 1195 } 1196 }, { 1197 .mfr_id = MANUFACTURER_MACRONIX, 1198 .dev_id = MX29F016, 1199 .name = "Macronix MX29F016", 1200 .devtypes = CFI_DEVICETYPE_X8, 1201 .uaddr = MTD_UADDR_0x0555_0x02AA, 1202 .dev_size = SIZE_2MiB, 1203 .cmd_set = P_ID_AMD_STD, 1204 .nr_regions = 1, 1205 .regions = { 1206 ERASEINFO(0x10000,32), 1207 } 1208 }, { 1209 .mfr_id = MANUFACTURER_MACRONIX, 1210 .dev_id = MX29F004T, 1211 .name = "Macronix MX29F004T", 1212 .devtypes = CFI_DEVICETYPE_X8, 1213 .uaddr = MTD_UADDR_0x0555_0x02AA, 1214 .dev_size = SIZE_512KiB, 1215 .cmd_set = P_ID_AMD_STD, 1216 .nr_regions = 4, 1217 .regions = { 1218 ERASEINFO(0x10000,7), 1219 ERASEINFO(0x08000,1), 1220 ERASEINFO(0x02000,2), 1221 ERASEINFO(0x04000,1), 1222 } 1223 }, { 1224 .mfr_id = MANUFACTURER_MACRONIX, 1225 .dev_id = MX29F004B, 1226 .name = "Macronix MX29F004B", 1227 .devtypes = CFI_DEVICETYPE_X8, 1228 .uaddr = MTD_UADDR_0x0555_0x02AA, 1229 .dev_size = SIZE_512KiB, 1230 .cmd_set = P_ID_AMD_STD, 1231 .nr_regions = 4, 1232 .regions = { 1233 ERASEINFO(0x04000,1), 1234 ERASEINFO(0x02000,2), 1235 ERASEINFO(0x08000,1), 1236 ERASEINFO(0x10000,7), 1237 } 1238 }, { 1239 .mfr_id = MANUFACTURER_MACRONIX, 1240 .dev_id = MX29F002T, 1241 .name = "Macronix MX29F002T", 1242 .devtypes = CFI_DEVICETYPE_X8, 1243 .uaddr = MTD_UADDR_0x0555_0x02AA, 1244 .dev_size = SIZE_256KiB, 1245 .cmd_set = P_ID_AMD_STD, 1246 .nr_regions = 4, 1247 .regions = { 1248 ERASEINFO(0x10000,3), 1249 ERASEINFO(0x08000,1), 1250 ERASEINFO(0x02000,2), 1251 ERASEINFO(0x04000,1), 1252 } 1253 }, { 1254 .mfr_id = MANUFACTURER_PMC, 1255 .dev_id = PM49FL002, 1256 .name = "PMC Pm49FL002", 1257 .devtypes = CFI_DEVICETYPE_X8, 1258 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1259 .dev_size = SIZE_256KiB, 1260 .cmd_set = P_ID_AMD_STD, 1261 .nr_regions = 1, 1262 .regions = { 1263 ERASEINFO( 0x01000, 64 ) 1264 } 1265 }, { 1266 .mfr_id = MANUFACTURER_PMC, 1267 .dev_id = PM49FL004, 1268 .name = "PMC Pm49FL004", 1269 .devtypes = CFI_DEVICETYPE_X8, 1270 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1271 .dev_size = SIZE_512KiB, 1272 .cmd_set = P_ID_AMD_STD, 1273 .nr_regions = 1, 1274 .regions = { 1275 ERASEINFO( 0x01000, 128 ) 1276 } 1277 }, { 1278 .mfr_id = MANUFACTURER_PMC, 1279 .dev_id = PM49FL008, 1280 .name = "PMC Pm49FL008", 1281 .devtypes = CFI_DEVICETYPE_X8, 1282 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1283 .dev_size = SIZE_1MiB, 1284 .cmd_set = P_ID_AMD_STD, 1285 .nr_regions = 1, 1286 .regions = { 1287 ERASEINFO( 0x01000, 256 ) 1288 } 1289 }, { 1290 .mfr_id = MANUFACTURER_SHARP, 1291 .dev_id = LH28F640BF, 1292 .name = "LH28F640BF", 1293 .devtypes = CFI_DEVICETYPE_X8, 1294 .uaddr = MTD_UADDR_UNNECESSARY, 1295 .dev_size = SIZE_4MiB, 1296 .cmd_set = P_ID_INTEL_STD, 1297 .nr_regions = 1, 1298 .regions = { 1299 ERASEINFO(0x40000,16), 1300 } 1301 }, { 1302 .mfr_id = MANUFACTURER_SST, 1303 .dev_id = SST39LF512, 1304 .name = "SST 39LF512", 1305 .devtypes = CFI_DEVICETYPE_X8, 1306 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1307 .dev_size = SIZE_64KiB, 1308 .cmd_set = P_ID_AMD_STD, 1309 .nr_regions = 1, 1310 .regions = { 1311 ERASEINFO(0x01000,16), 1312 } 1313 }, { 1314 .mfr_id = MANUFACTURER_SST, 1315 .dev_id = SST39LF010, 1316 .name = "SST 39LF010", 1317 .devtypes = CFI_DEVICETYPE_X8, 1318 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1319 .dev_size = SIZE_128KiB, 1320 .cmd_set = P_ID_AMD_STD, 1321 .nr_regions = 1, 1322 .regions = { 1323 ERASEINFO(0x01000,32), 1324 } 1325 }, { 1326 .mfr_id = MANUFACTURER_SST, 1327 .dev_id = SST29EE020, 1328 .name = "SST 29EE020", 1329 .devtypes = CFI_DEVICETYPE_X8, 1330 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1331 .dev_size = SIZE_256KiB, 1332 .cmd_set = P_ID_SST_PAGE, 1333 .nr_regions = 1, 1334 .regions = {ERASEINFO(0x01000,64), 1335 } 1336 }, { 1337 .mfr_id = MANUFACTURER_SST, 1338 .dev_id = SST29LE020, 1339 .name = "SST 29LE020", 1340 .devtypes = CFI_DEVICETYPE_X8, 1341 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1342 .dev_size = SIZE_256KiB, 1343 .cmd_set = P_ID_SST_PAGE, 1344 .nr_regions = 1, 1345 .regions = {ERASEINFO(0x01000,64), 1346 } 1347 }, { 1348 .mfr_id = MANUFACTURER_SST, 1349 .dev_id = SST39LF020, 1350 .name = "SST 39LF020", 1351 .devtypes = CFI_DEVICETYPE_X8, 1352 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1353 .dev_size = SIZE_256KiB, 1354 .cmd_set = P_ID_AMD_STD, 1355 .nr_regions = 1, 1356 .regions = { 1357 ERASEINFO(0x01000,64), 1358 } 1359 }, { 1360 .mfr_id = MANUFACTURER_SST, 1361 .dev_id = SST39LF040, 1362 .name = "SST 39LF040", 1363 .devtypes = CFI_DEVICETYPE_X8, 1364 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1365 .dev_size = SIZE_512KiB, 1366 .cmd_set = P_ID_AMD_STD, 1367 .nr_regions = 1, 1368 .regions = { 1369 ERASEINFO(0x01000,128), 1370 } 1371 }, { 1372 .mfr_id = MANUFACTURER_SST, 1373 .dev_id = SST39SF010A, 1374 .name = "SST 39SF010A", 1375 .devtypes = CFI_DEVICETYPE_X8, 1376 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1377 .dev_size = SIZE_128KiB, 1378 .cmd_set = P_ID_AMD_STD, 1379 .nr_regions = 1, 1380 .regions = { 1381 ERASEINFO(0x01000,32), 1382 } 1383 }, { 1384 .mfr_id = MANUFACTURER_SST, 1385 .dev_id = SST39SF020A, 1386 .name = "SST 39SF020A", 1387 .devtypes = CFI_DEVICETYPE_X8, 1388 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1389 .dev_size = SIZE_256KiB, 1390 .cmd_set = P_ID_AMD_STD, 1391 .nr_regions = 1, 1392 .regions = { 1393 ERASEINFO(0x01000,64), 1394 } 1395 }, { 1396 .mfr_id = MANUFACTURER_SST, 1397 .dev_id = SST39SF040, 1398 .name = "SST 39SF040", 1399 .devtypes = CFI_DEVICETYPE_X8, 1400 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1401 .dev_size = SIZE_512KiB, 1402 .cmd_set = P_ID_AMD_STD, 1403 .nr_regions = 1, 1404 .regions = { 1405 ERASEINFO(0x01000,128), 1406 } 1407 }, { 1408 .mfr_id = MANUFACTURER_SST, 1409 .dev_id = SST49LF040B, 1410 .name = "SST 49LF040B", 1411 .devtypes = CFI_DEVICETYPE_X8, 1412 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1413 .dev_size = SIZE_512KiB, 1414 .cmd_set = P_ID_AMD_STD, 1415 .nr_regions = 1, 1416 .regions = { 1417 ERASEINFO(0x01000,128), 1418 } 1419 }, { 1420 1421 .mfr_id = MANUFACTURER_SST, 1422 .dev_id = SST49LF004B, 1423 .name = "SST 49LF004B", 1424 .devtypes = CFI_DEVICETYPE_X8, 1425 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1426 .dev_size = SIZE_512KiB, 1427 .cmd_set = P_ID_AMD_STD, 1428 .nr_regions = 1, 1429 .regions = { 1430 ERASEINFO(0x01000,128), 1431 } 1432 }, { 1433 .mfr_id = MANUFACTURER_SST, 1434 .dev_id = SST49LF008A, 1435 .name = "SST 49LF008A", 1436 .devtypes = CFI_DEVICETYPE_X8, 1437 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1438 .dev_size = SIZE_1MiB, 1439 .cmd_set = P_ID_AMD_STD, 1440 .nr_regions = 1, 1441 .regions = { 1442 ERASEINFO(0x01000,256), 1443 } 1444 }, { 1445 .mfr_id = MANUFACTURER_SST, 1446 .dev_id = SST49LF030A, 1447 .name = "SST 49LF030A", 1448 .devtypes = CFI_DEVICETYPE_X8, 1449 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1450 .dev_size = SIZE_512KiB, 1451 .cmd_set = P_ID_AMD_STD, 1452 .nr_regions = 1, 1453 .regions = { 1454 ERASEINFO(0x01000,96), 1455 } 1456 }, { 1457 .mfr_id = MANUFACTURER_SST, 1458 .dev_id = SST49LF040A, 1459 .name = "SST 49LF040A", 1460 .devtypes = CFI_DEVICETYPE_X8, 1461 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1462 .dev_size = SIZE_512KiB, 1463 .cmd_set = P_ID_AMD_STD, 1464 .nr_regions = 1, 1465 .regions = { 1466 ERASEINFO(0x01000,128), 1467 } 1468 }, { 1469 .mfr_id = MANUFACTURER_SST, 1470 .dev_id = SST49LF080A, 1471 .name = "SST 49LF080A", 1472 .devtypes = CFI_DEVICETYPE_X8, 1473 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1474 .dev_size = SIZE_1MiB, 1475 .cmd_set = P_ID_AMD_STD, 1476 .nr_regions = 1, 1477 .regions = { 1478 ERASEINFO(0x01000,256), 1479 } 1480 }, { 1481 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1482 .dev_id = SST39LF160, 1483 .name = "SST 39LF160", 1484 .devtypes = CFI_DEVICETYPE_X16, 1485 .uaddr = MTD_UADDR_0xAAAA_0x5555, 1486 .dev_size = SIZE_2MiB, 1487 .cmd_set = P_ID_AMD_STD, 1488 .nr_regions = 2, 1489 .regions = { 1490 ERASEINFO(0x1000,256), 1491 ERASEINFO(0x1000,256) 1492 } 1493 }, { 1494 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1495 .dev_id = SST39VF1601, 1496 .name = "SST 39VF1601", 1497 .devtypes = CFI_DEVICETYPE_X16, 1498 .uaddr = MTD_UADDR_0xAAAA_0x5555, 1499 .dev_size = SIZE_2MiB, 1500 .cmd_set = P_ID_AMD_STD, 1501 .nr_regions = 2, 1502 .regions = { 1503 ERASEINFO(0x1000,256), 1504 ERASEINFO(0x1000,256) 1505 } 1506 }, { 1507 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1508 .dev_id = SST39VF3201, 1509 .name = "SST 39VF3201", 1510 .devtypes = CFI_DEVICETYPE_X16, 1511 .uaddr = MTD_UADDR_0xAAAA_0x5555, 1512 .dev_size = SIZE_4MiB, 1513 .cmd_set = P_ID_AMD_STD, 1514 .nr_regions = 4, 1515 .regions = { 1516 ERASEINFO(0x1000,256), 1517 ERASEINFO(0x1000,256), 1518 ERASEINFO(0x1000,256), 1519 ERASEINFO(0x1000,256) 1520 } 1521 }, { 1522 .mfr_id = MANUFACTURER_SST, 1523 .dev_id = SST36VF3203, 1524 .name = "SST 36VF3203", 1525 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1526 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1527 .dev_size = SIZE_4MiB, 1528 .cmd_set = P_ID_AMD_STD, 1529 .nr_regions = 1, 1530 .regions = { 1531 ERASEINFO(0x10000,64), 1532 } 1533 }, { 1534 .mfr_id = MANUFACTURER_ST, 1535 .dev_id = M29F800AB, 1536 .name = "ST M29F800AB", 1537 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1538 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1539 .dev_size = SIZE_1MiB, 1540 .cmd_set = P_ID_AMD_STD, 1541 .nr_regions = 4, 1542 .regions = { 1543 ERASEINFO(0x04000,1), 1544 ERASEINFO(0x02000,2), 1545 ERASEINFO(0x08000,1), 1546 ERASEINFO(0x10000,15), 1547 } 1548 }, { 1549 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1550 .dev_id = M29W800DT, 1551 .name = "ST M29W800DT", 1552 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1553 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1554 .dev_size = SIZE_1MiB, 1555 .cmd_set = P_ID_AMD_STD, 1556 .nr_regions = 4, 1557 .regions = { 1558 ERASEINFO(0x10000,15), 1559 ERASEINFO(0x08000,1), 1560 ERASEINFO(0x02000,2), 1561 ERASEINFO(0x04000,1) 1562 } 1563 }, { 1564 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1565 .dev_id = M29W800DB, 1566 .name = "ST M29W800DB", 1567 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1568 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1569 .dev_size = SIZE_1MiB, 1570 .cmd_set = P_ID_AMD_STD, 1571 .nr_regions = 4, 1572 .regions = { 1573 ERASEINFO(0x04000,1), 1574 ERASEINFO(0x02000,2), 1575 ERASEINFO(0x08000,1), 1576 ERASEINFO(0x10000,15) 1577 } 1578 }, { 1579 .mfr_id = MANUFACTURER_ST, 1580 .dev_id = M29W400DT, 1581 .name = "ST M29W400DT", 1582 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1583 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1584 .dev_size = SIZE_512KiB, 1585 .cmd_set = P_ID_AMD_STD, 1586 .nr_regions = 4, 1587 .regions = { 1588 ERASEINFO(0x04000,7), 1589 ERASEINFO(0x02000,1), 1590 ERASEINFO(0x08000,2), 1591 ERASEINFO(0x10000,1) 1592 } 1593 }, { 1594 .mfr_id = MANUFACTURER_ST, 1595 .dev_id = M29W400DB, 1596 .name = "ST M29W400DB", 1597 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1598 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1599 .dev_size = SIZE_512KiB, 1600 .cmd_set = P_ID_AMD_STD, 1601 .nr_regions = 4, 1602 .regions = { 1603 ERASEINFO(0x04000,1), 1604 ERASEINFO(0x02000,2), 1605 ERASEINFO(0x08000,1), 1606 ERASEINFO(0x10000,7) 1607 } 1608 }, { 1609 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1610 .dev_id = M29W160DT, 1611 .name = "ST M29W160DT", 1612 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1613 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1614 .dev_size = SIZE_2MiB, 1615 .cmd_set = P_ID_AMD_STD, 1616 .nr_regions = 4, 1617 .regions = { 1618 ERASEINFO(0x10000,31), 1619 ERASEINFO(0x08000,1), 1620 ERASEINFO(0x02000,2), 1621 ERASEINFO(0x04000,1) 1622 } 1623 }, { 1624 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1625 .dev_id = M29W160DB, 1626 .name = "ST M29W160DB", 1627 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1628 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1629 .dev_size = SIZE_2MiB, 1630 .cmd_set = P_ID_AMD_STD, 1631 .nr_regions = 4, 1632 .regions = { 1633 ERASEINFO(0x04000,1), 1634 ERASEINFO(0x02000,2), 1635 ERASEINFO(0x08000,1), 1636 ERASEINFO(0x10000,31) 1637 } 1638 }, { 1639 .mfr_id = MANUFACTURER_ST, 1640 .dev_id = M29W040B, 1641 .name = "ST M29W040B", 1642 .devtypes = CFI_DEVICETYPE_X8, 1643 .uaddr = MTD_UADDR_0x0555_0x02AA, 1644 .dev_size = SIZE_512KiB, 1645 .cmd_set = P_ID_AMD_STD, 1646 .nr_regions = 1, 1647 .regions = { 1648 ERASEINFO(0x10000,8), 1649 } 1650 }, { 1651 .mfr_id = MANUFACTURER_ST, 1652 .dev_id = M50FW040, 1653 .name = "ST M50FW040", 1654 .devtypes = CFI_DEVICETYPE_X8, 1655 .uaddr = MTD_UADDR_UNNECESSARY, 1656 .dev_size = SIZE_512KiB, 1657 .cmd_set = P_ID_INTEL_EXT, 1658 .nr_regions = 1, 1659 .regions = { 1660 ERASEINFO(0x10000,8), 1661 } 1662 }, { 1663 .mfr_id = MANUFACTURER_ST, 1664 .dev_id = M50FW080, 1665 .name = "ST M50FW080", 1666 .devtypes = CFI_DEVICETYPE_X8, 1667 .uaddr = MTD_UADDR_UNNECESSARY, 1668 .dev_size = SIZE_1MiB, 1669 .cmd_set = P_ID_INTEL_EXT, 1670 .nr_regions = 1, 1671 .regions = { 1672 ERASEINFO(0x10000,16), 1673 } 1674 }, { 1675 .mfr_id = MANUFACTURER_ST, 1676 .dev_id = M50FW016, 1677 .name = "ST M50FW016", 1678 .devtypes = CFI_DEVICETYPE_X8, 1679 .uaddr = MTD_UADDR_UNNECESSARY, 1680 .dev_size = SIZE_2MiB, 1681 .cmd_set = P_ID_INTEL_EXT, 1682 .nr_regions = 1, 1683 .regions = { 1684 ERASEINFO(0x10000,32), 1685 } 1686 }, { 1687 .mfr_id = MANUFACTURER_ST, 1688 .dev_id = M50LPW080, 1689 .name = "ST M50LPW080", 1690 .devtypes = CFI_DEVICETYPE_X8, 1691 .uaddr = MTD_UADDR_UNNECESSARY, 1692 .dev_size = SIZE_1MiB, 1693 .cmd_set = P_ID_INTEL_EXT, 1694 .nr_regions = 1, 1695 .regions = { 1696 ERASEINFO(0x10000,16), 1697 }, 1698 }, { 1699 .mfr_id = MANUFACTURER_ST, 1700 .dev_id = M50FLW080A, 1701 .name = "ST M50FLW080A", 1702 .devtypes = CFI_DEVICETYPE_X8, 1703 .uaddr = MTD_UADDR_UNNECESSARY, 1704 .dev_size = SIZE_1MiB, 1705 .cmd_set = P_ID_INTEL_EXT, 1706 .nr_regions = 4, 1707 .regions = { 1708 ERASEINFO(0x1000,16), 1709 ERASEINFO(0x10000,13), 1710 ERASEINFO(0x1000,16), 1711 ERASEINFO(0x1000,16), 1712 } 1713 }, { 1714 .mfr_id = MANUFACTURER_ST, 1715 .dev_id = M50FLW080B, 1716 .name = "ST M50FLW080B", 1717 .devtypes = CFI_DEVICETYPE_X8, 1718 .uaddr = MTD_UADDR_UNNECESSARY, 1719 .dev_size = SIZE_1MiB, 1720 .cmd_set = P_ID_INTEL_EXT, 1721 .nr_regions = 4, 1722 .regions = { 1723 ERASEINFO(0x1000,16), 1724 ERASEINFO(0x1000,16), 1725 ERASEINFO(0x10000,13), 1726 ERASEINFO(0x1000,16), 1727 } 1728 }, { 1729 .mfr_id = MANUFACTURER_TOSHIBA, 1730 .dev_id = TC58FVT160, 1731 .name = "Toshiba TC58FVT160", 1732 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1733 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1734 .dev_size = SIZE_2MiB, 1735 .cmd_set = P_ID_AMD_STD, 1736 .nr_regions = 4, 1737 .regions = { 1738 ERASEINFO(0x10000,31), 1739 ERASEINFO(0x08000,1), 1740 ERASEINFO(0x02000,2), 1741 ERASEINFO(0x04000,1) 1742 } 1743 }, { 1744 .mfr_id = MANUFACTURER_TOSHIBA, 1745 .dev_id = TC58FVB160, 1746 .name = "Toshiba TC58FVB160", 1747 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1748 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1749 .dev_size = SIZE_2MiB, 1750 .cmd_set = P_ID_AMD_STD, 1751 .nr_regions = 4, 1752 .regions = { 1753 ERASEINFO(0x04000,1), 1754 ERASEINFO(0x02000,2), 1755 ERASEINFO(0x08000,1), 1756 ERASEINFO(0x10000,31) 1757 } 1758 }, { 1759 .mfr_id = MANUFACTURER_TOSHIBA, 1760 .dev_id = TC58FVB321, 1761 .name = "Toshiba TC58FVB321", 1762 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1763 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1764 .dev_size = SIZE_4MiB, 1765 .cmd_set = P_ID_AMD_STD, 1766 .nr_regions = 2, 1767 .regions = { 1768 ERASEINFO(0x02000,8), 1769 ERASEINFO(0x10000,63) 1770 } 1771 }, { 1772 .mfr_id = MANUFACTURER_TOSHIBA, 1773 .dev_id = TC58FVT321, 1774 .name = "Toshiba TC58FVT321", 1775 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1776 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1777 .dev_size = SIZE_4MiB, 1778 .cmd_set = P_ID_AMD_STD, 1779 .nr_regions = 2, 1780 .regions = { 1781 ERASEINFO(0x10000,63), 1782 ERASEINFO(0x02000,8) 1783 } 1784 }, { 1785 .mfr_id = MANUFACTURER_TOSHIBA, 1786 .dev_id = TC58FVB641, 1787 .name = "Toshiba TC58FVB641", 1788 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1789 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1790 .dev_size = SIZE_8MiB, 1791 .cmd_set = P_ID_AMD_STD, 1792 .nr_regions = 2, 1793 .regions = { 1794 ERASEINFO(0x02000,8), 1795 ERASEINFO(0x10000,127) 1796 } 1797 }, { 1798 .mfr_id = MANUFACTURER_TOSHIBA, 1799 .dev_id = TC58FVT641, 1800 .name = "Toshiba TC58FVT641", 1801 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1802 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1803 .dev_size = SIZE_8MiB, 1804 .cmd_set = P_ID_AMD_STD, 1805 .nr_regions = 2, 1806 .regions = { 1807 ERASEINFO(0x10000,127), 1808 ERASEINFO(0x02000,8) 1809 } 1810 }, { 1811 .mfr_id = MANUFACTURER_WINBOND, 1812 .dev_id = W49V002A, 1813 .name = "Winbond W49V002A", 1814 .devtypes = CFI_DEVICETYPE_X8, 1815 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1816 .dev_size = SIZE_256KiB, 1817 .cmd_set = P_ID_AMD_STD, 1818 .nr_regions = 4, 1819 .regions = { 1820 ERASEINFO(0x10000, 3), 1821 ERASEINFO(0x08000, 1), 1822 ERASEINFO(0x02000, 2), 1823 ERASEINFO(0x04000, 1), 1824 } 1825 } 1826 }; 1827 1828 static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, 1829 struct cfi_private *cfi) 1830 { 1831 map_word result; 1832 unsigned long mask; 1833 int bank = 0; 1834 1835 /* According to JEDEC "Standard Manufacturer's Identification Code" 1836 * (http://www.jedec.org/download/search/jep106W.pdf) 1837 * several first banks can contain 0x7f instead of actual ID 1838 */ 1839 do { 1840 uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi); 1841 mask = (1 << (cfi->device_type * 8)) - 1; 1842 result = map_read(map, base + ofs); 1843 bank++; 1844 } while ((result.x[0] & mask) == CONTINUATION_CODE); 1845 1846 return result.x[0] & mask; 1847 } 1848 1849 static inline u32 jedec_read_id(struct map_info *map, uint32_t base, 1850 struct cfi_private *cfi) 1851 { 1852 map_word result; 1853 unsigned long mask; 1854 u32 ofs = cfi_build_cmd_addr(1, map, cfi); 1855 mask = (1 << (cfi->device_type * 8)) -1; 1856 result = map_read(map, base + ofs); 1857 return result.x[0] & mask; 1858 } 1859 1860 static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi) 1861 { 1862 /* Reset */ 1863 1864 /* after checking the datasheets for SST, MACRONIX and ATMEL 1865 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset 1866 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at 1867 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips 1868 * as they will ignore the writes and dont care what address 1869 * the F0 is written to */ 1870 if (cfi->addr_unlock1) { 1871 DEBUG( MTD_DEBUG_LEVEL3, 1872 "reset unlock called %x %x \n", 1873 cfi->addr_unlock1,cfi->addr_unlock2); 1874 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1875 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1876 } 1877 1878 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1879 /* Some misdesigned Intel chips do not respond for 0xF0 for a reset, 1880 * so ensure we're in read mode. Send both the Intel and the AMD command 1881 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so 1882 * this should be safe. 1883 */ 1884 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); 1885 /* FIXME - should have reset delay before continuing */ 1886 } 1887 1888 1889 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index) 1890 { 1891 int i,num_erase_regions; 1892 uint8_t uaddr; 1893 1894 if (! (jedec_table[index].devtypes & p_cfi->device_type)) { 1895 DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n", 1896 jedec_table[index].name, 4 * (1<<p_cfi->device_type)); 1897 return 0; 1898 } 1899 1900 printk(KERN_INFO "Found: %s\n",jedec_table[index].name); 1901 1902 num_erase_regions = jedec_table[index].nr_regions; 1903 1904 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); 1905 if (!p_cfi->cfiq) { 1906 //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name); 1907 return 0; 1908 } 1909 1910 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident)); 1911 1912 p_cfi->cfiq->P_ID = jedec_table[index].cmd_set; 1913 p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions; 1914 p_cfi->cfiq->DevSize = jedec_table[index].dev_size; 1915 p_cfi->cfi_mode = CFI_MODE_JEDEC; 1916 1917 for (i=0; i<num_erase_regions; i++){ 1918 p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i]; 1919 } 1920 p_cfi->cmdset_priv = NULL; 1921 1922 /* This may be redundant for some cases, but it doesn't hurt */ 1923 p_cfi->mfr = jedec_table[index].mfr_id; 1924 p_cfi->id = jedec_table[index].dev_id; 1925 1926 uaddr = jedec_table[index].uaddr; 1927 1928 /* The table has unlock addresses in _bytes_, and we try not to let 1929 our brains explode when we see the datasheets talking about address 1930 lines numbered from A-1 to A18. The CFI table has unlock addresses 1931 in device-words according to the mode the device is connected in */ 1932 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type; 1933 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type; 1934 1935 return 1; /* ok */ 1936 } 1937 1938 1939 /* 1940 * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing 1941 * the mapped address, unlock addresses, and proper chip ID. This function 1942 * attempts to minimize errors. It is doubtfull that this probe will ever 1943 * be perfect - consequently there should be some module parameters that 1944 * could be manually specified to force the chip info. 1945 */ 1946 static inline int jedec_match( uint32_t base, 1947 struct map_info *map, 1948 struct cfi_private *cfi, 1949 const struct amd_flash_info *finfo ) 1950 { 1951 int rc = 0; /* failure until all tests pass */ 1952 u32 mfr, id; 1953 uint8_t uaddr; 1954 1955 /* 1956 * The IDs must match. For X16 and X32 devices operating in 1957 * a lower width ( X8 or X16 ), the device ID's are usually just 1958 * the lower byte(s) of the larger device ID for wider mode. If 1959 * a part is found that doesn't fit this assumption (device id for 1960 * smaller width mode is completely unrealated to full-width mode) 1961 * then the jedec_table[] will have to be augmented with the IDs 1962 * for different widths. 1963 */ 1964 switch (cfi->device_type) { 1965 case CFI_DEVICETYPE_X8: 1966 mfr = (uint8_t)finfo->mfr_id; 1967 id = (uint8_t)finfo->dev_id; 1968 1969 /* bjd: it seems that if we do this, we can end up 1970 * detecting 16bit flashes as an 8bit device, even though 1971 * there aren't. 1972 */ 1973 if (finfo->dev_id > 0xff) { 1974 DEBUG( MTD_DEBUG_LEVEL3, "%s(): ID is not 8bit\n", 1975 __func__); 1976 goto match_done; 1977 } 1978 break; 1979 case CFI_DEVICETYPE_X16: 1980 mfr = (uint16_t)finfo->mfr_id; 1981 id = (uint16_t)finfo->dev_id; 1982 break; 1983 case CFI_DEVICETYPE_X32: 1984 mfr = (uint16_t)finfo->mfr_id; 1985 id = (uint32_t)finfo->dev_id; 1986 break; 1987 default: 1988 printk(KERN_WARNING 1989 "MTD %s(): Unsupported device type %d\n", 1990 __func__, cfi->device_type); 1991 goto match_done; 1992 } 1993 if ( cfi->mfr != mfr || cfi->id != id ) { 1994 goto match_done; 1995 } 1996 1997 /* the part size must fit in the memory window */ 1998 DEBUG( MTD_DEBUG_LEVEL3, 1999 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n", 2000 __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) ); 2001 if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) { 2002 DEBUG( MTD_DEBUG_LEVEL3, 2003 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n", 2004 __func__, finfo->mfr_id, finfo->dev_id, 2005 1 << finfo->dev_size ); 2006 goto match_done; 2007 } 2008 2009 if (! (finfo->devtypes & cfi->device_type)) 2010 goto match_done; 2011 2012 uaddr = finfo->uaddr; 2013 2014 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n", 2015 __func__, cfi->addr_unlock1, cfi->addr_unlock2 ); 2016 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr 2017 && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 || 2018 unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) { 2019 DEBUG( MTD_DEBUG_LEVEL3, 2020 "MTD %s(): 0x%.4x 0x%.4x did not match\n", 2021 __func__, 2022 unlock_addrs[uaddr].addr1, 2023 unlock_addrs[uaddr].addr2); 2024 goto match_done; 2025 } 2026 2027 /* 2028 * Make sure the ID's dissappear when the device is taken out of 2029 * ID mode. The only time this should fail when it should succeed 2030 * is when the ID's are written as data to the same 2031 * addresses. For this rare and unfortunate case the chip 2032 * cannot be probed correctly. 2033 * FIXME - write a driver that takes all of the chip info as 2034 * module parameters, doesn't probe but forces a load. 2035 */ 2036 DEBUG( MTD_DEBUG_LEVEL3, 2037 "MTD %s(): check ID's disappear when not in ID mode\n", 2038 __func__ ); 2039 jedec_reset( base, map, cfi ); 2040 mfr = jedec_read_mfr( map, base, cfi ); 2041 id = jedec_read_id( map, base, cfi ); 2042 if ( mfr == cfi->mfr && id == cfi->id ) { 2043 DEBUG( MTD_DEBUG_LEVEL3, 2044 "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n" 2045 "You might need to manually specify JEDEC parameters.\n", 2046 __func__, cfi->mfr, cfi->id ); 2047 goto match_done; 2048 } 2049 2050 /* all tests passed - mark as success */ 2051 rc = 1; 2052 2053 /* 2054 * Put the device back in ID mode - only need to do this if we 2055 * were truly frobbing a real device. 2056 */ 2057 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ ); 2058 if (cfi->addr_unlock1) { 2059 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2060 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 2061 } 2062 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2063 /* FIXME - should have a delay before continuing */ 2064 2065 match_done: 2066 return rc; 2067 } 2068 2069 2070 static int jedec_probe_chip(struct map_info *map, __u32 base, 2071 unsigned long *chip_map, struct cfi_private *cfi) 2072 { 2073 int i; 2074 enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED; 2075 u32 probe_offset1, probe_offset2; 2076 2077 retry: 2078 if (!cfi->numchips) { 2079 uaddr_idx++; 2080 2081 if (MTD_UADDR_UNNECESSARY == uaddr_idx) 2082 return 0; 2083 2084 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type; 2085 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type; 2086 } 2087 2088 /* Make certain we aren't probing past the end of map */ 2089 if (base >= map->size) { 2090 printk(KERN_NOTICE 2091 "Probe at base(0x%08x) past the end of the map(0x%08lx)\n", 2092 base, map->size -1); 2093 return 0; 2094 2095 } 2096 /* Ensure the unlock addresses we try stay inside the map */ 2097 probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi); 2098 probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi); 2099 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || 2100 ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) 2101 goto retry; 2102 2103 /* Reset */ 2104 jedec_reset(base, map, cfi); 2105 2106 /* Autoselect Mode */ 2107 if(cfi->addr_unlock1) { 2108 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2109 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 2110 } 2111 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2112 /* FIXME - should have a delay before continuing */ 2113 2114 if (!cfi->numchips) { 2115 /* This is the first time we're called. Set up the CFI 2116 stuff accordingly and return */ 2117 2118 cfi->mfr = jedec_read_mfr(map, base, cfi); 2119 cfi->id = jedec_read_id(map, base, cfi); 2120 DEBUG(MTD_DEBUG_LEVEL3, 2121 "Search for id:(%02x %02x) interleave(%d) type(%d)\n", 2122 cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type); 2123 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { 2124 if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) { 2125 DEBUG( MTD_DEBUG_LEVEL3, 2126 "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n", 2127 __func__, cfi->mfr, cfi->id, 2128 cfi->addr_unlock1, cfi->addr_unlock2 ); 2129 if (!cfi_jedec_setup(cfi, i)) 2130 return 0; 2131 goto ok_out; 2132 } 2133 } 2134 goto retry; 2135 } else { 2136 uint16_t mfr; 2137 uint16_t id; 2138 2139 /* Make sure it is a chip of the same manufacturer and id */ 2140 mfr = jedec_read_mfr(map, base, cfi); 2141 id = jedec_read_id(map, base, cfi); 2142 2143 if ((mfr != cfi->mfr) || (id != cfi->id)) { 2144 printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n", 2145 map->name, mfr, id, base); 2146 jedec_reset(base, map, cfi); 2147 return 0; 2148 } 2149 } 2150 2151 /* Check each previous chip locations to see if it's an alias */ 2152 for (i=0; i < (base >> cfi->chipshift); i++) { 2153 unsigned long start; 2154 if(!test_bit(i, chip_map)) { 2155 continue; /* Skip location; no valid chip at this address */ 2156 } 2157 start = i << cfi->chipshift; 2158 if (jedec_read_mfr(map, start, cfi) == cfi->mfr && 2159 jedec_read_id(map, start, cfi) == cfi->id) { 2160 /* Eep. This chip also looks like it's in autoselect mode. 2161 Is it an alias for the new one? */ 2162 jedec_reset(start, map, cfi); 2163 2164 /* If the device IDs go away, it's an alias */ 2165 if (jedec_read_mfr(map, base, cfi) != cfi->mfr || 2166 jedec_read_id(map, base, cfi) != cfi->id) { 2167 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 2168 map->name, base, start); 2169 return 0; 2170 } 2171 2172 /* Yes, it's actually got the device IDs as data. Most 2173 * unfortunate. Stick the new chip in read mode 2174 * too and if it's the same, assume it's an alias. */ 2175 /* FIXME: Use other modes to do a proper check */ 2176 jedec_reset(base, map, cfi); 2177 if (jedec_read_mfr(map, base, cfi) == cfi->mfr && 2178 jedec_read_id(map, base, cfi) == cfi->id) { 2179 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 2180 map->name, base, start); 2181 return 0; 2182 } 2183 } 2184 } 2185 2186 /* OK, if we got to here, then none of the previous chips appear to 2187 be aliases for the current one. */ 2188 set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ 2189 cfi->numchips++; 2190 2191 ok_out: 2192 /* Put it back into Read Mode */ 2193 jedec_reset(base, map, cfi); 2194 2195 printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", 2196 map->name, cfi_interleave(cfi), cfi->device_type*8, base, 2197 map->bankwidth*8); 2198 2199 return 1; 2200 } 2201 2202 static struct chip_probe jedec_chip_probe = { 2203 .name = "JEDEC", 2204 .probe_chip = jedec_probe_chip 2205 }; 2206 2207 static struct mtd_info *jedec_probe(struct map_info *map) 2208 { 2209 /* 2210 * Just use the generic probe stuff to call our CFI-specific 2211 * chip_probe routine in all the possible permutations, etc. 2212 */ 2213 return mtd_do_chip_probe(map, &jedec_chip_probe); 2214 } 2215 2216 static struct mtd_chip_driver jedec_chipdrv = { 2217 .probe = jedec_probe, 2218 .name = "jedec_probe", 2219 .module = THIS_MODULE 2220 }; 2221 2222 static int __init jedec_probe_init(void) 2223 { 2224 register_mtd_chip_driver(&jedec_chipdrv); 2225 return 0; 2226 } 2227 2228 static void __exit jedec_probe_exit(void) 2229 { 2230 unregister_mtd_chip_driver(&jedec_chipdrv); 2231 } 2232 2233 module_init(jedec_probe_init); 2234 module_exit(jedec_probe_exit); 2235 2236 MODULE_LICENSE("GPL"); 2237 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al."); 2238 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips"); 2239