1 /* 2 * Common Flash Interface support: 3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002) 4 * 5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp> 6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com> 7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com> 8 * 9 * 2_by_8 routines added by Simon Munton 10 * 11 * 4_by_16 work by Carolyn J. Smith 12 * 13 * XIP support hooks by Vitaly Wool (based on code for Intel flash 14 * by Nicolas Pitre) 15 * 16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0 17 * 18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 19 * 20 * This code is GPL 21 */ 22 23 #include <linux/module.h> 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/sched.h> 27 #include <asm/io.h> 28 #include <asm/byteorder.h> 29 30 #include <linux/errno.h> 31 #include <linux/slab.h> 32 #include <linux/delay.h> 33 #include <linux/interrupt.h> 34 #include <linux/reboot.h> 35 #include <linux/of.h> 36 #include <linux/of_platform.h> 37 #include <linux/mtd/map.h> 38 #include <linux/mtd/mtd.h> 39 #include <linux/mtd/cfi.h> 40 #include <linux/mtd/xip.h> 41 42 #define AMD_BOOTLOC_BUG 43 #define FORCE_WORD_WRITE 0 44 45 #define MAX_RETRIES 3 46 47 #define SST49LF004B 0x0060 48 #define SST49LF040B 0x0050 49 #define SST49LF008A 0x005a 50 #define AT49BV6416 0x00d6 51 52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); 53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); 54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); 55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); 56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); 57 static void cfi_amdstd_sync (struct mtd_info *); 58 static int cfi_amdstd_suspend (struct mtd_info *); 59 static void cfi_amdstd_resume (struct mtd_info *); 60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *); 61 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t, 62 size_t *, struct otp_info *); 63 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t, 64 size_t *, struct otp_info *); 65 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); 66 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t, 67 size_t *, u_char *); 68 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t, 69 size_t *, u_char *); 70 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t, 71 size_t *, u_char *); 72 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t); 73 74 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, 75 size_t *retlen, const u_char *buf); 76 77 static void cfi_amdstd_destroy(struct mtd_info *); 78 79 struct mtd_info *cfi_cmdset_0002(struct map_info *, int); 80 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *); 81 82 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode); 83 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr); 84 #include "fwh_lock.h" 85 86 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 87 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 88 89 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 90 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 91 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len); 92 93 static struct mtd_chip_driver cfi_amdstd_chipdrv = { 94 .probe = NULL, /* Not usable directly */ 95 .destroy = cfi_amdstd_destroy, 96 .name = "cfi_cmdset_0002", 97 .module = THIS_MODULE 98 }; 99 100 101 /* #define DEBUG_CFI_FEATURES */ 102 103 104 #ifdef DEBUG_CFI_FEATURES 105 static void cfi_tell_features(struct cfi_pri_amdstd *extp) 106 { 107 const char* erase_suspend[3] = { 108 "Not supported", "Read only", "Read/write" 109 }; 110 const char* top_bottom[6] = { 111 "No WP", "8x8KiB sectors at top & bottom, no WP", 112 "Bottom boot", "Top boot", 113 "Uniform, Bottom WP", "Uniform, Top WP" 114 }; 115 116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1); 117 printk(" Address sensitive unlock: %s\n", 118 (extp->SiliconRevision & 1) ? "Not required" : "Required"); 119 120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend)) 121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]); 122 else 123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend); 124 125 if (extp->BlkProt == 0) 126 printk(" Block protection: Not supported\n"); 127 else 128 printk(" Block protection: %d sectors per group\n", extp->BlkProt); 129 130 131 printk(" Temporary block unprotect: %s\n", 132 extp->TmpBlkUnprotect ? "Supported" : "Not supported"); 133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot); 134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps); 135 printk(" Burst mode: %s\n", 136 extp->BurstMode ? "Supported" : "Not supported"); 137 if (extp->PageMode == 0) 138 printk(" Page mode: Not supported\n"); 139 else 140 printk(" Page mode: %d word page\n", extp->PageMode << 2); 141 142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n", 143 extp->VppMin >> 4, extp->VppMin & 0xf); 144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n", 145 extp->VppMax >> 4, extp->VppMax & 0xf); 146 147 if (extp->TopBottom < ARRAY_SIZE(top_bottom)) 148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]); 149 else 150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom); 151 } 152 #endif 153 154 #ifdef AMD_BOOTLOC_BUG 155 /* Wheee. Bring me the head of someone at AMD. */ 156 static void fixup_amd_bootblock(struct mtd_info *mtd) 157 { 158 struct map_info *map = mtd->priv; 159 struct cfi_private *cfi = map->fldrv_priv; 160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; 161 __u8 major = extp->MajorVersion; 162 __u8 minor = extp->MinorVersion; 163 164 if (((major << 8) | minor) < 0x3131) { 165 /* CFI version 1.0 => don't trust bootloc */ 166 167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n", 168 map->name, cfi->mfr, cfi->id); 169 170 /* AFAICS all 29LV400 with a bottom boot block have a device ID 171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode. 172 * These were badly detected as they have the 0x80 bit set 173 * so treat them as a special case. 174 */ 175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) && 176 177 /* Macronix added CFI to their 2nd generation 178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD, 179 * Fujitsu, Spansion, EON, ESI and older Macronix) 180 * has CFI. 181 * 182 * Therefore also check the manufacturer. 183 * This reduces the risk of false detection due to 184 * the 8-bit device ID. 185 */ 186 (cfi->mfr == CFI_MFR_MACRONIX)) { 187 pr_debug("%s: Macronix MX29LV400C with bottom boot block" 188 " detected\n", map->name); 189 extp->TopBottom = 2; /* bottom boot */ 190 } else 191 if (cfi->id & 0x80) { 192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id); 193 extp->TopBottom = 3; /* top boot */ 194 } else { 195 extp->TopBottom = 2; /* bottom boot */ 196 } 197 198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;" 199 " deduced %s from Device ID\n", map->name, major, minor, 200 extp->TopBottom == 2 ? "bottom" : "top"); 201 } 202 } 203 #endif 204 205 static void fixup_use_write_buffers(struct mtd_info *mtd) 206 { 207 struct map_info *map = mtd->priv; 208 struct cfi_private *cfi = map->fldrv_priv; 209 if (cfi->cfiq->BufWriteTimeoutTyp) { 210 pr_debug("Using buffer write method\n"); 211 mtd->_write = cfi_amdstd_write_buffers; 212 } 213 } 214 215 /* Atmel chips don't use the same PRI format as AMD chips */ 216 static void fixup_convert_atmel_pri(struct mtd_info *mtd) 217 { 218 struct map_info *map = mtd->priv; 219 struct cfi_private *cfi = map->fldrv_priv; 220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; 221 struct cfi_pri_atmel atmel_pri; 222 223 memcpy(&atmel_pri, extp, sizeof(atmel_pri)); 224 memset((char *)extp + 5, 0, sizeof(*extp) - 5); 225 226 if (atmel_pri.Features & 0x02) 227 extp->EraseSuspend = 2; 228 229 /* Some chips got it backwards... */ 230 if (cfi->id == AT49BV6416) { 231 if (atmel_pri.BottomBoot) 232 extp->TopBottom = 3; 233 else 234 extp->TopBottom = 2; 235 } else { 236 if (atmel_pri.BottomBoot) 237 extp->TopBottom = 2; 238 else 239 extp->TopBottom = 3; 240 } 241 242 /* burst write mode not supported */ 243 cfi->cfiq->BufWriteTimeoutTyp = 0; 244 cfi->cfiq->BufWriteTimeoutMax = 0; 245 } 246 247 static void fixup_use_secsi(struct mtd_info *mtd) 248 { 249 /* Setup for chips with a secsi area */ 250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read; 251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read; 252 } 253 254 static void fixup_use_erase_chip(struct mtd_info *mtd) 255 { 256 struct map_info *map = mtd->priv; 257 struct cfi_private *cfi = map->fldrv_priv; 258 if ((cfi->cfiq->NumEraseRegions == 1) && 259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) { 260 mtd->_erase = cfi_amdstd_erase_chip; 261 } 262 263 } 264 265 /* 266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors 267 * locked by default. 268 */ 269 static void fixup_use_atmel_lock(struct mtd_info *mtd) 270 { 271 mtd->_lock = cfi_atmel_lock; 272 mtd->_unlock = cfi_atmel_unlock; 273 mtd->flags |= MTD_POWERUP_LOCK; 274 } 275 276 static void fixup_old_sst_eraseregion(struct mtd_info *mtd) 277 { 278 struct map_info *map = mtd->priv; 279 struct cfi_private *cfi = map->fldrv_priv; 280 281 /* 282 * These flashes report two separate eraseblock regions based on the 283 * sector_erase-size and block_erase-size, although they both operate on the 284 * same memory. This is not allowed according to CFI, so we just pick the 285 * sector_erase-size. 286 */ 287 cfi->cfiq->NumEraseRegions = 1; 288 } 289 290 static void fixup_sst39vf(struct mtd_info *mtd) 291 { 292 struct map_info *map = mtd->priv; 293 struct cfi_private *cfi = map->fldrv_priv; 294 295 fixup_old_sst_eraseregion(mtd); 296 297 cfi->addr_unlock1 = 0x5555; 298 cfi->addr_unlock2 = 0x2AAA; 299 } 300 301 static void fixup_sst39vf_rev_b(struct mtd_info *mtd) 302 { 303 struct map_info *map = mtd->priv; 304 struct cfi_private *cfi = map->fldrv_priv; 305 306 fixup_old_sst_eraseregion(mtd); 307 308 cfi->addr_unlock1 = 0x555; 309 cfi->addr_unlock2 = 0x2AA; 310 311 cfi->sector_erase_cmd = CMD(0x50); 312 } 313 314 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd) 315 { 316 struct map_info *map = mtd->priv; 317 struct cfi_private *cfi = map->fldrv_priv; 318 319 fixup_sst39vf_rev_b(mtd); 320 321 /* 322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where 323 * it should report a size of 8KBytes (0x0020*256). 324 */ 325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff; 326 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", 327 mtd->name); 328 } 329 330 static void fixup_s29gl064n_sectors(struct mtd_info *mtd) 331 { 332 struct map_info *map = mtd->priv; 333 struct cfi_private *cfi = map->fldrv_priv; 334 335 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) { 336 cfi->cfiq->EraseRegionInfo[0] |= 0x0040; 337 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n", 338 mtd->name); 339 } 340 } 341 342 static void fixup_s29gl032n_sectors(struct mtd_info *mtd) 343 { 344 struct map_info *map = mtd->priv; 345 struct cfi_private *cfi = map->fldrv_priv; 346 347 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) { 348 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040; 349 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n", 350 mtd->name); 351 } 352 } 353 354 static void fixup_s29ns512p_sectors(struct mtd_info *mtd) 355 { 356 struct map_info *map = mtd->priv; 357 struct cfi_private *cfi = map->fldrv_priv; 358 359 /* 360 * S29NS512P flash uses more than 8bits to report number of sectors, 361 * which is not permitted by CFI. 362 */ 363 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff; 364 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n", 365 mtd->name); 366 } 367 368 /* Used to fix CFI-Tables of chips without Extended Query Tables */ 369 static struct cfi_fixup cfi_nopri_fixup_table[] = { 370 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */ 371 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */ 372 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */ 373 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */ 374 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */ 375 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */ 376 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */ 377 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */ 378 { 0, 0, NULL } 379 }; 380 381 static struct cfi_fixup cfi_fixup_table[] = { 382 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri }, 383 #ifdef AMD_BOOTLOC_BUG 384 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock }, 385 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock }, 386 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock }, 387 #endif 388 { CFI_MFR_AMD, 0x0050, fixup_use_secsi }, 389 { CFI_MFR_AMD, 0x0053, fixup_use_secsi }, 390 { CFI_MFR_AMD, 0x0055, fixup_use_secsi }, 391 { CFI_MFR_AMD, 0x0056, fixup_use_secsi }, 392 { CFI_MFR_AMD, 0x005C, fixup_use_secsi }, 393 { CFI_MFR_AMD, 0x005F, fixup_use_secsi }, 394 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors }, 395 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors }, 396 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors }, 397 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors }, 398 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors }, 399 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */ 400 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */ 401 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */ 402 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */ 403 #if !FORCE_WORD_WRITE 404 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers }, 405 #endif 406 { 0, 0, NULL } 407 }; 408 static struct cfi_fixup jedec_fixup_table[] = { 409 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock }, 410 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock }, 411 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock }, 412 { 0, 0, NULL } 413 }; 414 415 static struct cfi_fixup fixup_table[] = { 416 /* The CFI vendor ids and the JEDEC vendor IDs appear 417 * to be common. It is like the devices id's are as 418 * well. This table is to pick all cases where 419 * we know that is the case. 420 */ 421 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip }, 422 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock }, 423 { 0, 0, NULL } 424 }; 425 426 427 static void cfi_fixup_major_minor(struct cfi_private *cfi, 428 struct cfi_pri_amdstd *extp) 429 { 430 if (cfi->mfr == CFI_MFR_SAMSUNG) { 431 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') || 432 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) { 433 /* 434 * Samsung K8P2815UQB and K8D6x16UxM chips 435 * report major=0 / minor=0. 436 * K8D3x16UxC chips report major=3 / minor=3. 437 */ 438 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu" 439 " Extended Query version to 1.%c\n", 440 extp->MinorVersion); 441 extp->MajorVersion = '1'; 442 } 443 } 444 445 /* 446 * SST 38VF640x chips report major=0xFF / minor=0xFF. 447 */ 448 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) { 449 extp->MajorVersion = '1'; 450 extp->MinorVersion = '0'; 451 } 452 } 453 454 static int is_m29ew(struct cfi_private *cfi) 455 { 456 if (cfi->mfr == CFI_MFR_INTEL && 457 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) || 458 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e))) 459 return 1; 460 return 0; 461 } 462 463 /* 464 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20: 465 * Some revisions of the M29EW suffer from erase suspend hang ups. In 466 * particular, it can occur when the sequence 467 * Erase Confirm -> Suspend -> Program -> Resume 468 * causes a lockup due to internal timing issues. The consequence is that the 469 * erase cannot be resumed without inserting a dummy command after programming 470 * and prior to resuming. [...] The work-around is to issue a dummy write cycle 471 * that writes an F0 command code before the RESUME command. 472 */ 473 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map, 474 unsigned long adr) 475 { 476 struct cfi_private *cfi = map->fldrv_priv; 477 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */ 478 if (is_m29ew(cfi)) 479 map_write(map, CMD(0xF0), adr); 480 } 481 482 /* 483 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22: 484 * 485 * Some revisions of the M29EW (for example, A1 and A2 step revisions) 486 * are affected by a problem that could cause a hang up when an ERASE SUSPEND 487 * command is issued after an ERASE RESUME operation without waiting for a 488 * minimum delay. The result is that once the ERASE seems to be completed 489 * (no bits are toggling), the contents of the Flash memory block on which 490 * the erase was ongoing could be inconsistent with the expected values 491 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84 492 * values), causing a consequent failure of the ERASE operation. 493 * The occurrence of this issue could be high, especially when file system 494 * operations on the Flash are intensive. As a result, it is recommended 495 * that a patch be applied. Intensive file system operations can cause many 496 * calls to the garbage routine to free Flash space (also by erasing physical 497 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME 498 * commands can occur. The problem disappears when a delay is inserted after 499 * the RESUME command by using the udelay() function available in Linux. 500 * The DELAY value must be tuned based on the customer's platform. 501 * The maximum value that fixes the problem in all cases is 500us. 502 * But, in our experience, a delay of 30 µs to 50 µs is sufficient 503 * in most cases. 504 * We have chosen 500µs because this latency is acceptable. 505 */ 506 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi) 507 { 508 /* 509 * Resolving the Delay After Resume Issue see Micron TN-13-07 510 * Worst case delay must be 500µs but 30-50µs should be ok as well 511 */ 512 if (is_m29ew(cfi)) 513 cfi_udelay(500); 514 } 515 516 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary) 517 { 518 struct cfi_private *cfi = map->fldrv_priv; 519 struct device_node __maybe_unused *np = map->device_node; 520 struct mtd_info *mtd; 521 int i; 522 523 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL); 524 if (!mtd) 525 return NULL; 526 mtd->priv = map; 527 mtd->type = MTD_NORFLASH; 528 529 /* Fill in the default mtd operations */ 530 mtd->_erase = cfi_amdstd_erase_varsize; 531 mtd->_write = cfi_amdstd_write_words; 532 mtd->_read = cfi_amdstd_read; 533 mtd->_sync = cfi_amdstd_sync; 534 mtd->_suspend = cfi_amdstd_suspend; 535 mtd->_resume = cfi_amdstd_resume; 536 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg; 537 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg; 538 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info; 539 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info; 540 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg; 541 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg; 542 mtd->flags = MTD_CAP_NORFLASH; 543 mtd->name = map->name; 544 mtd->writesize = 1; 545 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; 546 547 pr_debug("MTD %s(): write buffer size %d\n", __func__, 548 mtd->writebufsize); 549 550 mtd->_panic_write = cfi_amdstd_panic_write; 551 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot; 552 553 if (cfi->cfi_mode==CFI_MODE_CFI){ 554 unsigned char bootloc; 555 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR; 556 struct cfi_pri_amdstd *extp; 557 558 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu"); 559 if (extp) { 560 /* 561 * It's a real CFI chip, not one for which the probe 562 * routine faked a CFI structure. 563 */ 564 cfi_fixup_major_minor(cfi, extp); 565 566 /* 567 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5 568 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19 569 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf 570 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf 571 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf 572 */ 573 if (extp->MajorVersion != '1' || 574 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) { 575 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query " 576 "version %c.%c (%#02x/%#02x).\n", 577 extp->MajorVersion, extp->MinorVersion, 578 extp->MajorVersion, extp->MinorVersion); 579 kfree(extp); 580 kfree(mtd); 581 return NULL; 582 } 583 584 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n", 585 extp->MajorVersion, extp->MinorVersion); 586 587 /* Install our own private info structure */ 588 cfi->cmdset_priv = extp; 589 590 /* Apply cfi device specific fixups */ 591 cfi_fixup(mtd, cfi_fixup_table); 592 593 #ifdef DEBUG_CFI_FEATURES 594 /* Tell the user about it in lots of lovely detail */ 595 cfi_tell_features(extp); 596 #endif 597 598 #ifdef CONFIG_OF 599 if (np && of_property_read_bool( 600 np, "use-advanced-sector-protection") 601 && extp->BlkProtUnprot == 8) { 602 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n"); 603 mtd->_lock = cfi_ppb_lock; 604 mtd->_unlock = cfi_ppb_unlock; 605 mtd->_is_locked = cfi_ppb_is_locked; 606 } 607 #endif 608 609 bootloc = extp->TopBottom; 610 if ((bootloc < 2) || (bootloc > 5)) { 611 printk(KERN_WARNING "%s: CFI contains unrecognised boot " 612 "bank location (%d). Assuming bottom.\n", 613 map->name, bootloc); 614 bootloc = 2; 615 } 616 617 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) { 618 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name); 619 620 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) { 621 int j = (cfi->cfiq->NumEraseRegions-1)-i; 622 623 swap(cfi->cfiq->EraseRegionInfo[i], 624 cfi->cfiq->EraseRegionInfo[j]); 625 } 626 } 627 /* Set the default CFI lock/unlock addresses */ 628 cfi->addr_unlock1 = 0x555; 629 cfi->addr_unlock2 = 0x2aa; 630 } 631 cfi_fixup(mtd, cfi_nopri_fixup_table); 632 633 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) { 634 kfree(mtd); 635 return NULL; 636 } 637 638 } /* CFI mode */ 639 else if (cfi->cfi_mode == CFI_MODE_JEDEC) { 640 /* Apply jedec specific fixups */ 641 cfi_fixup(mtd, jedec_fixup_table); 642 } 643 /* Apply generic fixups */ 644 cfi_fixup(mtd, fixup_table); 645 646 for (i=0; i< cfi->numchips; i++) { 647 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp; 648 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp; 649 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp; 650 /* 651 * First calculate the timeout max according to timeout field 652 * of struct cfi_ident that probed from chip's CFI aera, if 653 * available. Specify a minimum of 2000us, in case the CFI data 654 * is wrong. 655 */ 656 if (cfi->cfiq->BufWriteTimeoutTyp && 657 cfi->cfiq->BufWriteTimeoutMax) 658 cfi->chips[i].buffer_write_time_max = 659 1 << (cfi->cfiq->BufWriteTimeoutTyp + 660 cfi->cfiq->BufWriteTimeoutMax); 661 else 662 cfi->chips[i].buffer_write_time_max = 0; 663 664 cfi->chips[i].buffer_write_time_max = 665 max(cfi->chips[i].buffer_write_time_max, 2000); 666 667 cfi->chips[i].ref_point_counter = 0; 668 init_waitqueue_head(&(cfi->chips[i].wq)); 669 } 670 671 map->fldrv = &cfi_amdstd_chipdrv; 672 673 return cfi_amdstd_setup(mtd); 674 } 675 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002"))); 676 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002"))); 677 EXPORT_SYMBOL_GPL(cfi_cmdset_0002); 678 EXPORT_SYMBOL_GPL(cfi_cmdset_0006); 679 EXPORT_SYMBOL_GPL(cfi_cmdset_0701); 680 681 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd) 682 { 683 struct map_info *map = mtd->priv; 684 struct cfi_private *cfi = map->fldrv_priv; 685 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave; 686 unsigned long offset = 0; 687 int i,j; 688 689 printk(KERN_NOTICE "number of %s chips: %d\n", 690 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips); 691 /* Select the correct geometry setup */ 692 mtd->size = devsize * cfi->numchips; 693 694 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips; 695 mtd->eraseregions = kmalloc_array(mtd->numeraseregions, 696 sizeof(struct mtd_erase_region_info), 697 GFP_KERNEL); 698 if (!mtd->eraseregions) 699 goto setup_err; 700 701 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) { 702 unsigned long ernum, ersize; 703 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave; 704 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1; 705 706 if (mtd->erasesize < ersize) { 707 mtd->erasesize = ersize; 708 } 709 for (j=0; j<cfi->numchips; j++) { 710 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset; 711 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize; 712 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum; 713 } 714 offset += (ersize * ernum); 715 } 716 if (offset != devsize) { 717 /* Argh */ 718 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize); 719 goto setup_err; 720 } 721 722 __module_get(THIS_MODULE); 723 register_reboot_notifier(&mtd->reboot_notifier); 724 return mtd; 725 726 setup_err: 727 kfree(mtd->eraseregions); 728 kfree(mtd); 729 kfree(cfi->cmdset_priv); 730 kfree(cfi->cfiq); 731 return NULL; 732 } 733 734 /* 735 * Return true if the chip is ready. 736 * 737 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any 738 * non-suspended sector) and is indicated by no toggle bits toggling. 739 * 740 * Note that anything more complicated than checking if no bits are toggling 741 * (including checking DQ5 for an error status) is tricky to get working 742 * correctly and is therefore not done (particularly with interleaved chips 743 * as each chip must be checked independently of the others). 744 */ 745 static int __xipram chip_ready(struct map_info *map, unsigned long addr) 746 { 747 map_word d, t; 748 749 d = map_read(map, addr); 750 t = map_read(map, addr); 751 752 return map_word_equal(map, d, t); 753 } 754 755 /* 756 * Return true if the chip is ready and has the correct value. 757 * 758 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any 759 * non-suspended sector) and it is indicated by no bits toggling. 760 * 761 * Error are indicated by toggling bits or bits held with the wrong value, 762 * or with bits toggling. 763 * 764 * Note that anything more complicated than checking if no bits are toggling 765 * (including checking DQ5 for an error status) is tricky to get working 766 * correctly and is therefore not done (particularly with interleaved chips 767 * as each chip must be checked independently of the others). 768 * 769 */ 770 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected) 771 { 772 map_word oldd, curd; 773 774 oldd = map_read(map, addr); 775 curd = map_read(map, addr); 776 777 return map_word_equal(map, oldd, curd) && 778 map_word_equal(map, curd, expected); 779 } 780 781 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode) 782 { 783 DECLARE_WAITQUEUE(wait, current); 784 struct cfi_private *cfi = map->fldrv_priv; 785 unsigned long timeo; 786 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv; 787 788 resettime: 789 timeo = jiffies + HZ; 790 retry: 791 switch (chip->state) { 792 793 case FL_STATUS: 794 for (;;) { 795 if (chip_ready(map, adr)) 796 break; 797 798 if (time_after(jiffies, timeo)) { 799 printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); 800 return -EIO; 801 } 802 mutex_unlock(&chip->mutex); 803 cfi_udelay(1); 804 mutex_lock(&chip->mutex); 805 /* Someone else might have been playing with it. */ 806 goto retry; 807 } 808 809 case FL_READY: 810 case FL_CFI_QUERY: 811 case FL_JEDEC_QUERY: 812 return 0; 813 814 case FL_ERASING: 815 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || 816 !(mode == FL_READY || mode == FL_POINT || 817 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) 818 goto sleep; 819 820 /* Do not allow suspend iff read/write to EB address */ 821 if ((adr & chip->in_progress_block_mask) == 822 chip->in_progress_block_addr) 823 goto sleep; 824 825 /* Erase suspend */ 826 /* It's harmless to issue the Erase-Suspend and Erase-Resume 827 * commands when the erase algorithm isn't in progress. */ 828 map_write(map, CMD(0xB0), chip->in_progress_block_addr); 829 chip->oldstate = FL_ERASING; 830 chip->state = FL_ERASE_SUSPENDING; 831 chip->erase_suspended = 1; 832 for (;;) { 833 if (chip_ready(map, adr)) 834 break; 835 836 if (time_after(jiffies, timeo)) { 837 /* Should have suspended the erase by now. 838 * Send an Erase-Resume command as either 839 * there was an error (so leave the erase 840 * routine to recover from it) or we trying to 841 * use the erase-in-progress sector. */ 842 put_chip(map, chip, adr); 843 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__); 844 return -EIO; 845 } 846 847 mutex_unlock(&chip->mutex); 848 cfi_udelay(1); 849 mutex_lock(&chip->mutex); 850 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING. 851 So we can just loop here. */ 852 } 853 chip->state = FL_READY; 854 return 0; 855 856 case FL_XIP_WHILE_ERASING: 857 if (mode != FL_READY && mode != FL_POINT && 858 (!cfip || !(cfip->EraseSuspend&2))) 859 goto sleep; 860 chip->oldstate = chip->state; 861 chip->state = FL_READY; 862 return 0; 863 864 case FL_SHUTDOWN: 865 /* The machine is rebooting */ 866 return -EIO; 867 868 case FL_POINT: 869 /* Only if there's no operation suspended... */ 870 if (mode == FL_READY && chip->oldstate == FL_READY) 871 return 0; 872 873 default: 874 sleep: 875 set_current_state(TASK_UNINTERRUPTIBLE); 876 add_wait_queue(&chip->wq, &wait); 877 mutex_unlock(&chip->mutex); 878 schedule(); 879 remove_wait_queue(&chip->wq, &wait); 880 mutex_lock(&chip->mutex); 881 goto resettime; 882 } 883 } 884 885 886 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr) 887 { 888 struct cfi_private *cfi = map->fldrv_priv; 889 890 switch(chip->oldstate) { 891 case FL_ERASING: 892 cfi_fixup_m29ew_erase_suspend(map, 893 chip->in_progress_block_addr); 894 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr); 895 cfi_fixup_m29ew_delay_after_resume(cfi); 896 chip->oldstate = FL_READY; 897 chip->state = FL_ERASING; 898 break; 899 900 case FL_XIP_WHILE_ERASING: 901 chip->state = chip->oldstate; 902 chip->oldstate = FL_READY; 903 break; 904 905 case FL_READY: 906 case FL_STATUS: 907 break; 908 default: 909 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate); 910 } 911 wake_up(&chip->wq); 912 } 913 914 #ifdef CONFIG_MTD_XIP 915 916 /* 917 * No interrupt what so ever can be serviced while the flash isn't in array 918 * mode. This is ensured by the xip_disable() and xip_enable() functions 919 * enclosing any code path where the flash is known not to be in array mode. 920 * And within a XIP disabled code path, only functions marked with __xipram 921 * may be called and nothing else (it's a good thing to inspect generated 922 * assembly to make sure inline functions were actually inlined and that gcc 923 * didn't emit calls to its own support functions). Also configuring MTD CFI 924 * support to a single buswidth and a single interleave is also recommended. 925 */ 926 927 static void xip_disable(struct map_info *map, struct flchip *chip, 928 unsigned long adr) 929 { 930 /* TODO: chips with no XIP use should ignore and return */ 931 (void) map_read(map, adr); /* ensure mmu mapping is up to date */ 932 local_irq_disable(); 933 } 934 935 static void __xipram xip_enable(struct map_info *map, struct flchip *chip, 936 unsigned long adr) 937 { 938 struct cfi_private *cfi = map->fldrv_priv; 939 940 if (chip->state != FL_POINT && chip->state != FL_READY) { 941 map_write(map, CMD(0xf0), adr); 942 chip->state = FL_READY; 943 } 944 (void) map_read(map, adr); 945 xip_iprefetch(); 946 local_irq_enable(); 947 } 948 949 /* 950 * When a delay is required for the flash operation to complete, the 951 * xip_udelay() function is polling for both the given timeout and pending 952 * (but still masked) hardware interrupts. Whenever there is an interrupt 953 * pending then the flash erase operation is suspended, array mode restored 954 * and interrupts unmasked. Task scheduling might also happen at that 955 * point. The CPU eventually returns from the interrupt or the call to 956 * schedule() and the suspended flash operation is resumed for the remaining 957 * of the delay period. 958 * 959 * Warning: this function _will_ fool interrupt latency tracing tools. 960 */ 961 962 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip, 963 unsigned long adr, int usec) 964 { 965 struct cfi_private *cfi = map->fldrv_priv; 966 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; 967 map_word status, OK = CMD(0x80); 968 unsigned long suspended, start = xip_currtime(); 969 flstate_t oldstate; 970 971 do { 972 cpu_relax(); 973 if (xip_irqpending() && extp && 974 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) && 975 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) { 976 /* 977 * Let's suspend the erase operation when supported. 978 * Note that we currently don't try to suspend 979 * interleaved chips if there is already another 980 * operation suspended (imagine what happens 981 * when one chip was already done with the current 982 * operation while another chip suspended it, then 983 * we resume the whole thing at once). Yes, it 984 * can happen! 985 */ 986 map_write(map, CMD(0xb0), adr); 987 usec -= xip_elapsed_since(start); 988 suspended = xip_currtime(); 989 do { 990 if (xip_elapsed_since(suspended) > 100000) { 991 /* 992 * The chip doesn't want to suspend 993 * after waiting for 100 msecs. 994 * This is a critical error but there 995 * is not much we can do here. 996 */ 997 return; 998 } 999 status = map_read(map, adr); 1000 } while (!map_word_andequal(map, status, OK, OK)); 1001 1002 /* Suspend succeeded */ 1003 oldstate = chip->state; 1004 if (!map_word_bitsset(map, status, CMD(0x40))) 1005 break; 1006 chip->state = FL_XIP_WHILE_ERASING; 1007 chip->erase_suspended = 1; 1008 map_write(map, CMD(0xf0), adr); 1009 (void) map_read(map, adr); 1010 xip_iprefetch(); 1011 local_irq_enable(); 1012 mutex_unlock(&chip->mutex); 1013 xip_iprefetch(); 1014 cond_resched(); 1015 1016 /* 1017 * We're back. However someone else might have 1018 * decided to go write to the chip if we are in 1019 * a suspended erase state. If so let's wait 1020 * until it's done. 1021 */ 1022 mutex_lock(&chip->mutex); 1023 while (chip->state != FL_XIP_WHILE_ERASING) { 1024 DECLARE_WAITQUEUE(wait, current); 1025 set_current_state(TASK_UNINTERRUPTIBLE); 1026 add_wait_queue(&chip->wq, &wait); 1027 mutex_unlock(&chip->mutex); 1028 schedule(); 1029 remove_wait_queue(&chip->wq, &wait); 1030 mutex_lock(&chip->mutex); 1031 } 1032 /* Disallow XIP again */ 1033 local_irq_disable(); 1034 1035 /* Correct Erase Suspend Hangups for M29EW */ 1036 cfi_fixup_m29ew_erase_suspend(map, adr); 1037 /* Resume the write or erase operation */ 1038 map_write(map, cfi->sector_erase_cmd, adr); 1039 chip->state = oldstate; 1040 start = xip_currtime(); 1041 } else if (usec >= 1000000/HZ) { 1042 /* 1043 * Try to save on CPU power when waiting delay 1044 * is at least a system timer tick period. 1045 * No need to be extremely accurate here. 1046 */ 1047 xip_cpu_idle(); 1048 } 1049 status = map_read(map, adr); 1050 } while (!map_word_andequal(map, status, OK, OK) 1051 && xip_elapsed_since(start) < usec); 1052 } 1053 1054 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec) 1055 1056 /* 1057 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while 1058 * the flash is actively programming or erasing since we have to poll for 1059 * the operation to complete anyway. We can't do that in a generic way with 1060 * a XIP setup so do it before the actual flash operation in this case 1061 * and stub it out from INVALIDATE_CACHE_UDELAY. 1062 */ 1063 #define XIP_INVAL_CACHED_RANGE(map, from, size) \ 1064 INVALIDATE_CACHED_RANGE(map, from, size) 1065 1066 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ 1067 UDELAY(map, chip, adr, usec) 1068 1069 /* 1070 * Extra notes: 1071 * 1072 * Activating this XIP support changes the way the code works a bit. For 1073 * example the code to suspend the current process when concurrent access 1074 * happens is never executed because xip_udelay() will always return with the 1075 * same chip state as it was entered with. This is why there is no care for 1076 * the presence of add_wait_queue() or schedule() calls from within a couple 1077 * xip_disable()'d areas of code, like in do_erase_oneblock for example. 1078 * The queueing and scheduling are always happening within xip_udelay(). 1079 * 1080 * Similarly, get_chip() and put_chip() just happen to always be executed 1081 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state 1082 * is in array mode, therefore never executing many cases therein and not 1083 * causing any problem with XIP. 1084 */ 1085 1086 #else 1087 1088 #define xip_disable(map, chip, adr) 1089 #define xip_enable(map, chip, adr) 1090 #define XIP_INVAL_CACHED_RANGE(x...) 1091 1092 #define UDELAY(map, chip, adr, usec) \ 1093 do { \ 1094 mutex_unlock(&chip->mutex); \ 1095 cfi_udelay(usec); \ 1096 mutex_lock(&chip->mutex); \ 1097 } while (0) 1098 1099 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ 1100 do { \ 1101 mutex_unlock(&chip->mutex); \ 1102 INVALIDATE_CACHED_RANGE(map, adr, len); \ 1103 cfi_udelay(usec); \ 1104 mutex_lock(&chip->mutex); \ 1105 } while (0) 1106 1107 #endif 1108 1109 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) 1110 { 1111 unsigned long cmd_addr; 1112 struct cfi_private *cfi = map->fldrv_priv; 1113 int ret; 1114 1115 adr += chip->start; 1116 1117 /* Ensure cmd read/writes are aligned. */ 1118 cmd_addr = adr & ~(map_bankwidth(map)-1); 1119 1120 mutex_lock(&chip->mutex); 1121 ret = get_chip(map, chip, cmd_addr, FL_READY); 1122 if (ret) { 1123 mutex_unlock(&chip->mutex); 1124 return ret; 1125 } 1126 1127 if (chip->state != FL_POINT && chip->state != FL_READY) { 1128 map_write(map, CMD(0xf0), cmd_addr); 1129 chip->state = FL_READY; 1130 } 1131 1132 map_copy_from(map, buf, adr, len); 1133 1134 put_chip(map, chip, cmd_addr); 1135 1136 mutex_unlock(&chip->mutex); 1137 return 0; 1138 } 1139 1140 1141 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) 1142 { 1143 struct map_info *map = mtd->priv; 1144 struct cfi_private *cfi = map->fldrv_priv; 1145 unsigned long ofs; 1146 int chipnum; 1147 int ret = 0; 1148 1149 /* ofs: offset within the first chip that the first read should start */ 1150 chipnum = (from >> cfi->chipshift); 1151 ofs = from - (chipnum << cfi->chipshift); 1152 1153 while (len) { 1154 unsigned long thislen; 1155 1156 if (chipnum >= cfi->numchips) 1157 break; 1158 1159 if ((len + ofs -1) >> cfi->chipshift) 1160 thislen = (1<<cfi->chipshift) - ofs; 1161 else 1162 thislen = len; 1163 1164 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); 1165 if (ret) 1166 break; 1167 1168 *retlen += thislen; 1169 len -= thislen; 1170 buf += thislen; 1171 1172 ofs = 0; 1173 chipnum++; 1174 } 1175 return ret; 1176 } 1177 1178 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip, 1179 loff_t adr, size_t len, u_char *buf, size_t grouplen); 1180 1181 static inline void otp_enter(struct map_info *map, struct flchip *chip, 1182 loff_t adr, size_t len) 1183 { 1184 struct cfi_private *cfi = map->fldrv_priv; 1185 1186 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1187 cfi->device_type, NULL); 1188 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1189 cfi->device_type, NULL); 1190 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, 1191 cfi->device_type, NULL); 1192 1193 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len); 1194 } 1195 1196 static inline void otp_exit(struct map_info *map, struct flchip *chip, 1197 loff_t adr, size_t len) 1198 { 1199 struct cfi_private *cfi = map->fldrv_priv; 1200 1201 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1202 cfi->device_type, NULL); 1203 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1204 cfi->device_type, NULL); 1205 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, 1206 cfi->device_type, NULL); 1207 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, 1208 cfi->device_type, NULL); 1209 1210 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len); 1211 } 1212 1213 static inline int do_read_secsi_onechip(struct map_info *map, 1214 struct flchip *chip, loff_t adr, 1215 size_t len, u_char *buf, 1216 size_t grouplen) 1217 { 1218 DECLARE_WAITQUEUE(wait, current); 1219 unsigned long timeo = jiffies + HZ; 1220 1221 retry: 1222 mutex_lock(&chip->mutex); 1223 1224 if (chip->state != FL_READY){ 1225 set_current_state(TASK_UNINTERRUPTIBLE); 1226 add_wait_queue(&chip->wq, &wait); 1227 1228 mutex_unlock(&chip->mutex); 1229 1230 schedule(); 1231 remove_wait_queue(&chip->wq, &wait); 1232 timeo = jiffies + HZ; 1233 1234 goto retry; 1235 } 1236 1237 adr += chip->start; 1238 1239 chip->state = FL_READY; 1240 1241 otp_enter(map, chip, adr, len); 1242 map_copy_from(map, buf, adr, len); 1243 otp_exit(map, chip, adr, len); 1244 1245 wake_up(&chip->wq); 1246 mutex_unlock(&chip->mutex); 1247 1248 return 0; 1249 } 1250 1251 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) 1252 { 1253 struct map_info *map = mtd->priv; 1254 struct cfi_private *cfi = map->fldrv_priv; 1255 unsigned long ofs; 1256 int chipnum; 1257 int ret = 0; 1258 1259 /* ofs: offset within the first chip that the first read should start */ 1260 /* 8 secsi bytes per chip */ 1261 chipnum=from>>3; 1262 ofs=from & 7; 1263 1264 while (len) { 1265 unsigned long thislen; 1266 1267 if (chipnum >= cfi->numchips) 1268 break; 1269 1270 if ((len + ofs -1) >> 3) 1271 thislen = (1<<3) - ofs; 1272 else 1273 thislen = len; 1274 1275 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, 1276 thislen, buf, 0); 1277 if (ret) 1278 break; 1279 1280 *retlen += thislen; 1281 len -= thislen; 1282 buf += thislen; 1283 1284 ofs = 0; 1285 chipnum++; 1286 } 1287 return ret; 1288 } 1289 1290 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, 1291 unsigned long adr, map_word datum, 1292 int mode); 1293 1294 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr, 1295 size_t len, u_char *buf, size_t grouplen) 1296 { 1297 int ret; 1298 while (len) { 1299 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1); 1300 int gap = adr - bus_ofs; 1301 int n = min_t(int, len, map_bankwidth(map) - gap); 1302 map_word datum = map_word_ff(map); 1303 1304 if (n != map_bankwidth(map)) { 1305 /* partial write of a word, load old contents */ 1306 otp_enter(map, chip, bus_ofs, map_bankwidth(map)); 1307 datum = map_read(map, bus_ofs); 1308 otp_exit(map, chip, bus_ofs, map_bankwidth(map)); 1309 } 1310 1311 datum = map_word_load_partial(map, datum, buf, gap, n); 1312 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE); 1313 if (ret) 1314 return ret; 1315 1316 adr += n; 1317 buf += n; 1318 len -= n; 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr, 1325 size_t len, u_char *buf, size_t grouplen) 1326 { 1327 struct cfi_private *cfi = map->fldrv_priv; 1328 uint8_t lockreg; 1329 unsigned long timeo; 1330 int ret; 1331 1332 /* make sure area matches group boundaries */ 1333 if ((adr != 0) || (len != grouplen)) 1334 return -EINVAL; 1335 1336 mutex_lock(&chip->mutex); 1337 ret = get_chip(map, chip, chip->start, FL_LOCKING); 1338 if (ret) { 1339 mutex_unlock(&chip->mutex); 1340 return ret; 1341 } 1342 chip->state = FL_LOCKING; 1343 1344 /* Enter lock register command */ 1345 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1346 cfi->device_type, NULL); 1347 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1348 cfi->device_type, NULL); 1349 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi, 1350 cfi->device_type, NULL); 1351 1352 /* read lock register */ 1353 lockreg = cfi_read_query(map, 0); 1354 1355 /* set bit 0 to protect extended memory block */ 1356 lockreg &= ~0x01; 1357 1358 /* set bit 0 to protect extended memory block */ 1359 /* write lock register */ 1360 map_write(map, CMD(0xA0), chip->start); 1361 map_write(map, CMD(lockreg), chip->start); 1362 1363 /* wait for chip to become ready */ 1364 timeo = jiffies + msecs_to_jiffies(2); 1365 for (;;) { 1366 if (chip_ready(map, adr)) 1367 break; 1368 1369 if (time_after(jiffies, timeo)) { 1370 pr_err("Waiting for chip to be ready timed out.\n"); 1371 ret = -EIO; 1372 break; 1373 } 1374 UDELAY(map, chip, 0, 1); 1375 } 1376 1377 /* exit protection commands */ 1378 map_write(map, CMD(0x90), chip->start); 1379 map_write(map, CMD(0x00), chip->start); 1380 1381 chip->state = FL_READY; 1382 put_chip(map, chip, chip->start); 1383 mutex_unlock(&chip->mutex); 1384 1385 return ret; 1386 } 1387 1388 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len, 1389 size_t *retlen, u_char *buf, 1390 otp_op_t action, int user_regs) 1391 { 1392 struct map_info *map = mtd->priv; 1393 struct cfi_private *cfi = map->fldrv_priv; 1394 int ofs_factor = cfi->interleave * cfi->device_type; 1395 unsigned long base; 1396 int chipnum; 1397 struct flchip *chip; 1398 uint8_t otp, lockreg; 1399 int ret; 1400 1401 size_t user_size, factory_size, otpsize; 1402 loff_t user_offset, factory_offset, otpoffset; 1403 int user_locked = 0, otplocked; 1404 1405 *retlen = 0; 1406 1407 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) { 1408 chip = &cfi->chips[chipnum]; 1409 factory_size = 0; 1410 user_size = 0; 1411 1412 /* Micron M29EW family */ 1413 if (is_m29ew(cfi)) { 1414 base = chip->start; 1415 1416 /* check whether secsi area is factory locked 1417 or user lockable */ 1418 mutex_lock(&chip->mutex); 1419 ret = get_chip(map, chip, base, FL_CFI_QUERY); 1420 if (ret) { 1421 mutex_unlock(&chip->mutex); 1422 return ret; 1423 } 1424 cfi_qry_mode_on(base, map, cfi); 1425 otp = cfi_read_query(map, base + 0x3 * ofs_factor); 1426 cfi_qry_mode_off(base, map, cfi); 1427 put_chip(map, chip, base); 1428 mutex_unlock(&chip->mutex); 1429 1430 if (otp & 0x80) { 1431 /* factory locked */ 1432 factory_offset = 0; 1433 factory_size = 0x100; 1434 } else { 1435 /* customer lockable */ 1436 user_offset = 0; 1437 user_size = 0x100; 1438 1439 mutex_lock(&chip->mutex); 1440 ret = get_chip(map, chip, base, FL_LOCKING); 1441 if (ret) { 1442 mutex_unlock(&chip->mutex); 1443 return ret; 1444 } 1445 1446 /* Enter lock register command */ 1447 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, 1448 chip->start, map, cfi, 1449 cfi->device_type, NULL); 1450 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, 1451 chip->start, map, cfi, 1452 cfi->device_type, NULL); 1453 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, 1454 chip->start, map, cfi, 1455 cfi->device_type, NULL); 1456 /* read lock register */ 1457 lockreg = cfi_read_query(map, 0); 1458 /* exit protection commands */ 1459 map_write(map, CMD(0x90), chip->start); 1460 map_write(map, CMD(0x00), chip->start); 1461 put_chip(map, chip, chip->start); 1462 mutex_unlock(&chip->mutex); 1463 1464 user_locked = ((lockreg & 0x01) == 0x00); 1465 } 1466 } 1467 1468 otpsize = user_regs ? user_size : factory_size; 1469 if (!otpsize) 1470 continue; 1471 otpoffset = user_regs ? user_offset : factory_offset; 1472 otplocked = user_regs ? user_locked : 1; 1473 1474 if (!action) { 1475 /* return otpinfo */ 1476 struct otp_info *otpinfo; 1477 len -= sizeof(*otpinfo); 1478 if (len <= 0) 1479 return -ENOSPC; 1480 otpinfo = (struct otp_info *)buf; 1481 otpinfo->start = from; 1482 otpinfo->length = otpsize; 1483 otpinfo->locked = otplocked; 1484 buf += sizeof(*otpinfo); 1485 *retlen += sizeof(*otpinfo); 1486 from += otpsize; 1487 } else if ((from < otpsize) && (len > 0)) { 1488 size_t size; 1489 size = (len < otpsize - from) ? len : otpsize - from; 1490 ret = action(map, chip, otpoffset + from, size, buf, 1491 otpsize); 1492 if (ret < 0) 1493 return ret; 1494 1495 buf += size; 1496 len -= size; 1497 *retlen += size; 1498 from = 0; 1499 } else { 1500 from -= otpsize; 1501 } 1502 } 1503 return 0; 1504 } 1505 1506 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len, 1507 size_t *retlen, struct otp_info *buf) 1508 { 1509 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf, 1510 NULL, 0); 1511 } 1512 1513 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len, 1514 size_t *retlen, struct otp_info *buf) 1515 { 1516 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf, 1517 NULL, 1); 1518 } 1519 1520 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, 1521 size_t len, size_t *retlen, 1522 u_char *buf) 1523 { 1524 return cfi_amdstd_otp_walk(mtd, from, len, retlen, 1525 buf, do_read_secsi_onechip, 0); 1526 } 1527 1528 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, 1529 size_t len, size_t *retlen, 1530 u_char *buf) 1531 { 1532 return cfi_amdstd_otp_walk(mtd, from, len, retlen, 1533 buf, do_read_secsi_onechip, 1); 1534 } 1535 1536 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from, 1537 size_t len, size_t *retlen, 1538 u_char *buf) 1539 { 1540 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf, 1541 do_otp_write, 1); 1542 } 1543 1544 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, 1545 size_t len) 1546 { 1547 size_t retlen; 1548 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL, 1549 do_otp_lock, 1); 1550 } 1551 1552 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, 1553 unsigned long adr, map_word datum, 1554 int mode) 1555 { 1556 struct cfi_private *cfi = map->fldrv_priv; 1557 unsigned long timeo = jiffies + HZ; 1558 /* 1559 * We use a 1ms + 1 jiffies generic timeout for writes (most devices 1560 * have a max write time of a few hundreds usec). However, we should 1561 * use the maximum timeout value given by the chip at probe time 1562 * instead. Unfortunately, struct flchip does have a field for 1563 * maximum timeout, only for typical which can be far too short 1564 * depending of the conditions. The ' + 1' is to avoid having a 1565 * timeout of 0 jiffies if HZ is smaller than 1000. 1566 */ 1567 unsigned long uWriteTimeout = (HZ / 1000) + 1; 1568 int ret = 0; 1569 map_word oldd; 1570 int retry_cnt = 0; 1571 1572 adr += chip->start; 1573 1574 mutex_lock(&chip->mutex); 1575 ret = get_chip(map, chip, adr, mode); 1576 if (ret) { 1577 mutex_unlock(&chip->mutex); 1578 return ret; 1579 } 1580 1581 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", 1582 __func__, adr, datum.x[0]); 1583 1584 if (mode == FL_OTP_WRITE) 1585 otp_enter(map, chip, adr, map_bankwidth(map)); 1586 1587 /* 1588 * Check for a NOP for the case when the datum to write is already 1589 * present - it saves time and works around buggy chips that corrupt 1590 * data at other locations when 0xff is written to a location that 1591 * already contains 0xff. 1592 */ 1593 oldd = map_read(map, adr); 1594 if (map_word_equal(map, oldd, datum)) { 1595 pr_debug("MTD %s(): NOP\n", 1596 __func__); 1597 goto op_done; 1598 } 1599 1600 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map)); 1601 ENABLE_VPP(map); 1602 xip_disable(map, chip, adr); 1603 1604 retry: 1605 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1606 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 1607 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1608 map_write(map, datum, adr); 1609 chip->state = mode; 1610 1611 INVALIDATE_CACHE_UDELAY(map, chip, 1612 adr, map_bankwidth(map), 1613 chip->word_write_time); 1614 1615 /* See comment above for timeout value. */ 1616 timeo = jiffies + uWriteTimeout; 1617 for (;;) { 1618 if (chip->state != mode) { 1619 /* Someone's suspended the write. Sleep */ 1620 DECLARE_WAITQUEUE(wait, current); 1621 1622 set_current_state(TASK_UNINTERRUPTIBLE); 1623 add_wait_queue(&chip->wq, &wait); 1624 mutex_unlock(&chip->mutex); 1625 schedule(); 1626 remove_wait_queue(&chip->wq, &wait); 1627 timeo = jiffies + (HZ / 2); /* FIXME */ 1628 mutex_lock(&chip->mutex); 1629 continue; 1630 } 1631 1632 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){ 1633 xip_enable(map, chip, adr); 1634 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__); 1635 xip_disable(map, chip, adr); 1636 break; 1637 } 1638 1639 if (chip_ready(map, adr)) 1640 break; 1641 1642 /* Latency issues. Drop the lock, wait a while and retry */ 1643 UDELAY(map, chip, adr, 1); 1644 } 1645 /* Did we succeed? */ 1646 if (!chip_good(map, adr, datum)) { 1647 /* reset on all failures. */ 1648 map_write(map, CMD(0xF0), chip->start); 1649 /* FIXME - should have reset delay before continuing */ 1650 1651 if (++retry_cnt <= MAX_RETRIES) 1652 goto retry; 1653 1654 ret = -EIO; 1655 } 1656 xip_enable(map, chip, adr); 1657 op_done: 1658 if (mode == FL_OTP_WRITE) 1659 otp_exit(map, chip, adr, map_bankwidth(map)); 1660 chip->state = FL_READY; 1661 DISABLE_VPP(map); 1662 put_chip(map, chip, adr); 1663 mutex_unlock(&chip->mutex); 1664 1665 return ret; 1666 } 1667 1668 1669 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len, 1670 size_t *retlen, const u_char *buf) 1671 { 1672 struct map_info *map = mtd->priv; 1673 struct cfi_private *cfi = map->fldrv_priv; 1674 int ret = 0; 1675 int chipnum; 1676 unsigned long ofs, chipstart; 1677 DECLARE_WAITQUEUE(wait, current); 1678 1679 chipnum = to >> cfi->chipshift; 1680 ofs = to - (chipnum << cfi->chipshift); 1681 chipstart = cfi->chips[chipnum].start; 1682 1683 /* If it's not bus-aligned, do the first byte write */ 1684 if (ofs & (map_bankwidth(map)-1)) { 1685 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1); 1686 int i = ofs - bus_ofs; 1687 int n = 0; 1688 map_word tmp_buf; 1689 1690 retry: 1691 mutex_lock(&cfi->chips[chipnum].mutex); 1692 1693 if (cfi->chips[chipnum].state != FL_READY) { 1694 set_current_state(TASK_UNINTERRUPTIBLE); 1695 add_wait_queue(&cfi->chips[chipnum].wq, &wait); 1696 1697 mutex_unlock(&cfi->chips[chipnum].mutex); 1698 1699 schedule(); 1700 remove_wait_queue(&cfi->chips[chipnum].wq, &wait); 1701 goto retry; 1702 } 1703 1704 /* Load 'tmp_buf' with old contents of flash */ 1705 tmp_buf = map_read(map, bus_ofs+chipstart); 1706 1707 mutex_unlock(&cfi->chips[chipnum].mutex); 1708 1709 /* Number of bytes to copy from buffer */ 1710 n = min_t(int, len, map_bankwidth(map)-i); 1711 1712 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); 1713 1714 ret = do_write_oneword(map, &cfi->chips[chipnum], 1715 bus_ofs, tmp_buf, FL_WRITING); 1716 if (ret) 1717 return ret; 1718 1719 ofs += n; 1720 buf += n; 1721 (*retlen) += n; 1722 len -= n; 1723 1724 if (ofs >> cfi->chipshift) { 1725 chipnum ++; 1726 ofs = 0; 1727 if (chipnum == cfi->numchips) 1728 return 0; 1729 } 1730 } 1731 1732 /* We are now aligned, write as much as possible */ 1733 while(len >= map_bankwidth(map)) { 1734 map_word datum; 1735 1736 datum = map_word_load(map, buf); 1737 1738 ret = do_write_oneword(map, &cfi->chips[chipnum], 1739 ofs, datum, FL_WRITING); 1740 if (ret) 1741 return ret; 1742 1743 ofs += map_bankwidth(map); 1744 buf += map_bankwidth(map); 1745 (*retlen) += map_bankwidth(map); 1746 len -= map_bankwidth(map); 1747 1748 if (ofs >> cfi->chipshift) { 1749 chipnum ++; 1750 ofs = 0; 1751 if (chipnum == cfi->numchips) 1752 return 0; 1753 chipstart = cfi->chips[chipnum].start; 1754 } 1755 } 1756 1757 /* Write the trailing bytes if any */ 1758 if (len & (map_bankwidth(map)-1)) { 1759 map_word tmp_buf; 1760 1761 retry1: 1762 mutex_lock(&cfi->chips[chipnum].mutex); 1763 1764 if (cfi->chips[chipnum].state != FL_READY) { 1765 set_current_state(TASK_UNINTERRUPTIBLE); 1766 add_wait_queue(&cfi->chips[chipnum].wq, &wait); 1767 1768 mutex_unlock(&cfi->chips[chipnum].mutex); 1769 1770 schedule(); 1771 remove_wait_queue(&cfi->chips[chipnum].wq, &wait); 1772 goto retry1; 1773 } 1774 1775 tmp_buf = map_read(map, ofs + chipstart); 1776 1777 mutex_unlock(&cfi->chips[chipnum].mutex); 1778 1779 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); 1780 1781 ret = do_write_oneword(map, &cfi->chips[chipnum], 1782 ofs, tmp_buf, FL_WRITING); 1783 if (ret) 1784 return ret; 1785 1786 (*retlen) += len; 1787 } 1788 1789 return 0; 1790 } 1791 1792 1793 /* 1794 * FIXME: interleaved mode not tested, and probably not supported! 1795 */ 1796 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, 1797 unsigned long adr, const u_char *buf, 1798 int len) 1799 { 1800 struct cfi_private *cfi = map->fldrv_priv; 1801 unsigned long timeo = jiffies + HZ; 1802 /* 1803 * Timeout is calculated according to CFI data, if available. 1804 * See more comments in cfi_cmdset_0002(). 1805 */ 1806 unsigned long uWriteTimeout = 1807 usecs_to_jiffies(chip->buffer_write_time_max); 1808 int ret = -EIO; 1809 unsigned long cmd_adr; 1810 int z, words; 1811 map_word datum; 1812 1813 adr += chip->start; 1814 cmd_adr = adr; 1815 1816 mutex_lock(&chip->mutex); 1817 ret = get_chip(map, chip, adr, FL_WRITING); 1818 if (ret) { 1819 mutex_unlock(&chip->mutex); 1820 return ret; 1821 } 1822 1823 datum = map_word_load(map, buf); 1824 1825 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", 1826 __func__, adr, datum.x[0]); 1827 1828 XIP_INVAL_CACHED_RANGE(map, adr, len); 1829 ENABLE_VPP(map); 1830 xip_disable(map, chip, cmd_adr); 1831 1832 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1833 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 1834 1835 /* Write Buffer Load */ 1836 map_write(map, CMD(0x25), cmd_adr); 1837 1838 chip->state = FL_WRITING_TO_BUFFER; 1839 1840 /* Write length of data to come */ 1841 words = len / map_bankwidth(map); 1842 map_write(map, CMD(words - 1), cmd_adr); 1843 /* Write data */ 1844 z = 0; 1845 while(z < words * map_bankwidth(map)) { 1846 datum = map_word_load(map, buf); 1847 map_write(map, datum, adr + z); 1848 1849 z += map_bankwidth(map); 1850 buf += map_bankwidth(map); 1851 } 1852 z -= map_bankwidth(map); 1853 1854 adr += z; 1855 1856 /* Write Buffer Program Confirm: GO GO GO */ 1857 map_write(map, CMD(0x29), cmd_adr); 1858 chip->state = FL_WRITING; 1859 1860 INVALIDATE_CACHE_UDELAY(map, chip, 1861 adr, map_bankwidth(map), 1862 chip->word_write_time); 1863 1864 timeo = jiffies + uWriteTimeout; 1865 1866 for (;;) { 1867 if (chip->state != FL_WRITING) { 1868 /* Someone's suspended the write. Sleep */ 1869 DECLARE_WAITQUEUE(wait, current); 1870 1871 set_current_state(TASK_UNINTERRUPTIBLE); 1872 add_wait_queue(&chip->wq, &wait); 1873 mutex_unlock(&chip->mutex); 1874 schedule(); 1875 remove_wait_queue(&chip->wq, &wait); 1876 timeo = jiffies + (HZ / 2); /* FIXME */ 1877 mutex_lock(&chip->mutex); 1878 continue; 1879 } 1880 1881 if (time_after(jiffies, timeo) && !chip_ready(map, adr)) 1882 break; 1883 1884 if (chip_good(map, adr, datum)) { 1885 xip_enable(map, chip, adr); 1886 goto op_done; 1887 } 1888 1889 /* Latency issues. Drop the lock, wait a while and retry */ 1890 UDELAY(map, chip, adr, 1); 1891 } 1892 1893 /* 1894 * Recovery from write-buffer programming failures requires 1895 * the write-to-buffer-reset sequence. Since the last part 1896 * of the sequence also works as a normal reset, we can run 1897 * the same commands regardless of why we are here. 1898 * See e.g. 1899 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf 1900 */ 1901 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1902 cfi->device_type, NULL); 1903 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1904 cfi->device_type, NULL); 1905 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi, 1906 cfi->device_type, NULL); 1907 xip_enable(map, chip, adr); 1908 /* FIXME - should have reset delay before continuing */ 1909 1910 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n", 1911 __func__, adr); 1912 1913 ret = -EIO; 1914 op_done: 1915 chip->state = FL_READY; 1916 DISABLE_VPP(map); 1917 put_chip(map, chip, adr); 1918 mutex_unlock(&chip->mutex); 1919 1920 return ret; 1921 } 1922 1923 1924 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, 1925 size_t *retlen, const u_char *buf) 1926 { 1927 struct map_info *map = mtd->priv; 1928 struct cfi_private *cfi = map->fldrv_priv; 1929 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; 1930 int ret = 0; 1931 int chipnum; 1932 unsigned long ofs; 1933 1934 chipnum = to >> cfi->chipshift; 1935 ofs = to - (chipnum << cfi->chipshift); 1936 1937 /* If it's not bus-aligned, do the first word write */ 1938 if (ofs & (map_bankwidth(map)-1)) { 1939 size_t local_len = (-ofs)&(map_bankwidth(map)-1); 1940 if (local_len > len) 1941 local_len = len; 1942 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), 1943 local_len, retlen, buf); 1944 if (ret) 1945 return ret; 1946 ofs += local_len; 1947 buf += local_len; 1948 len -= local_len; 1949 1950 if (ofs >> cfi->chipshift) { 1951 chipnum ++; 1952 ofs = 0; 1953 if (chipnum == cfi->numchips) 1954 return 0; 1955 } 1956 } 1957 1958 /* Write buffer is worth it only if more than one word to write... */ 1959 while (len >= map_bankwidth(map) * 2) { 1960 /* We must not cross write block boundaries */ 1961 int size = wbufsize - (ofs & (wbufsize-1)); 1962 1963 if (size > len) 1964 size = len; 1965 if (size % map_bankwidth(map)) 1966 size -= size % map_bankwidth(map); 1967 1968 ret = do_write_buffer(map, &cfi->chips[chipnum], 1969 ofs, buf, size); 1970 if (ret) 1971 return ret; 1972 1973 ofs += size; 1974 buf += size; 1975 (*retlen) += size; 1976 len -= size; 1977 1978 if (ofs >> cfi->chipshift) { 1979 chipnum ++; 1980 ofs = 0; 1981 if (chipnum == cfi->numchips) 1982 return 0; 1983 } 1984 } 1985 1986 if (len) { 1987 size_t retlen_dregs = 0; 1988 1989 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), 1990 len, &retlen_dregs, buf); 1991 1992 *retlen += retlen_dregs; 1993 return ret; 1994 } 1995 1996 return 0; 1997 } 1998 1999 /* 2000 * Wait for the flash chip to become ready to write data 2001 * 2002 * This is only called during the panic_write() path. When panic_write() 2003 * is called, the kernel is in the process of a panic, and will soon be 2004 * dead. Therefore we don't take any locks, and attempt to get access 2005 * to the chip as soon as possible. 2006 */ 2007 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip, 2008 unsigned long adr) 2009 { 2010 struct cfi_private *cfi = map->fldrv_priv; 2011 int retries = 10; 2012 int i; 2013 2014 /* 2015 * If the driver thinks the chip is idle, and no toggle bits 2016 * are changing, then the chip is actually idle for sure. 2017 */ 2018 if (chip->state == FL_READY && chip_ready(map, adr)) 2019 return 0; 2020 2021 /* 2022 * Try several times to reset the chip and then wait for it 2023 * to become idle. The upper limit of a few milliseconds of 2024 * delay isn't a big problem: the kernel is dying anyway. It 2025 * is more important to save the messages. 2026 */ 2027 while (retries > 0) { 2028 const unsigned long timeo = (HZ / 1000) + 1; 2029 2030 /* send the reset command */ 2031 map_write(map, CMD(0xF0), chip->start); 2032 2033 /* wait for the chip to become ready */ 2034 for (i = 0; i < jiffies_to_usecs(timeo); i++) { 2035 if (chip_ready(map, adr)) 2036 return 0; 2037 2038 udelay(1); 2039 } 2040 2041 retries--; 2042 } 2043 2044 /* the chip never became ready */ 2045 return -EBUSY; 2046 } 2047 2048 /* 2049 * Write out one word of data to a single flash chip during a kernel panic 2050 * 2051 * This is only called during the panic_write() path. When panic_write() 2052 * is called, the kernel is in the process of a panic, and will soon be 2053 * dead. Therefore we don't take any locks, and attempt to get access 2054 * to the chip as soon as possible. 2055 * 2056 * The implementation of this routine is intentionally similar to 2057 * do_write_oneword(), in order to ease code maintenance. 2058 */ 2059 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip, 2060 unsigned long adr, map_word datum) 2061 { 2062 const unsigned long uWriteTimeout = (HZ / 1000) + 1; 2063 struct cfi_private *cfi = map->fldrv_priv; 2064 int retry_cnt = 0; 2065 map_word oldd; 2066 int ret = 0; 2067 int i; 2068 2069 adr += chip->start; 2070 2071 ret = cfi_amdstd_panic_wait(map, chip, adr); 2072 if (ret) 2073 return ret; 2074 2075 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n", 2076 __func__, adr, datum.x[0]); 2077 2078 /* 2079 * Check for a NOP for the case when the datum to write is already 2080 * present - it saves time and works around buggy chips that corrupt 2081 * data at other locations when 0xff is written to a location that 2082 * already contains 0xff. 2083 */ 2084 oldd = map_read(map, adr); 2085 if (map_word_equal(map, oldd, datum)) { 2086 pr_debug("MTD %s(): NOP\n", __func__); 2087 goto op_done; 2088 } 2089 2090 ENABLE_VPP(map); 2091 2092 retry: 2093 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2094 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2095 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2096 map_write(map, datum, adr); 2097 2098 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) { 2099 if (chip_ready(map, adr)) 2100 break; 2101 2102 udelay(1); 2103 } 2104 2105 if (!chip_good(map, adr, datum)) { 2106 /* reset on all failures. */ 2107 map_write(map, CMD(0xF0), chip->start); 2108 /* FIXME - should have reset delay before continuing */ 2109 2110 if (++retry_cnt <= MAX_RETRIES) 2111 goto retry; 2112 2113 ret = -EIO; 2114 } 2115 2116 op_done: 2117 DISABLE_VPP(map); 2118 return ret; 2119 } 2120 2121 /* 2122 * Write out some data during a kernel panic 2123 * 2124 * This is used by the mtdoops driver to save the dying messages from a 2125 * kernel which has panic'd. 2126 * 2127 * This routine ignores all of the locking used throughout the rest of the 2128 * driver, in order to ensure that the data gets written out no matter what 2129 * state this driver (and the flash chip itself) was in when the kernel crashed. 2130 * 2131 * The implementation of this routine is intentionally similar to 2132 * cfi_amdstd_write_words(), in order to ease code maintenance. 2133 */ 2134 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, 2135 size_t *retlen, const u_char *buf) 2136 { 2137 struct map_info *map = mtd->priv; 2138 struct cfi_private *cfi = map->fldrv_priv; 2139 unsigned long ofs, chipstart; 2140 int ret = 0; 2141 int chipnum; 2142 2143 chipnum = to >> cfi->chipshift; 2144 ofs = to - (chipnum << cfi->chipshift); 2145 chipstart = cfi->chips[chipnum].start; 2146 2147 /* If it's not bus aligned, do the first byte write */ 2148 if (ofs & (map_bankwidth(map) - 1)) { 2149 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1); 2150 int i = ofs - bus_ofs; 2151 int n = 0; 2152 map_word tmp_buf; 2153 2154 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs); 2155 if (ret) 2156 return ret; 2157 2158 /* Load 'tmp_buf' with old contents of flash */ 2159 tmp_buf = map_read(map, bus_ofs + chipstart); 2160 2161 /* Number of bytes to copy from buffer */ 2162 n = min_t(int, len, map_bankwidth(map) - i); 2163 2164 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); 2165 2166 ret = do_panic_write_oneword(map, &cfi->chips[chipnum], 2167 bus_ofs, tmp_buf); 2168 if (ret) 2169 return ret; 2170 2171 ofs += n; 2172 buf += n; 2173 (*retlen) += n; 2174 len -= n; 2175 2176 if (ofs >> cfi->chipshift) { 2177 chipnum++; 2178 ofs = 0; 2179 if (chipnum == cfi->numchips) 2180 return 0; 2181 } 2182 } 2183 2184 /* We are now aligned, write as much as possible */ 2185 while (len >= map_bankwidth(map)) { 2186 map_word datum; 2187 2188 datum = map_word_load(map, buf); 2189 2190 ret = do_panic_write_oneword(map, &cfi->chips[chipnum], 2191 ofs, datum); 2192 if (ret) 2193 return ret; 2194 2195 ofs += map_bankwidth(map); 2196 buf += map_bankwidth(map); 2197 (*retlen) += map_bankwidth(map); 2198 len -= map_bankwidth(map); 2199 2200 if (ofs >> cfi->chipshift) { 2201 chipnum++; 2202 ofs = 0; 2203 if (chipnum == cfi->numchips) 2204 return 0; 2205 2206 chipstart = cfi->chips[chipnum].start; 2207 } 2208 } 2209 2210 /* Write the trailing bytes if any */ 2211 if (len & (map_bankwidth(map) - 1)) { 2212 map_word tmp_buf; 2213 2214 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs); 2215 if (ret) 2216 return ret; 2217 2218 tmp_buf = map_read(map, ofs + chipstart); 2219 2220 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); 2221 2222 ret = do_panic_write_oneword(map, &cfi->chips[chipnum], 2223 ofs, tmp_buf); 2224 if (ret) 2225 return ret; 2226 2227 (*retlen) += len; 2228 } 2229 2230 return 0; 2231 } 2232 2233 2234 /* 2235 * Handle devices with one erase region, that only implement 2236 * the chip erase command. 2237 */ 2238 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip) 2239 { 2240 struct cfi_private *cfi = map->fldrv_priv; 2241 unsigned long timeo = jiffies + HZ; 2242 unsigned long int adr; 2243 DECLARE_WAITQUEUE(wait, current); 2244 int ret = 0; 2245 int retry_cnt = 0; 2246 2247 adr = cfi->addr_unlock1; 2248 2249 mutex_lock(&chip->mutex); 2250 ret = get_chip(map, chip, adr, FL_WRITING); 2251 if (ret) { 2252 mutex_unlock(&chip->mutex); 2253 return ret; 2254 } 2255 2256 pr_debug("MTD %s(): ERASE 0x%.8lx\n", 2257 __func__, chip->start); 2258 2259 XIP_INVAL_CACHED_RANGE(map, adr, map->size); 2260 ENABLE_VPP(map); 2261 xip_disable(map, chip, adr); 2262 2263 retry: 2264 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2265 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2266 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2267 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2268 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2269 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2270 2271 chip->state = FL_ERASING; 2272 chip->erase_suspended = 0; 2273 chip->in_progress_block_addr = adr; 2274 chip->in_progress_block_mask = ~(map->size - 1); 2275 2276 INVALIDATE_CACHE_UDELAY(map, chip, 2277 adr, map->size, 2278 chip->erase_time*500); 2279 2280 timeo = jiffies + (HZ*20); 2281 2282 for (;;) { 2283 if (chip->state != FL_ERASING) { 2284 /* Someone's suspended the erase. Sleep */ 2285 set_current_state(TASK_UNINTERRUPTIBLE); 2286 add_wait_queue(&chip->wq, &wait); 2287 mutex_unlock(&chip->mutex); 2288 schedule(); 2289 remove_wait_queue(&chip->wq, &wait); 2290 mutex_lock(&chip->mutex); 2291 continue; 2292 } 2293 if (chip->erase_suspended) { 2294 /* This erase was suspended and resumed. 2295 Adjust the timeout */ 2296 timeo = jiffies + (HZ*20); /* FIXME */ 2297 chip->erase_suspended = 0; 2298 } 2299 2300 if (chip_good(map, adr, map_word_ff(map))) 2301 break; 2302 2303 if (time_after(jiffies, timeo)) { 2304 printk(KERN_WARNING "MTD %s(): software timeout\n", 2305 __func__); 2306 ret = -EIO; 2307 break; 2308 } 2309 2310 /* Latency issues. Drop the lock, wait a while and retry */ 2311 UDELAY(map, chip, adr, 1000000/HZ); 2312 } 2313 /* Did we succeed? */ 2314 if (ret) { 2315 /* reset on all failures. */ 2316 map_write(map, CMD(0xF0), chip->start); 2317 /* FIXME - should have reset delay before continuing */ 2318 2319 if (++retry_cnt <= MAX_RETRIES) { 2320 ret = 0; 2321 goto retry; 2322 } 2323 } 2324 2325 chip->state = FL_READY; 2326 xip_enable(map, chip, adr); 2327 DISABLE_VPP(map); 2328 put_chip(map, chip, adr); 2329 mutex_unlock(&chip->mutex); 2330 2331 return ret; 2332 } 2333 2334 2335 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk) 2336 { 2337 struct cfi_private *cfi = map->fldrv_priv; 2338 unsigned long timeo = jiffies + HZ; 2339 DECLARE_WAITQUEUE(wait, current); 2340 int ret = 0; 2341 int retry_cnt = 0; 2342 2343 adr += chip->start; 2344 2345 mutex_lock(&chip->mutex); 2346 ret = get_chip(map, chip, adr, FL_ERASING); 2347 if (ret) { 2348 mutex_unlock(&chip->mutex); 2349 return ret; 2350 } 2351 2352 pr_debug("MTD %s(): ERASE 0x%.8lx\n", 2353 __func__, adr); 2354 2355 XIP_INVAL_CACHED_RANGE(map, adr, len); 2356 ENABLE_VPP(map); 2357 xip_disable(map, chip, adr); 2358 2359 retry: 2360 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2361 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2362 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2363 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2364 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2365 map_write(map, cfi->sector_erase_cmd, adr); 2366 2367 chip->state = FL_ERASING; 2368 chip->erase_suspended = 0; 2369 chip->in_progress_block_addr = adr; 2370 chip->in_progress_block_mask = ~(len - 1); 2371 2372 INVALIDATE_CACHE_UDELAY(map, chip, 2373 adr, len, 2374 chip->erase_time*500); 2375 2376 timeo = jiffies + (HZ*20); 2377 2378 for (;;) { 2379 if (chip->state != FL_ERASING) { 2380 /* Someone's suspended the erase. Sleep */ 2381 set_current_state(TASK_UNINTERRUPTIBLE); 2382 add_wait_queue(&chip->wq, &wait); 2383 mutex_unlock(&chip->mutex); 2384 schedule(); 2385 remove_wait_queue(&chip->wq, &wait); 2386 mutex_lock(&chip->mutex); 2387 continue; 2388 } 2389 if (chip->erase_suspended) { 2390 /* This erase was suspended and resumed. 2391 Adjust the timeout */ 2392 timeo = jiffies + (HZ*20); /* FIXME */ 2393 chip->erase_suspended = 0; 2394 } 2395 2396 if (chip_good(map, adr, map_word_ff(map))) 2397 break; 2398 2399 if (time_after(jiffies, timeo)) { 2400 printk(KERN_WARNING "MTD %s(): software timeout\n", 2401 __func__); 2402 ret = -EIO; 2403 break; 2404 } 2405 2406 /* Latency issues. Drop the lock, wait a while and retry */ 2407 UDELAY(map, chip, adr, 1000000/HZ); 2408 } 2409 /* Did we succeed? */ 2410 if (ret) { 2411 /* reset on all failures. */ 2412 map_write(map, CMD(0xF0), chip->start); 2413 /* FIXME - should have reset delay before continuing */ 2414 2415 if (++retry_cnt <= MAX_RETRIES) { 2416 ret = 0; 2417 goto retry; 2418 } 2419 } 2420 2421 chip->state = FL_READY; 2422 xip_enable(map, chip, adr); 2423 DISABLE_VPP(map); 2424 put_chip(map, chip, adr); 2425 mutex_unlock(&chip->mutex); 2426 return ret; 2427 } 2428 2429 2430 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) 2431 { 2432 return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr, 2433 instr->len, NULL); 2434 } 2435 2436 2437 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr) 2438 { 2439 struct map_info *map = mtd->priv; 2440 struct cfi_private *cfi = map->fldrv_priv; 2441 2442 if (instr->addr != 0) 2443 return -EINVAL; 2444 2445 if (instr->len != mtd->size) 2446 return -EINVAL; 2447 2448 return do_erase_chip(map, &cfi->chips[0]); 2449 } 2450 2451 static int do_atmel_lock(struct map_info *map, struct flchip *chip, 2452 unsigned long adr, int len, void *thunk) 2453 { 2454 struct cfi_private *cfi = map->fldrv_priv; 2455 int ret; 2456 2457 mutex_lock(&chip->mutex); 2458 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); 2459 if (ret) 2460 goto out_unlock; 2461 chip->state = FL_LOCKING; 2462 2463 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len); 2464 2465 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2466 cfi->device_type, NULL); 2467 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 2468 cfi->device_type, NULL); 2469 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, 2470 cfi->device_type, NULL); 2471 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2472 cfi->device_type, NULL); 2473 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 2474 cfi->device_type, NULL); 2475 map_write(map, CMD(0x40), chip->start + adr); 2476 2477 chip->state = FL_READY; 2478 put_chip(map, chip, adr + chip->start); 2479 ret = 0; 2480 2481 out_unlock: 2482 mutex_unlock(&chip->mutex); 2483 return ret; 2484 } 2485 2486 static int do_atmel_unlock(struct map_info *map, struct flchip *chip, 2487 unsigned long adr, int len, void *thunk) 2488 { 2489 struct cfi_private *cfi = map->fldrv_priv; 2490 int ret; 2491 2492 mutex_lock(&chip->mutex); 2493 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING); 2494 if (ret) 2495 goto out_unlock; 2496 chip->state = FL_UNLOCKING; 2497 2498 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len); 2499 2500 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2501 cfi->device_type, NULL); 2502 map_write(map, CMD(0x70), adr); 2503 2504 chip->state = FL_READY; 2505 put_chip(map, chip, adr + chip->start); 2506 ret = 0; 2507 2508 out_unlock: 2509 mutex_unlock(&chip->mutex); 2510 return ret; 2511 } 2512 2513 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2514 { 2515 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL); 2516 } 2517 2518 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2519 { 2520 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL); 2521 } 2522 2523 /* 2524 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking 2525 */ 2526 2527 struct ppb_lock { 2528 struct flchip *chip; 2529 unsigned long adr; 2530 int locked; 2531 }; 2532 2533 #define MAX_SECTORS 512 2534 2535 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1) 2536 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2) 2537 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3) 2538 2539 static int __maybe_unused do_ppb_xxlock(struct map_info *map, 2540 struct flchip *chip, 2541 unsigned long adr, int len, void *thunk) 2542 { 2543 struct cfi_private *cfi = map->fldrv_priv; 2544 unsigned long timeo; 2545 int ret; 2546 2547 adr += chip->start; 2548 mutex_lock(&chip->mutex); 2549 ret = get_chip(map, chip, adr, FL_LOCKING); 2550 if (ret) { 2551 mutex_unlock(&chip->mutex); 2552 return ret; 2553 } 2554 2555 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len); 2556 2557 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2558 cfi->device_type, NULL); 2559 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 2560 cfi->device_type, NULL); 2561 /* PPB entry command */ 2562 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi, 2563 cfi->device_type, NULL); 2564 2565 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) { 2566 chip->state = FL_LOCKING; 2567 map_write(map, CMD(0xA0), adr); 2568 map_write(map, CMD(0x00), adr); 2569 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) { 2570 /* 2571 * Unlocking of one specific sector is not supported, so we 2572 * have to unlock all sectors of this device instead 2573 */ 2574 chip->state = FL_UNLOCKING; 2575 map_write(map, CMD(0x80), chip->start); 2576 map_write(map, CMD(0x30), chip->start); 2577 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) { 2578 chip->state = FL_JEDEC_QUERY; 2579 /* Return locked status: 0->locked, 1->unlocked */ 2580 ret = !cfi_read_query(map, adr); 2581 } else 2582 BUG(); 2583 2584 /* 2585 * Wait for some time as unlocking of all sectors takes quite long 2586 */ 2587 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */ 2588 for (;;) { 2589 if (chip_ready(map, adr)) 2590 break; 2591 2592 if (time_after(jiffies, timeo)) { 2593 printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); 2594 ret = -EIO; 2595 break; 2596 } 2597 2598 UDELAY(map, chip, adr, 1); 2599 } 2600 2601 /* Exit BC commands */ 2602 map_write(map, CMD(0x90), chip->start); 2603 map_write(map, CMD(0x00), chip->start); 2604 2605 chip->state = FL_READY; 2606 put_chip(map, chip, adr); 2607 mutex_unlock(&chip->mutex); 2608 2609 return ret; 2610 } 2611 2612 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, 2613 uint64_t len) 2614 { 2615 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len, 2616 DO_XXLOCK_ONEBLOCK_LOCK); 2617 } 2618 2619 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, 2620 uint64_t len) 2621 { 2622 struct mtd_erase_region_info *regions = mtd->eraseregions; 2623 struct map_info *map = mtd->priv; 2624 struct cfi_private *cfi = map->fldrv_priv; 2625 struct ppb_lock *sect; 2626 unsigned long adr; 2627 loff_t offset; 2628 uint64_t length; 2629 int chipnum; 2630 int i; 2631 int sectors; 2632 int ret; 2633 2634 /* 2635 * PPB unlocking always unlocks all sectors of the flash chip. 2636 * We need to re-lock all previously locked sectors. So lets 2637 * first check the locking status of all sectors and save 2638 * it for future use. 2639 */ 2640 sect = kcalloc(MAX_SECTORS, sizeof(struct ppb_lock), GFP_KERNEL); 2641 if (!sect) 2642 return -ENOMEM; 2643 2644 /* 2645 * This code to walk all sectors is a slightly modified version 2646 * of the cfi_varsize_frob() code. 2647 */ 2648 i = 0; 2649 chipnum = 0; 2650 adr = 0; 2651 sectors = 0; 2652 offset = 0; 2653 length = mtd->size; 2654 2655 while (length) { 2656 int size = regions[i].erasesize; 2657 2658 /* 2659 * Only test sectors that shall not be unlocked. The other 2660 * sectors shall be unlocked, so lets keep their locking 2661 * status at "unlocked" (locked=0) for the final re-locking. 2662 */ 2663 if ((offset < ofs) || (offset >= (ofs + len))) { 2664 sect[sectors].chip = &cfi->chips[chipnum]; 2665 sect[sectors].adr = adr; 2666 sect[sectors].locked = do_ppb_xxlock( 2667 map, &cfi->chips[chipnum], adr, 0, 2668 DO_XXLOCK_ONEBLOCK_GETLOCK); 2669 } 2670 2671 adr += size; 2672 offset += size; 2673 length -= size; 2674 2675 if (offset == regions[i].offset + size * regions[i].numblocks) 2676 i++; 2677 2678 if (adr >> cfi->chipshift) { 2679 if (offset >= (ofs + len)) 2680 break; 2681 adr = 0; 2682 chipnum++; 2683 2684 if (chipnum >= cfi->numchips) 2685 break; 2686 } 2687 2688 sectors++; 2689 if (sectors >= MAX_SECTORS) { 2690 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n", 2691 MAX_SECTORS); 2692 kfree(sect); 2693 return -EINVAL; 2694 } 2695 } 2696 2697 /* Now unlock the whole chip */ 2698 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len, 2699 DO_XXLOCK_ONEBLOCK_UNLOCK); 2700 if (ret) { 2701 kfree(sect); 2702 return ret; 2703 } 2704 2705 /* 2706 * PPB unlocking always unlocks all sectors of the flash chip. 2707 * We need to re-lock all previously locked sectors. 2708 */ 2709 for (i = 0; i < sectors; i++) { 2710 if (sect[i].locked) 2711 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0, 2712 DO_XXLOCK_ONEBLOCK_LOCK); 2713 } 2714 2715 kfree(sect); 2716 return ret; 2717 } 2718 2719 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, 2720 uint64_t len) 2721 { 2722 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len, 2723 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0; 2724 } 2725 2726 static void cfi_amdstd_sync (struct mtd_info *mtd) 2727 { 2728 struct map_info *map = mtd->priv; 2729 struct cfi_private *cfi = map->fldrv_priv; 2730 int i; 2731 struct flchip *chip; 2732 int ret = 0; 2733 DECLARE_WAITQUEUE(wait, current); 2734 2735 for (i=0; !ret && i<cfi->numchips; i++) { 2736 chip = &cfi->chips[i]; 2737 2738 retry: 2739 mutex_lock(&chip->mutex); 2740 2741 switch(chip->state) { 2742 case FL_READY: 2743 case FL_STATUS: 2744 case FL_CFI_QUERY: 2745 case FL_JEDEC_QUERY: 2746 chip->oldstate = chip->state; 2747 chip->state = FL_SYNCING; 2748 /* No need to wake_up() on this state change - 2749 * as the whole point is that nobody can do anything 2750 * with the chip now anyway. 2751 */ 2752 case FL_SYNCING: 2753 mutex_unlock(&chip->mutex); 2754 break; 2755 2756 default: 2757 /* Not an idle state */ 2758 set_current_state(TASK_UNINTERRUPTIBLE); 2759 add_wait_queue(&chip->wq, &wait); 2760 2761 mutex_unlock(&chip->mutex); 2762 2763 schedule(); 2764 2765 remove_wait_queue(&chip->wq, &wait); 2766 2767 goto retry; 2768 } 2769 } 2770 2771 /* Unlock the chips again */ 2772 2773 for (i--; i >=0; i--) { 2774 chip = &cfi->chips[i]; 2775 2776 mutex_lock(&chip->mutex); 2777 2778 if (chip->state == FL_SYNCING) { 2779 chip->state = chip->oldstate; 2780 wake_up(&chip->wq); 2781 } 2782 mutex_unlock(&chip->mutex); 2783 } 2784 } 2785 2786 2787 static int cfi_amdstd_suspend(struct mtd_info *mtd) 2788 { 2789 struct map_info *map = mtd->priv; 2790 struct cfi_private *cfi = map->fldrv_priv; 2791 int i; 2792 struct flchip *chip; 2793 int ret = 0; 2794 2795 for (i=0; !ret && i<cfi->numchips; i++) { 2796 chip = &cfi->chips[i]; 2797 2798 mutex_lock(&chip->mutex); 2799 2800 switch(chip->state) { 2801 case FL_READY: 2802 case FL_STATUS: 2803 case FL_CFI_QUERY: 2804 case FL_JEDEC_QUERY: 2805 chip->oldstate = chip->state; 2806 chip->state = FL_PM_SUSPENDED; 2807 /* No need to wake_up() on this state change - 2808 * as the whole point is that nobody can do anything 2809 * with the chip now anyway. 2810 */ 2811 case FL_PM_SUSPENDED: 2812 break; 2813 2814 default: 2815 ret = -EAGAIN; 2816 break; 2817 } 2818 mutex_unlock(&chip->mutex); 2819 } 2820 2821 /* Unlock the chips again */ 2822 2823 if (ret) { 2824 for (i--; i >=0; i--) { 2825 chip = &cfi->chips[i]; 2826 2827 mutex_lock(&chip->mutex); 2828 2829 if (chip->state == FL_PM_SUSPENDED) { 2830 chip->state = chip->oldstate; 2831 wake_up(&chip->wq); 2832 } 2833 mutex_unlock(&chip->mutex); 2834 } 2835 } 2836 2837 return ret; 2838 } 2839 2840 2841 static void cfi_amdstd_resume(struct mtd_info *mtd) 2842 { 2843 struct map_info *map = mtd->priv; 2844 struct cfi_private *cfi = map->fldrv_priv; 2845 int i; 2846 struct flchip *chip; 2847 2848 for (i=0; i<cfi->numchips; i++) { 2849 2850 chip = &cfi->chips[i]; 2851 2852 mutex_lock(&chip->mutex); 2853 2854 if (chip->state == FL_PM_SUSPENDED) { 2855 chip->state = FL_READY; 2856 map_write(map, CMD(0xF0), chip->start); 2857 wake_up(&chip->wq); 2858 } 2859 else 2860 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n"); 2861 2862 mutex_unlock(&chip->mutex); 2863 } 2864 } 2865 2866 2867 /* 2868 * Ensure that the flash device is put back into read array mode before 2869 * unloading the driver or rebooting. On some systems, rebooting while 2870 * the flash is in query/program/erase mode will prevent the CPU from 2871 * fetching the bootloader code, requiring a hard reset or power cycle. 2872 */ 2873 static int cfi_amdstd_reset(struct mtd_info *mtd) 2874 { 2875 struct map_info *map = mtd->priv; 2876 struct cfi_private *cfi = map->fldrv_priv; 2877 int i, ret; 2878 struct flchip *chip; 2879 2880 for (i = 0; i < cfi->numchips; i++) { 2881 2882 chip = &cfi->chips[i]; 2883 2884 mutex_lock(&chip->mutex); 2885 2886 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN); 2887 if (!ret) { 2888 map_write(map, CMD(0xF0), chip->start); 2889 chip->state = FL_SHUTDOWN; 2890 put_chip(map, chip, chip->start); 2891 } 2892 2893 mutex_unlock(&chip->mutex); 2894 } 2895 2896 return 0; 2897 } 2898 2899 2900 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val, 2901 void *v) 2902 { 2903 struct mtd_info *mtd; 2904 2905 mtd = container_of(nb, struct mtd_info, reboot_notifier); 2906 cfi_amdstd_reset(mtd); 2907 return NOTIFY_DONE; 2908 } 2909 2910 2911 static void cfi_amdstd_destroy(struct mtd_info *mtd) 2912 { 2913 struct map_info *map = mtd->priv; 2914 struct cfi_private *cfi = map->fldrv_priv; 2915 2916 cfi_amdstd_reset(mtd); 2917 unregister_reboot_notifier(&mtd->reboot_notifier); 2918 kfree(cfi->cmdset_priv); 2919 kfree(cfi->cfiq); 2920 kfree(cfi); 2921 kfree(mtd->eraseregions); 2922 } 2923 2924 MODULE_LICENSE("GPL"); 2925 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al."); 2926 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips"); 2927 MODULE_ALIAS("cfi_cmdset_0006"); 2928 MODULE_ALIAS("cfi_cmdset_0701"); 2929