1 /* 2 * WM8505/WM8650 SD/MMC Host Controller 3 * 4 * Copyright (C) 2010 Tony Prisk 5 * Copyright (C) 2008 WonderMedia Technologies, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation 10 */ 11 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/ioport.h> 16 #include <linux/errno.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/delay.h> 19 #include <linux/io.h> 20 #include <linux/irq.h> 21 #include <linux/clk.h> 22 #include <linux/gpio.h> 23 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_device.h> 28 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sd.h> 32 33 #include <asm/byteorder.h> 34 35 36 #define DRIVER_NAME "wmt-sdhc" 37 38 39 /* MMC/SD controller registers */ 40 #define SDMMC_CTLR 0x00 41 #define SDMMC_CMD 0x01 42 #define SDMMC_RSPTYPE 0x02 43 #define SDMMC_ARG 0x04 44 #define SDMMC_BUSMODE 0x08 45 #define SDMMC_BLKLEN 0x0C 46 #define SDMMC_BLKCNT 0x0E 47 #define SDMMC_RSP 0x10 48 #define SDMMC_CBCR 0x20 49 #define SDMMC_INTMASK0 0x24 50 #define SDMMC_INTMASK1 0x25 51 #define SDMMC_STS0 0x28 52 #define SDMMC_STS1 0x29 53 #define SDMMC_STS2 0x2A 54 #define SDMMC_STS3 0x2B 55 #define SDMMC_RSPTIMEOUT 0x2C 56 #define SDMMC_CLK 0x30 /* VT8500 only */ 57 #define SDMMC_EXTCTRL 0x34 58 #define SDMMC_SBLKLEN 0x38 59 #define SDMMC_DMATIMEOUT 0x3C 60 61 62 /* SDMMC_CTLR bit fields */ 63 #define CTLR_CMD_START 0x01 64 #define CTLR_CMD_WRITE 0x04 65 #define CTLR_FIFO_RESET 0x08 66 67 /* SDMMC_BUSMODE bit fields */ 68 #define BM_SPI_MODE 0x01 69 #define BM_FOURBIT_MODE 0x02 70 #define BM_EIGHTBIT_MODE 0x04 71 #define BM_SD_OFF 0x10 72 #define BM_SPI_CS 0x20 73 #define BM_SD_POWER 0x40 74 #define BM_SOFT_RESET 0x80 75 #define BM_ONEBIT_MASK 0xFD 76 77 /* SDMMC_BLKLEN bit fields */ 78 #define BLKL_CRCERR_ABORT 0x0800 79 #define BLKL_CD_POL_HIGH 0x1000 80 #define BLKL_GPI_CD 0x2000 81 #define BLKL_DATA3_CD 0x4000 82 #define BLKL_INT_ENABLE 0x8000 83 84 /* SDMMC_INTMASK0 bit fields */ 85 #define INT0_MBLK_TRAN_DONE_INT_EN 0x10 86 #define INT0_BLK_TRAN_DONE_INT_EN 0x20 87 #define INT0_CD_INT_EN 0x40 88 #define INT0_DI_INT_EN 0x80 89 90 /* SDMMC_INTMASK1 bit fields */ 91 #define INT1_CMD_RES_TRAN_DONE_INT_EN 0x02 92 #define INT1_CMD_RES_TOUT_INT_EN 0x04 93 #define INT1_MBLK_AUTO_STOP_INT_EN 0x08 94 #define INT1_DATA_TOUT_INT_EN 0x10 95 #define INT1_RESCRC_ERR_INT_EN 0x20 96 #define INT1_RCRC_ERR_INT_EN 0x40 97 #define INT1_WCRC_ERR_INT_EN 0x80 98 99 /* SDMMC_STS0 bit fields */ 100 #define STS0_WRITE_PROTECT 0x02 101 #define STS0_CD_DATA3 0x04 102 #define STS0_CD_GPI 0x08 103 #define STS0_MBLK_DONE 0x10 104 #define STS0_BLK_DONE 0x20 105 #define STS0_CARD_DETECT 0x40 106 #define STS0_DEVICE_INS 0x80 107 108 /* SDMMC_STS1 bit fields */ 109 #define STS1_SDIO_INT 0x01 110 #define STS1_CMDRSP_DONE 0x02 111 #define STS1_RSP_TIMEOUT 0x04 112 #define STS1_AUTOSTOP_DONE 0x08 113 #define STS1_DATA_TIMEOUT 0x10 114 #define STS1_RSP_CRC_ERR 0x20 115 #define STS1_RCRC_ERR 0x40 116 #define STS1_WCRC_ERR 0x80 117 118 /* SDMMC_STS2 bit fields */ 119 #define STS2_CMD_RES_BUSY 0x10 120 #define STS2_DATARSP_BUSY 0x20 121 #define STS2_DIS_FORCECLK 0x80 122 123 124 /* MMC/SD DMA Controller Registers */ 125 #define SDDMA_GCR 0x100 126 #define SDDMA_IER 0x104 127 #define SDDMA_ISR 0x108 128 #define SDDMA_DESPR 0x10C 129 #define SDDMA_RBR 0x110 130 #define SDDMA_DAR 0x114 131 #define SDDMA_BAR 0x118 132 #define SDDMA_CPR 0x11C 133 #define SDDMA_CCR 0x120 134 135 136 /* SDDMA_GCR bit fields */ 137 #define DMA_GCR_DMA_EN 0x00000001 138 #define DMA_GCR_SOFT_RESET 0x00000100 139 140 /* SDDMA_IER bit fields */ 141 #define DMA_IER_INT_EN 0x00000001 142 143 /* SDDMA_ISR bit fields */ 144 #define DMA_ISR_INT_STS 0x00000001 145 146 /* SDDMA_RBR bit fields */ 147 #define DMA_RBR_FORMAT 0x40000000 148 #define DMA_RBR_END 0x80000000 149 150 /* SDDMA_CCR bit fields */ 151 #define DMA_CCR_RUN 0x00000080 152 #define DMA_CCR_IF_TO_PERIPHERAL 0x00000000 153 #define DMA_CCR_PERIPHERAL_TO_IF 0x00400000 154 155 /* SDDMA_CCR event status */ 156 #define DMA_CCR_EVT_NO_STATUS 0x00000000 157 #define DMA_CCR_EVT_UNDERRUN 0x00000001 158 #define DMA_CCR_EVT_OVERRUN 0x00000002 159 #define DMA_CCR_EVT_DESP_READ 0x00000003 160 #define DMA_CCR_EVT_DATA_RW 0x00000004 161 #define DMA_CCR_EVT_EARLY_END 0x00000005 162 #define DMA_CCR_EVT_SUCCESS 0x0000000F 163 164 #define PDMA_READ 0x00 165 #define PDMA_WRITE 0x01 166 167 #define WMT_SD_POWER_OFF 0 168 #define WMT_SD_POWER_ON 1 169 170 struct wmt_dma_descriptor { 171 u32 flags; 172 u32 data_buffer_addr; 173 u32 branch_addr; 174 u32 reserved1; 175 }; 176 177 struct wmt_mci_caps { 178 unsigned int f_min; 179 unsigned int f_max; 180 u32 ocr_avail; 181 u32 caps; 182 u32 max_seg_size; 183 u32 max_segs; 184 u32 max_blk_size; 185 }; 186 187 struct wmt_mci_priv { 188 struct mmc_host *mmc; 189 void __iomem *sdmmc_base; 190 191 int irq_regular; 192 int irq_dma; 193 194 void *dma_desc_buffer; 195 dma_addr_t dma_desc_device_addr; 196 197 struct completion cmdcomp; 198 struct completion datacomp; 199 200 struct completion *comp_cmd; 201 struct completion *comp_dma; 202 203 struct mmc_request *req; 204 struct mmc_command *cmd; 205 206 struct clk *clk_sdmmc; 207 struct device *dev; 208 209 u8 power_inverted; 210 u8 cd_inverted; 211 }; 212 213 static void wmt_set_sd_power(struct wmt_mci_priv *priv, int enable) 214 { 215 u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); 216 217 if (enable ^ priv->power_inverted) 218 reg_tmp &= ~BM_SD_OFF; 219 else 220 reg_tmp |= BM_SD_OFF; 221 222 writeb(reg_tmp, priv->sdmmc_base + SDMMC_BUSMODE); 223 } 224 225 static void wmt_mci_read_response(struct mmc_host *mmc) 226 { 227 struct wmt_mci_priv *priv; 228 int idx1, idx2; 229 u8 tmp_resp; 230 u32 response; 231 232 priv = mmc_priv(mmc); 233 234 for (idx1 = 0; idx1 < 4; idx1++) { 235 response = 0; 236 for (idx2 = 0; idx2 < 4; idx2++) { 237 if ((idx1 == 3) && (idx2 == 3)) 238 tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP); 239 else 240 tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP + 241 (idx1*4) + idx2 + 1); 242 response |= (tmp_resp << (idx2 * 8)); 243 } 244 priv->cmd->resp[idx1] = cpu_to_be32(response); 245 } 246 } 247 248 static void wmt_mci_start_command(struct wmt_mci_priv *priv) 249 { 250 u32 reg_tmp; 251 252 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR); 253 writeb(reg_tmp | CTLR_CMD_START, priv->sdmmc_base + SDMMC_CTLR); 254 } 255 256 static int wmt_mci_send_command(struct mmc_host *mmc, u8 command, u8 cmdtype, 257 u32 arg, u8 rsptype) 258 { 259 struct wmt_mci_priv *priv; 260 u32 reg_tmp; 261 262 priv = mmc_priv(mmc); 263 264 /* write command, arg, resptype registers */ 265 writeb(command, priv->sdmmc_base + SDMMC_CMD); 266 writel(arg, priv->sdmmc_base + SDMMC_ARG); 267 writeb(rsptype, priv->sdmmc_base + SDMMC_RSPTYPE); 268 269 /* reset response FIFO */ 270 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR); 271 writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR); 272 273 /* ensure clock enabled - VT3465 */ 274 wmt_set_sd_power(priv, WMT_SD_POWER_ON); 275 276 /* clear status bits */ 277 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0); 278 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1); 279 writeb(0xFF, priv->sdmmc_base + SDMMC_STS2); 280 writeb(0xFF, priv->sdmmc_base + SDMMC_STS3); 281 282 /* set command type */ 283 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR); 284 writeb((reg_tmp & 0x0F) | (cmdtype << 4), 285 priv->sdmmc_base + SDMMC_CTLR); 286 287 return 0; 288 } 289 290 static void wmt_mci_disable_dma(struct wmt_mci_priv *priv) 291 { 292 writel(DMA_ISR_INT_STS, priv->sdmmc_base + SDDMA_ISR); 293 writel(0, priv->sdmmc_base + SDDMA_IER); 294 } 295 296 static void wmt_complete_data_request(struct wmt_mci_priv *priv) 297 { 298 struct mmc_request *req; 299 req = priv->req; 300 301 req->data->bytes_xfered = req->data->blksz * req->data->blocks; 302 303 /* unmap the DMA pages used for write data */ 304 if (req->data->flags & MMC_DATA_WRITE) 305 dma_unmap_sg(mmc_dev(priv->mmc), req->data->sg, 306 req->data->sg_len, DMA_TO_DEVICE); 307 else 308 dma_unmap_sg(mmc_dev(priv->mmc), req->data->sg, 309 req->data->sg_len, DMA_FROM_DEVICE); 310 311 /* Check if the DMA ISR returned a data error */ 312 if ((req->cmd->error) || (req->data->error)) 313 mmc_request_done(priv->mmc, req); 314 else { 315 wmt_mci_read_response(priv->mmc); 316 if (!req->data->stop) { 317 /* single-block read/write requests end here */ 318 mmc_request_done(priv->mmc, req); 319 } else { 320 /* 321 * we change the priv->cmd variable so the response is 322 * stored in the stop struct rather than the original 323 * calling command struct 324 */ 325 priv->comp_cmd = &priv->cmdcomp; 326 init_completion(priv->comp_cmd); 327 priv->cmd = req->data->stop; 328 wmt_mci_send_command(priv->mmc, req->data->stop->opcode, 329 7, req->data->stop->arg, 9); 330 wmt_mci_start_command(priv); 331 } 332 } 333 } 334 335 static irqreturn_t wmt_mci_dma_isr(int irq_num, void *data) 336 { 337 struct wmt_mci_priv *priv; 338 339 int status; 340 341 priv = (struct wmt_mci_priv *)data; 342 343 status = readl(priv->sdmmc_base + SDDMA_CCR) & 0x0F; 344 345 if (status != DMA_CCR_EVT_SUCCESS) { 346 dev_err(priv->dev, "DMA Error: Status = %d\n", status); 347 priv->req->data->error = -ETIMEDOUT; 348 complete(priv->comp_dma); 349 return IRQ_HANDLED; 350 } 351 352 priv->req->data->error = 0; 353 354 wmt_mci_disable_dma(priv); 355 356 complete(priv->comp_dma); 357 358 if (priv->comp_cmd) { 359 if (completion_done(priv->comp_cmd)) { 360 /* 361 * if the command (regular) interrupt has already 362 * completed, finish off the request otherwise we wait 363 * for the command interrupt and finish from there. 364 */ 365 wmt_complete_data_request(priv); 366 } 367 } 368 369 return IRQ_HANDLED; 370 } 371 372 static irqreturn_t wmt_mci_regular_isr(int irq_num, void *data) 373 { 374 struct wmt_mci_priv *priv; 375 u32 status0; 376 u32 status1; 377 u32 status2; 378 u32 reg_tmp; 379 int cmd_done; 380 381 priv = (struct wmt_mci_priv *)data; 382 cmd_done = 0; 383 status0 = readb(priv->sdmmc_base + SDMMC_STS0); 384 status1 = readb(priv->sdmmc_base + SDMMC_STS1); 385 status2 = readb(priv->sdmmc_base + SDMMC_STS2); 386 387 /* Check for card insertion */ 388 reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0); 389 if ((reg_tmp & INT0_DI_INT_EN) && (status0 & STS0_DEVICE_INS)) { 390 mmc_detect_change(priv->mmc, 0); 391 if (priv->cmd) 392 priv->cmd->error = -ETIMEDOUT; 393 if (priv->comp_cmd) 394 complete(priv->comp_cmd); 395 if (priv->comp_dma) { 396 wmt_mci_disable_dma(priv); 397 complete(priv->comp_dma); 398 } 399 writeb(STS0_DEVICE_INS, priv->sdmmc_base + SDMMC_STS0); 400 return IRQ_HANDLED; 401 } 402 403 if ((!priv->req->data) || 404 ((priv->req->data->stop) && (priv->cmd == priv->req->data->stop))) { 405 /* handle non-data & stop_transmission requests */ 406 if (status1 & STS1_CMDRSP_DONE) { 407 priv->cmd->error = 0; 408 cmd_done = 1; 409 } else if ((status1 & STS1_RSP_TIMEOUT) || 410 (status1 & STS1_DATA_TIMEOUT)) { 411 priv->cmd->error = -ETIMEDOUT; 412 cmd_done = 1; 413 } 414 415 if (cmd_done) { 416 priv->comp_cmd = NULL; 417 418 if (!priv->cmd->error) 419 wmt_mci_read_response(priv->mmc); 420 421 priv->cmd = NULL; 422 423 mmc_request_done(priv->mmc, priv->req); 424 } 425 } else { 426 /* handle data requests */ 427 if (status1 & STS1_CMDRSP_DONE) { 428 if (priv->cmd) 429 priv->cmd->error = 0; 430 if (priv->comp_cmd) 431 complete(priv->comp_cmd); 432 } 433 434 if ((status1 & STS1_RSP_TIMEOUT) || 435 (status1 & STS1_DATA_TIMEOUT)) { 436 if (priv->cmd) 437 priv->cmd->error = -ETIMEDOUT; 438 if (priv->comp_cmd) 439 complete(priv->comp_cmd); 440 if (priv->comp_dma) { 441 wmt_mci_disable_dma(priv); 442 complete(priv->comp_dma); 443 } 444 } 445 446 if (priv->comp_dma) { 447 /* 448 * If the dma interrupt has already completed, finish 449 * off the request; otherwise we wait for the DMA 450 * interrupt and finish from there. 451 */ 452 if (completion_done(priv->comp_dma)) 453 wmt_complete_data_request(priv); 454 } 455 } 456 457 writeb(status0, priv->sdmmc_base + SDMMC_STS0); 458 writeb(status1, priv->sdmmc_base + SDMMC_STS1); 459 writeb(status2, priv->sdmmc_base + SDMMC_STS2); 460 461 return IRQ_HANDLED; 462 } 463 464 static void wmt_reset_hardware(struct mmc_host *mmc) 465 { 466 struct wmt_mci_priv *priv; 467 u32 reg_tmp; 468 469 priv = mmc_priv(mmc); 470 471 /* reset controller */ 472 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); 473 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE); 474 475 /* reset response FIFO */ 476 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR); 477 writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR); 478 479 /* enable GPI pin to detect card */ 480 writew(BLKL_INT_ENABLE | BLKL_GPI_CD, priv->sdmmc_base + SDMMC_BLKLEN); 481 482 /* clear interrupt status */ 483 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0); 484 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1); 485 486 /* setup interrupts */ 487 writeb(INT0_CD_INT_EN | INT0_DI_INT_EN, priv->sdmmc_base + 488 SDMMC_INTMASK0); 489 writeb(INT1_DATA_TOUT_INT_EN | INT1_CMD_RES_TRAN_DONE_INT_EN | 490 INT1_CMD_RES_TOUT_INT_EN, priv->sdmmc_base + SDMMC_INTMASK1); 491 492 /* set the DMA timeout */ 493 writew(8191, priv->sdmmc_base + SDMMC_DMATIMEOUT); 494 495 /* auto clock freezing enable */ 496 reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2); 497 writeb(reg_tmp | STS2_DIS_FORCECLK, priv->sdmmc_base + SDMMC_STS2); 498 499 /* set a default clock speed of 400Khz */ 500 clk_set_rate(priv->clk_sdmmc, 400000); 501 } 502 503 static int wmt_dma_init(struct mmc_host *mmc) 504 { 505 struct wmt_mci_priv *priv; 506 507 priv = mmc_priv(mmc); 508 509 writel(DMA_GCR_SOFT_RESET, priv->sdmmc_base + SDDMA_GCR); 510 writel(DMA_GCR_DMA_EN, priv->sdmmc_base + SDDMA_GCR); 511 if ((readl(priv->sdmmc_base + SDDMA_GCR) & DMA_GCR_DMA_EN) != 0) 512 return 0; 513 else 514 return 1; 515 } 516 517 static void wmt_dma_init_descriptor(struct wmt_dma_descriptor *desc, 518 u16 req_count, u32 buffer_addr, u32 branch_addr, int end) 519 { 520 desc->flags = 0x40000000 | req_count; 521 if (end) 522 desc->flags |= 0x80000000; 523 desc->data_buffer_addr = buffer_addr; 524 desc->branch_addr = branch_addr; 525 } 526 527 static void wmt_dma_config(struct mmc_host *mmc, u32 descaddr, u8 dir) 528 { 529 struct wmt_mci_priv *priv; 530 u32 reg_tmp; 531 532 priv = mmc_priv(mmc); 533 534 /* Enable DMA Interrupts */ 535 writel(DMA_IER_INT_EN, priv->sdmmc_base + SDDMA_IER); 536 537 /* Write DMA Descriptor Pointer Register */ 538 writel(descaddr, priv->sdmmc_base + SDDMA_DESPR); 539 540 writel(0x00, priv->sdmmc_base + SDDMA_CCR); 541 542 if (dir == PDMA_WRITE) { 543 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR); 544 writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base + 545 SDDMA_CCR); 546 } else { 547 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR); 548 writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base + 549 SDDMA_CCR); 550 } 551 } 552 553 static void wmt_dma_start(struct wmt_mci_priv *priv) 554 { 555 u32 reg_tmp; 556 557 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR); 558 writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR); 559 } 560 561 static void wmt_mci_request(struct mmc_host *mmc, struct mmc_request *req) 562 { 563 struct wmt_mci_priv *priv; 564 struct wmt_dma_descriptor *desc; 565 u8 command; 566 u8 cmdtype; 567 u32 arg; 568 u8 rsptype; 569 u32 reg_tmp; 570 571 struct scatterlist *sg; 572 int i; 573 int sg_cnt; 574 int offset; 575 u32 dma_address; 576 int desc_cnt; 577 578 priv = mmc_priv(mmc); 579 priv->req = req; 580 581 /* 582 * Use the cmd variable to pass a pointer to the resp[] structure 583 * This is required on multi-block requests to pass the pointer to the 584 * stop command 585 */ 586 priv->cmd = req->cmd; 587 588 command = req->cmd->opcode; 589 arg = req->cmd->arg; 590 rsptype = mmc_resp_type(req->cmd); 591 cmdtype = 0; 592 593 /* rsptype=7 only valid for SPI commands - should be =2 for SD */ 594 if (rsptype == 7) 595 rsptype = 2; 596 /* rsptype=21 is R1B, convert for controller */ 597 if (rsptype == 21) 598 rsptype = 9; 599 600 if (!req->data) { 601 wmt_mci_send_command(mmc, command, cmdtype, arg, rsptype); 602 wmt_mci_start_command(priv); 603 /* completion is now handled in the regular_isr() */ 604 } 605 if (req->data) { 606 priv->comp_cmd = &priv->cmdcomp; 607 init_completion(priv->comp_cmd); 608 609 wmt_dma_init(mmc); 610 611 /* set controller data length */ 612 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN); 613 writew((reg_tmp & 0xF800) | (req->data->blksz - 1), 614 priv->sdmmc_base + SDMMC_BLKLEN); 615 616 /* set controller block count */ 617 writew(req->data->blocks, priv->sdmmc_base + SDMMC_BLKCNT); 618 619 desc = (struct wmt_dma_descriptor *)priv->dma_desc_buffer; 620 621 if (req->data->flags & MMC_DATA_WRITE) { 622 sg_cnt = dma_map_sg(mmc_dev(mmc), req->data->sg, 623 req->data->sg_len, DMA_TO_DEVICE); 624 cmdtype = 1; 625 if (req->data->blocks > 1) 626 cmdtype = 3; 627 } else { 628 sg_cnt = dma_map_sg(mmc_dev(mmc), req->data->sg, 629 req->data->sg_len, DMA_FROM_DEVICE); 630 cmdtype = 2; 631 if (req->data->blocks > 1) 632 cmdtype = 4; 633 } 634 635 dma_address = priv->dma_desc_device_addr + 16; 636 desc_cnt = 0; 637 638 for_each_sg(req->data->sg, sg, sg_cnt, i) { 639 offset = 0; 640 while (offset < sg_dma_len(sg)) { 641 wmt_dma_init_descriptor(desc, req->data->blksz, 642 sg_dma_address(sg)+offset, 643 dma_address, 0); 644 desc++; 645 desc_cnt++; 646 offset += req->data->blksz; 647 dma_address += 16; 648 if (desc_cnt == req->data->blocks) 649 break; 650 } 651 } 652 desc--; 653 desc->flags |= 0x80000000; 654 655 if (req->data->flags & MMC_DATA_WRITE) 656 wmt_dma_config(mmc, priv->dma_desc_device_addr, 657 PDMA_WRITE); 658 else 659 wmt_dma_config(mmc, priv->dma_desc_device_addr, 660 PDMA_READ); 661 662 wmt_mci_send_command(mmc, command, cmdtype, arg, rsptype); 663 664 priv->comp_dma = &priv->datacomp; 665 init_completion(priv->comp_dma); 666 667 wmt_dma_start(priv); 668 wmt_mci_start_command(priv); 669 } 670 } 671 672 static void wmt_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 673 { 674 struct wmt_mci_priv *priv; 675 u32 reg_tmp; 676 677 priv = mmc_priv(mmc); 678 679 if (ios->power_mode == MMC_POWER_UP) { 680 wmt_reset_hardware(mmc); 681 682 wmt_set_sd_power(priv, WMT_SD_POWER_ON); 683 } 684 if (ios->power_mode == MMC_POWER_OFF) 685 wmt_set_sd_power(priv, WMT_SD_POWER_OFF); 686 687 if (ios->clock != 0) 688 clk_set_rate(priv->clk_sdmmc, ios->clock); 689 690 switch (ios->bus_width) { 691 case MMC_BUS_WIDTH_8: 692 reg_tmp = readb(priv->sdmmc_base + SDMMC_EXTCTRL); 693 writeb(reg_tmp | 0x04, priv->sdmmc_base + SDMMC_EXTCTRL); 694 break; 695 case MMC_BUS_WIDTH_4: 696 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); 697 writeb(reg_tmp | BM_FOURBIT_MODE, priv->sdmmc_base + 698 SDMMC_BUSMODE); 699 700 reg_tmp = readb(priv->sdmmc_base + SDMMC_EXTCTRL); 701 writeb(reg_tmp & 0xFB, priv->sdmmc_base + SDMMC_EXTCTRL); 702 break; 703 case MMC_BUS_WIDTH_1: 704 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); 705 writeb(reg_tmp & BM_ONEBIT_MASK, priv->sdmmc_base + 706 SDMMC_BUSMODE); 707 708 reg_tmp = readb(priv->sdmmc_base + SDMMC_EXTCTRL); 709 writeb(reg_tmp & 0xFB, priv->sdmmc_base + SDMMC_EXTCTRL); 710 break; 711 } 712 } 713 714 static int wmt_mci_get_ro(struct mmc_host *mmc) 715 { 716 struct wmt_mci_priv *priv = mmc_priv(mmc); 717 718 return !(readb(priv->sdmmc_base + SDMMC_STS0) & STS0_WRITE_PROTECT); 719 } 720 721 static int wmt_mci_get_cd(struct mmc_host *mmc) 722 { 723 struct wmt_mci_priv *priv = mmc_priv(mmc); 724 u32 cd = (readb(priv->sdmmc_base + SDMMC_STS0) & STS0_CD_GPI) >> 3; 725 726 return !(cd ^ priv->cd_inverted); 727 } 728 729 static struct mmc_host_ops wmt_mci_ops = { 730 .request = wmt_mci_request, 731 .set_ios = wmt_mci_set_ios, 732 .get_ro = wmt_mci_get_ro, 733 .get_cd = wmt_mci_get_cd, 734 }; 735 736 /* Controller capabilities */ 737 static struct wmt_mci_caps wm8505_caps = { 738 .f_min = 390425, 739 .f_max = 50000000, 740 .ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34, 741 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | 742 MMC_CAP_SD_HIGHSPEED, 743 .max_seg_size = 65024, 744 .max_segs = 128, 745 .max_blk_size = 2048, 746 }; 747 748 static struct of_device_id wmt_mci_dt_ids[] = { 749 { .compatible = "wm,wm8505-sdhc", .data = &wm8505_caps }, 750 { /* Sentinel */ }, 751 }; 752 753 static int wmt_mci_probe(struct platform_device *pdev) 754 { 755 struct mmc_host *mmc; 756 struct wmt_mci_priv *priv; 757 struct device_node *np = pdev->dev.of_node; 758 const struct of_device_id *of_id = 759 of_match_device(wmt_mci_dt_ids, &pdev->dev); 760 const struct wmt_mci_caps *wmt_caps; 761 int ret; 762 int regular_irq, dma_irq; 763 764 if (!of_id || !of_id->data) { 765 dev_err(&pdev->dev, "Controller capabilities data missing\n"); 766 return -EFAULT; 767 } 768 769 wmt_caps = of_id->data; 770 771 if (!np) { 772 dev_err(&pdev->dev, "Missing SDMMC description in devicetree\n"); 773 return -EFAULT; 774 } 775 776 regular_irq = irq_of_parse_and_map(np, 0); 777 dma_irq = irq_of_parse_and_map(np, 1); 778 779 if (!regular_irq || !dma_irq) { 780 dev_err(&pdev->dev, "Getting IRQs failed!\n"); 781 ret = -ENXIO; 782 goto fail1; 783 } 784 785 mmc = mmc_alloc_host(sizeof(struct wmt_mci_priv), &pdev->dev); 786 if (!mmc) { 787 dev_err(&pdev->dev, "Failed to allocate mmc_host\n"); 788 ret = -ENOMEM; 789 goto fail1; 790 } 791 792 mmc->ops = &wmt_mci_ops; 793 mmc->f_min = wmt_caps->f_min; 794 mmc->f_max = wmt_caps->f_max; 795 mmc->ocr_avail = wmt_caps->ocr_avail; 796 mmc->caps = wmt_caps->caps; 797 798 mmc->max_seg_size = wmt_caps->max_seg_size; 799 mmc->max_segs = wmt_caps->max_segs; 800 mmc->max_blk_size = wmt_caps->max_blk_size; 801 802 mmc->max_req_size = (16*512*mmc->max_segs); 803 mmc->max_blk_count = mmc->max_req_size / 512; 804 805 priv = mmc_priv(mmc); 806 priv->mmc = mmc; 807 priv->dev = &pdev->dev; 808 809 priv->power_inverted = 0; 810 priv->cd_inverted = 0; 811 812 if (of_get_property(np, "sdon-inverted", NULL)) 813 priv->power_inverted = 1; 814 if (of_get_property(np, "cd-inverted", NULL)) 815 priv->cd_inverted = 1; 816 817 priv->sdmmc_base = of_iomap(np, 0); 818 if (!priv->sdmmc_base) { 819 dev_err(&pdev->dev, "Failed to map IO space\n"); 820 ret = -ENOMEM; 821 goto fail2; 822 } 823 824 priv->irq_regular = regular_irq; 825 priv->irq_dma = dma_irq; 826 827 ret = request_irq(regular_irq, wmt_mci_regular_isr, 0, "sdmmc", priv); 828 if (ret) { 829 dev_err(&pdev->dev, "Register regular IRQ fail\n"); 830 goto fail3; 831 } 832 833 ret = request_irq(dma_irq, wmt_mci_dma_isr, 32, "sdmmc", priv); 834 if (ret) { 835 dev_err(&pdev->dev, "Register DMA IRQ fail\n"); 836 goto fail4; 837 } 838 839 /* alloc some DMA buffers for descriptors/transfers */ 840 priv->dma_desc_buffer = dma_alloc_coherent(&pdev->dev, 841 mmc->max_blk_count * 16, 842 &priv->dma_desc_device_addr, 843 GFP_KERNEL); 844 if (!priv->dma_desc_buffer) { 845 dev_err(&pdev->dev, "DMA alloc fail\n"); 846 ret = -EPERM; 847 goto fail5; 848 } 849 850 platform_set_drvdata(pdev, mmc); 851 852 priv->clk_sdmmc = of_clk_get(np, 0); 853 if (IS_ERR(priv->clk_sdmmc)) { 854 dev_err(&pdev->dev, "Error getting clock\n"); 855 ret = PTR_ERR(priv->clk_sdmmc); 856 goto fail5; 857 } 858 859 clk_prepare_enable(priv->clk_sdmmc); 860 861 /* configure the controller to a known 'ready' state */ 862 wmt_reset_hardware(mmc); 863 864 mmc_add_host(mmc); 865 866 dev_info(&pdev->dev, "WMT SDHC Controller initialized\n"); 867 868 return 0; 869 fail5: 870 free_irq(dma_irq, priv); 871 fail4: 872 free_irq(regular_irq, priv); 873 fail3: 874 iounmap(priv->sdmmc_base); 875 fail2: 876 mmc_free_host(mmc); 877 fail1: 878 return ret; 879 } 880 881 static int wmt_mci_remove(struct platform_device *pdev) 882 { 883 struct mmc_host *mmc; 884 struct wmt_mci_priv *priv; 885 struct resource *res; 886 u32 reg_tmp; 887 888 mmc = platform_get_drvdata(pdev); 889 priv = mmc_priv(mmc); 890 891 /* reset SD controller */ 892 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); 893 writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE); 894 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN); 895 writew(reg_tmp & ~(0xA000), priv->sdmmc_base + SDMMC_BLKLEN); 896 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0); 897 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1); 898 899 /* release the dma buffers */ 900 dma_free_coherent(&pdev->dev, priv->mmc->max_blk_count * 16, 901 priv->dma_desc_buffer, priv->dma_desc_device_addr); 902 903 mmc_remove_host(mmc); 904 905 free_irq(priv->irq_regular, priv); 906 free_irq(priv->irq_dma, priv); 907 908 iounmap(priv->sdmmc_base); 909 910 clk_disable_unprepare(priv->clk_sdmmc); 911 clk_put(priv->clk_sdmmc); 912 913 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 914 release_mem_region(res->start, resource_size(res)); 915 916 mmc_free_host(mmc); 917 918 dev_info(&pdev->dev, "WMT MCI device removed\n"); 919 920 return 0; 921 } 922 923 #ifdef CONFIG_PM 924 static int wmt_mci_suspend(struct device *dev) 925 { 926 u32 reg_tmp; 927 struct platform_device *pdev = to_platform_device(dev); 928 struct mmc_host *mmc = platform_get_drvdata(pdev); 929 struct wmt_mci_priv *priv; 930 931 if (!mmc) 932 return 0; 933 934 priv = mmc_priv(mmc); 935 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); 936 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + 937 SDMMC_BUSMODE); 938 939 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN); 940 writew(reg_tmp & 0x5FFF, priv->sdmmc_base + SDMMC_BLKLEN); 941 942 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0); 943 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1); 944 945 clk_disable(priv->clk_sdmmc); 946 return 0; 947 } 948 949 static int wmt_mci_resume(struct device *dev) 950 { 951 u32 reg_tmp; 952 struct platform_device *pdev = to_platform_device(dev); 953 struct mmc_host *mmc = platform_get_drvdata(pdev); 954 struct wmt_mci_priv *priv; 955 956 if (mmc) { 957 priv = mmc_priv(mmc); 958 clk_enable(priv->clk_sdmmc); 959 960 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE); 961 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + 962 SDMMC_BUSMODE); 963 964 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN); 965 writew(reg_tmp | (BLKL_GPI_CD | BLKL_INT_ENABLE), 966 priv->sdmmc_base + SDMMC_BLKLEN); 967 968 reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0); 969 writeb(reg_tmp | INT0_DI_INT_EN, priv->sdmmc_base + 970 SDMMC_INTMASK0); 971 972 } 973 974 return 0; 975 } 976 977 static const struct dev_pm_ops wmt_mci_pm = { 978 .suspend = wmt_mci_suspend, 979 .resume = wmt_mci_resume, 980 }; 981 982 #define wmt_mci_pm_ops (&wmt_mci_pm) 983 984 #else /* !CONFIG_PM */ 985 986 #define wmt_mci_pm_ops NULL 987 988 #endif 989 990 static struct platform_driver wmt_mci_driver = { 991 .probe = wmt_mci_probe, 992 .remove = wmt_mci_remove, 993 .driver = { 994 .name = DRIVER_NAME, 995 .owner = THIS_MODULE, 996 .pm = wmt_mci_pm_ops, 997 .of_match_table = wmt_mci_dt_ids, 998 }, 999 }; 1000 1001 module_platform_driver(wmt_mci_driver); 1002 1003 MODULE_DESCRIPTION("Wondermedia MMC/SD Driver"); 1004 MODULE_AUTHOR("Tony Prisk"); 1005 MODULE_LICENSE("GPL v2"); 1006 MODULE_DEVICE_TABLE(of, wmt_mci_dt_ids); 1007