1 /* 2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver 3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/module.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/highmem.h> 15 #include <linux/delay.h> 16 17 #include <linux/mmc/host.h> 18 19 #define DRV_NAME "via_sdmmc" 20 21 #define PCI_DEVICE_ID_VIA_9530 0x9530 22 23 #define VIA_CRDR_SDC_OFF 0x200 24 #define VIA_CRDR_DDMA_OFF 0x400 25 #define VIA_CRDR_PCICTRL_OFF 0x600 26 27 #define VIA_CRDR_MIN_CLOCK 375000 28 #define VIA_CRDR_MAX_CLOCK 48000000 29 30 /* 31 * PCI registers 32 */ 33 34 #define VIA_CRDR_PCI_WORK_MODE 0x40 35 #define VIA_CRDR_PCI_DBG_MODE 0x41 36 37 /* 38 * SDC MMIO Registers 39 */ 40 41 #define VIA_CRDR_SDCTRL 0x0 42 #define VIA_CRDR_SDCTRL_START 0x01 43 #define VIA_CRDR_SDCTRL_WRITE 0x04 44 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10 45 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20 46 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30 47 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40 48 #define VIA_CRDR_SDCTRL_STOP 0x70 49 50 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0 51 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000 52 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000 53 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000 54 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000 55 56 #define VIA_CRDR_SDCARG 0x4 57 58 #define VIA_CRDR_SDBUSMODE 0x8 59 #define VIA_CRDR_SDMODE_4BIT 0x02 60 #define VIA_CRDR_SDMODE_CLK_ON 0x40 61 62 #define VIA_CRDR_SDBLKLEN 0xc 63 /* 64 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048. 65 * Bit 11 - Bit 13 : Reserved. 66 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design. 67 * INTEN : Enable SD host interrupt. 68 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536. 69 */ 70 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000 71 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000 72 #define VIA_CRDR_MAX_BLOCK_COUNT 65536 73 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048 74 75 #define VIA_CRDR_SDRESP0 0x10 76 #define VIA_CRDR_SDRESP1 0x14 77 #define VIA_CRDR_SDRESP2 0x18 78 #define VIA_CRDR_SDRESP3 0x1c 79 80 #define VIA_CRDR_SDCURBLKCNT 0x20 81 82 #define VIA_CRDR_SDINTMASK 0x24 83 /* 84 * MBDIE : Multiple Blocks transfer Done Interrupt Enable 85 * BDDIE : Block Data transfer Done Interrupt Enable 86 * CIRIE : Card Insertion or Removal Interrupt Enable 87 * CRDIE : Command-Response transfer Done Interrupt Enable 88 * CRTOIE : Command-Response response TimeOut Interrupt Enable 89 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable 90 * DTIE : Data access Timeout Interrupt Enable 91 * SCIE : reSponse CRC error Interrupt Enable 92 * RCIE : Read data CRC error Interrupt Enable 93 * WCIE : Write data CRC error Interrupt Enable 94 */ 95 #define VIA_CRDR_SDINTMASK_MBDIE 0x10 96 #define VIA_CRDR_SDINTMASK_BDDIE 0x20 97 #define VIA_CRDR_SDINTMASK_CIRIE 0x80 98 #define VIA_CRDR_SDINTMASK_CRDIE 0x200 99 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400 100 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800 101 #define VIA_CRDR_SDINTMASK_DTIE 0x1000 102 #define VIA_CRDR_SDINTMASK_SCIE 0x2000 103 #define VIA_CRDR_SDINTMASK_RCIE 0x4000 104 #define VIA_CRDR_SDINTMASK_WCIE 0x8000 105 106 #define VIA_CRDR_SDACTIVE_INTMASK \ 107 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \ 108 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \ 109 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \ 110 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE) 111 112 #define VIA_CRDR_SDSTATUS 0x28 113 /* 114 * CECC : Reserved 115 * WP : SD card Write Protect status 116 * SLOTD : Reserved 117 * SLOTG : SD SLOT status(Gpi pin status) 118 * MBD : Multiple Blocks transfer Done interrupt status 119 * BDD : Block Data transfer Done interrupt status 120 * CD : Reserved 121 * CIR : Card Insertion or Removal interrupt detected on GPI pin 122 * IO : Reserved 123 * CRD : Command-Response transfer Done interrupt status 124 * CRTO : Command-Response response TimeOut interrupt status 125 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status 126 * DT : Data access Timeout interrupt status 127 * SC : reSponse CRC error interrupt status 128 * RC : Read data CRC error interrupt status 129 * WC : Write data CRC error interrupt status 130 */ 131 #define VIA_CRDR_SDSTS_CECC 0x01 132 #define VIA_CRDR_SDSTS_WP 0x02 133 #define VIA_CRDR_SDSTS_SLOTD 0x04 134 #define VIA_CRDR_SDSTS_SLOTG 0x08 135 #define VIA_CRDR_SDSTS_MBD 0x10 136 #define VIA_CRDR_SDSTS_BDD 0x20 137 #define VIA_CRDR_SDSTS_CD 0x40 138 #define VIA_CRDR_SDSTS_CIR 0x80 139 #define VIA_CRDR_SDSTS_IO 0x100 140 #define VIA_CRDR_SDSTS_CRD 0x200 141 #define VIA_CRDR_SDSTS_CRTO 0x400 142 #define VIA_CRDR_SDSTS_ASCRDIE 0x800 143 #define VIA_CRDR_SDSTS_DT 0x1000 144 #define VIA_CRDR_SDSTS_SC 0x2000 145 #define VIA_CRDR_SDSTS_RC 0x4000 146 #define VIA_CRDR_SDSTS_WC 0x8000 147 148 #define VIA_CRDR_SDSTS_IGN_MASK\ 149 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO) 150 #define VIA_CRDR_SDSTS_INT_MASK \ 151 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \ 152 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \ 153 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \ 154 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 155 #define VIA_CRDR_SDSTS_W1C_MASK \ 156 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \ 157 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \ 158 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \ 159 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 160 #define VIA_CRDR_SDSTS_CMD_MASK \ 161 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC) 162 #define VIA_CRDR_SDSTS_DATA_MASK\ 163 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \ 164 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 165 166 #define VIA_CRDR_SDSTATUS2 0x2a 167 /* 168 * CFE : Enable SD host automatic Clock FReezing 169 */ 170 #define VIA_CRDR_SDSTS_CFE 0x80 171 172 #define VIA_CRDR_SDRSPTMO 0x2C 173 174 #define VIA_CRDR_SDCLKSEL 0x30 175 176 #define VIA_CRDR_SDEXTCTRL 0x34 177 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01 178 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02 179 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04 180 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08 181 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10 182 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20 183 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40 184 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80 185 /* 0x38-0xFF reserved */ 186 187 /* 188 * Data DMA Control Registers 189 */ 190 191 #define VIA_CRDR_DMABASEADD 0x0 192 #define VIA_CRDR_DMACOUNTER 0x4 193 194 #define VIA_CRDR_DMACTRL 0x8 195 /* 196 * DIR :Transaction Direction 197 * 0 : From card to memory 198 * 1 : From memory to card 199 */ 200 #define VIA_CRDR_DMACTRL_DIR 0x100 201 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000 202 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000 203 204 #define VIA_CRDR_DMASTS 0xc 205 206 #define VIA_CRDR_DMASTART 0x10 207 /*0x14-0xFF reserved*/ 208 209 /* 210 * PCI Control Registers 211 */ 212 213 /*0x0 - 0x1 reserved*/ 214 #define VIA_CRDR_PCICLKGATT 0x2 215 /* 216 * SFTRST : 217 * 0 : Soft reset all the controller and it will be de-asserted automatically 218 * 1 : Soft reset is de-asserted 219 */ 220 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01 221 /* 222 * 3V3 : Pad power select 223 * 0 : 1.8V 224 * 1 : 3.3V 225 * NOTE : No mater what the actual value should be, this bit always 226 * read as 0. This is a hardware bug. 227 */ 228 #define VIA_CRDR_PCICLKGATT_3V3 0x10 229 /* 230 * PAD_PWRON : Pad Power on/off select 231 * 0 : Power off 232 * 1 : Power on 233 * NOTE : No mater what the actual value should be, this bit always 234 * read as 0. This is a hardware bug. 235 */ 236 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20 237 238 #define VIA_CRDR_PCISDCCLK 0x5 239 240 #define VIA_CRDR_PCIDMACLK 0x7 241 #define VIA_CRDR_PCIDMACLK_SDC 0x2 242 243 #define VIA_CRDR_PCIINTCTRL 0x8 244 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04 245 246 #define VIA_CRDR_PCIINTSTATUS 0x9 247 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04 248 249 #define VIA_CRDR_PCITMOCTRL 0xa 250 #define VIA_CRDR_PCITMOCTRL_NO 0x0 251 #define VIA_CRDR_PCITMOCTRL_32US 0x1 252 #define VIA_CRDR_PCITMOCTRL_256US 0x2 253 #define VIA_CRDR_PCITMOCTRL_1024US 0x3 254 #define VIA_CRDR_PCITMOCTRL_256MS 0x4 255 #define VIA_CRDR_PCITMOCTRL_512MS 0x5 256 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6 257 258 /*0xB-0xFF reserved*/ 259 260 enum PCI_HOST_CLK_CONTROL { 261 PCI_CLK_375K = 0x03, 262 PCI_CLK_8M = 0x04, 263 PCI_CLK_12M = 0x00, 264 PCI_CLK_16M = 0x05, 265 PCI_CLK_24M = 0x01, 266 PCI_CLK_33M = 0x06, 267 PCI_CLK_48M = 0x02 268 }; 269 270 struct sdhcreg { 271 u32 sdcontrol_reg; 272 u32 sdcmdarg_reg; 273 u32 sdbusmode_reg; 274 u32 sdblklen_reg; 275 u32 sdresp_reg[4]; 276 u32 sdcurblkcnt_reg; 277 u32 sdintmask_reg; 278 u32 sdstatus_reg; 279 u32 sdrsptmo_reg; 280 u32 sdclksel_reg; 281 u32 sdextctrl_reg; 282 }; 283 284 struct pcictrlreg { 285 u8 reserve[2]; 286 u8 pciclkgat_reg; 287 u8 pcinfcclk_reg; 288 u8 pcimscclk_reg; 289 u8 pcisdclk_reg; 290 u8 pcicaclk_reg; 291 u8 pcidmaclk_reg; 292 u8 pciintctrl_reg; 293 u8 pciintstatus_reg; 294 u8 pcitmoctrl_reg; 295 u8 Resv; 296 }; 297 298 struct via_crdr_mmc_host { 299 struct mmc_host *mmc; 300 struct mmc_request *mrq; 301 struct mmc_command *cmd; 302 struct mmc_data *data; 303 304 void __iomem *mmiobase; 305 void __iomem *sdhc_mmiobase; 306 void __iomem *ddma_mmiobase; 307 void __iomem *pcictrl_mmiobase; 308 309 struct pcictrlreg pm_pcictrl_reg; 310 struct sdhcreg pm_sdhc_reg; 311 312 struct work_struct carddet_work; 313 struct tasklet_struct finish_tasklet; 314 315 struct timer_list timer; 316 spinlock_t lock; 317 u8 power; 318 int reject; 319 unsigned int quirks; 320 }; 321 322 /* some devices need a very long delay for power to stabilize */ 323 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001 324 325 static struct pci_device_id via_ids[] = { 326 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530, 327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, 328 {0,} 329 }; 330 331 MODULE_DEVICE_TABLE(pci, via_ids); 332 333 static void via_print_sdchc(struct via_crdr_mmc_host *host) 334 { 335 void __iomem *addrbase = host->sdhc_mmiobase; 336 337 pr_debug("SDC MMIO Registers:\n"); 338 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n", 339 readl(addrbase + VIA_CRDR_SDCTRL), 340 readl(addrbase + VIA_CRDR_SDCARG), 341 readl(addrbase + VIA_CRDR_SDBUSMODE)); 342 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n", 343 readl(addrbase + VIA_CRDR_SDBLKLEN), 344 readl(addrbase + VIA_CRDR_SDCURBLKCNT), 345 readl(addrbase + VIA_CRDR_SDINTMASK)); 346 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n", 347 readl(addrbase + VIA_CRDR_SDSTATUS), 348 readl(addrbase + VIA_CRDR_SDCLKSEL), 349 readl(addrbase + VIA_CRDR_SDEXTCTRL)); 350 } 351 352 static void via_print_pcictrl(struct via_crdr_mmc_host *host) 353 { 354 void __iomem *addrbase = host->pcictrl_mmiobase; 355 356 pr_debug("PCI Control Registers:\n"); 357 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n", 358 readb(addrbase + VIA_CRDR_PCICLKGATT), 359 readb(addrbase + VIA_CRDR_PCISDCCLK), 360 readb(addrbase + VIA_CRDR_PCIDMACLK)); 361 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n", 362 readb(addrbase + VIA_CRDR_PCIINTCTRL), 363 readb(addrbase + VIA_CRDR_PCIINTSTATUS)); 364 } 365 366 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host) 367 { 368 struct pcictrlreg *pm_pcictrl_reg; 369 void __iomem *addrbase; 370 371 pm_pcictrl_reg = &(host->pm_pcictrl_reg); 372 addrbase = host->pcictrl_mmiobase; 373 374 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT); 375 pm_pcictrl_reg->pciclkgat_reg |= 376 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON; 377 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK); 378 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK); 379 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL); 380 pm_pcictrl_reg->pciintstatus_reg = 381 readb(addrbase + VIA_CRDR_PCIINTSTATUS); 382 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL); 383 } 384 385 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host) 386 { 387 struct pcictrlreg *pm_pcictrl_reg; 388 void __iomem *addrbase; 389 390 pm_pcictrl_reg = &(host->pm_pcictrl_reg); 391 addrbase = host->pcictrl_mmiobase; 392 393 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT); 394 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK); 395 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK); 396 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL); 397 writeb(pm_pcictrl_reg->pciintstatus_reg, 398 addrbase + VIA_CRDR_PCIINTSTATUS); 399 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL); 400 } 401 402 static void via_save_sdcreg(struct via_crdr_mmc_host *host) 403 { 404 struct sdhcreg *pm_sdhc_reg; 405 void __iomem *addrbase; 406 407 pm_sdhc_reg = &(host->pm_sdhc_reg); 408 addrbase = host->sdhc_mmiobase; 409 410 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL); 411 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG); 412 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE); 413 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN); 414 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT); 415 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK); 416 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS); 417 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO); 418 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL); 419 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL); 420 } 421 422 static void via_restore_sdcreg(struct via_crdr_mmc_host *host) 423 { 424 struct sdhcreg *pm_sdhc_reg; 425 void __iomem *addrbase; 426 427 pm_sdhc_reg = &(host->pm_sdhc_reg); 428 addrbase = host->sdhc_mmiobase; 429 430 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL); 431 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG); 432 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE); 433 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN); 434 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT); 435 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK); 436 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS); 437 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO); 438 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL); 439 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL); 440 } 441 442 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost) 443 { 444 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY) 445 msleep(300); 446 else 447 msleep(3); 448 } 449 450 static void via_set_ddma(struct via_crdr_mmc_host *host, 451 dma_addr_t dmaaddr, u32 count, int dir, int enirq) 452 { 453 void __iomem *addrbase; 454 u32 ctrl_data = 0; 455 456 if (enirq) 457 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ; 458 459 if (dir) 460 ctrl_data |= VIA_CRDR_DMACTRL_DIR; 461 462 addrbase = host->ddma_mmiobase; 463 464 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD); 465 writel(count, addrbase + VIA_CRDR_DMACOUNTER); 466 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL); 467 writel(0x01, addrbase + VIA_CRDR_DMASTART); 468 469 /* It seems that our DMA can not work normally with 375kHz clock */ 470 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */ 471 addrbase = host->pcictrl_mmiobase; 472 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) { 473 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n"); 474 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK); 475 } 476 } 477 478 static void via_sdc_preparedata(struct via_crdr_mmc_host *host, 479 struct mmc_data *data) 480 { 481 void __iomem *addrbase; 482 u32 blk_reg; 483 int count; 484 485 WARN_ON(host->data); 486 487 /* Sanity checks */ 488 BUG_ON(data->blksz > host->mmc->max_blk_size); 489 BUG_ON(data->blocks > host->mmc->max_blk_count); 490 491 host->data = data; 492 493 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 494 ((data->flags & MMC_DATA_READ) ? 495 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE)); 496 BUG_ON(count != 1); 497 498 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg), 499 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1); 500 501 addrbase = host->sdhc_mmiobase; 502 503 blk_reg = data->blksz - 1; 504 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 505 blk_reg |= (data->blocks) << 16; 506 507 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN); 508 } 509 510 static void via_sdc_get_response(struct via_crdr_mmc_host *host, 511 struct mmc_command *cmd) 512 { 513 void __iomem *addrbase = host->sdhc_mmiobase; 514 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0); 515 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1); 516 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2); 517 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3); 518 519 if (cmd->flags & MMC_RSP_136) { 520 cmd->resp[0] = ((u8) (dwdata1)) | 521 (((u8) (dwdata0 >> 24)) << 8) | 522 (((u8) (dwdata0 >> 16)) << 16) | 523 (((u8) (dwdata0 >> 8)) << 24); 524 525 cmd->resp[1] = ((u8) (dwdata2)) | 526 (((u8) (dwdata1 >> 24)) << 8) | 527 (((u8) (dwdata1 >> 16)) << 16) | 528 (((u8) (dwdata1 >> 8)) << 24); 529 530 cmd->resp[2] = ((u8) (dwdata3)) | 531 (((u8) (dwdata2 >> 24)) << 8) | 532 (((u8) (dwdata2 >> 16)) << 16) | 533 (((u8) (dwdata2 >> 8)) << 24); 534 535 cmd->resp[3] = 0xff | 536 ((((u8) (dwdata3 >> 24))) << 8) | 537 (((u8) (dwdata3 >> 16)) << 16) | 538 (((u8) (dwdata3 >> 8)) << 24); 539 } else { 540 dwdata0 >>= 8; 541 cmd->resp[0] = ((dwdata0 & 0xff) << 24) | 542 (((dwdata0 >> 8) & 0xff) << 16) | 543 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff); 544 545 dwdata1 >>= 8; 546 cmd->resp[1] = ((dwdata1 & 0xff) << 24) | 547 (((dwdata1 >> 8) & 0xff) << 16) | 548 (((dwdata1 >> 16) & 0xff) << 8); 549 } 550 } 551 552 static void via_sdc_send_command(struct via_crdr_mmc_host *host, 553 struct mmc_command *cmd) 554 { 555 void __iomem *addrbase; 556 struct mmc_data *data; 557 u32 cmdctrl = 0; 558 559 WARN_ON(host->cmd); 560 561 data = cmd->data; 562 mod_timer(&host->timer, jiffies + HZ); 563 host->cmd = cmd; 564 565 /*Command index*/ 566 cmdctrl = cmd->opcode << 8; 567 568 /*Response type*/ 569 switch (mmc_resp_type(cmd)) { 570 case MMC_RSP_NONE: 571 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE; 572 break; 573 case MMC_RSP_R1: 574 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1; 575 break; 576 case MMC_RSP_R1B: 577 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B; 578 break; 579 case MMC_RSP_R2: 580 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2; 581 break; 582 case MMC_RSP_R3: 583 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3; 584 break; 585 default: 586 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc)); 587 break; 588 } 589 590 if (!(cmd->data)) 591 goto nodata; 592 593 via_sdc_preparedata(host, data); 594 595 /*Command control*/ 596 if (data->blocks > 1) { 597 if (data->flags & MMC_DATA_WRITE) { 598 cmdctrl |= VIA_CRDR_SDCTRL_WRITE; 599 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR; 600 } else { 601 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD; 602 } 603 } else { 604 if (data->flags & MMC_DATA_WRITE) { 605 cmdctrl |= VIA_CRDR_SDCTRL_WRITE; 606 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR; 607 } else { 608 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD; 609 } 610 } 611 612 nodata: 613 if (cmd == host->mrq->stop) 614 cmdctrl |= VIA_CRDR_SDCTRL_STOP; 615 616 cmdctrl |= VIA_CRDR_SDCTRL_START; 617 618 addrbase = host->sdhc_mmiobase; 619 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG); 620 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL); 621 } 622 623 static void via_sdc_finish_data(struct via_crdr_mmc_host *host) 624 { 625 struct mmc_data *data; 626 627 BUG_ON(!host->data); 628 629 data = host->data; 630 host->data = NULL; 631 632 if (data->error) 633 data->bytes_xfered = 0; 634 else 635 data->bytes_xfered = data->blocks * data->blksz; 636 637 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 638 ((data->flags & MMC_DATA_READ) ? 639 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE)); 640 641 if (data->stop) 642 via_sdc_send_command(host, data->stop); 643 else 644 tasklet_schedule(&host->finish_tasklet); 645 } 646 647 static void via_sdc_finish_command(struct via_crdr_mmc_host *host) 648 { 649 via_sdc_get_response(host, host->cmd); 650 651 host->cmd->error = 0; 652 653 if (!host->cmd->data) 654 tasklet_schedule(&host->finish_tasklet); 655 656 host->cmd = NULL; 657 } 658 659 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq) 660 { 661 void __iomem *addrbase; 662 struct via_crdr_mmc_host *host; 663 unsigned long flags; 664 u16 status; 665 666 host = mmc_priv(mmc); 667 668 spin_lock_irqsave(&host->lock, flags); 669 670 addrbase = host->pcictrl_mmiobase; 671 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK); 672 673 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 674 status &= VIA_CRDR_SDSTS_W1C_MASK; 675 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 676 677 WARN_ON(host->mrq != NULL); 678 host->mrq = mrq; 679 680 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 681 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) { 682 host->mrq->cmd->error = -ENOMEDIUM; 683 tasklet_schedule(&host->finish_tasklet); 684 } else { 685 via_sdc_send_command(host, mrq->cmd); 686 } 687 688 mmiowb(); 689 spin_unlock_irqrestore(&host->lock, flags); 690 } 691 692 static void via_sdc_set_power(struct via_crdr_mmc_host *host, 693 unsigned short power, unsigned int on) 694 { 695 unsigned long flags; 696 u8 gatt; 697 698 spin_lock_irqsave(&host->lock, flags); 699 700 host->power = (1 << power); 701 702 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 703 if (host->power == MMC_VDD_165_195) 704 gatt &= ~VIA_CRDR_PCICLKGATT_3V3; 705 else 706 gatt |= VIA_CRDR_PCICLKGATT_3V3; 707 if (on) 708 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON; 709 else 710 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON; 711 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 712 713 mmiowb(); 714 spin_unlock_irqrestore(&host->lock, flags); 715 716 via_pwron_sleep(host); 717 } 718 719 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 720 { 721 struct via_crdr_mmc_host *host; 722 unsigned long flags; 723 void __iomem *addrbase; 724 u32 org_data, sdextctrl; 725 u8 clock; 726 727 host = mmc_priv(mmc); 728 729 spin_lock_irqsave(&host->lock, flags); 730 731 addrbase = host->sdhc_mmiobase; 732 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE); 733 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL); 734 735 if (ios->bus_width == MMC_BUS_WIDTH_1) 736 org_data &= ~VIA_CRDR_SDMODE_4BIT; 737 else 738 org_data |= VIA_CRDR_SDMODE_4BIT; 739 740 if (ios->power_mode == MMC_POWER_OFF) 741 org_data &= ~VIA_CRDR_SDMODE_CLK_ON; 742 else 743 org_data |= VIA_CRDR_SDMODE_CLK_ON; 744 745 if (ios->timing == MMC_TIMING_SD_HS) 746 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD; 747 else 748 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD; 749 750 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE); 751 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL); 752 753 if (ios->clock >= 48000000) 754 clock = PCI_CLK_48M; 755 else if (ios->clock >= 33000000) 756 clock = PCI_CLK_33M; 757 else if (ios->clock >= 24000000) 758 clock = PCI_CLK_24M; 759 else if (ios->clock >= 16000000) 760 clock = PCI_CLK_16M; 761 else if (ios->clock >= 12000000) 762 clock = PCI_CLK_12M; 763 else if (ios->clock >= 8000000) 764 clock = PCI_CLK_8M; 765 else 766 clock = PCI_CLK_375K; 767 768 addrbase = host->pcictrl_mmiobase; 769 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock) 770 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK); 771 772 mmiowb(); 773 spin_unlock_irqrestore(&host->lock, flags); 774 775 if (ios->power_mode != MMC_POWER_OFF) 776 via_sdc_set_power(host, ios->vdd, 1); 777 else 778 via_sdc_set_power(host, ios->vdd, 0); 779 } 780 781 static int via_sdc_get_ro(struct mmc_host *mmc) 782 { 783 struct via_crdr_mmc_host *host; 784 unsigned long flags; 785 u16 status; 786 787 host = mmc_priv(mmc); 788 789 spin_lock_irqsave(&host->lock, flags); 790 791 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 792 793 spin_unlock_irqrestore(&host->lock, flags); 794 795 return !(status & VIA_CRDR_SDSTS_WP); 796 } 797 798 static const struct mmc_host_ops via_sdc_ops = { 799 .request = via_sdc_request, 800 .set_ios = via_sdc_set_ios, 801 .get_ro = via_sdc_get_ro, 802 }; 803 804 static void via_reset_pcictrl(struct via_crdr_mmc_host *host) 805 { 806 unsigned long flags; 807 u8 gatt; 808 809 spin_lock_irqsave(&host->lock, flags); 810 811 via_save_pcictrlreg(host); 812 via_save_sdcreg(host); 813 814 spin_unlock_irqrestore(&host->lock, flags); 815 816 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON; 817 if (host->power == MMC_VDD_165_195) 818 gatt &= VIA_CRDR_PCICLKGATT_3V3; 819 else 820 gatt |= VIA_CRDR_PCICLKGATT_3V3; 821 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 822 via_pwron_sleep(host); 823 gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 824 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 825 msleep(3); 826 827 spin_lock_irqsave(&host->lock, flags); 828 829 via_restore_pcictrlreg(host); 830 via_restore_sdcreg(host); 831 832 mmiowb(); 833 spin_unlock_irqrestore(&host->lock, flags); 834 } 835 836 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask) 837 { 838 BUG_ON(intmask == 0); 839 840 if (!host->cmd) { 841 pr_err("%s: Got command interrupt 0x%x even " 842 "though no command operation was in progress.\n", 843 mmc_hostname(host->mmc), intmask); 844 return; 845 } 846 847 if (intmask & VIA_CRDR_SDSTS_CRTO) 848 host->cmd->error = -ETIMEDOUT; 849 else if (intmask & VIA_CRDR_SDSTS_SC) 850 host->cmd->error = -EILSEQ; 851 852 if (host->cmd->error) 853 tasklet_schedule(&host->finish_tasklet); 854 else if (intmask & VIA_CRDR_SDSTS_CRD) 855 via_sdc_finish_command(host); 856 } 857 858 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask) 859 { 860 BUG_ON(intmask == 0); 861 862 if (intmask & VIA_CRDR_SDSTS_DT) 863 host->data->error = -ETIMEDOUT; 864 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)) 865 host->data->error = -EILSEQ; 866 867 via_sdc_finish_data(host); 868 } 869 870 static irqreturn_t via_sdc_isr(int irq, void *dev_id) 871 { 872 struct via_crdr_mmc_host *sdhost = dev_id; 873 void __iomem *addrbase; 874 u8 pci_status; 875 u16 sd_status; 876 irqreturn_t result; 877 878 if (!sdhost) 879 return IRQ_NONE; 880 881 spin_lock(&sdhost->lock); 882 883 addrbase = sdhost->pcictrl_mmiobase; 884 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS); 885 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) { 886 result = IRQ_NONE; 887 goto out; 888 } 889 890 addrbase = sdhost->sdhc_mmiobase; 891 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS); 892 sd_status &= VIA_CRDR_SDSTS_INT_MASK; 893 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK; 894 if (!sd_status) { 895 result = IRQ_NONE; 896 goto out; 897 } 898 899 if (sd_status & VIA_CRDR_SDSTS_CIR) { 900 writew(sd_status & VIA_CRDR_SDSTS_CIR, 901 addrbase + VIA_CRDR_SDSTATUS); 902 903 schedule_work(&sdhost->carddet_work); 904 } 905 906 sd_status &= ~VIA_CRDR_SDSTS_CIR; 907 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) { 908 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK, 909 addrbase + VIA_CRDR_SDSTATUS); 910 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK); 911 } 912 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) { 913 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK, 914 addrbase + VIA_CRDR_SDSTATUS); 915 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK); 916 } 917 918 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK); 919 if (sd_status) { 920 pr_err("%s: Unexpected interrupt 0x%x\n", 921 mmc_hostname(sdhost->mmc), sd_status); 922 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS); 923 } 924 925 result = IRQ_HANDLED; 926 927 mmiowb(); 928 out: 929 spin_unlock(&sdhost->lock); 930 931 return result; 932 } 933 934 static void via_sdc_timeout(unsigned long ulongdata) 935 { 936 struct via_crdr_mmc_host *sdhost; 937 unsigned long flags; 938 939 sdhost = (struct via_crdr_mmc_host *)ulongdata; 940 941 spin_lock_irqsave(&sdhost->lock, flags); 942 943 if (sdhost->mrq) { 944 pr_err("%s: Timeout waiting for hardware interrupt." 945 "cmd:0x%x\n", mmc_hostname(sdhost->mmc), 946 sdhost->mrq->cmd->opcode); 947 948 if (sdhost->data) { 949 writel(VIA_CRDR_DMACTRL_SFTRST, 950 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL); 951 sdhost->data->error = -ETIMEDOUT; 952 via_sdc_finish_data(sdhost); 953 } else { 954 if (sdhost->cmd) 955 sdhost->cmd->error = -ETIMEDOUT; 956 else 957 sdhost->mrq->cmd->error = -ETIMEDOUT; 958 tasklet_schedule(&sdhost->finish_tasklet); 959 } 960 } 961 962 mmiowb(); 963 spin_unlock_irqrestore(&sdhost->lock, flags); 964 } 965 966 static void via_sdc_tasklet_finish(unsigned long param) 967 { 968 struct via_crdr_mmc_host *host; 969 unsigned long flags; 970 struct mmc_request *mrq; 971 972 host = (struct via_crdr_mmc_host *)param; 973 974 spin_lock_irqsave(&host->lock, flags); 975 976 del_timer(&host->timer); 977 mrq = host->mrq; 978 host->mrq = NULL; 979 host->cmd = NULL; 980 host->data = NULL; 981 982 spin_unlock_irqrestore(&host->lock, flags); 983 984 mmc_request_done(host->mmc, mrq); 985 } 986 987 static void via_sdc_card_detect(struct work_struct *work) 988 { 989 struct via_crdr_mmc_host *host; 990 void __iomem *addrbase; 991 unsigned long flags; 992 u16 status; 993 994 host = container_of(work, struct via_crdr_mmc_host, carddet_work); 995 996 addrbase = host->ddma_mmiobase; 997 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL); 998 999 spin_lock_irqsave(&host->lock, flags); 1000 1001 addrbase = host->pcictrl_mmiobase; 1002 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK); 1003 1004 addrbase = host->sdhc_mmiobase; 1005 status = readw(addrbase + VIA_CRDR_SDSTATUS); 1006 if (!(status & VIA_CRDR_SDSTS_SLOTG)) { 1007 if (host->mrq) { 1008 pr_err("%s: Card removed during transfer!\n", 1009 mmc_hostname(host->mmc)); 1010 host->mrq->cmd->error = -ENOMEDIUM; 1011 tasklet_schedule(&host->finish_tasklet); 1012 } 1013 1014 mmiowb(); 1015 spin_unlock_irqrestore(&host->lock, flags); 1016 1017 via_reset_pcictrl(host); 1018 1019 spin_lock_irqsave(&host->lock, flags); 1020 } 1021 1022 mmiowb(); 1023 spin_unlock_irqrestore(&host->lock, flags); 1024 1025 via_print_pcictrl(host); 1026 via_print_sdchc(host); 1027 1028 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1029 } 1030 1031 static void via_init_mmc_host(struct via_crdr_mmc_host *host) 1032 { 1033 struct mmc_host *mmc = host->mmc; 1034 void __iomem *addrbase; 1035 u32 lenreg; 1036 u32 status; 1037 1038 init_timer(&host->timer); 1039 host->timer.data = (unsigned long)host; 1040 host->timer.function = via_sdc_timeout; 1041 1042 spin_lock_init(&host->lock); 1043 1044 mmc->f_min = VIA_CRDR_MIN_CLOCK; 1045 mmc->f_max = VIA_CRDR_MAX_CLOCK; 1046 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1047 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED; 1048 mmc->ops = &via_sdc_ops; 1049 1050 /*Hardware cannot do scatter lists*/ 1051 mmc->max_segs = 1; 1052 1053 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH; 1054 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT; 1055 1056 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; 1057 mmc->max_req_size = mmc->max_seg_size; 1058 1059 INIT_WORK(&host->carddet_work, via_sdc_card_detect); 1060 1061 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish, 1062 (unsigned long)host); 1063 1064 addrbase = host->sdhc_mmiobase; 1065 writel(0x0, addrbase + VIA_CRDR_SDINTMASK); 1066 msleep(1); 1067 1068 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 1069 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN); 1070 1071 status = readw(addrbase + VIA_CRDR_SDSTATUS); 1072 status &= VIA_CRDR_SDSTS_W1C_MASK; 1073 writew(status, addrbase + VIA_CRDR_SDSTATUS); 1074 1075 status = readw(addrbase + VIA_CRDR_SDSTATUS2); 1076 status |= VIA_CRDR_SDSTS_CFE; 1077 writew(status, addrbase + VIA_CRDR_SDSTATUS2); 1078 1079 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL); 1080 1081 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK); 1082 msleep(1); 1083 } 1084 1085 static int via_sd_probe(struct pci_dev *pcidev, 1086 const struct pci_device_id *id) 1087 { 1088 struct mmc_host *mmc; 1089 struct via_crdr_mmc_host *sdhost; 1090 u32 base, len; 1091 u8 gatt; 1092 int ret; 1093 1094 pr_info(DRV_NAME 1095 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n", 1096 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, 1097 (int)pcidev->revision); 1098 1099 ret = pci_enable_device(pcidev); 1100 if (ret) 1101 return ret; 1102 1103 ret = pci_request_regions(pcidev, DRV_NAME); 1104 if (ret) 1105 goto disable; 1106 1107 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0); 1108 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0); 1109 1110 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev); 1111 if (!mmc) { 1112 ret = -ENOMEM; 1113 goto release; 1114 } 1115 1116 sdhost = mmc_priv(mmc); 1117 sdhost->mmc = mmc; 1118 dev_set_drvdata(&pcidev->dev, sdhost); 1119 1120 len = pci_resource_len(pcidev, 0); 1121 base = pci_resource_start(pcidev, 0); 1122 sdhost->mmiobase = ioremap_nocache(base, len); 1123 if (!sdhost->mmiobase) { 1124 ret = -ENOMEM; 1125 goto free_mmc_host; 1126 } 1127 1128 sdhost->sdhc_mmiobase = 1129 sdhost->mmiobase + VIA_CRDR_SDC_OFF; 1130 sdhost->ddma_mmiobase = 1131 sdhost->mmiobase + VIA_CRDR_DDMA_OFF; 1132 sdhost->pcictrl_mmiobase = 1133 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF; 1134 1135 sdhost->power = MMC_VDD_165_195; 1136 1137 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON; 1138 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1139 via_pwron_sleep(sdhost); 1140 gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 1141 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1142 msleep(3); 1143 1144 via_init_mmc_host(sdhost); 1145 1146 ret = 1147 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME, 1148 sdhost); 1149 if (ret) 1150 goto unmap; 1151 1152 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN, 1153 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1154 writeb(VIA_CRDR_PCITMOCTRL_1024MS, 1155 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL); 1156 1157 /* device-specific quirks */ 1158 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO && 1159 pcidev->subsystem_device == 0x3891) 1160 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY; 1161 1162 mmc_add_host(mmc); 1163 1164 return 0; 1165 1166 unmap: 1167 iounmap(sdhost->mmiobase); 1168 free_mmc_host: 1169 dev_set_drvdata(&pcidev->dev, NULL); 1170 mmc_free_host(mmc); 1171 release: 1172 pci_release_regions(pcidev); 1173 disable: 1174 pci_disable_device(pcidev); 1175 1176 return ret; 1177 } 1178 1179 static void via_sd_remove(struct pci_dev *pcidev) 1180 { 1181 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev); 1182 unsigned long flags; 1183 u8 gatt; 1184 1185 spin_lock_irqsave(&sdhost->lock, flags); 1186 1187 /* Ensure we don't accept more commands from mmc layer */ 1188 sdhost->reject = 1; 1189 1190 /* Disable generating further interrupts */ 1191 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1192 mmiowb(); 1193 1194 if (sdhost->mrq) { 1195 pr_err("%s: Controller removed during " 1196 "transfer\n", mmc_hostname(sdhost->mmc)); 1197 1198 /* make sure all DMA is stopped */ 1199 writel(VIA_CRDR_DMACTRL_SFTRST, 1200 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL); 1201 mmiowb(); 1202 sdhost->mrq->cmd->error = -ENOMEDIUM; 1203 if (sdhost->mrq->stop) 1204 sdhost->mrq->stop->error = -ENOMEDIUM; 1205 tasklet_schedule(&sdhost->finish_tasklet); 1206 } 1207 spin_unlock_irqrestore(&sdhost->lock, flags); 1208 1209 mmc_remove_host(sdhost->mmc); 1210 1211 free_irq(pcidev->irq, sdhost); 1212 1213 del_timer_sync(&sdhost->timer); 1214 1215 tasklet_kill(&sdhost->finish_tasklet); 1216 1217 /* switch off power */ 1218 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1219 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON; 1220 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1221 1222 iounmap(sdhost->mmiobase); 1223 dev_set_drvdata(&pcidev->dev, NULL); 1224 mmc_free_host(sdhost->mmc); 1225 pci_release_regions(pcidev); 1226 pci_disable_device(pcidev); 1227 1228 pr_info(DRV_NAME 1229 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n", 1230 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); 1231 } 1232 1233 #ifdef CONFIG_PM 1234 1235 static void via_init_sdc_pm(struct via_crdr_mmc_host *host) 1236 { 1237 struct sdhcreg *pm_sdhcreg; 1238 void __iomem *addrbase; 1239 u32 lenreg; 1240 u16 status; 1241 1242 pm_sdhcreg = &(host->pm_sdhc_reg); 1243 addrbase = host->sdhc_mmiobase; 1244 1245 writel(0x0, addrbase + VIA_CRDR_SDINTMASK); 1246 1247 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 1248 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN); 1249 1250 status = readw(addrbase + VIA_CRDR_SDSTATUS); 1251 status &= VIA_CRDR_SDSTS_W1C_MASK; 1252 writew(status, addrbase + VIA_CRDR_SDSTATUS); 1253 1254 status = readw(addrbase + VIA_CRDR_SDSTATUS2); 1255 status |= VIA_CRDR_SDSTS_CFE; 1256 writew(status, addrbase + VIA_CRDR_SDSTATUS2); 1257 1258 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL); 1259 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG); 1260 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK); 1261 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO); 1262 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL); 1263 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL); 1264 1265 via_print_pcictrl(host); 1266 via_print_sdchc(host); 1267 } 1268 1269 static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state) 1270 { 1271 struct via_crdr_mmc_host *host; 1272 int ret = 0; 1273 1274 host = pci_get_drvdata(pcidev); 1275 1276 via_save_pcictrlreg(host); 1277 via_save_sdcreg(host); 1278 1279 ret = mmc_suspend_host(host->mmc); 1280 1281 pci_save_state(pcidev); 1282 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0); 1283 pci_disable_device(pcidev); 1284 pci_set_power_state(pcidev, pci_choose_state(pcidev, state)); 1285 1286 return ret; 1287 } 1288 1289 static int via_sd_resume(struct pci_dev *pcidev) 1290 { 1291 struct via_crdr_mmc_host *sdhost; 1292 int ret = 0; 1293 u8 gatt; 1294 1295 sdhost = pci_get_drvdata(pcidev); 1296 1297 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON; 1298 if (sdhost->power == MMC_VDD_165_195) 1299 gatt &= ~VIA_CRDR_PCICLKGATT_3V3; 1300 else 1301 gatt |= VIA_CRDR_PCICLKGATT_3V3; 1302 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1303 via_pwron_sleep(sdhost); 1304 gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 1305 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1306 msleep(3); 1307 1308 msleep(100); 1309 1310 pci_set_power_state(pcidev, PCI_D0); 1311 pci_restore_state(pcidev); 1312 ret = pci_enable_device(pcidev); 1313 if (ret) 1314 return ret; 1315 1316 via_restore_pcictrlreg(sdhost); 1317 via_init_sdc_pm(sdhost); 1318 1319 ret = mmc_resume_host(sdhost->mmc); 1320 1321 return ret; 1322 } 1323 1324 #else /* CONFIG_PM */ 1325 1326 #define via_sd_suspend NULL 1327 #define via_sd_resume NULL 1328 1329 #endif /* CONFIG_PM */ 1330 1331 static struct pci_driver via_sd_driver = { 1332 .name = DRV_NAME, 1333 .id_table = via_ids, 1334 .probe = via_sd_probe, 1335 .remove = via_sd_remove, 1336 .suspend = via_sd_suspend, 1337 .resume = via_sd_resume, 1338 }; 1339 1340 module_pci_driver(via_sd_driver); 1341 1342 MODULE_LICENSE("GPL"); 1343 MODULE_AUTHOR("VIA Technologies Inc."); 1344 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver"); 1345