1 /* 2 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver 3 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or (at 8 * your option) any later version. 9 */ 10 11 #include <linux/pci.h> 12 #include <linux/module.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/highmem.h> 15 #include <linux/delay.h> 16 #include <linux/interrupt.h> 17 18 #include <linux/mmc/host.h> 19 20 #define DRV_NAME "via_sdmmc" 21 22 #define PCI_DEVICE_ID_VIA_9530 0x9530 23 24 #define VIA_CRDR_SDC_OFF 0x200 25 #define VIA_CRDR_DDMA_OFF 0x400 26 #define VIA_CRDR_PCICTRL_OFF 0x600 27 28 #define VIA_CRDR_MIN_CLOCK 375000 29 #define VIA_CRDR_MAX_CLOCK 48000000 30 31 /* 32 * PCI registers 33 */ 34 35 #define VIA_CRDR_PCI_WORK_MODE 0x40 36 #define VIA_CRDR_PCI_DBG_MODE 0x41 37 38 /* 39 * SDC MMIO Registers 40 */ 41 42 #define VIA_CRDR_SDCTRL 0x0 43 #define VIA_CRDR_SDCTRL_START 0x01 44 #define VIA_CRDR_SDCTRL_WRITE 0x04 45 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10 46 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20 47 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30 48 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40 49 #define VIA_CRDR_SDCTRL_STOP 0x70 50 51 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0 52 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000 53 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000 54 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000 55 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000 56 57 #define VIA_CRDR_SDCARG 0x4 58 59 #define VIA_CRDR_SDBUSMODE 0x8 60 #define VIA_CRDR_SDMODE_4BIT 0x02 61 #define VIA_CRDR_SDMODE_CLK_ON 0x40 62 63 #define VIA_CRDR_SDBLKLEN 0xc 64 /* 65 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048. 66 * Bit 11 - Bit 13 : Reserved. 67 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design. 68 * INTEN : Enable SD host interrupt. 69 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536. 70 */ 71 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000 72 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000 73 #define VIA_CRDR_MAX_BLOCK_COUNT 65536 74 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048 75 76 #define VIA_CRDR_SDRESP0 0x10 77 #define VIA_CRDR_SDRESP1 0x14 78 #define VIA_CRDR_SDRESP2 0x18 79 #define VIA_CRDR_SDRESP3 0x1c 80 81 #define VIA_CRDR_SDCURBLKCNT 0x20 82 83 #define VIA_CRDR_SDINTMASK 0x24 84 /* 85 * MBDIE : Multiple Blocks transfer Done Interrupt Enable 86 * BDDIE : Block Data transfer Done Interrupt Enable 87 * CIRIE : Card Insertion or Removal Interrupt Enable 88 * CRDIE : Command-Response transfer Done Interrupt Enable 89 * CRTOIE : Command-Response response TimeOut Interrupt Enable 90 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable 91 * DTIE : Data access Timeout Interrupt Enable 92 * SCIE : reSponse CRC error Interrupt Enable 93 * RCIE : Read data CRC error Interrupt Enable 94 * WCIE : Write data CRC error Interrupt Enable 95 */ 96 #define VIA_CRDR_SDINTMASK_MBDIE 0x10 97 #define VIA_CRDR_SDINTMASK_BDDIE 0x20 98 #define VIA_CRDR_SDINTMASK_CIRIE 0x80 99 #define VIA_CRDR_SDINTMASK_CRDIE 0x200 100 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400 101 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800 102 #define VIA_CRDR_SDINTMASK_DTIE 0x1000 103 #define VIA_CRDR_SDINTMASK_SCIE 0x2000 104 #define VIA_CRDR_SDINTMASK_RCIE 0x4000 105 #define VIA_CRDR_SDINTMASK_WCIE 0x8000 106 107 #define VIA_CRDR_SDACTIVE_INTMASK \ 108 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \ 109 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \ 110 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \ 111 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE) 112 113 #define VIA_CRDR_SDSTATUS 0x28 114 /* 115 * CECC : Reserved 116 * WP : SD card Write Protect status 117 * SLOTD : Reserved 118 * SLOTG : SD SLOT status(Gpi pin status) 119 * MBD : Multiple Blocks transfer Done interrupt status 120 * BDD : Block Data transfer Done interrupt status 121 * CD : Reserved 122 * CIR : Card Insertion or Removal interrupt detected on GPI pin 123 * IO : Reserved 124 * CRD : Command-Response transfer Done interrupt status 125 * CRTO : Command-Response response TimeOut interrupt status 126 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status 127 * DT : Data access Timeout interrupt status 128 * SC : reSponse CRC error interrupt status 129 * RC : Read data CRC error interrupt status 130 * WC : Write data CRC error interrupt status 131 */ 132 #define VIA_CRDR_SDSTS_CECC 0x01 133 #define VIA_CRDR_SDSTS_WP 0x02 134 #define VIA_CRDR_SDSTS_SLOTD 0x04 135 #define VIA_CRDR_SDSTS_SLOTG 0x08 136 #define VIA_CRDR_SDSTS_MBD 0x10 137 #define VIA_CRDR_SDSTS_BDD 0x20 138 #define VIA_CRDR_SDSTS_CD 0x40 139 #define VIA_CRDR_SDSTS_CIR 0x80 140 #define VIA_CRDR_SDSTS_IO 0x100 141 #define VIA_CRDR_SDSTS_CRD 0x200 142 #define VIA_CRDR_SDSTS_CRTO 0x400 143 #define VIA_CRDR_SDSTS_ASCRDIE 0x800 144 #define VIA_CRDR_SDSTS_DT 0x1000 145 #define VIA_CRDR_SDSTS_SC 0x2000 146 #define VIA_CRDR_SDSTS_RC 0x4000 147 #define VIA_CRDR_SDSTS_WC 0x8000 148 149 #define VIA_CRDR_SDSTS_IGN_MASK\ 150 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO) 151 #define VIA_CRDR_SDSTS_INT_MASK \ 152 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \ 153 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \ 154 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \ 155 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 156 #define VIA_CRDR_SDSTS_W1C_MASK \ 157 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \ 158 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \ 159 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \ 160 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 161 #define VIA_CRDR_SDSTS_CMD_MASK \ 162 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC) 163 #define VIA_CRDR_SDSTS_DATA_MASK\ 164 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \ 165 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 166 167 #define VIA_CRDR_SDSTATUS2 0x2a 168 /* 169 * CFE : Enable SD host automatic Clock FReezing 170 */ 171 #define VIA_CRDR_SDSTS_CFE 0x80 172 173 #define VIA_CRDR_SDRSPTMO 0x2C 174 175 #define VIA_CRDR_SDCLKSEL 0x30 176 177 #define VIA_CRDR_SDEXTCTRL 0x34 178 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01 179 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02 180 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04 181 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08 182 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10 183 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20 184 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40 185 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80 186 /* 0x38-0xFF reserved */ 187 188 /* 189 * Data DMA Control Registers 190 */ 191 192 #define VIA_CRDR_DMABASEADD 0x0 193 #define VIA_CRDR_DMACOUNTER 0x4 194 195 #define VIA_CRDR_DMACTRL 0x8 196 /* 197 * DIR :Transaction Direction 198 * 0 : From card to memory 199 * 1 : From memory to card 200 */ 201 #define VIA_CRDR_DMACTRL_DIR 0x100 202 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000 203 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000 204 205 #define VIA_CRDR_DMASTS 0xc 206 207 #define VIA_CRDR_DMASTART 0x10 208 /*0x14-0xFF reserved*/ 209 210 /* 211 * PCI Control Registers 212 */ 213 214 /*0x0 - 0x1 reserved*/ 215 #define VIA_CRDR_PCICLKGATT 0x2 216 /* 217 * SFTRST : 218 * 0 : Soft reset all the controller and it will be de-asserted automatically 219 * 1 : Soft reset is de-asserted 220 */ 221 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01 222 /* 223 * 3V3 : Pad power select 224 * 0 : 1.8V 225 * 1 : 3.3V 226 * NOTE : No mater what the actual value should be, this bit always 227 * read as 0. This is a hardware bug. 228 */ 229 #define VIA_CRDR_PCICLKGATT_3V3 0x10 230 /* 231 * PAD_PWRON : Pad Power on/off select 232 * 0 : Power off 233 * 1 : Power on 234 * NOTE : No mater what the actual value should be, this bit always 235 * read as 0. This is a hardware bug. 236 */ 237 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20 238 239 #define VIA_CRDR_PCISDCCLK 0x5 240 241 #define VIA_CRDR_PCIDMACLK 0x7 242 #define VIA_CRDR_PCIDMACLK_SDC 0x2 243 244 #define VIA_CRDR_PCIINTCTRL 0x8 245 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04 246 247 #define VIA_CRDR_PCIINTSTATUS 0x9 248 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04 249 250 #define VIA_CRDR_PCITMOCTRL 0xa 251 #define VIA_CRDR_PCITMOCTRL_NO 0x0 252 #define VIA_CRDR_PCITMOCTRL_32US 0x1 253 #define VIA_CRDR_PCITMOCTRL_256US 0x2 254 #define VIA_CRDR_PCITMOCTRL_1024US 0x3 255 #define VIA_CRDR_PCITMOCTRL_256MS 0x4 256 #define VIA_CRDR_PCITMOCTRL_512MS 0x5 257 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6 258 259 /*0xB-0xFF reserved*/ 260 261 enum PCI_HOST_CLK_CONTROL { 262 PCI_CLK_375K = 0x03, 263 PCI_CLK_8M = 0x04, 264 PCI_CLK_12M = 0x00, 265 PCI_CLK_16M = 0x05, 266 PCI_CLK_24M = 0x01, 267 PCI_CLK_33M = 0x06, 268 PCI_CLK_48M = 0x02 269 }; 270 271 struct sdhcreg { 272 u32 sdcontrol_reg; 273 u32 sdcmdarg_reg; 274 u32 sdbusmode_reg; 275 u32 sdblklen_reg; 276 u32 sdresp_reg[4]; 277 u32 sdcurblkcnt_reg; 278 u32 sdintmask_reg; 279 u32 sdstatus_reg; 280 u32 sdrsptmo_reg; 281 u32 sdclksel_reg; 282 u32 sdextctrl_reg; 283 }; 284 285 struct pcictrlreg { 286 u8 reserve[2]; 287 u8 pciclkgat_reg; 288 u8 pcinfcclk_reg; 289 u8 pcimscclk_reg; 290 u8 pcisdclk_reg; 291 u8 pcicaclk_reg; 292 u8 pcidmaclk_reg; 293 u8 pciintctrl_reg; 294 u8 pciintstatus_reg; 295 u8 pcitmoctrl_reg; 296 u8 Resv; 297 }; 298 299 struct via_crdr_mmc_host { 300 struct mmc_host *mmc; 301 struct mmc_request *mrq; 302 struct mmc_command *cmd; 303 struct mmc_data *data; 304 305 void __iomem *mmiobase; 306 void __iomem *sdhc_mmiobase; 307 void __iomem *ddma_mmiobase; 308 void __iomem *pcictrl_mmiobase; 309 310 struct pcictrlreg pm_pcictrl_reg; 311 struct sdhcreg pm_sdhc_reg; 312 313 struct work_struct carddet_work; 314 struct tasklet_struct finish_tasklet; 315 316 struct timer_list timer; 317 spinlock_t lock; 318 u8 power; 319 int reject; 320 unsigned int quirks; 321 }; 322 323 /* some devices need a very long delay for power to stabilize */ 324 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001 325 326 static const struct pci_device_id via_ids[] = { 327 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530, 328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, 329 {0,} 330 }; 331 332 MODULE_DEVICE_TABLE(pci, via_ids); 333 334 static void via_print_sdchc(struct via_crdr_mmc_host *host) 335 { 336 void __iomem *addrbase = host->sdhc_mmiobase; 337 338 pr_debug("SDC MMIO Registers:\n"); 339 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n", 340 readl(addrbase + VIA_CRDR_SDCTRL), 341 readl(addrbase + VIA_CRDR_SDCARG), 342 readl(addrbase + VIA_CRDR_SDBUSMODE)); 343 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n", 344 readl(addrbase + VIA_CRDR_SDBLKLEN), 345 readl(addrbase + VIA_CRDR_SDCURBLKCNT), 346 readl(addrbase + VIA_CRDR_SDINTMASK)); 347 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n", 348 readl(addrbase + VIA_CRDR_SDSTATUS), 349 readl(addrbase + VIA_CRDR_SDCLKSEL), 350 readl(addrbase + VIA_CRDR_SDEXTCTRL)); 351 } 352 353 static void via_print_pcictrl(struct via_crdr_mmc_host *host) 354 { 355 void __iomem *addrbase = host->pcictrl_mmiobase; 356 357 pr_debug("PCI Control Registers:\n"); 358 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n", 359 readb(addrbase + VIA_CRDR_PCICLKGATT), 360 readb(addrbase + VIA_CRDR_PCISDCCLK), 361 readb(addrbase + VIA_CRDR_PCIDMACLK)); 362 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n", 363 readb(addrbase + VIA_CRDR_PCIINTCTRL), 364 readb(addrbase + VIA_CRDR_PCIINTSTATUS)); 365 } 366 367 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host) 368 { 369 struct pcictrlreg *pm_pcictrl_reg; 370 void __iomem *addrbase; 371 372 pm_pcictrl_reg = &(host->pm_pcictrl_reg); 373 addrbase = host->pcictrl_mmiobase; 374 375 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT); 376 pm_pcictrl_reg->pciclkgat_reg |= 377 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON; 378 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK); 379 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK); 380 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL); 381 pm_pcictrl_reg->pciintstatus_reg = 382 readb(addrbase + VIA_CRDR_PCIINTSTATUS); 383 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL); 384 } 385 386 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host) 387 { 388 struct pcictrlreg *pm_pcictrl_reg; 389 void __iomem *addrbase; 390 391 pm_pcictrl_reg = &(host->pm_pcictrl_reg); 392 addrbase = host->pcictrl_mmiobase; 393 394 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT); 395 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK); 396 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK); 397 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL); 398 writeb(pm_pcictrl_reg->pciintstatus_reg, 399 addrbase + VIA_CRDR_PCIINTSTATUS); 400 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL); 401 } 402 403 static void via_save_sdcreg(struct via_crdr_mmc_host *host) 404 { 405 struct sdhcreg *pm_sdhc_reg; 406 void __iomem *addrbase; 407 408 pm_sdhc_reg = &(host->pm_sdhc_reg); 409 addrbase = host->sdhc_mmiobase; 410 411 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL); 412 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG); 413 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE); 414 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN); 415 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT); 416 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK); 417 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS); 418 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO); 419 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL); 420 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL); 421 } 422 423 static void via_restore_sdcreg(struct via_crdr_mmc_host *host) 424 { 425 struct sdhcreg *pm_sdhc_reg; 426 void __iomem *addrbase; 427 428 pm_sdhc_reg = &(host->pm_sdhc_reg); 429 addrbase = host->sdhc_mmiobase; 430 431 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL); 432 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG); 433 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE); 434 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN); 435 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT); 436 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK); 437 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS); 438 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO); 439 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL); 440 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL); 441 } 442 443 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost) 444 { 445 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY) 446 msleep(300); 447 else 448 msleep(3); 449 } 450 451 static void via_set_ddma(struct via_crdr_mmc_host *host, 452 dma_addr_t dmaaddr, u32 count, int dir, int enirq) 453 { 454 void __iomem *addrbase; 455 u32 ctrl_data = 0; 456 457 if (enirq) 458 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ; 459 460 if (dir) 461 ctrl_data |= VIA_CRDR_DMACTRL_DIR; 462 463 addrbase = host->ddma_mmiobase; 464 465 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD); 466 writel(count, addrbase + VIA_CRDR_DMACOUNTER); 467 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL); 468 writel(0x01, addrbase + VIA_CRDR_DMASTART); 469 470 /* It seems that our DMA can not work normally with 375kHz clock */ 471 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */ 472 addrbase = host->pcictrl_mmiobase; 473 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) { 474 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n"); 475 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK); 476 } 477 } 478 479 static void via_sdc_preparedata(struct via_crdr_mmc_host *host, 480 struct mmc_data *data) 481 { 482 void __iomem *addrbase; 483 u32 blk_reg; 484 int count; 485 486 WARN_ON(host->data); 487 488 /* Sanity checks */ 489 BUG_ON(data->blksz > host->mmc->max_blk_size); 490 BUG_ON(data->blocks > host->mmc->max_blk_count); 491 492 host->data = data; 493 494 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 495 ((data->flags & MMC_DATA_READ) ? 496 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE)); 497 BUG_ON(count != 1); 498 499 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg), 500 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1); 501 502 addrbase = host->sdhc_mmiobase; 503 504 blk_reg = data->blksz - 1; 505 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 506 blk_reg |= (data->blocks) << 16; 507 508 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN); 509 } 510 511 static void via_sdc_get_response(struct via_crdr_mmc_host *host, 512 struct mmc_command *cmd) 513 { 514 void __iomem *addrbase = host->sdhc_mmiobase; 515 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0); 516 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1); 517 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2); 518 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3); 519 520 if (cmd->flags & MMC_RSP_136) { 521 cmd->resp[0] = ((u8) (dwdata1)) | 522 (((u8) (dwdata0 >> 24)) << 8) | 523 (((u8) (dwdata0 >> 16)) << 16) | 524 (((u8) (dwdata0 >> 8)) << 24); 525 526 cmd->resp[1] = ((u8) (dwdata2)) | 527 (((u8) (dwdata1 >> 24)) << 8) | 528 (((u8) (dwdata1 >> 16)) << 16) | 529 (((u8) (dwdata1 >> 8)) << 24); 530 531 cmd->resp[2] = ((u8) (dwdata3)) | 532 (((u8) (dwdata2 >> 24)) << 8) | 533 (((u8) (dwdata2 >> 16)) << 16) | 534 (((u8) (dwdata2 >> 8)) << 24); 535 536 cmd->resp[3] = 0xff | 537 ((((u8) (dwdata3 >> 24))) << 8) | 538 (((u8) (dwdata3 >> 16)) << 16) | 539 (((u8) (dwdata3 >> 8)) << 24); 540 } else { 541 dwdata0 >>= 8; 542 cmd->resp[0] = ((dwdata0 & 0xff) << 24) | 543 (((dwdata0 >> 8) & 0xff) << 16) | 544 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff); 545 546 dwdata1 >>= 8; 547 cmd->resp[1] = ((dwdata1 & 0xff) << 24) | 548 (((dwdata1 >> 8) & 0xff) << 16) | 549 (((dwdata1 >> 16) & 0xff) << 8); 550 } 551 } 552 553 static void via_sdc_send_command(struct via_crdr_mmc_host *host, 554 struct mmc_command *cmd) 555 { 556 void __iomem *addrbase; 557 struct mmc_data *data; 558 u32 cmdctrl = 0; 559 560 WARN_ON(host->cmd); 561 562 data = cmd->data; 563 mod_timer(&host->timer, jiffies + HZ); 564 host->cmd = cmd; 565 566 /*Command index*/ 567 cmdctrl = cmd->opcode << 8; 568 569 /*Response type*/ 570 switch (mmc_resp_type(cmd)) { 571 case MMC_RSP_NONE: 572 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE; 573 break; 574 case MMC_RSP_R1: 575 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1; 576 break; 577 case MMC_RSP_R1B: 578 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B; 579 break; 580 case MMC_RSP_R2: 581 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2; 582 break; 583 case MMC_RSP_R3: 584 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3; 585 break; 586 default: 587 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc)); 588 break; 589 } 590 591 if (!(cmd->data)) 592 goto nodata; 593 594 via_sdc_preparedata(host, data); 595 596 /*Command control*/ 597 if (data->blocks > 1) { 598 if (data->flags & MMC_DATA_WRITE) { 599 cmdctrl |= VIA_CRDR_SDCTRL_WRITE; 600 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR; 601 } else { 602 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD; 603 } 604 } else { 605 if (data->flags & MMC_DATA_WRITE) { 606 cmdctrl |= VIA_CRDR_SDCTRL_WRITE; 607 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR; 608 } else { 609 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD; 610 } 611 } 612 613 nodata: 614 if (cmd == host->mrq->stop) 615 cmdctrl |= VIA_CRDR_SDCTRL_STOP; 616 617 cmdctrl |= VIA_CRDR_SDCTRL_START; 618 619 addrbase = host->sdhc_mmiobase; 620 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG); 621 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL); 622 } 623 624 static void via_sdc_finish_data(struct via_crdr_mmc_host *host) 625 { 626 struct mmc_data *data; 627 628 BUG_ON(!host->data); 629 630 data = host->data; 631 host->data = NULL; 632 633 if (data->error) 634 data->bytes_xfered = 0; 635 else 636 data->bytes_xfered = data->blocks * data->blksz; 637 638 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 639 ((data->flags & MMC_DATA_READ) ? 640 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE)); 641 642 if (data->stop) 643 via_sdc_send_command(host, data->stop); 644 else 645 tasklet_schedule(&host->finish_tasklet); 646 } 647 648 static void via_sdc_finish_command(struct via_crdr_mmc_host *host) 649 { 650 via_sdc_get_response(host, host->cmd); 651 652 host->cmd->error = 0; 653 654 if (!host->cmd->data) 655 tasklet_schedule(&host->finish_tasklet); 656 657 host->cmd = NULL; 658 } 659 660 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq) 661 { 662 void __iomem *addrbase; 663 struct via_crdr_mmc_host *host; 664 unsigned long flags; 665 u16 status; 666 667 host = mmc_priv(mmc); 668 669 spin_lock_irqsave(&host->lock, flags); 670 671 addrbase = host->pcictrl_mmiobase; 672 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK); 673 674 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 675 status &= VIA_CRDR_SDSTS_W1C_MASK; 676 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 677 678 WARN_ON(host->mrq != NULL); 679 host->mrq = mrq; 680 681 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 682 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) { 683 host->mrq->cmd->error = -ENOMEDIUM; 684 tasklet_schedule(&host->finish_tasklet); 685 } else { 686 via_sdc_send_command(host, mrq->cmd); 687 } 688 689 spin_unlock_irqrestore(&host->lock, flags); 690 } 691 692 static void via_sdc_set_power(struct via_crdr_mmc_host *host, 693 unsigned short power, unsigned int on) 694 { 695 unsigned long flags; 696 u8 gatt; 697 698 spin_lock_irqsave(&host->lock, flags); 699 700 host->power = (1 << power); 701 702 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 703 if (host->power == MMC_VDD_165_195) 704 gatt &= ~VIA_CRDR_PCICLKGATT_3V3; 705 else 706 gatt |= VIA_CRDR_PCICLKGATT_3V3; 707 if (on) 708 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON; 709 else 710 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON; 711 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 712 713 spin_unlock_irqrestore(&host->lock, flags); 714 715 via_pwron_sleep(host); 716 } 717 718 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 719 { 720 struct via_crdr_mmc_host *host; 721 unsigned long flags; 722 void __iomem *addrbase; 723 u32 org_data, sdextctrl; 724 u8 clock; 725 726 host = mmc_priv(mmc); 727 728 spin_lock_irqsave(&host->lock, flags); 729 730 addrbase = host->sdhc_mmiobase; 731 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE); 732 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL); 733 734 if (ios->bus_width == MMC_BUS_WIDTH_1) 735 org_data &= ~VIA_CRDR_SDMODE_4BIT; 736 else 737 org_data |= VIA_CRDR_SDMODE_4BIT; 738 739 if (ios->power_mode == MMC_POWER_OFF) 740 org_data &= ~VIA_CRDR_SDMODE_CLK_ON; 741 else 742 org_data |= VIA_CRDR_SDMODE_CLK_ON; 743 744 if (ios->timing == MMC_TIMING_SD_HS) 745 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD; 746 else 747 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD; 748 749 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE); 750 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL); 751 752 if (ios->clock >= 48000000) 753 clock = PCI_CLK_48M; 754 else if (ios->clock >= 33000000) 755 clock = PCI_CLK_33M; 756 else if (ios->clock >= 24000000) 757 clock = PCI_CLK_24M; 758 else if (ios->clock >= 16000000) 759 clock = PCI_CLK_16M; 760 else if (ios->clock >= 12000000) 761 clock = PCI_CLK_12M; 762 else if (ios->clock >= 8000000) 763 clock = PCI_CLK_8M; 764 else 765 clock = PCI_CLK_375K; 766 767 addrbase = host->pcictrl_mmiobase; 768 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock) 769 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK); 770 771 spin_unlock_irqrestore(&host->lock, flags); 772 773 if (ios->power_mode != MMC_POWER_OFF) 774 via_sdc_set_power(host, ios->vdd, 1); 775 else 776 via_sdc_set_power(host, ios->vdd, 0); 777 } 778 779 static int via_sdc_get_ro(struct mmc_host *mmc) 780 { 781 struct via_crdr_mmc_host *host; 782 unsigned long flags; 783 u16 status; 784 785 host = mmc_priv(mmc); 786 787 spin_lock_irqsave(&host->lock, flags); 788 789 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 790 791 spin_unlock_irqrestore(&host->lock, flags); 792 793 return !(status & VIA_CRDR_SDSTS_WP); 794 } 795 796 static const struct mmc_host_ops via_sdc_ops = { 797 .request = via_sdc_request, 798 .set_ios = via_sdc_set_ios, 799 .get_ro = via_sdc_get_ro, 800 }; 801 802 static void via_reset_pcictrl(struct via_crdr_mmc_host *host) 803 { 804 unsigned long flags; 805 u8 gatt; 806 807 spin_lock_irqsave(&host->lock, flags); 808 809 via_save_pcictrlreg(host); 810 via_save_sdcreg(host); 811 812 spin_unlock_irqrestore(&host->lock, flags); 813 814 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON; 815 if (host->power == MMC_VDD_165_195) 816 gatt &= VIA_CRDR_PCICLKGATT_3V3; 817 else 818 gatt |= VIA_CRDR_PCICLKGATT_3V3; 819 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 820 via_pwron_sleep(host); 821 gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 822 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 823 msleep(3); 824 825 spin_lock_irqsave(&host->lock, flags); 826 827 via_restore_pcictrlreg(host); 828 via_restore_sdcreg(host); 829 830 spin_unlock_irqrestore(&host->lock, flags); 831 } 832 833 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask) 834 { 835 BUG_ON(intmask == 0); 836 837 if (!host->cmd) { 838 pr_err("%s: Got command interrupt 0x%x even " 839 "though no command operation was in progress.\n", 840 mmc_hostname(host->mmc), intmask); 841 return; 842 } 843 844 if (intmask & VIA_CRDR_SDSTS_CRTO) 845 host->cmd->error = -ETIMEDOUT; 846 else if (intmask & VIA_CRDR_SDSTS_SC) 847 host->cmd->error = -EILSEQ; 848 849 if (host->cmd->error) 850 tasklet_schedule(&host->finish_tasklet); 851 else if (intmask & VIA_CRDR_SDSTS_CRD) 852 via_sdc_finish_command(host); 853 } 854 855 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask) 856 { 857 BUG_ON(intmask == 0); 858 859 if (intmask & VIA_CRDR_SDSTS_DT) 860 host->data->error = -ETIMEDOUT; 861 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)) 862 host->data->error = -EILSEQ; 863 864 via_sdc_finish_data(host); 865 } 866 867 static irqreturn_t via_sdc_isr(int irq, void *dev_id) 868 { 869 struct via_crdr_mmc_host *sdhost = dev_id; 870 void __iomem *addrbase; 871 u8 pci_status; 872 u16 sd_status; 873 irqreturn_t result; 874 875 if (!sdhost) 876 return IRQ_NONE; 877 878 spin_lock(&sdhost->lock); 879 880 addrbase = sdhost->pcictrl_mmiobase; 881 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS); 882 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) { 883 result = IRQ_NONE; 884 goto out; 885 } 886 887 addrbase = sdhost->sdhc_mmiobase; 888 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS); 889 sd_status &= VIA_CRDR_SDSTS_INT_MASK; 890 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK; 891 if (!sd_status) { 892 result = IRQ_NONE; 893 goto out; 894 } 895 896 if (sd_status & VIA_CRDR_SDSTS_CIR) { 897 writew(sd_status & VIA_CRDR_SDSTS_CIR, 898 addrbase + VIA_CRDR_SDSTATUS); 899 900 schedule_work(&sdhost->carddet_work); 901 } 902 903 sd_status &= ~VIA_CRDR_SDSTS_CIR; 904 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) { 905 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK, 906 addrbase + VIA_CRDR_SDSTATUS); 907 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK); 908 } 909 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) { 910 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK, 911 addrbase + VIA_CRDR_SDSTATUS); 912 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK); 913 } 914 915 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK); 916 if (sd_status) { 917 pr_err("%s: Unexpected interrupt 0x%x\n", 918 mmc_hostname(sdhost->mmc), sd_status); 919 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS); 920 } 921 922 result = IRQ_HANDLED; 923 924 out: 925 spin_unlock(&sdhost->lock); 926 927 return result; 928 } 929 930 static void via_sdc_timeout(struct timer_list *t) 931 { 932 struct via_crdr_mmc_host *sdhost; 933 unsigned long flags; 934 935 sdhost = from_timer(sdhost, t, timer); 936 937 spin_lock_irqsave(&sdhost->lock, flags); 938 939 if (sdhost->mrq) { 940 pr_err("%s: Timeout waiting for hardware interrupt." 941 "cmd:0x%x\n", mmc_hostname(sdhost->mmc), 942 sdhost->mrq->cmd->opcode); 943 944 if (sdhost->data) { 945 writel(VIA_CRDR_DMACTRL_SFTRST, 946 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL); 947 sdhost->data->error = -ETIMEDOUT; 948 via_sdc_finish_data(sdhost); 949 } else { 950 if (sdhost->cmd) 951 sdhost->cmd->error = -ETIMEDOUT; 952 else 953 sdhost->mrq->cmd->error = -ETIMEDOUT; 954 tasklet_schedule(&sdhost->finish_tasklet); 955 } 956 } 957 958 spin_unlock_irqrestore(&sdhost->lock, flags); 959 } 960 961 static void via_sdc_tasklet_finish(unsigned long param) 962 { 963 struct via_crdr_mmc_host *host; 964 unsigned long flags; 965 struct mmc_request *mrq; 966 967 host = (struct via_crdr_mmc_host *)param; 968 969 spin_lock_irqsave(&host->lock, flags); 970 971 del_timer(&host->timer); 972 mrq = host->mrq; 973 host->mrq = NULL; 974 host->cmd = NULL; 975 host->data = NULL; 976 977 spin_unlock_irqrestore(&host->lock, flags); 978 979 mmc_request_done(host->mmc, mrq); 980 } 981 982 static void via_sdc_card_detect(struct work_struct *work) 983 { 984 struct via_crdr_mmc_host *host; 985 void __iomem *addrbase; 986 unsigned long flags; 987 u16 status; 988 989 host = container_of(work, struct via_crdr_mmc_host, carddet_work); 990 991 addrbase = host->ddma_mmiobase; 992 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL); 993 994 spin_lock_irqsave(&host->lock, flags); 995 996 addrbase = host->pcictrl_mmiobase; 997 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK); 998 999 addrbase = host->sdhc_mmiobase; 1000 status = readw(addrbase + VIA_CRDR_SDSTATUS); 1001 if (!(status & VIA_CRDR_SDSTS_SLOTG)) { 1002 if (host->mrq) { 1003 pr_err("%s: Card removed during transfer!\n", 1004 mmc_hostname(host->mmc)); 1005 host->mrq->cmd->error = -ENOMEDIUM; 1006 tasklet_schedule(&host->finish_tasklet); 1007 } 1008 1009 spin_unlock_irqrestore(&host->lock, flags); 1010 1011 via_reset_pcictrl(host); 1012 1013 spin_lock_irqsave(&host->lock, flags); 1014 } 1015 1016 spin_unlock_irqrestore(&host->lock, flags); 1017 1018 via_print_pcictrl(host); 1019 via_print_sdchc(host); 1020 1021 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1022 } 1023 1024 static void via_init_mmc_host(struct via_crdr_mmc_host *host) 1025 { 1026 struct mmc_host *mmc = host->mmc; 1027 void __iomem *addrbase; 1028 u32 lenreg; 1029 u32 status; 1030 1031 timer_setup(&host->timer, via_sdc_timeout, 0); 1032 1033 spin_lock_init(&host->lock); 1034 1035 mmc->f_min = VIA_CRDR_MIN_CLOCK; 1036 mmc->f_max = VIA_CRDR_MAX_CLOCK; 1037 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1038 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED; 1039 mmc->ops = &via_sdc_ops; 1040 1041 /*Hardware cannot do scatter lists*/ 1042 mmc->max_segs = 1; 1043 1044 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH; 1045 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT; 1046 1047 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; 1048 mmc->max_req_size = mmc->max_seg_size; 1049 1050 INIT_WORK(&host->carddet_work, via_sdc_card_detect); 1051 1052 tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish, 1053 (unsigned long)host); 1054 1055 addrbase = host->sdhc_mmiobase; 1056 writel(0x0, addrbase + VIA_CRDR_SDINTMASK); 1057 msleep(1); 1058 1059 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 1060 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN); 1061 1062 status = readw(addrbase + VIA_CRDR_SDSTATUS); 1063 status &= VIA_CRDR_SDSTS_W1C_MASK; 1064 writew(status, addrbase + VIA_CRDR_SDSTATUS); 1065 1066 status = readw(addrbase + VIA_CRDR_SDSTATUS2); 1067 status |= VIA_CRDR_SDSTS_CFE; 1068 writew(status, addrbase + VIA_CRDR_SDSTATUS2); 1069 1070 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL); 1071 1072 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK); 1073 msleep(1); 1074 } 1075 1076 static int via_sd_probe(struct pci_dev *pcidev, 1077 const struct pci_device_id *id) 1078 { 1079 struct mmc_host *mmc; 1080 struct via_crdr_mmc_host *sdhost; 1081 u32 base, len; 1082 u8 gatt; 1083 int ret; 1084 1085 pr_info(DRV_NAME 1086 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n", 1087 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, 1088 (int)pcidev->revision); 1089 1090 ret = pci_enable_device(pcidev); 1091 if (ret) 1092 return ret; 1093 1094 ret = pci_request_regions(pcidev, DRV_NAME); 1095 if (ret) 1096 goto disable; 1097 1098 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0); 1099 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0); 1100 1101 mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev); 1102 if (!mmc) { 1103 ret = -ENOMEM; 1104 goto release; 1105 } 1106 1107 sdhost = mmc_priv(mmc); 1108 sdhost->mmc = mmc; 1109 dev_set_drvdata(&pcidev->dev, sdhost); 1110 1111 len = pci_resource_len(pcidev, 0); 1112 base = pci_resource_start(pcidev, 0); 1113 sdhost->mmiobase = ioremap_nocache(base, len); 1114 if (!sdhost->mmiobase) { 1115 ret = -ENOMEM; 1116 goto free_mmc_host; 1117 } 1118 1119 sdhost->sdhc_mmiobase = 1120 sdhost->mmiobase + VIA_CRDR_SDC_OFF; 1121 sdhost->ddma_mmiobase = 1122 sdhost->mmiobase + VIA_CRDR_DDMA_OFF; 1123 sdhost->pcictrl_mmiobase = 1124 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF; 1125 1126 sdhost->power = MMC_VDD_165_195; 1127 1128 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON; 1129 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1130 via_pwron_sleep(sdhost); 1131 gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 1132 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1133 msleep(3); 1134 1135 via_init_mmc_host(sdhost); 1136 1137 ret = 1138 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME, 1139 sdhost); 1140 if (ret) 1141 goto unmap; 1142 1143 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN, 1144 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1145 writeb(VIA_CRDR_PCITMOCTRL_1024MS, 1146 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL); 1147 1148 /* device-specific quirks */ 1149 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO && 1150 pcidev->subsystem_device == 0x3891) 1151 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY; 1152 1153 mmc_add_host(mmc); 1154 1155 return 0; 1156 1157 unmap: 1158 iounmap(sdhost->mmiobase); 1159 free_mmc_host: 1160 dev_set_drvdata(&pcidev->dev, NULL); 1161 mmc_free_host(mmc); 1162 release: 1163 pci_release_regions(pcidev); 1164 disable: 1165 pci_disable_device(pcidev); 1166 1167 return ret; 1168 } 1169 1170 static void via_sd_remove(struct pci_dev *pcidev) 1171 { 1172 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev); 1173 unsigned long flags; 1174 u8 gatt; 1175 1176 spin_lock_irqsave(&sdhost->lock, flags); 1177 1178 /* Ensure we don't accept more commands from mmc layer */ 1179 sdhost->reject = 1; 1180 1181 /* Disable generating further interrupts */ 1182 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1183 1184 if (sdhost->mrq) { 1185 pr_err("%s: Controller removed during " 1186 "transfer\n", mmc_hostname(sdhost->mmc)); 1187 1188 /* make sure all DMA is stopped */ 1189 writel(VIA_CRDR_DMACTRL_SFTRST, 1190 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL); 1191 sdhost->mrq->cmd->error = -ENOMEDIUM; 1192 if (sdhost->mrq->stop) 1193 sdhost->mrq->stop->error = -ENOMEDIUM; 1194 tasklet_schedule(&sdhost->finish_tasklet); 1195 } 1196 spin_unlock_irqrestore(&sdhost->lock, flags); 1197 1198 mmc_remove_host(sdhost->mmc); 1199 1200 free_irq(pcidev->irq, sdhost); 1201 1202 del_timer_sync(&sdhost->timer); 1203 1204 tasklet_kill(&sdhost->finish_tasklet); 1205 1206 /* switch off power */ 1207 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1208 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON; 1209 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1210 1211 iounmap(sdhost->mmiobase); 1212 dev_set_drvdata(&pcidev->dev, NULL); 1213 mmc_free_host(sdhost->mmc); 1214 pci_release_regions(pcidev); 1215 pci_disable_device(pcidev); 1216 1217 pr_info(DRV_NAME 1218 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n", 1219 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); 1220 } 1221 1222 #ifdef CONFIG_PM 1223 1224 static void via_init_sdc_pm(struct via_crdr_mmc_host *host) 1225 { 1226 struct sdhcreg *pm_sdhcreg; 1227 void __iomem *addrbase; 1228 u32 lenreg; 1229 u16 status; 1230 1231 pm_sdhcreg = &(host->pm_sdhc_reg); 1232 addrbase = host->sdhc_mmiobase; 1233 1234 writel(0x0, addrbase + VIA_CRDR_SDINTMASK); 1235 1236 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 1237 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN); 1238 1239 status = readw(addrbase + VIA_CRDR_SDSTATUS); 1240 status &= VIA_CRDR_SDSTS_W1C_MASK; 1241 writew(status, addrbase + VIA_CRDR_SDSTATUS); 1242 1243 status = readw(addrbase + VIA_CRDR_SDSTATUS2); 1244 status |= VIA_CRDR_SDSTS_CFE; 1245 writew(status, addrbase + VIA_CRDR_SDSTATUS2); 1246 1247 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL); 1248 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG); 1249 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK); 1250 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO); 1251 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL); 1252 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL); 1253 1254 via_print_pcictrl(host); 1255 via_print_sdchc(host); 1256 } 1257 1258 static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state) 1259 { 1260 struct via_crdr_mmc_host *host; 1261 1262 host = pci_get_drvdata(pcidev); 1263 1264 via_save_pcictrlreg(host); 1265 via_save_sdcreg(host); 1266 1267 pci_save_state(pcidev); 1268 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0); 1269 pci_disable_device(pcidev); 1270 pci_set_power_state(pcidev, pci_choose_state(pcidev, state)); 1271 1272 return 0; 1273 } 1274 1275 static int via_sd_resume(struct pci_dev *pcidev) 1276 { 1277 struct via_crdr_mmc_host *sdhost; 1278 int ret = 0; 1279 u8 gatt; 1280 1281 sdhost = pci_get_drvdata(pcidev); 1282 1283 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON; 1284 if (sdhost->power == MMC_VDD_165_195) 1285 gatt &= ~VIA_CRDR_PCICLKGATT_3V3; 1286 else 1287 gatt |= VIA_CRDR_PCICLKGATT_3V3; 1288 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1289 via_pwron_sleep(sdhost); 1290 gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 1291 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1292 msleep(3); 1293 1294 msleep(100); 1295 1296 pci_set_power_state(pcidev, PCI_D0); 1297 pci_restore_state(pcidev); 1298 ret = pci_enable_device(pcidev); 1299 if (ret) 1300 return ret; 1301 1302 via_restore_pcictrlreg(sdhost); 1303 via_init_sdc_pm(sdhost); 1304 1305 return ret; 1306 } 1307 1308 #else /* CONFIG_PM */ 1309 1310 #define via_sd_suspend NULL 1311 #define via_sd_resume NULL 1312 1313 #endif /* CONFIG_PM */ 1314 1315 static struct pci_driver via_sd_driver = { 1316 .name = DRV_NAME, 1317 .id_table = via_ids, 1318 .probe = via_sd_probe, 1319 .remove = via_sd_remove, 1320 .suspend = via_sd_suspend, 1321 .resume = via_sd_resume, 1322 }; 1323 1324 module_pci_driver(via_sd_driver); 1325 1326 MODULE_LICENSE("GPL"); 1327 MODULE_AUTHOR("VIA Technologies Inc."); 1328 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver"); 1329