1f0bf7f61SHarald Welte /* 2f0bf7f61SHarald Welte * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver 3f0bf7f61SHarald Welte * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved. 4f0bf7f61SHarald Welte * 5f0bf7f61SHarald Welte * This program is free software; you can redistribute it and/or modify 6f0bf7f61SHarald Welte * it under the terms of the GNU General Public License as published by 7f0bf7f61SHarald Welte * the Free Software Foundation; either version 2 of the License, or (at 8f0bf7f61SHarald Welte * your option) any later version. 9f0bf7f61SHarald Welte */ 10f0bf7f61SHarald Welte 11f0bf7f61SHarald Welte #include <linux/pci.h> 1288b47679SPaul Gortmaker #include <linux/module.h> 13f0bf7f61SHarald Welte #include <linux/dma-mapping.h> 14f0bf7f61SHarald Welte #include <linux/highmem.h> 15f0bf7f61SHarald Welte #include <linux/delay.h> 16f0bf7f61SHarald Welte 17f0bf7f61SHarald Welte #include <linux/mmc/host.h> 18f0bf7f61SHarald Welte 19f0bf7f61SHarald Welte #define DRV_NAME "via_sdmmc" 20f0bf7f61SHarald Welte 21f0bf7f61SHarald Welte #define PCI_DEVICE_ID_VIA_9530 0x9530 22f0bf7f61SHarald Welte 23f0bf7f61SHarald Welte #define VIA_CRDR_SDC_OFF 0x200 24f0bf7f61SHarald Welte #define VIA_CRDR_DDMA_OFF 0x400 25f0bf7f61SHarald Welte #define VIA_CRDR_PCICTRL_OFF 0x600 26f0bf7f61SHarald Welte 27f0bf7f61SHarald Welte #define VIA_CRDR_MIN_CLOCK 375000 28f0bf7f61SHarald Welte #define VIA_CRDR_MAX_CLOCK 48000000 29f0bf7f61SHarald Welte 30f0bf7f61SHarald Welte /* 31f0bf7f61SHarald Welte * PCI registers 32f0bf7f61SHarald Welte */ 33f0bf7f61SHarald Welte 34f0bf7f61SHarald Welte #define VIA_CRDR_PCI_WORK_MODE 0x40 35f0bf7f61SHarald Welte #define VIA_CRDR_PCI_DBG_MODE 0x41 36f0bf7f61SHarald Welte 37f0bf7f61SHarald Welte /* 38f0bf7f61SHarald Welte * SDC MMIO Registers 39f0bf7f61SHarald Welte */ 40f0bf7f61SHarald Welte 41f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL 0x0 42f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_START 0x01 43f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_WRITE 0x04 44f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10 45f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20 46f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_MULTI_WR 0x30 47f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_MULTI_RD 0x40 48f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_STOP 0x70 49f0bf7f61SHarald Welte 50f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_RSP_NONE 0x0 51f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_RSP_R1 0x10000 52f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_RSP_R2 0x20000 53f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_RSP_R3 0x30000 54f0bf7f61SHarald Welte #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000 55f0bf7f61SHarald Welte 56f0bf7f61SHarald Welte #define VIA_CRDR_SDCARG 0x4 57f0bf7f61SHarald Welte 58f0bf7f61SHarald Welte #define VIA_CRDR_SDBUSMODE 0x8 59f0bf7f61SHarald Welte #define VIA_CRDR_SDMODE_4BIT 0x02 60f0bf7f61SHarald Welte #define VIA_CRDR_SDMODE_CLK_ON 0x40 61f0bf7f61SHarald Welte 62f0bf7f61SHarald Welte #define VIA_CRDR_SDBLKLEN 0xc 63f0bf7f61SHarald Welte /* 64f0bf7f61SHarald Welte * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048. 65f0bf7f61SHarald Welte * Bit 11 - Bit 13 : Reserved. 66f0bf7f61SHarald Welte * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design. 67f0bf7f61SHarald Welte * INTEN : Enable SD host interrupt. 68f0bf7f61SHarald Welte * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536. 69f0bf7f61SHarald Welte */ 70f0bf7f61SHarald Welte #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000 71f0bf7f61SHarald Welte #define VIA_CRDR_SDBLKLEN_INTEN 0x8000 72f0bf7f61SHarald Welte #define VIA_CRDR_MAX_BLOCK_COUNT 65536 73f0bf7f61SHarald Welte #define VIA_CRDR_MAX_BLOCK_LENGTH 2048 74f0bf7f61SHarald Welte 75f0bf7f61SHarald Welte #define VIA_CRDR_SDRESP0 0x10 76f0bf7f61SHarald Welte #define VIA_CRDR_SDRESP1 0x14 77f0bf7f61SHarald Welte #define VIA_CRDR_SDRESP2 0x18 78f0bf7f61SHarald Welte #define VIA_CRDR_SDRESP3 0x1c 79f0bf7f61SHarald Welte 80f0bf7f61SHarald Welte #define VIA_CRDR_SDCURBLKCNT 0x20 81f0bf7f61SHarald Welte 82f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK 0x24 83f0bf7f61SHarald Welte /* 84f0bf7f61SHarald Welte * MBDIE : Multiple Blocks transfer Done Interrupt Enable 85f0bf7f61SHarald Welte * BDDIE : Block Data transfer Done Interrupt Enable 86f0bf7f61SHarald Welte * CIRIE : Card Insertion or Removal Interrupt Enable 87f0bf7f61SHarald Welte * CRDIE : Command-Response transfer Done Interrupt Enable 88f0bf7f61SHarald Welte * CRTOIE : Command-Response response TimeOut Interrupt Enable 89f0bf7f61SHarald Welte * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable 90f0bf7f61SHarald Welte * DTIE : Data access Timeout Interrupt Enable 91f0bf7f61SHarald Welte * SCIE : reSponse CRC error Interrupt Enable 92f0bf7f61SHarald Welte * RCIE : Read data CRC error Interrupt Enable 93f0bf7f61SHarald Welte * WCIE : Write data CRC error Interrupt Enable 94f0bf7f61SHarald Welte */ 95f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_MBDIE 0x10 96f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_BDDIE 0x20 97f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_CIRIE 0x80 98f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_CRDIE 0x200 99f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_CRTOIE 0x400 100f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800 101f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_DTIE 0x1000 102f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_SCIE 0x2000 103f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_RCIE 0x4000 104f0bf7f61SHarald Welte #define VIA_CRDR_SDINTMASK_WCIE 0x8000 105f0bf7f61SHarald Welte 106f0bf7f61SHarald Welte #define VIA_CRDR_SDACTIVE_INTMASK \ 107f0bf7f61SHarald Welte (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \ 108f0bf7f61SHarald Welte | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \ 109f0bf7f61SHarald Welte | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \ 110f0bf7f61SHarald Welte | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE) 111f0bf7f61SHarald Welte 112f0bf7f61SHarald Welte #define VIA_CRDR_SDSTATUS 0x28 113f0bf7f61SHarald Welte /* 114f0bf7f61SHarald Welte * CECC : Reserved 115f0bf7f61SHarald Welte * WP : SD card Write Protect status 116f0bf7f61SHarald Welte * SLOTD : Reserved 117f0bf7f61SHarald Welte * SLOTG : SD SLOT status(Gpi pin status) 118f0bf7f61SHarald Welte * MBD : Multiple Blocks transfer Done interrupt status 119f0bf7f61SHarald Welte * BDD : Block Data transfer Done interrupt status 120f0bf7f61SHarald Welte * CD : Reserved 121f0bf7f61SHarald Welte * CIR : Card Insertion or Removal interrupt detected on GPI pin 122f0bf7f61SHarald Welte * IO : Reserved 123f0bf7f61SHarald Welte * CRD : Command-Response transfer Done interrupt status 124f0bf7f61SHarald Welte * CRTO : Command-Response response TimeOut interrupt status 125f0bf7f61SHarald Welte * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status 126f0bf7f61SHarald Welte * DT : Data access Timeout interrupt status 127f0bf7f61SHarald Welte * SC : reSponse CRC error interrupt status 128f0bf7f61SHarald Welte * RC : Read data CRC error interrupt status 129f0bf7f61SHarald Welte * WC : Write data CRC error interrupt status 130f0bf7f61SHarald Welte */ 131f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_CECC 0x01 132f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_WP 0x02 133f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_SLOTD 0x04 134f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_SLOTG 0x08 135f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_MBD 0x10 136f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_BDD 0x20 137f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_CD 0x40 138f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_CIR 0x80 139f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_IO 0x100 140f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_CRD 0x200 141f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_CRTO 0x400 142f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_ASCRDIE 0x800 143f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_DT 0x1000 144f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_SC 0x2000 145f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_RC 0x4000 146f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_WC 0x8000 147f0bf7f61SHarald Welte 148f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_IGN_MASK\ 149f0bf7f61SHarald Welte (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO) 150f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_INT_MASK \ 151f0bf7f61SHarald Welte (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \ 152f0bf7f61SHarald Welte | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \ 153f0bf7f61SHarald Welte | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \ 154f0bf7f61SHarald Welte | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 155f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_W1C_MASK \ 156f0bf7f61SHarald Welte (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \ 157f0bf7f61SHarald Welte | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \ 158f0bf7f61SHarald Welte | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \ 159f0bf7f61SHarald Welte | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 160f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_CMD_MASK \ 161f0bf7f61SHarald Welte (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC) 162f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_DATA_MASK\ 163f0bf7f61SHarald Welte (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \ 164f0bf7f61SHarald Welte | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 165f0bf7f61SHarald Welte 166f0bf7f61SHarald Welte #define VIA_CRDR_SDSTATUS2 0x2a 167f0bf7f61SHarald Welte /* 168f0bf7f61SHarald Welte * CFE : Enable SD host automatic Clock FReezing 169f0bf7f61SHarald Welte */ 170f0bf7f61SHarald Welte #define VIA_CRDR_SDSTS_CFE 0x80 171f0bf7f61SHarald Welte 172f0bf7f61SHarald Welte #define VIA_CRDR_SDRSPTMO 0x2C 173f0bf7f61SHarald Welte 174f0bf7f61SHarald Welte #define VIA_CRDR_SDCLKSEL 0x30 175f0bf7f61SHarald Welte 176f0bf7f61SHarald Welte #define VIA_CRDR_SDEXTCTRL 0x34 177f0bf7f61SHarald Welte #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01 178f0bf7f61SHarald Welte #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02 179f0bf7f61SHarald Welte #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04 180f0bf7f61SHarald Welte #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08 181f0bf7f61SHarald Welte #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10 182f0bf7f61SHarald Welte #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20 183f0bf7f61SHarald Welte #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40 184f0bf7f61SHarald Welte #define VIA_CRDR_SDEXTCTRL_HISPD 0x80 185f0bf7f61SHarald Welte /* 0x38-0xFF reserved */ 186f0bf7f61SHarald Welte 187f0bf7f61SHarald Welte /* 188f0bf7f61SHarald Welte * Data DMA Control Registers 189f0bf7f61SHarald Welte */ 190f0bf7f61SHarald Welte 191f0bf7f61SHarald Welte #define VIA_CRDR_DMABASEADD 0x0 192f0bf7f61SHarald Welte #define VIA_CRDR_DMACOUNTER 0x4 193f0bf7f61SHarald Welte 194f0bf7f61SHarald Welte #define VIA_CRDR_DMACTRL 0x8 195f0bf7f61SHarald Welte /* 196f0bf7f61SHarald Welte * DIR :Transaction Direction 197f0bf7f61SHarald Welte * 0 : From card to memory 198f0bf7f61SHarald Welte * 1 : From memory to card 199f0bf7f61SHarald Welte */ 200f0bf7f61SHarald Welte #define VIA_CRDR_DMACTRL_DIR 0x100 201f0bf7f61SHarald Welte #define VIA_CRDR_DMACTRL_ENIRQ 0x10000 202f0bf7f61SHarald Welte #define VIA_CRDR_DMACTRL_SFTRST 0x1000000 203f0bf7f61SHarald Welte 204f0bf7f61SHarald Welte #define VIA_CRDR_DMASTS 0xc 205f0bf7f61SHarald Welte 206f0bf7f61SHarald Welte #define VIA_CRDR_DMASTART 0x10 207f0bf7f61SHarald Welte /*0x14-0xFF reserved*/ 208f0bf7f61SHarald Welte 209f0bf7f61SHarald Welte /* 210f0bf7f61SHarald Welte * PCI Control Registers 211f0bf7f61SHarald Welte */ 212f0bf7f61SHarald Welte 213f0bf7f61SHarald Welte /*0x0 - 0x1 reserved*/ 214f0bf7f61SHarald Welte #define VIA_CRDR_PCICLKGATT 0x2 215f0bf7f61SHarald Welte /* 216f0bf7f61SHarald Welte * SFTRST : 217f0bf7f61SHarald Welte * 0 : Soft reset all the controller and it will be de-asserted automatically 218f0bf7f61SHarald Welte * 1 : Soft reset is de-asserted 219f0bf7f61SHarald Welte */ 220f0bf7f61SHarald Welte #define VIA_CRDR_PCICLKGATT_SFTRST 0x01 221f0bf7f61SHarald Welte /* 222f0bf7f61SHarald Welte * 3V3 : Pad power select 223f0bf7f61SHarald Welte * 0 : 1.8V 224f0bf7f61SHarald Welte * 1 : 3.3V 225f0bf7f61SHarald Welte * NOTE : No mater what the actual value should be, this bit always 226f0bf7f61SHarald Welte * read as 0. This is a hardware bug. 227f0bf7f61SHarald Welte */ 228f0bf7f61SHarald Welte #define VIA_CRDR_PCICLKGATT_3V3 0x10 229f0bf7f61SHarald Welte /* 230f0bf7f61SHarald Welte * PAD_PWRON : Pad Power on/off select 231f0bf7f61SHarald Welte * 0 : Power off 232f0bf7f61SHarald Welte * 1 : Power on 233f0bf7f61SHarald Welte * NOTE : No mater what the actual value should be, this bit always 234f0bf7f61SHarald Welte * read as 0. This is a hardware bug. 235f0bf7f61SHarald Welte */ 236f0bf7f61SHarald Welte #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20 237f0bf7f61SHarald Welte 238f0bf7f61SHarald Welte #define VIA_CRDR_PCISDCCLK 0x5 239f0bf7f61SHarald Welte 240f0bf7f61SHarald Welte #define VIA_CRDR_PCIDMACLK 0x7 241f0bf7f61SHarald Welte #define VIA_CRDR_PCIDMACLK_SDC 0x2 242f0bf7f61SHarald Welte 243f0bf7f61SHarald Welte #define VIA_CRDR_PCIINTCTRL 0x8 244f0bf7f61SHarald Welte #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04 245f0bf7f61SHarald Welte 246f0bf7f61SHarald Welte #define VIA_CRDR_PCIINTSTATUS 0x9 247f0bf7f61SHarald Welte #define VIA_CRDR_PCIINTSTATUS_SDC 0x04 248f0bf7f61SHarald Welte 249f0bf7f61SHarald Welte #define VIA_CRDR_PCITMOCTRL 0xa 250f0bf7f61SHarald Welte #define VIA_CRDR_PCITMOCTRL_NO 0x0 251f0bf7f61SHarald Welte #define VIA_CRDR_PCITMOCTRL_32US 0x1 252f0bf7f61SHarald Welte #define VIA_CRDR_PCITMOCTRL_256US 0x2 253f0bf7f61SHarald Welte #define VIA_CRDR_PCITMOCTRL_1024US 0x3 254f0bf7f61SHarald Welte #define VIA_CRDR_PCITMOCTRL_256MS 0x4 255f0bf7f61SHarald Welte #define VIA_CRDR_PCITMOCTRL_512MS 0x5 256f0bf7f61SHarald Welte #define VIA_CRDR_PCITMOCTRL_1024MS 0x6 257f0bf7f61SHarald Welte 258f0bf7f61SHarald Welte /*0xB-0xFF reserved*/ 259f0bf7f61SHarald Welte 260f0bf7f61SHarald Welte enum PCI_HOST_CLK_CONTROL { 261f0bf7f61SHarald Welte PCI_CLK_375K = 0x03, 262f0bf7f61SHarald Welte PCI_CLK_8M = 0x04, 263f0bf7f61SHarald Welte PCI_CLK_12M = 0x00, 264f0bf7f61SHarald Welte PCI_CLK_16M = 0x05, 265f0bf7f61SHarald Welte PCI_CLK_24M = 0x01, 266f0bf7f61SHarald Welte PCI_CLK_33M = 0x06, 267f0bf7f61SHarald Welte PCI_CLK_48M = 0x02 268f0bf7f61SHarald Welte }; 269f0bf7f61SHarald Welte 270f0bf7f61SHarald Welte struct sdhcreg { 271f0bf7f61SHarald Welte u32 sdcontrol_reg; 272f0bf7f61SHarald Welte u32 sdcmdarg_reg; 273f0bf7f61SHarald Welte u32 sdbusmode_reg; 274f0bf7f61SHarald Welte u32 sdblklen_reg; 275f0bf7f61SHarald Welte u32 sdresp_reg[4]; 276f0bf7f61SHarald Welte u32 sdcurblkcnt_reg; 277f0bf7f61SHarald Welte u32 sdintmask_reg; 278f0bf7f61SHarald Welte u32 sdstatus_reg; 279f0bf7f61SHarald Welte u32 sdrsptmo_reg; 280f0bf7f61SHarald Welte u32 sdclksel_reg; 281f0bf7f61SHarald Welte u32 sdextctrl_reg; 282f0bf7f61SHarald Welte }; 283f0bf7f61SHarald Welte 284f0bf7f61SHarald Welte struct pcictrlreg { 285f0bf7f61SHarald Welte u8 reserve[2]; 286f0bf7f61SHarald Welte u8 pciclkgat_reg; 287f0bf7f61SHarald Welte u8 pcinfcclk_reg; 288f0bf7f61SHarald Welte u8 pcimscclk_reg; 289f0bf7f61SHarald Welte u8 pcisdclk_reg; 290f0bf7f61SHarald Welte u8 pcicaclk_reg; 291f0bf7f61SHarald Welte u8 pcidmaclk_reg; 292f0bf7f61SHarald Welte u8 pciintctrl_reg; 293f0bf7f61SHarald Welte u8 pciintstatus_reg; 294f0bf7f61SHarald Welte u8 pcitmoctrl_reg; 295f0bf7f61SHarald Welte u8 Resv; 296f0bf7f61SHarald Welte }; 297f0bf7f61SHarald Welte 298f0bf7f61SHarald Welte struct via_crdr_mmc_host { 299f0bf7f61SHarald Welte struct mmc_host *mmc; 300f0bf7f61SHarald Welte struct mmc_request *mrq; 301f0bf7f61SHarald Welte struct mmc_command *cmd; 302f0bf7f61SHarald Welte struct mmc_data *data; 303f0bf7f61SHarald Welte 304f0bf7f61SHarald Welte void __iomem *mmiobase; 305f0bf7f61SHarald Welte void __iomem *sdhc_mmiobase; 306f0bf7f61SHarald Welte void __iomem *ddma_mmiobase; 307f0bf7f61SHarald Welte void __iomem *pcictrl_mmiobase; 308f0bf7f61SHarald Welte 309f0bf7f61SHarald Welte struct pcictrlreg pm_pcictrl_reg; 310f0bf7f61SHarald Welte struct sdhcreg pm_sdhc_reg; 311f0bf7f61SHarald Welte 312f0bf7f61SHarald Welte struct work_struct carddet_work; 313f0bf7f61SHarald Welte struct tasklet_struct finish_tasklet; 314f0bf7f61SHarald Welte 315f0bf7f61SHarald Welte struct timer_list timer; 316f0bf7f61SHarald Welte spinlock_t lock; 317f0bf7f61SHarald Welte u8 power; 318f0bf7f61SHarald Welte int reject; 319f0bf7f61SHarald Welte unsigned int quirks; 320f0bf7f61SHarald Welte }; 321f0bf7f61SHarald Welte 322f0bf7f61SHarald Welte /* some devices need a very long delay for power to stabilize */ 323f0bf7f61SHarald Welte #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001 324f0bf7f61SHarald Welte 325f0bf7f61SHarald Welte static struct pci_device_id via_ids[] = { 326f0bf7f61SHarald Welte {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_9530, 327f0bf7f61SHarald Welte PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, 328f0bf7f61SHarald Welte {0,} 329f0bf7f61SHarald Welte }; 330f0bf7f61SHarald Welte 331f0bf7f61SHarald Welte MODULE_DEVICE_TABLE(pci, via_ids); 332f0bf7f61SHarald Welte 333f0bf7f61SHarald Welte static void via_print_sdchc(struct via_crdr_mmc_host *host) 334f0bf7f61SHarald Welte { 335f0bf7f61SHarald Welte void __iomem *addrbase = host->sdhc_mmiobase; 336f0bf7f61SHarald Welte 337f0bf7f61SHarald Welte pr_debug("SDC MMIO Registers:\n"); 338f0bf7f61SHarald Welte pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n", 339f0bf7f61SHarald Welte readl(addrbase + VIA_CRDR_SDCTRL), 340f0bf7f61SHarald Welte readl(addrbase + VIA_CRDR_SDCARG), 341f0bf7f61SHarald Welte readl(addrbase + VIA_CRDR_SDBUSMODE)); 342f0bf7f61SHarald Welte pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n", 343f0bf7f61SHarald Welte readl(addrbase + VIA_CRDR_SDBLKLEN), 344f0bf7f61SHarald Welte readl(addrbase + VIA_CRDR_SDCURBLKCNT), 345f0bf7f61SHarald Welte readl(addrbase + VIA_CRDR_SDINTMASK)); 346f0bf7f61SHarald Welte pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n", 347f0bf7f61SHarald Welte readl(addrbase + VIA_CRDR_SDSTATUS), 348f0bf7f61SHarald Welte readl(addrbase + VIA_CRDR_SDCLKSEL), 349f0bf7f61SHarald Welte readl(addrbase + VIA_CRDR_SDEXTCTRL)); 350f0bf7f61SHarald Welte } 351f0bf7f61SHarald Welte 352f0bf7f61SHarald Welte static void via_print_pcictrl(struct via_crdr_mmc_host *host) 353f0bf7f61SHarald Welte { 354f0bf7f61SHarald Welte void __iomem *addrbase = host->pcictrl_mmiobase; 355f0bf7f61SHarald Welte 356f0bf7f61SHarald Welte pr_debug("PCI Control Registers:\n"); 357f0bf7f61SHarald Welte pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n", 358f0bf7f61SHarald Welte readb(addrbase + VIA_CRDR_PCICLKGATT), 359f0bf7f61SHarald Welte readb(addrbase + VIA_CRDR_PCISDCCLK), 360f0bf7f61SHarald Welte readb(addrbase + VIA_CRDR_PCIDMACLK)); 361f0bf7f61SHarald Welte pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n", 362f0bf7f61SHarald Welte readb(addrbase + VIA_CRDR_PCIINTCTRL), 363f0bf7f61SHarald Welte readb(addrbase + VIA_CRDR_PCIINTSTATUS)); 364f0bf7f61SHarald Welte } 365f0bf7f61SHarald Welte 366f0bf7f61SHarald Welte static void via_save_pcictrlreg(struct via_crdr_mmc_host *host) 367f0bf7f61SHarald Welte { 368f0bf7f61SHarald Welte struct pcictrlreg *pm_pcictrl_reg; 369f0bf7f61SHarald Welte void __iomem *addrbase; 370f0bf7f61SHarald Welte 371f0bf7f61SHarald Welte pm_pcictrl_reg = &(host->pm_pcictrl_reg); 372f0bf7f61SHarald Welte addrbase = host->pcictrl_mmiobase; 373f0bf7f61SHarald Welte 374f0bf7f61SHarald Welte pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT); 375f0bf7f61SHarald Welte pm_pcictrl_reg->pciclkgat_reg |= 376f0bf7f61SHarald Welte VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON; 377f0bf7f61SHarald Welte pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK); 378f0bf7f61SHarald Welte pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK); 379f0bf7f61SHarald Welte pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL); 380f0bf7f61SHarald Welte pm_pcictrl_reg->pciintstatus_reg = 381f0bf7f61SHarald Welte readb(addrbase + VIA_CRDR_PCIINTSTATUS); 382f0bf7f61SHarald Welte pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL); 383f0bf7f61SHarald Welte } 384f0bf7f61SHarald Welte 385f0bf7f61SHarald Welte static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host) 386f0bf7f61SHarald Welte { 387f0bf7f61SHarald Welte struct pcictrlreg *pm_pcictrl_reg; 388f0bf7f61SHarald Welte void __iomem *addrbase; 389f0bf7f61SHarald Welte 390f0bf7f61SHarald Welte pm_pcictrl_reg = &(host->pm_pcictrl_reg); 391f0bf7f61SHarald Welte addrbase = host->pcictrl_mmiobase; 392f0bf7f61SHarald Welte 393f0bf7f61SHarald Welte writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT); 394f0bf7f61SHarald Welte writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK); 395f0bf7f61SHarald Welte writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK); 396f0bf7f61SHarald Welte writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL); 397f0bf7f61SHarald Welte writeb(pm_pcictrl_reg->pciintstatus_reg, 398f0bf7f61SHarald Welte addrbase + VIA_CRDR_PCIINTSTATUS); 399f0bf7f61SHarald Welte writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL); 400f0bf7f61SHarald Welte } 401f0bf7f61SHarald Welte 402f0bf7f61SHarald Welte static void via_save_sdcreg(struct via_crdr_mmc_host *host) 403f0bf7f61SHarald Welte { 404f0bf7f61SHarald Welte struct sdhcreg *pm_sdhc_reg; 405f0bf7f61SHarald Welte void __iomem *addrbase; 406f0bf7f61SHarald Welte 407f0bf7f61SHarald Welte pm_sdhc_reg = &(host->pm_sdhc_reg); 408f0bf7f61SHarald Welte addrbase = host->sdhc_mmiobase; 409f0bf7f61SHarald Welte 410f0bf7f61SHarald Welte pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL); 411f0bf7f61SHarald Welte pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG); 412f0bf7f61SHarald Welte pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE); 413f0bf7f61SHarald Welte pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN); 414f0bf7f61SHarald Welte pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT); 415f0bf7f61SHarald Welte pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK); 416f0bf7f61SHarald Welte pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS); 417f0bf7f61SHarald Welte pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO); 418f0bf7f61SHarald Welte pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL); 419f0bf7f61SHarald Welte pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL); 420f0bf7f61SHarald Welte } 421f0bf7f61SHarald Welte 422f0bf7f61SHarald Welte static void via_restore_sdcreg(struct via_crdr_mmc_host *host) 423f0bf7f61SHarald Welte { 424f0bf7f61SHarald Welte struct sdhcreg *pm_sdhc_reg; 425f0bf7f61SHarald Welte void __iomem *addrbase; 426f0bf7f61SHarald Welte 427f0bf7f61SHarald Welte pm_sdhc_reg = &(host->pm_sdhc_reg); 428f0bf7f61SHarald Welte addrbase = host->sdhc_mmiobase; 429f0bf7f61SHarald Welte 430f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL); 431f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG); 432f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE); 433f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN); 434f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT); 435f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK); 436f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS); 437f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO); 438f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL); 439f0bf7f61SHarald Welte writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL); 440f0bf7f61SHarald Welte } 441f0bf7f61SHarald Welte 442f0bf7f61SHarald Welte static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost) 443f0bf7f61SHarald Welte { 444f0bf7f61SHarald Welte if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY) 445f0bf7f61SHarald Welte msleep(300); 446f0bf7f61SHarald Welte else 447f0bf7f61SHarald Welte msleep(3); 448f0bf7f61SHarald Welte } 449f0bf7f61SHarald Welte 450f0bf7f61SHarald Welte static void via_set_ddma(struct via_crdr_mmc_host *host, 451f0bf7f61SHarald Welte dma_addr_t dmaaddr, u32 count, int dir, int enirq) 452f0bf7f61SHarald Welte { 453f0bf7f61SHarald Welte void __iomem *addrbase; 454f0bf7f61SHarald Welte u32 ctrl_data = 0; 455f0bf7f61SHarald Welte 456f0bf7f61SHarald Welte if (enirq) 457f0bf7f61SHarald Welte ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ; 458f0bf7f61SHarald Welte 459f0bf7f61SHarald Welte if (dir) 460f0bf7f61SHarald Welte ctrl_data |= VIA_CRDR_DMACTRL_DIR; 461f0bf7f61SHarald Welte 462f0bf7f61SHarald Welte addrbase = host->ddma_mmiobase; 463f0bf7f61SHarald Welte 464f0bf7f61SHarald Welte writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD); 465f0bf7f61SHarald Welte writel(count, addrbase + VIA_CRDR_DMACOUNTER); 466f0bf7f61SHarald Welte writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL); 467f0bf7f61SHarald Welte writel(0x01, addrbase + VIA_CRDR_DMASTART); 468f0bf7f61SHarald Welte 469f0bf7f61SHarald Welte /* It seems that our DMA can not work normally with 375kHz clock */ 470f0bf7f61SHarald Welte /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */ 471f0bf7f61SHarald Welte addrbase = host->pcictrl_mmiobase; 472f0bf7f61SHarald Welte if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) { 473f0bf7f61SHarald Welte dev_info(host->mmc->parent, "forcing card speed to 8MHz\n"); 474f0bf7f61SHarald Welte writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK); 475f0bf7f61SHarald Welte } 476f0bf7f61SHarald Welte } 477f0bf7f61SHarald Welte 478f0bf7f61SHarald Welte static void via_sdc_preparedata(struct via_crdr_mmc_host *host, 479f0bf7f61SHarald Welte struct mmc_data *data) 480f0bf7f61SHarald Welte { 481f0bf7f61SHarald Welte void __iomem *addrbase; 482f0bf7f61SHarald Welte u32 blk_reg; 483f0bf7f61SHarald Welte int count; 484f0bf7f61SHarald Welte 485f0bf7f61SHarald Welte WARN_ON(host->data); 486f0bf7f61SHarald Welte 487f0bf7f61SHarald Welte /* Sanity checks */ 488f0bf7f61SHarald Welte BUG_ON(data->blksz > host->mmc->max_blk_size); 489f0bf7f61SHarald Welte BUG_ON(data->blocks > host->mmc->max_blk_count); 490f0bf7f61SHarald Welte 491f0bf7f61SHarald Welte host->data = data; 492f0bf7f61SHarald Welte 493f0bf7f61SHarald Welte count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 494f0bf7f61SHarald Welte ((data->flags & MMC_DATA_READ) ? 495f0bf7f61SHarald Welte PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE)); 496f0bf7f61SHarald Welte BUG_ON(count != 1); 497f0bf7f61SHarald Welte 498f0bf7f61SHarald Welte via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg), 499f0bf7f61SHarald Welte (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1); 500f0bf7f61SHarald Welte 501f0bf7f61SHarald Welte addrbase = host->sdhc_mmiobase; 502f0bf7f61SHarald Welte 503f0bf7f61SHarald Welte blk_reg = data->blksz - 1; 504f0bf7f61SHarald Welte blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 505f0bf7f61SHarald Welte blk_reg |= (data->blocks) << 16; 506f0bf7f61SHarald Welte 507f0bf7f61SHarald Welte writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN); 508f0bf7f61SHarald Welte } 509f0bf7f61SHarald Welte 510f0bf7f61SHarald Welte static void via_sdc_get_response(struct via_crdr_mmc_host *host, 511f0bf7f61SHarald Welte struct mmc_command *cmd) 512f0bf7f61SHarald Welte { 513f0bf7f61SHarald Welte void __iomem *addrbase = host->sdhc_mmiobase; 514f0bf7f61SHarald Welte u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0); 515f0bf7f61SHarald Welte u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1); 516f0bf7f61SHarald Welte u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2); 517f0bf7f61SHarald Welte u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3); 518f0bf7f61SHarald Welte 519f0bf7f61SHarald Welte if (cmd->flags & MMC_RSP_136) { 520f0bf7f61SHarald Welte cmd->resp[0] = ((u8) (dwdata1)) | 521f0bf7f61SHarald Welte (((u8) (dwdata0 >> 24)) << 8) | 522f0bf7f61SHarald Welte (((u8) (dwdata0 >> 16)) << 16) | 523f0bf7f61SHarald Welte (((u8) (dwdata0 >> 8)) << 24); 524f0bf7f61SHarald Welte 525f0bf7f61SHarald Welte cmd->resp[1] = ((u8) (dwdata2)) | 526f0bf7f61SHarald Welte (((u8) (dwdata1 >> 24)) << 8) | 527f0bf7f61SHarald Welte (((u8) (dwdata1 >> 16)) << 16) | 528f0bf7f61SHarald Welte (((u8) (dwdata1 >> 8)) << 24); 529f0bf7f61SHarald Welte 530f0bf7f61SHarald Welte cmd->resp[2] = ((u8) (dwdata3)) | 531f0bf7f61SHarald Welte (((u8) (dwdata2 >> 24)) << 8) | 532f0bf7f61SHarald Welte (((u8) (dwdata2 >> 16)) << 16) | 533f0bf7f61SHarald Welte (((u8) (dwdata2 >> 8)) << 24); 534f0bf7f61SHarald Welte 535f0bf7f61SHarald Welte cmd->resp[3] = 0xff | 536f0bf7f61SHarald Welte ((((u8) (dwdata3 >> 24))) << 8) | 537f0bf7f61SHarald Welte (((u8) (dwdata3 >> 16)) << 16) | 538f0bf7f61SHarald Welte (((u8) (dwdata3 >> 8)) << 24); 539f0bf7f61SHarald Welte } else { 540f0bf7f61SHarald Welte dwdata0 >>= 8; 541f0bf7f61SHarald Welte cmd->resp[0] = ((dwdata0 & 0xff) << 24) | 542f0bf7f61SHarald Welte (((dwdata0 >> 8) & 0xff) << 16) | 543f0bf7f61SHarald Welte (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff); 544f0bf7f61SHarald Welte 545f0bf7f61SHarald Welte dwdata1 >>= 8; 546f0bf7f61SHarald Welte cmd->resp[1] = ((dwdata1 & 0xff) << 24) | 547f0bf7f61SHarald Welte (((dwdata1 >> 8) & 0xff) << 16) | 548f0bf7f61SHarald Welte (((dwdata1 >> 16) & 0xff) << 8); 549f0bf7f61SHarald Welte } 550f0bf7f61SHarald Welte } 551f0bf7f61SHarald Welte 552f0bf7f61SHarald Welte static void via_sdc_send_command(struct via_crdr_mmc_host *host, 553f0bf7f61SHarald Welte struct mmc_command *cmd) 554f0bf7f61SHarald Welte { 555f0bf7f61SHarald Welte void __iomem *addrbase; 556f0bf7f61SHarald Welte struct mmc_data *data; 557f0bf7f61SHarald Welte u32 cmdctrl = 0; 558f0bf7f61SHarald Welte 559f0bf7f61SHarald Welte WARN_ON(host->cmd); 560f0bf7f61SHarald Welte 561f0bf7f61SHarald Welte data = cmd->data; 562f0bf7f61SHarald Welte mod_timer(&host->timer, jiffies + HZ); 563f0bf7f61SHarald Welte host->cmd = cmd; 564f0bf7f61SHarald Welte 565f0bf7f61SHarald Welte /*Command index*/ 566f0bf7f61SHarald Welte cmdctrl = cmd->opcode << 8; 567f0bf7f61SHarald Welte 568f0bf7f61SHarald Welte /*Response type*/ 569f0bf7f61SHarald Welte switch (mmc_resp_type(cmd)) { 570f0bf7f61SHarald Welte case MMC_RSP_NONE: 571f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE; 572f0bf7f61SHarald Welte break; 573f0bf7f61SHarald Welte case MMC_RSP_R1: 574f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1; 575f0bf7f61SHarald Welte break; 576f0bf7f61SHarald Welte case MMC_RSP_R1B: 577f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B; 578f0bf7f61SHarald Welte break; 579f0bf7f61SHarald Welte case MMC_RSP_R2: 580f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2; 581f0bf7f61SHarald Welte break; 582f0bf7f61SHarald Welte case MMC_RSP_R3: 583f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3; 584f0bf7f61SHarald Welte break; 585f0bf7f61SHarald Welte default: 586f0bf7f61SHarald Welte pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc)); 587f0bf7f61SHarald Welte break; 588f0bf7f61SHarald Welte } 589f0bf7f61SHarald Welte 590f0bf7f61SHarald Welte if (!(cmd->data)) 591f0bf7f61SHarald Welte goto nodata; 592f0bf7f61SHarald Welte 593f0bf7f61SHarald Welte via_sdc_preparedata(host, data); 594f0bf7f61SHarald Welte 595f0bf7f61SHarald Welte /*Command control*/ 596f0bf7f61SHarald Welte if (data->blocks > 1) { 597f0bf7f61SHarald Welte if (data->flags & MMC_DATA_WRITE) { 598f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_WRITE; 599f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR; 600f0bf7f61SHarald Welte } else { 601f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD; 602f0bf7f61SHarald Welte } 603f0bf7f61SHarald Welte } else { 604f0bf7f61SHarald Welte if (data->flags & MMC_DATA_WRITE) { 605f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_WRITE; 606f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR; 607f0bf7f61SHarald Welte } else { 608f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD; 609f0bf7f61SHarald Welte } 610f0bf7f61SHarald Welte } 611f0bf7f61SHarald Welte 612f0bf7f61SHarald Welte nodata: 613f0bf7f61SHarald Welte if (cmd == host->mrq->stop) 614f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_STOP; 615f0bf7f61SHarald Welte 616f0bf7f61SHarald Welte cmdctrl |= VIA_CRDR_SDCTRL_START; 617f0bf7f61SHarald Welte 618f0bf7f61SHarald Welte addrbase = host->sdhc_mmiobase; 619f0bf7f61SHarald Welte writel(cmd->arg, addrbase + VIA_CRDR_SDCARG); 620f0bf7f61SHarald Welte writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL); 621f0bf7f61SHarald Welte } 622f0bf7f61SHarald Welte 623f0bf7f61SHarald Welte static void via_sdc_finish_data(struct via_crdr_mmc_host *host) 624f0bf7f61SHarald Welte { 625f0bf7f61SHarald Welte struct mmc_data *data; 626f0bf7f61SHarald Welte 627f0bf7f61SHarald Welte BUG_ON(!host->data); 628f0bf7f61SHarald Welte 629f0bf7f61SHarald Welte data = host->data; 630f0bf7f61SHarald Welte host->data = NULL; 631f0bf7f61SHarald Welte 632f0bf7f61SHarald Welte if (data->error) 633f0bf7f61SHarald Welte data->bytes_xfered = 0; 634f0bf7f61SHarald Welte else 635f0bf7f61SHarald Welte data->bytes_xfered = data->blocks * data->blksz; 636f0bf7f61SHarald Welte 637f0bf7f61SHarald Welte dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 638f0bf7f61SHarald Welte ((data->flags & MMC_DATA_READ) ? 639f0bf7f61SHarald Welte PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE)); 640f0bf7f61SHarald Welte 641f0bf7f61SHarald Welte if (data->stop) 642f0bf7f61SHarald Welte via_sdc_send_command(host, data->stop); 643f0bf7f61SHarald Welte else 644f0bf7f61SHarald Welte tasklet_schedule(&host->finish_tasklet); 645f0bf7f61SHarald Welte } 646f0bf7f61SHarald Welte 647f0bf7f61SHarald Welte static void via_sdc_finish_command(struct via_crdr_mmc_host *host) 648f0bf7f61SHarald Welte { 649f0bf7f61SHarald Welte via_sdc_get_response(host, host->cmd); 650f0bf7f61SHarald Welte 651f0bf7f61SHarald Welte host->cmd->error = 0; 652f0bf7f61SHarald Welte 653f0bf7f61SHarald Welte if (!host->cmd->data) 654f0bf7f61SHarald Welte tasklet_schedule(&host->finish_tasklet); 655f0bf7f61SHarald Welte 656f0bf7f61SHarald Welte host->cmd = NULL; 657f0bf7f61SHarald Welte } 658f0bf7f61SHarald Welte 659f0bf7f61SHarald Welte static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq) 660f0bf7f61SHarald Welte { 661f0bf7f61SHarald Welte void __iomem *addrbase; 662f0bf7f61SHarald Welte struct via_crdr_mmc_host *host; 663f0bf7f61SHarald Welte unsigned long flags; 664f0bf7f61SHarald Welte u16 status; 665f0bf7f61SHarald Welte 666f0bf7f61SHarald Welte host = mmc_priv(mmc); 667f0bf7f61SHarald Welte 668f0bf7f61SHarald Welte spin_lock_irqsave(&host->lock, flags); 669f0bf7f61SHarald Welte 670f0bf7f61SHarald Welte addrbase = host->pcictrl_mmiobase; 671f0bf7f61SHarald Welte writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK); 672f0bf7f61SHarald Welte 673f0bf7f61SHarald Welte status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 674f0bf7f61SHarald Welte status &= VIA_CRDR_SDSTS_W1C_MASK; 675f0bf7f61SHarald Welte writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 676f0bf7f61SHarald Welte 677f0bf7f61SHarald Welte WARN_ON(host->mrq != NULL); 678f0bf7f61SHarald Welte host->mrq = mrq; 679f0bf7f61SHarald Welte 680f0bf7f61SHarald Welte status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 681f0bf7f61SHarald Welte if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) { 682f0bf7f61SHarald Welte host->mrq->cmd->error = -ENOMEDIUM; 683f0bf7f61SHarald Welte tasklet_schedule(&host->finish_tasklet); 684f0bf7f61SHarald Welte } else { 685f0bf7f61SHarald Welte via_sdc_send_command(host, mrq->cmd); 686f0bf7f61SHarald Welte } 687f0bf7f61SHarald Welte 688f0bf7f61SHarald Welte mmiowb(); 689f0bf7f61SHarald Welte spin_unlock_irqrestore(&host->lock, flags); 690f0bf7f61SHarald Welte } 691f0bf7f61SHarald Welte 692f0bf7f61SHarald Welte static void via_sdc_set_power(struct via_crdr_mmc_host *host, 693f0bf7f61SHarald Welte unsigned short power, unsigned int on) 694f0bf7f61SHarald Welte { 695f0bf7f61SHarald Welte unsigned long flags; 696f0bf7f61SHarald Welte u8 gatt; 697f0bf7f61SHarald Welte 698f0bf7f61SHarald Welte spin_lock_irqsave(&host->lock, flags); 699f0bf7f61SHarald Welte 700f0bf7f61SHarald Welte host->power = (1 << power); 701f0bf7f61SHarald Welte 702f0bf7f61SHarald Welte gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 703f0bf7f61SHarald Welte if (host->power == MMC_VDD_165_195) 704f0bf7f61SHarald Welte gatt &= ~VIA_CRDR_PCICLKGATT_3V3; 705f0bf7f61SHarald Welte else 706f0bf7f61SHarald Welte gatt |= VIA_CRDR_PCICLKGATT_3V3; 707f0bf7f61SHarald Welte if (on) 708f0bf7f61SHarald Welte gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON; 709f0bf7f61SHarald Welte else 710f0bf7f61SHarald Welte gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON; 711f0bf7f61SHarald Welte writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 712f0bf7f61SHarald Welte 713f0bf7f61SHarald Welte mmiowb(); 714f0bf7f61SHarald Welte spin_unlock_irqrestore(&host->lock, flags); 715f0bf7f61SHarald Welte 716f0bf7f61SHarald Welte via_pwron_sleep(host); 717f0bf7f61SHarald Welte } 718f0bf7f61SHarald Welte 719f0bf7f61SHarald Welte static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 720f0bf7f61SHarald Welte { 721f0bf7f61SHarald Welte struct via_crdr_mmc_host *host; 722f0bf7f61SHarald Welte unsigned long flags; 723f0bf7f61SHarald Welte void __iomem *addrbase; 724f0bf7f61SHarald Welte u32 org_data, sdextctrl; 725f0bf7f61SHarald Welte u8 clock; 726f0bf7f61SHarald Welte 727f0bf7f61SHarald Welte host = mmc_priv(mmc); 728f0bf7f61SHarald Welte 729f0bf7f61SHarald Welte spin_lock_irqsave(&host->lock, flags); 730f0bf7f61SHarald Welte 731f0bf7f61SHarald Welte addrbase = host->sdhc_mmiobase; 732f0bf7f61SHarald Welte org_data = readl(addrbase + VIA_CRDR_SDBUSMODE); 733f0bf7f61SHarald Welte sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL); 734f0bf7f61SHarald Welte 735f0bf7f61SHarald Welte if (ios->bus_width == MMC_BUS_WIDTH_1) 736f0bf7f61SHarald Welte org_data &= ~VIA_CRDR_SDMODE_4BIT; 737f0bf7f61SHarald Welte else 738f0bf7f61SHarald Welte org_data |= VIA_CRDR_SDMODE_4BIT; 739f0bf7f61SHarald Welte 740f0bf7f61SHarald Welte if (ios->power_mode == MMC_POWER_OFF) 741f0bf7f61SHarald Welte org_data &= ~VIA_CRDR_SDMODE_CLK_ON; 742f0bf7f61SHarald Welte else 743f0bf7f61SHarald Welte org_data |= VIA_CRDR_SDMODE_CLK_ON; 744f0bf7f61SHarald Welte 745f0bf7f61SHarald Welte if (ios->timing == MMC_TIMING_SD_HS) 746f0bf7f61SHarald Welte sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD; 747f0bf7f61SHarald Welte else 748f0bf7f61SHarald Welte sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD; 749f0bf7f61SHarald Welte 750f0bf7f61SHarald Welte writel(org_data, addrbase + VIA_CRDR_SDBUSMODE); 751f0bf7f61SHarald Welte writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL); 752f0bf7f61SHarald Welte 753f0bf7f61SHarald Welte if (ios->clock >= 48000000) 754f0bf7f61SHarald Welte clock = PCI_CLK_48M; 755f0bf7f61SHarald Welte else if (ios->clock >= 33000000) 756f0bf7f61SHarald Welte clock = PCI_CLK_33M; 757f0bf7f61SHarald Welte else if (ios->clock >= 24000000) 758f0bf7f61SHarald Welte clock = PCI_CLK_24M; 759f0bf7f61SHarald Welte else if (ios->clock >= 16000000) 760f0bf7f61SHarald Welte clock = PCI_CLK_16M; 761f0bf7f61SHarald Welte else if (ios->clock >= 12000000) 762f0bf7f61SHarald Welte clock = PCI_CLK_12M; 763f0bf7f61SHarald Welte else if (ios->clock >= 8000000) 764f0bf7f61SHarald Welte clock = PCI_CLK_8M; 765f0bf7f61SHarald Welte else 766f0bf7f61SHarald Welte clock = PCI_CLK_375K; 767f0bf7f61SHarald Welte 768f0bf7f61SHarald Welte addrbase = host->pcictrl_mmiobase; 769f0bf7f61SHarald Welte if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock) 770f0bf7f61SHarald Welte writeb(clock, addrbase + VIA_CRDR_PCISDCCLK); 771f0bf7f61SHarald Welte 772f0bf7f61SHarald Welte mmiowb(); 773f0bf7f61SHarald Welte spin_unlock_irqrestore(&host->lock, flags); 774f0bf7f61SHarald Welte 775f0bf7f61SHarald Welte if (ios->power_mode != MMC_POWER_OFF) 776f0bf7f61SHarald Welte via_sdc_set_power(host, ios->vdd, 1); 777f0bf7f61SHarald Welte else 778f0bf7f61SHarald Welte via_sdc_set_power(host, ios->vdd, 0); 779f0bf7f61SHarald Welte } 780f0bf7f61SHarald Welte 781f0bf7f61SHarald Welte static int via_sdc_get_ro(struct mmc_host *mmc) 782f0bf7f61SHarald Welte { 783f0bf7f61SHarald Welte struct via_crdr_mmc_host *host; 784f0bf7f61SHarald Welte unsigned long flags; 785f0bf7f61SHarald Welte u16 status; 786f0bf7f61SHarald Welte 787f0bf7f61SHarald Welte host = mmc_priv(mmc); 788f0bf7f61SHarald Welte 789f0bf7f61SHarald Welte spin_lock_irqsave(&host->lock, flags); 790f0bf7f61SHarald Welte 791f0bf7f61SHarald Welte status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 792f0bf7f61SHarald Welte 793f0bf7f61SHarald Welte spin_unlock_irqrestore(&host->lock, flags); 794f0bf7f61SHarald Welte 795f0bf7f61SHarald Welte return !(status & VIA_CRDR_SDSTS_WP); 796f0bf7f61SHarald Welte } 797f0bf7f61SHarald Welte 798f0bf7f61SHarald Welte static const struct mmc_host_ops via_sdc_ops = { 799f0bf7f61SHarald Welte .request = via_sdc_request, 800f0bf7f61SHarald Welte .set_ios = via_sdc_set_ios, 801f0bf7f61SHarald Welte .get_ro = via_sdc_get_ro, 802f0bf7f61SHarald Welte }; 803f0bf7f61SHarald Welte 804f0bf7f61SHarald Welte static void via_reset_pcictrl(struct via_crdr_mmc_host *host) 805f0bf7f61SHarald Welte { 806f0bf7f61SHarald Welte unsigned long flags; 807f0bf7f61SHarald Welte u8 gatt; 808f0bf7f61SHarald Welte 809f0bf7f61SHarald Welte spin_lock_irqsave(&host->lock, flags); 810f0bf7f61SHarald Welte 811f0bf7f61SHarald Welte via_save_pcictrlreg(host); 812f0bf7f61SHarald Welte via_save_sdcreg(host); 813f0bf7f61SHarald Welte 814f0bf7f61SHarald Welte spin_unlock_irqrestore(&host->lock, flags); 815f0bf7f61SHarald Welte 816f0bf7f61SHarald Welte gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON; 817f0bf7f61SHarald Welte if (host->power == MMC_VDD_165_195) 818f0bf7f61SHarald Welte gatt &= VIA_CRDR_PCICLKGATT_3V3; 819f0bf7f61SHarald Welte else 820f0bf7f61SHarald Welte gatt |= VIA_CRDR_PCICLKGATT_3V3; 821f0bf7f61SHarald Welte writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 822f0bf7f61SHarald Welte via_pwron_sleep(host); 823f0bf7f61SHarald Welte gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 824f0bf7f61SHarald Welte writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 825f0bf7f61SHarald Welte msleep(3); 826f0bf7f61SHarald Welte 827f0bf7f61SHarald Welte spin_lock_irqsave(&host->lock, flags); 828f0bf7f61SHarald Welte 829f0bf7f61SHarald Welte via_restore_pcictrlreg(host); 830f0bf7f61SHarald Welte via_restore_sdcreg(host); 831f0bf7f61SHarald Welte 832f0bf7f61SHarald Welte mmiowb(); 833f0bf7f61SHarald Welte spin_unlock_irqrestore(&host->lock, flags); 834f0bf7f61SHarald Welte } 835f0bf7f61SHarald Welte 836f0bf7f61SHarald Welte static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask) 837f0bf7f61SHarald Welte { 838f0bf7f61SHarald Welte BUG_ON(intmask == 0); 839f0bf7f61SHarald Welte 840f0bf7f61SHarald Welte if (!host->cmd) { 841f0bf7f61SHarald Welte pr_err("%s: Got command interrupt 0x%x even " 842f0bf7f61SHarald Welte "though no command operation was in progress.\n", 843f0bf7f61SHarald Welte mmc_hostname(host->mmc), intmask); 844f0bf7f61SHarald Welte return; 845f0bf7f61SHarald Welte } 846f0bf7f61SHarald Welte 847f0bf7f61SHarald Welte if (intmask & VIA_CRDR_SDSTS_CRTO) 848f0bf7f61SHarald Welte host->cmd->error = -ETIMEDOUT; 849f0bf7f61SHarald Welte else if (intmask & VIA_CRDR_SDSTS_SC) 850f0bf7f61SHarald Welte host->cmd->error = -EILSEQ; 851f0bf7f61SHarald Welte 852f0bf7f61SHarald Welte if (host->cmd->error) 853f0bf7f61SHarald Welte tasklet_schedule(&host->finish_tasklet); 854f0bf7f61SHarald Welte else if (intmask & VIA_CRDR_SDSTS_CRD) 855f0bf7f61SHarald Welte via_sdc_finish_command(host); 856f0bf7f61SHarald Welte } 857f0bf7f61SHarald Welte 858f0bf7f61SHarald Welte static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask) 859f0bf7f61SHarald Welte { 860f0bf7f61SHarald Welte BUG_ON(intmask == 0); 861f0bf7f61SHarald Welte 862f0bf7f61SHarald Welte if (intmask & VIA_CRDR_SDSTS_DT) 863f0bf7f61SHarald Welte host->data->error = -ETIMEDOUT; 864f0bf7f61SHarald Welte else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)) 865f0bf7f61SHarald Welte host->data->error = -EILSEQ; 866f0bf7f61SHarald Welte 867f0bf7f61SHarald Welte via_sdc_finish_data(host); 868f0bf7f61SHarald Welte } 869f0bf7f61SHarald Welte 870f0bf7f61SHarald Welte static irqreturn_t via_sdc_isr(int irq, void *dev_id) 871f0bf7f61SHarald Welte { 872f0bf7f61SHarald Welte struct via_crdr_mmc_host *sdhost = dev_id; 873f0bf7f61SHarald Welte void __iomem *addrbase; 874f0bf7f61SHarald Welte u8 pci_status; 875f0bf7f61SHarald Welte u16 sd_status; 876f0bf7f61SHarald Welte irqreturn_t result; 877f0bf7f61SHarald Welte 878f0bf7f61SHarald Welte if (!sdhost) 879f0bf7f61SHarald Welte return IRQ_NONE; 880f0bf7f61SHarald Welte 881f0bf7f61SHarald Welte spin_lock(&sdhost->lock); 882f0bf7f61SHarald Welte 883f0bf7f61SHarald Welte addrbase = sdhost->pcictrl_mmiobase; 884f0bf7f61SHarald Welte pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS); 885f0bf7f61SHarald Welte if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) { 886f0bf7f61SHarald Welte result = IRQ_NONE; 887f0bf7f61SHarald Welte goto out; 888f0bf7f61SHarald Welte } 889f0bf7f61SHarald Welte 890f0bf7f61SHarald Welte addrbase = sdhost->sdhc_mmiobase; 891f0bf7f61SHarald Welte sd_status = readw(addrbase + VIA_CRDR_SDSTATUS); 892f0bf7f61SHarald Welte sd_status &= VIA_CRDR_SDSTS_INT_MASK; 893f0bf7f61SHarald Welte sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK; 894f0bf7f61SHarald Welte if (!sd_status) { 895f0bf7f61SHarald Welte result = IRQ_NONE; 896f0bf7f61SHarald Welte goto out; 897f0bf7f61SHarald Welte } 898f0bf7f61SHarald Welte 899f0bf7f61SHarald Welte if (sd_status & VIA_CRDR_SDSTS_CIR) { 900f0bf7f61SHarald Welte writew(sd_status & VIA_CRDR_SDSTS_CIR, 901f0bf7f61SHarald Welte addrbase + VIA_CRDR_SDSTATUS); 902f0bf7f61SHarald Welte 903f0bf7f61SHarald Welte schedule_work(&sdhost->carddet_work); 904f0bf7f61SHarald Welte } 905f0bf7f61SHarald Welte 906f0bf7f61SHarald Welte sd_status &= ~VIA_CRDR_SDSTS_CIR; 907f0bf7f61SHarald Welte if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) { 908f0bf7f61SHarald Welte writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK, 909f0bf7f61SHarald Welte addrbase + VIA_CRDR_SDSTATUS); 910f0bf7f61SHarald Welte via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK); 911f0bf7f61SHarald Welte } 912f0bf7f61SHarald Welte if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) { 913f0bf7f61SHarald Welte writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK, 914f0bf7f61SHarald Welte addrbase + VIA_CRDR_SDSTATUS); 915f0bf7f61SHarald Welte via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK); 916f0bf7f61SHarald Welte } 917f0bf7f61SHarald Welte 918f0bf7f61SHarald Welte sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK); 919f0bf7f61SHarald Welte if (sd_status) { 920f0bf7f61SHarald Welte pr_err("%s: Unexpected interrupt 0x%x\n", 921f0bf7f61SHarald Welte mmc_hostname(sdhost->mmc), sd_status); 922f0bf7f61SHarald Welte writew(sd_status, addrbase + VIA_CRDR_SDSTATUS); 923f0bf7f61SHarald Welte } 924f0bf7f61SHarald Welte 925f0bf7f61SHarald Welte result = IRQ_HANDLED; 926f0bf7f61SHarald Welte 927f0bf7f61SHarald Welte mmiowb(); 928f0bf7f61SHarald Welte out: 929f0bf7f61SHarald Welte spin_unlock(&sdhost->lock); 930f0bf7f61SHarald Welte 931f0bf7f61SHarald Welte return result; 932f0bf7f61SHarald Welte } 933f0bf7f61SHarald Welte 934f0bf7f61SHarald Welte static void via_sdc_timeout(unsigned long ulongdata) 935f0bf7f61SHarald Welte { 936f0bf7f61SHarald Welte struct via_crdr_mmc_host *sdhost; 937f0bf7f61SHarald Welte unsigned long flags; 938f0bf7f61SHarald Welte 939f0bf7f61SHarald Welte sdhost = (struct via_crdr_mmc_host *)ulongdata; 940f0bf7f61SHarald Welte 941f0bf7f61SHarald Welte spin_lock_irqsave(&sdhost->lock, flags); 942f0bf7f61SHarald Welte 943f0bf7f61SHarald Welte if (sdhost->mrq) { 944f0bf7f61SHarald Welte pr_err("%s: Timeout waiting for hardware interrupt." 945f0bf7f61SHarald Welte "cmd:0x%x\n", mmc_hostname(sdhost->mmc), 946f0bf7f61SHarald Welte sdhost->mrq->cmd->opcode); 947f0bf7f61SHarald Welte 948f0bf7f61SHarald Welte if (sdhost->data) { 949f0bf7f61SHarald Welte writel(VIA_CRDR_DMACTRL_SFTRST, 950f0bf7f61SHarald Welte sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL); 951f0bf7f61SHarald Welte sdhost->data->error = -ETIMEDOUT; 952f0bf7f61SHarald Welte via_sdc_finish_data(sdhost); 953f0bf7f61SHarald Welte } else { 954f0bf7f61SHarald Welte if (sdhost->cmd) 955f0bf7f61SHarald Welte sdhost->cmd->error = -ETIMEDOUT; 956f0bf7f61SHarald Welte else 957f0bf7f61SHarald Welte sdhost->mrq->cmd->error = -ETIMEDOUT; 958f0bf7f61SHarald Welte tasklet_schedule(&sdhost->finish_tasklet); 959f0bf7f61SHarald Welte } 960f0bf7f61SHarald Welte } 961f0bf7f61SHarald Welte 962f0bf7f61SHarald Welte mmiowb(); 963f0bf7f61SHarald Welte spin_unlock_irqrestore(&sdhost->lock, flags); 964f0bf7f61SHarald Welte } 965f0bf7f61SHarald Welte 966f0bf7f61SHarald Welte static void via_sdc_tasklet_finish(unsigned long param) 967f0bf7f61SHarald Welte { 968f0bf7f61SHarald Welte struct via_crdr_mmc_host *host; 969f0bf7f61SHarald Welte unsigned long flags; 970f0bf7f61SHarald Welte struct mmc_request *mrq; 971f0bf7f61SHarald Welte 972f0bf7f61SHarald Welte host = (struct via_crdr_mmc_host *)param; 973f0bf7f61SHarald Welte 974f0bf7f61SHarald Welte spin_lock_irqsave(&host->lock, flags); 975f0bf7f61SHarald Welte 976f0bf7f61SHarald Welte del_timer(&host->timer); 977f0bf7f61SHarald Welte mrq = host->mrq; 978f0bf7f61SHarald Welte host->mrq = NULL; 979f0bf7f61SHarald Welte host->cmd = NULL; 980f0bf7f61SHarald Welte host->data = NULL; 981f0bf7f61SHarald Welte 982f0bf7f61SHarald Welte spin_unlock_irqrestore(&host->lock, flags); 983f0bf7f61SHarald Welte 984f0bf7f61SHarald Welte mmc_request_done(host->mmc, mrq); 985f0bf7f61SHarald Welte } 986f0bf7f61SHarald Welte 987f0bf7f61SHarald Welte static void via_sdc_card_detect(struct work_struct *work) 988f0bf7f61SHarald Welte { 989f0bf7f61SHarald Welte struct via_crdr_mmc_host *host; 990f0bf7f61SHarald Welte void __iomem *addrbase; 991f0bf7f61SHarald Welte unsigned long flags; 992f0bf7f61SHarald Welte u16 status; 993f0bf7f61SHarald Welte 994f0bf7f61SHarald Welte host = container_of(work, struct via_crdr_mmc_host, carddet_work); 995f0bf7f61SHarald Welte 996f0bf7f61SHarald Welte addrbase = host->ddma_mmiobase; 997f0bf7f61SHarald Welte writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL); 998f0bf7f61SHarald Welte 999f0bf7f61SHarald Welte spin_lock_irqsave(&host->lock, flags); 1000f0bf7f61SHarald Welte 1001f0bf7f61SHarald Welte addrbase = host->pcictrl_mmiobase; 1002f0bf7f61SHarald Welte writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK); 1003f0bf7f61SHarald Welte 1004f0bf7f61SHarald Welte addrbase = host->sdhc_mmiobase; 1005f0bf7f61SHarald Welte status = readw(addrbase + VIA_CRDR_SDSTATUS); 1006f0bf7f61SHarald Welte if (!(status & VIA_CRDR_SDSTS_SLOTG)) { 1007f0bf7f61SHarald Welte if (host->mrq) { 1008f0bf7f61SHarald Welte pr_err("%s: Card removed during transfer!\n", 1009f0bf7f61SHarald Welte mmc_hostname(host->mmc)); 1010f0bf7f61SHarald Welte host->mrq->cmd->error = -ENOMEDIUM; 1011f0bf7f61SHarald Welte tasklet_schedule(&host->finish_tasklet); 1012f0bf7f61SHarald Welte } 1013f0bf7f61SHarald Welte 1014f0bf7f61SHarald Welte mmiowb(); 1015f0bf7f61SHarald Welte spin_unlock_irqrestore(&host->lock, flags); 1016f0bf7f61SHarald Welte 1017f0bf7f61SHarald Welte via_reset_pcictrl(host); 1018f0bf7f61SHarald Welte 1019f0bf7f61SHarald Welte spin_lock_irqsave(&host->lock, flags); 1020f0bf7f61SHarald Welte } 1021f0bf7f61SHarald Welte 1022f0bf7f61SHarald Welte mmiowb(); 1023f0bf7f61SHarald Welte spin_unlock_irqrestore(&host->lock, flags); 1024f0bf7f61SHarald Welte 1025f0bf7f61SHarald Welte via_print_pcictrl(host); 1026f0bf7f61SHarald Welte via_print_sdchc(host); 1027f0bf7f61SHarald Welte 1028f0bf7f61SHarald Welte mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1029f0bf7f61SHarald Welte } 1030f0bf7f61SHarald Welte 1031f0bf7f61SHarald Welte static void via_init_mmc_host(struct via_crdr_mmc_host *host) 1032f0bf7f61SHarald Welte { 1033f0bf7f61SHarald Welte struct mmc_host *mmc = host->mmc; 1034f0bf7f61SHarald Welte void __iomem *addrbase; 1035f0bf7f61SHarald Welte u32 lenreg; 1036f0bf7f61SHarald Welte u32 status; 1037f0bf7f61SHarald Welte 1038f0bf7f61SHarald Welte init_timer(&host->timer); 1039f0bf7f61SHarald Welte host->timer.data = (unsigned long)host; 1040f0bf7f61SHarald Welte host->timer.function = via_sdc_timeout; 1041f0bf7f61SHarald Welte 1042f0bf7f61SHarald Welte spin_lock_init(&host->lock); 1043f0bf7f61SHarald Welte 1044f0bf7f61SHarald Welte mmc->f_min = VIA_CRDR_MIN_CLOCK; 1045f0bf7f61SHarald Welte mmc->f_max = VIA_CRDR_MAX_CLOCK; 1046f0bf7f61SHarald Welte mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1047f0bf7f61SHarald Welte mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED; 1048f0bf7f61SHarald Welte mmc->ops = &via_sdc_ops; 1049f0bf7f61SHarald Welte 1050f0bf7f61SHarald Welte /*Hardware cannot do scatter lists*/ 1051a36274e0SMartin K. Petersen mmc->max_segs = 1; 1052f0bf7f61SHarald Welte 1053f0bf7f61SHarald Welte mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH; 1054f0bf7f61SHarald Welte mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT; 1055f0bf7f61SHarald Welte 1056f0bf7f61SHarald Welte mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; 1057f0bf7f61SHarald Welte mmc->max_req_size = mmc->max_seg_size; 1058f0bf7f61SHarald Welte 1059f0bf7f61SHarald Welte INIT_WORK(&host->carddet_work, via_sdc_card_detect); 1060f0bf7f61SHarald Welte 1061f0bf7f61SHarald Welte tasklet_init(&host->finish_tasklet, via_sdc_tasklet_finish, 1062f0bf7f61SHarald Welte (unsigned long)host); 1063f0bf7f61SHarald Welte 1064f0bf7f61SHarald Welte addrbase = host->sdhc_mmiobase; 1065f0bf7f61SHarald Welte writel(0x0, addrbase + VIA_CRDR_SDINTMASK); 1066f0bf7f61SHarald Welte msleep(1); 1067f0bf7f61SHarald Welte 1068f0bf7f61SHarald Welte lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 1069f0bf7f61SHarald Welte writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN); 1070f0bf7f61SHarald Welte 1071f0bf7f61SHarald Welte status = readw(addrbase + VIA_CRDR_SDSTATUS); 1072f0bf7f61SHarald Welte status &= VIA_CRDR_SDSTS_W1C_MASK; 1073f0bf7f61SHarald Welte writew(status, addrbase + VIA_CRDR_SDSTATUS); 1074f0bf7f61SHarald Welte 1075f0bf7f61SHarald Welte status = readw(addrbase + VIA_CRDR_SDSTATUS2); 1076f0bf7f61SHarald Welte status |= VIA_CRDR_SDSTS_CFE; 1077f0bf7f61SHarald Welte writew(status, addrbase + VIA_CRDR_SDSTATUS2); 1078f0bf7f61SHarald Welte 1079f0bf7f61SHarald Welte writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL); 1080f0bf7f61SHarald Welte 1081f0bf7f61SHarald Welte writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK); 1082f0bf7f61SHarald Welte msleep(1); 1083f0bf7f61SHarald Welte } 1084f0bf7f61SHarald Welte 1085f0bf7f61SHarald Welte static int __devinit via_sd_probe(struct pci_dev *pcidev, 1086f0bf7f61SHarald Welte const struct pci_device_id *id) 1087f0bf7f61SHarald Welte { 1088f0bf7f61SHarald Welte struct mmc_host *mmc; 1089f0bf7f61SHarald Welte struct via_crdr_mmc_host *sdhost; 1090f0bf7f61SHarald Welte u32 base, len; 1091cf5e23e1SSergei Shtylyov u8 gatt; 1092f0bf7f61SHarald Welte int ret; 1093f0bf7f61SHarald Welte 1094f0bf7f61SHarald Welte pr_info(DRV_NAME 1095f0bf7f61SHarald Welte ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n", 1096f0bf7f61SHarald Welte pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, 1097cf5e23e1SSergei Shtylyov (int)pcidev->revision); 1098f0bf7f61SHarald Welte 1099f0bf7f61SHarald Welte ret = pci_enable_device(pcidev); 1100f0bf7f61SHarald Welte if (ret) 1101f0bf7f61SHarald Welte return ret; 1102f0bf7f61SHarald Welte 1103f0bf7f61SHarald Welte ret = pci_request_regions(pcidev, DRV_NAME); 1104f0bf7f61SHarald Welte if (ret) 1105f0bf7f61SHarald Welte goto disable; 1106f0bf7f61SHarald Welte 1107f0bf7f61SHarald Welte pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0); 1108f0bf7f61SHarald Welte pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0); 1109f0bf7f61SHarald Welte 1110f0bf7f61SHarald Welte mmc = mmc_alloc_host(sizeof(struct via_crdr_mmc_host), &pcidev->dev); 1111f0bf7f61SHarald Welte if (!mmc) { 1112f0bf7f61SHarald Welte ret = -ENOMEM; 1113f0bf7f61SHarald Welte goto release; 1114f0bf7f61SHarald Welte } 1115f0bf7f61SHarald Welte 1116f0bf7f61SHarald Welte sdhost = mmc_priv(mmc); 1117f0bf7f61SHarald Welte sdhost->mmc = mmc; 1118f0bf7f61SHarald Welte dev_set_drvdata(&pcidev->dev, sdhost); 1119f0bf7f61SHarald Welte 1120f0bf7f61SHarald Welte len = pci_resource_len(pcidev, 0); 1121f0bf7f61SHarald Welte base = pci_resource_start(pcidev, 0); 1122f0bf7f61SHarald Welte sdhost->mmiobase = ioremap_nocache(base, len); 1123f0bf7f61SHarald Welte if (!sdhost->mmiobase) { 1124f0bf7f61SHarald Welte ret = -ENOMEM; 1125f0bf7f61SHarald Welte goto free_mmc_host; 1126f0bf7f61SHarald Welte } 1127f0bf7f61SHarald Welte 1128f0bf7f61SHarald Welte sdhost->sdhc_mmiobase = 1129f0bf7f61SHarald Welte sdhost->mmiobase + VIA_CRDR_SDC_OFF; 1130f0bf7f61SHarald Welte sdhost->ddma_mmiobase = 1131f0bf7f61SHarald Welte sdhost->mmiobase + VIA_CRDR_DDMA_OFF; 1132f0bf7f61SHarald Welte sdhost->pcictrl_mmiobase = 1133f0bf7f61SHarald Welte sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF; 1134f0bf7f61SHarald Welte 1135f0bf7f61SHarald Welte sdhost->power = MMC_VDD_165_195; 1136f0bf7f61SHarald Welte 1137f0bf7f61SHarald Welte gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON; 1138f0bf7f61SHarald Welte writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1139f0bf7f61SHarald Welte via_pwron_sleep(sdhost); 1140f0bf7f61SHarald Welte gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 1141f0bf7f61SHarald Welte writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1142f0bf7f61SHarald Welte msleep(3); 1143f0bf7f61SHarald Welte 1144f0bf7f61SHarald Welte via_init_mmc_host(sdhost); 1145f0bf7f61SHarald Welte 1146f0bf7f61SHarald Welte ret = 1147f0bf7f61SHarald Welte request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME, 1148f0bf7f61SHarald Welte sdhost); 1149f0bf7f61SHarald Welte if (ret) 1150f0bf7f61SHarald Welte goto unmap; 1151f0bf7f61SHarald Welte 1152f0bf7f61SHarald Welte writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN, 1153f0bf7f61SHarald Welte sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1154f0bf7f61SHarald Welte writeb(VIA_CRDR_PCITMOCTRL_1024MS, 1155f0bf7f61SHarald Welte sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL); 1156f0bf7f61SHarald Welte 1157f0bf7f61SHarald Welte /* device-specific quirks */ 1158f0bf7f61SHarald Welte if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO && 1159f0bf7f61SHarald Welte pcidev->subsystem_device == 0x3891) 1160f0bf7f61SHarald Welte sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY; 1161f0bf7f61SHarald Welte 1162f0bf7f61SHarald Welte mmc_add_host(mmc); 1163f0bf7f61SHarald Welte 1164f0bf7f61SHarald Welte return 0; 1165f0bf7f61SHarald Welte 1166f0bf7f61SHarald Welte unmap: 1167f0bf7f61SHarald Welte iounmap(sdhost->mmiobase); 1168f0bf7f61SHarald Welte free_mmc_host: 1169f0bf7f61SHarald Welte dev_set_drvdata(&pcidev->dev, NULL); 1170f0bf7f61SHarald Welte mmc_free_host(mmc); 1171f0bf7f61SHarald Welte release: 1172f0bf7f61SHarald Welte pci_release_regions(pcidev); 1173f0bf7f61SHarald Welte disable: 1174f0bf7f61SHarald Welte pci_disable_device(pcidev); 1175f0bf7f61SHarald Welte 1176f0bf7f61SHarald Welte return ret; 1177f0bf7f61SHarald Welte } 1178f0bf7f61SHarald Welte 1179f0bf7f61SHarald Welte static void __devexit via_sd_remove(struct pci_dev *pcidev) 1180f0bf7f61SHarald Welte { 1181f0bf7f61SHarald Welte struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev); 1182f0bf7f61SHarald Welte unsigned long flags; 1183f0bf7f61SHarald Welte u8 gatt; 1184f0bf7f61SHarald Welte 1185f0bf7f61SHarald Welte spin_lock_irqsave(&sdhost->lock, flags); 1186f0bf7f61SHarald Welte 1187f0bf7f61SHarald Welte /* Ensure we don't accept more commands from mmc layer */ 1188f0bf7f61SHarald Welte sdhost->reject = 1; 1189f0bf7f61SHarald Welte 1190f0bf7f61SHarald Welte /* Disable generating further interrupts */ 1191f0bf7f61SHarald Welte writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1192f0bf7f61SHarald Welte mmiowb(); 1193f0bf7f61SHarald Welte 1194f0bf7f61SHarald Welte if (sdhost->mrq) { 1195a3c76eb9SGirish K S pr_err("%s: Controller removed during " 1196f0bf7f61SHarald Welte "transfer\n", mmc_hostname(sdhost->mmc)); 1197f0bf7f61SHarald Welte 1198f0bf7f61SHarald Welte /* make sure all DMA is stopped */ 1199f0bf7f61SHarald Welte writel(VIA_CRDR_DMACTRL_SFTRST, 1200f0bf7f61SHarald Welte sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL); 1201f0bf7f61SHarald Welte mmiowb(); 1202f0bf7f61SHarald Welte sdhost->mrq->cmd->error = -ENOMEDIUM; 1203f0bf7f61SHarald Welte if (sdhost->mrq->stop) 1204f0bf7f61SHarald Welte sdhost->mrq->stop->error = -ENOMEDIUM; 1205f0bf7f61SHarald Welte tasklet_schedule(&sdhost->finish_tasklet); 1206f0bf7f61SHarald Welte } 1207f0bf7f61SHarald Welte spin_unlock_irqrestore(&sdhost->lock, flags); 1208f0bf7f61SHarald Welte 1209f0bf7f61SHarald Welte mmc_remove_host(sdhost->mmc); 1210f0bf7f61SHarald Welte 1211f0bf7f61SHarald Welte free_irq(pcidev->irq, sdhost); 1212f0bf7f61SHarald Welte 1213f0bf7f61SHarald Welte del_timer_sync(&sdhost->timer); 1214f0bf7f61SHarald Welte 1215f0bf7f61SHarald Welte tasklet_kill(&sdhost->finish_tasklet); 1216f0bf7f61SHarald Welte 1217f0bf7f61SHarald Welte /* switch off power */ 1218f0bf7f61SHarald Welte gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1219f0bf7f61SHarald Welte gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON; 1220f0bf7f61SHarald Welte writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1221f0bf7f61SHarald Welte 1222f0bf7f61SHarald Welte iounmap(sdhost->mmiobase); 1223f0bf7f61SHarald Welte dev_set_drvdata(&pcidev->dev, NULL); 1224f0bf7f61SHarald Welte mmc_free_host(sdhost->mmc); 1225f0bf7f61SHarald Welte pci_release_regions(pcidev); 1226f0bf7f61SHarald Welte pci_disable_device(pcidev); 1227f0bf7f61SHarald Welte 1228f0bf7f61SHarald Welte pr_info(DRV_NAME 1229f0bf7f61SHarald Welte ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n", 1230f0bf7f61SHarald Welte pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); 1231f0bf7f61SHarald Welte } 1232f0bf7f61SHarald Welte 1233f0bf7f61SHarald Welte #ifdef CONFIG_PM 1234f0bf7f61SHarald Welte 1235f0bf7f61SHarald Welte static void via_init_sdc_pm(struct via_crdr_mmc_host *host) 1236f0bf7f61SHarald Welte { 1237f0bf7f61SHarald Welte struct sdhcreg *pm_sdhcreg; 1238f0bf7f61SHarald Welte void __iomem *addrbase; 1239f0bf7f61SHarald Welte u32 lenreg; 1240f0bf7f61SHarald Welte u16 status; 1241f0bf7f61SHarald Welte 1242f0bf7f61SHarald Welte pm_sdhcreg = &(host->pm_sdhc_reg); 1243f0bf7f61SHarald Welte addrbase = host->sdhc_mmiobase; 1244f0bf7f61SHarald Welte 1245f0bf7f61SHarald Welte writel(0x0, addrbase + VIA_CRDR_SDINTMASK); 1246f0bf7f61SHarald Welte 1247f0bf7f61SHarald Welte lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 1248f0bf7f61SHarald Welte writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN); 1249f0bf7f61SHarald Welte 1250f0bf7f61SHarald Welte status = readw(addrbase + VIA_CRDR_SDSTATUS); 1251f0bf7f61SHarald Welte status &= VIA_CRDR_SDSTS_W1C_MASK; 1252f0bf7f61SHarald Welte writew(status, addrbase + VIA_CRDR_SDSTATUS); 1253f0bf7f61SHarald Welte 1254f0bf7f61SHarald Welte status = readw(addrbase + VIA_CRDR_SDSTATUS2); 1255f0bf7f61SHarald Welte status |= VIA_CRDR_SDSTS_CFE; 1256f0bf7f61SHarald Welte writew(status, addrbase + VIA_CRDR_SDSTATUS2); 1257f0bf7f61SHarald Welte 1258f0bf7f61SHarald Welte writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL); 1259f0bf7f61SHarald Welte writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG); 1260f0bf7f61SHarald Welte writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK); 1261f0bf7f61SHarald Welte writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO); 1262f0bf7f61SHarald Welte writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL); 1263f0bf7f61SHarald Welte writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL); 1264f0bf7f61SHarald Welte 1265f0bf7f61SHarald Welte via_print_pcictrl(host); 1266f0bf7f61SHarald Welte via_print_sdchc(host); 1267f0bf7f61SHarald Welte } 1268f0bf7f61SHarald Welte 1269f0bf7f61SHarald Welte static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state) 1270f0bf7f61SHarald Welte { 1271f0bf7f61SHarald Welte struct via_crdr_mmc_host *host; 1272f0bf7f61SHarald Welte int ret = 0; 1273f0bf7f61SHarald Welte 1274f0bf7f61SHarald Welte host = pci_get_drvdata(pcidev); 1275f0bf7f61SHarald Welte 1276f0bf7f61SHarald Welte via_save_pcictrlreg(host); 1277f0bf7f61SHarald Welte via_save_sdcreg(host); 1278f0bf7f61SHarald Welte 12791a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 1280f0bf7f61SHarald Welte 1281f0bf7f61SHarald Welte pci_save_state(pcidev); 1282f0bf7f61SHarald Welte pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0); 1283f0bf7f61SHarald Welte pci_disable_device(pcidev); 1284f0bf7f61SHarald Welte pci_set_power_state(pcidev, pci_choose_state(pcidev, state)); 1285f0bf7f61SHarald Welte 1286f0bf7f61SHarald Welte return ret; 1287f0bf7f61SHarald Welte } 1288f0bf7f61SHarald Welte 1289f0bf7f61SHarald Welte static int via_sd_resume(struct pci_dev *pcidev) 1290f0bf7f61SHarald Welte { 1291f0bf7f61SHarald Welte struct via_crdr_mmc_host *sdhost; 1292f0bf7f61SHarald Welte int ret = 0; 1293f0bf7f61SHarald Welte u8 gatt; 1294f0bf7f61SHarald Welte 1295f0bf7f61SHarald Welte sdhost = pci_get_drvdata(pcidev); 1296f0bf7f61SHarald Welte 1297f0bf7f61SHarald Welte gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON; 1298f0bf7f61SHarald Welte if (sdhost->power == MMC_VDD_165_195) 1299f0bf7f61SHarald Welte gatt &= ~VIA_CRDR_PCICLKGATT_3V3; 1300f0bf7f61SHarald Welte else 1301f0bf7f61SHarald Welte gatt |= VIA_CRDR_PCICLKGATT_3V3; 1302f0bf7f61SHarald Welte writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1303f0bf7f61SHarald Welte via_pwron_sleep(sdhost); 1304f0bf7f61SHarald Welte gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 1305f0bf7f61SHarald Welte writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1306f0bf7f61SHarald Welte msleep(3); 1307f0bf7f61SHarald Welte 1308f0bf7f61SHarald Welte msleep(100); 1309f0bf7f61SHarald Welte 1310f0bf7f61SHarald Welte pci_set_power_state(pcidev, PCI_D0); 1311f0bf7f61SHarald Welte pci_restore_state(pcidev); 1312f0bf7f61SHarald Welte ret = pci_enable_device(pcidev); 1313f0bf7f61SHarald Welte if (ret) 1314f0bf7f61SHarald Welte return ret; 1315f0bf7f61SHarald Welte 1316f0bf7f61SHarald Welte via_restore_pcictrlreg(sdhost); 1317f0bf7f61SHarald Welte via_init_sdc_pm(sdhost); 1318f0bf7f61SHarald Welte 1319f0bf7f61SHarald Welte ret = mmc_resume_host(sdhost->mmc); 1320f0bf7f61SHarald Welte 1321f0bf7f61SHarald Welte return ret; 1322f0bf7f61SHarald Welte } 1323f0bf7f61SHarald Welte 1324f0bf7f61SHarald Welte #else /* CONFIG_PM */ 1325f0bf7f61SHarald Welte 1326f0bf7f61SHarald Welte #define via_sd_suspend NULL 1327f0bf7f61SHarald Welte #define via_sd_resume NULL 1328f0bf7f61SHarald Welte 1329f0bf7f61SHarald Welte #endif /* CONFIG_PM */ 1330f0bf7f61SHarald Welte 1331f0bf7f61SHarald Welte static struct pci_driver via_sd_driver = { 1332f0bf7f61SHarald Welte .name = DRV_NAME, 1333f0bf7f61SHarald Welte .id_table = via_ids, 1334f0bf7f61SHarald Welte .probe = via_sd_probe, 1335f0bf7f61SHarald Welte .remove = __devexit_p(via_sd_remove), 1336f0bf7f61SHarald Welte .suspend = via_sd_suspend, 1337f0bf7f61SHarald Welte .resume = via_sd_resume, 1338f0bf7f61SHarald Welte }; 1339f0bf7f61SHarald Welte 13400d4de8f5SSachin Kamat module_pci_driver(via_sd_driver); 1341f0bf7f61SHarald Welte 1342f0bf7f61SHarald Welte MODULE_LICENSE("GPL"); 1343f0bf7f61SHarald Welte MODULE_AUTHOR("VIA Technologies Inc."); 1344f0bf7f61SHarald Welte MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver"); 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