1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2017-2018 Socionext Inc. 4 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/mfd/tmio.h> 12 #include <linux/mmc/host.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 20 #include "tmio_mmc.h" 21 22 #define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16) 23 #define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10) 24 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop 25 #define UNIPHIER_SD_CC_EXT_MODE 0x1b0 26 #define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1) 27 #define UNIPHIER_SD_HOST_MODE 0x1c8 28 #define UNIPHIER_SD_VOLT 0x1e4 29 #define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0) 30 #define UNIPHIER_SD_VOLT_OFF 0 31 #define UNIPHIER_SD_VOLT_330 1 // 3.3V signal 32 #define UNIPHIER_SD_VOLT_180 2 // 1.8V signal 33 #define UNIPHIER_SD_DMA_MODE 0x410 34 #define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16) 35 #define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0 36 #define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1 37 #define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4) 38 #define UNIPHIER_SD_DMA_MODE_WIDTH_8 0 39 #define UNIPHIER_SD_DMA_MODE_WIDTH_16 1 40 #define UNIPHIER_SD_DMA_MODE_WIDTH_32 2 41 #define UNIPHIER_SD_DMA_MODE_WIDTH_64 3 42 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed 43 #define UNIPHIER_SD_DMA_CTL 0x414 44 #define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared) 45 #define UNIPHIER_SD_DMA_RST 0x418 46 #define UNIPHIER_SD_DMA_RST_CH1 BIT(9) 47 #define UNIPHIER_SD_DMA_RST_CH0 BIT(8) 48 #define UNIPHIER_SD_DMA_ADDR_L 0x440 49 #define UNIPHIER_SD_DMA_ADDR_H 0x444 50 51 /* 52 * IP is extended to support various features: built-in DMA engine, 53 * 1/1024 divisor, etc. 54 */ 55 #define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0) 56 /* RX channel of the built-in DMA controller is broken (Pro5) */ 57 #define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1) 58 59 struct uniphier_sd_priv { 60 struct tmio_mmc_data tmio_data; 61 struct pinctrl *pinctrl; 62 struct pinctrl_state *pinstate_default; 63 struct pinctrl_state *pinstate_uhs; 64 struct clk *clk; 65 struct reset_control *rst; 66 struct reset_control *rst_br; 67 struct reset_control *rst_hw; 68 struct dma_chan *chan; 69 enum dma_data_direction dma_dir; 70 unsigned long clk_rate; 71 unsigned long caps; 72 }; 73 74 static void *uniphier_sd_priv(struct tmio_mmc_host *host) 75 { 76 return container_of(host->pdata, struct uniphier_sd_priv, tmio_data); 77 } 78 79 static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable) 80 { 81 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 82 } 83 84 /* external DMA engine */ 85 static void uniphier_sd_external_dma_issue(unsigned long arg) 86 { 87 struct tmio_mmc_host *host = (void *)arg; 88 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 89 90 uniphier_sd_dma_endisable(host, 1); 91 dma_async_issue_pending(priv->chan); 92 } 93 94 static void uniphier_sd_external_dma_callback(void *param, 95 const struct dmaengine_result *result) 96 { 97 struct tmio_mmc_host *host = param; 98 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 99 unsigned long flags; 100 101 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 102 priv->dma_dir); 103 104 spin_lock_irqsave(&host->lock, flags); 105 106 if (result->result == DMA_TRANS_NOERROR) { 107 /* 108 * When the external DMA engine is enabled, strangely enough, 109 * the DATAEND flag can be asserted even if the DMA engine has 110 * not been kicked yet. Enable the TMIO_STAT_DATAEND irq only 111 * after we make sure the DMA engine finishes the transfer, 112 * hence, in this callback. 113 */ 114 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 115 } else { 116 host->data->error = -ETIMEDOUT; 117 tmio_mmc_do_data_irq(host); 118 } 119 120 spin_unlock_irqrestore(&host->lock, flags); 121 } 122 123 static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host, 124 struct mmc_data *data) 125 { 126 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 127 enum dma_transfer_direction dma_tx_dir; 128 struct dma_async_tx_descriptor *desc; 129 dma_cookie_t cookie; 130 int sg_len; 131 132 if (!priv->chan) 133 goto force_pio; 134 135 if (data->flags & MMC_DATA_READ) { 136 priv->dma_dir = DMA_FROM_DEVICE; 137 dma_tx_dir = DMA_DEV_TO_MEM; 138 } else { 139 priv->dma_dir = DMA_TO_DEVICE; 140 dma_tx_dir = DMA_MEM_TO_DEV; 141 } 142 143 sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 144 priv->dma_dir); 145 if (sg_len == 0) 146 goto force_pio; 147 148 desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len, 149 dma_tx_dir, DMA_CTRL_ACK); 150 if (!desc) 151 goto unmap_sg; 152 153 desc->callback_result = uniphier_sd_external_dma_callback; 154 desc->callback_param = host; 155 156 cookie = dmaengine_submit(desc); 157 if (cookie < 0) 158 goto unmap_sg; 159 160 host->dma_on = true; 161 162 return; 163 164 unmap_sg: 165 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 166 priv->dma_dir); 167 force_pio: 168 uniphier_sd_dma_endisable(host, 0); 169 } 170 171 static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host, 172 bool enable) 173 { 174 } 175 176 static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host, 177 struct tmio_mmc_data *pdata) 178 { 179 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 180 struct dma_chan *chan; 181 182 chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx"); 183 if (IS_ERR(chan)) { 184 dev_warn(mmc_dev(host->mmc), 185 "failed to request DMA channel. falling back to PIO\n"); 186 return; /* just use PIO even for -EPROBE_DEFER */ 187 } 188 189 /* this driver uses a single channel for both RX an TX */ 190 priv->chan = chan; 191 host->chan_rx = chan; 192 host->chan_tx = chan; 193 194 tasklet_init(&host->dma_issue, uniphier_sd_external_dma_issue, 195 (unsigned long)host); 196 } 197 198 static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host) 199 { 200 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 201 202 if (priv->chan) 203 dma_release_channel(priv->chan); 204 } 205 206 static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host) 207 { 208 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 209 210 uniphier_sd_dma_endisable(host, 0); 211 212 if (priv->chan) 213 dmaengine_terminate_sync(priv->chan); 214 } 215 216 static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host) 217 { 218 uniphier_sd_dma_endisable(host, 0); 219 220 tmio_mmc_do_data_irq(host); 221 } 222 223 static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = { 224 .start = uniphier_sd_external_dma_start, 225 .enable = uniphier_sd_external_dma_enable, 226 .request = uniphier_sd_external_dma_request, 227 .release = uniphier_sd_external_dma_release, 228 .abort = uniphier_sd_external_dma_abort, 229 .dataend = uniphier_sd_external_dma_dataend, 230 }; 231 232 static void uniphier_sd_internal_dma_issue(unsigned long arg) 233 { 234 struct tmio_mmc_host *host = (void *)arg; 235 unsigned long flags; 236 237 spin_lock_irqsave(&host->lock, flags); 238 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 239 spin_unlock_irqrestore(&host->lock, flags); 240 241 uniphier_sd_dma_endisable(host, 1); 242 writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL); 243 } 244 245 static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host, 246 struct mmc_data *data) 247 { 248 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 249 struct scatterlist *sg = host->sg_ptr; 250 dma_addr_t dma_addr; 251 unsigned int dma_mode_dir; 252 u32 dma_mode; 253 int sg_len; 254 255 if (WARN_ON(host->sg_len != 1)) 256 goto force_pio; 257 258 if (!IS_ALIGNED(sg->offset, 8)) 259 goto force_pio; 260 261 if (data->flags & MMC_DATA_READ) { 262 priv->dma_dir = DMA_FROM_DEVICE; 263 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV; 264 } else { 265 priv->dma_dir = DMA_TO_DEVICE; 266 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV; 267 } 268 269 sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir); 270 if (sg_len == 0) 271 goto force_pio; 272 273 dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir); 274 dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK, 275 UNIPHIER_SD_DMA_MODE_WIDTH_64); 276 dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC; 277 278 writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE); 279 280 dma_addr = sg_dma_address(data->sg); 281 writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L); 282 writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H); 283 284 host->dma_on = true; 285 286 return; 287 force_pio: 288 uniphier_sd_dma_endisable(host, 0); 289 } 290 291 static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host, 292 bool enable) 293 { 294 } 295 296 static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host, 297 struct tmio_mmc_data *pdata) 298 { 299 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 300 301 /* 302 * Due to a hardware bug, Pro5 cannot use DMA for RX. 303 * We can still use DMA for TX, but PIO for RX. 304 */ 305 if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX)) 306 host->chan_rx = (void *)0xdeadbeaf; 307 308 host->chan_tx = (void *)0xdeadbeaf; 309 310 tasklet_init(&host->dma_issue, uniphier_sd_internal_dma_issue, 311 (unsigned long)host); 312 } 313 314 static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host) 315 { 316 /* Each value is set to zero to assume "disabling" each DMA */ 317 host->chan_rx = NULL; 318 host->chan_tx = NULL; 319 } 320 321 static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host) 322 { 323 u32 tmp; 324 325 uniphier_sd_dma_endisable(host, 0); 326 327 tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST); 328 tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0); 329 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); 330 331 tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0; 332 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); 333 } 334 335 static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host) 336 { 337 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 338 339 uniphier_sd_dma_endisable(host, 0); 340 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir); 341 342 tmio_mmc_do_data_irq(host); 343 } 344 345 static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = { 346 .start = uniphier_sd_internal_dma_start, 347 .enable = uniphier_sd_internal_dma_enable, 348 .request = uniphier_sd_internal_dma_request, 349 .release = uniphier_sd_internal_dma_release, 350 .abort = uniphier_sd_internal_dma_abort, 351 .dataend = uniphier_sd_internal_dma_dataend, 352 }; 353 354 static int uniphier_sd_clk_enable(struct tmio_mmc_host *host) 355 { 356 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 357 struct mmc_host *mmc = host->mmc; 358 int ret; 359 360 ret = clk_prepare_enable(priv->clk); 361 if (ret) 362 return ret; 363 364 ret = clk_set_rate(priv->clk, ULONG_MAX); 365 if (ret) 366 goto disable_clk; 367 368 priv->clk_rate = clk_get_rate(priv->clk); 369 370 /* If max-frequency property is set, use it. */ 371 if (!mmc->f_max) 372 mmc->f_max = priv->clk_rate; 373 374 /* 375 * 1/512 is the finest divisor in the original IP. Newer versions 376 * also supports 1/1024 divisor. (UniPhier-specific extension) 377 */ 378 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 379 mmc->f_min = priv->clk_rate / 1024; 380 else 381 mmc->f_min = priv->clk_rate / 512; 382 383 ret = reset_control_deassert(priv->rst); 384 if (ret) 385 goto disable_clk; 386 387 ret = reset_control_deassert(priv->rst_br); 388 if (ret) 389 goto assert_rst; 390 391 return 0; 392 393 assert_rst: 394 reset_control_assert(priv->rst); 395 disable_clk: 396 clk_disable_unprepare(priv->clk); 397 398 return ret; 399 } 400 401 static void uniphier_sd_clk_disable(struct tmio_mmc_host *host) 402 { 403 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 404 405 reset_control_assert(priv->rst_br); 406 reset_control_assert(priv->rst); 407 clk_disable_unprepare(priv->clk); 408 } 409 410 static void uniphier_sd_hw_reset(struct tmio_mmc_host *host) 411 { 412 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 413 414 reset_control_assert(priv->rst_hw); 415 /* For eMMC, minimum is 1us but give it 9us for good measure */ 416 udelay(9); 417 reset_control_deassert(priv->rst_hw); 418 /* For eMMC, minimum is 200us but give it 300us for good measure */ 419 usleep_range(300, 1000); 420 } 421 422 static void uniphier_sd_set_clock(struct tmio_mmc_host *host, 423 unsigned int clock) 424 { 425 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 426 unsigned long divisor; 427 u32 tmp; 428 429 tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 430 431 /* stop the clock before changing its rate to avoid a glitch signal */ 432 tmp &= ~CLK_CTL_SCLKEN; 433 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 434 435 if (clock == 0) 436 return; 437 438 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024; 439 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1; 440 tmp &= ~CLK_CTL_DIV_MASK; 441 442 divisor = priv->clk_rate / clock; 443 444 /* 445 * In the original IP, bit[7:0] represents the divisor. 446 * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 447 * 448 * The IP does not define a way to achieve 1/1. For UniPhier variants, 449 * bit10 is used for 1/1. Newer versions of UniPhier variants use 450 * bit16 for 1/1024. 451 */ 452 if (divisor <= 1) 453 tmp |= UNIPHIER_SD_CLK_CTL_DIV1; 454 else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512) 455 tmp |= UNIPHIER_SD_CLK_CTL_DIV1024; 456 else 457 tmp |= roundup_pow_of_two(divisor) >> 2; 458 459 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 460 461 tmp |= CLK_CTL_SCLKEN; 462 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 463 } 464 465 static void uniphier_sd_host_init(struct tmio_mmc_host *host) 466 { 467 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 468 u32 val; 469 470 /* 471 * Connected to 32bit AXI. 472 * This register holds settings for SoC-specific internal bus 473 * connection. What is worse, the register spec was changed, 474 * breaking the backward compatibility. Write an appropriate 475 * value depending on a flag associated with a compatible string. 476 */ 477 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 478 val = 0x00000101; 479 else 480 val = 0x00000000; 481 482 writel(val, host->ctl + UNIPHIER_SD_HOST_MODE); 483 484 val = 0; 485 /* 486 * If supported, the controller can automatically 487 * enable/disable the clock line to the card. 488 */ 489 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 490 val |= UNIPHIER_SD_CLKCTL_OFFEN; 491 492 writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 493 } 494 495 static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc, 496 struct mmc_ios *ios) 497 { 498 struct tmio_mmc_host *host = mmc_priv(mmc); 499 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 500 struct pinctrl_state *pinstate; 501 u32 val, tmp; 502 503 switch (ios->signal_voltage) { 504 case MMC_SIGNAL_VOLTAGE_330: 505 val = UNIPHIER_SD_VOLT_330; 506 pinstate = priv->pinstate_default; 507 break; 508 case MMC_SIGNAL_VOLTAGE_180: 509 val = UNIPHIER_SD_VOLT_180; 510 pinstate = priv->pinstate_uhs; 511 break; 512 default: 513 return -ENOTSUPP; 514 } 515 516 tmp = readl(host->ctl + UNIPHIER_SD_VOLT); 517 tmp &= ~UNIPHIER_SD_VOLT_MASK; 518 tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val); 519 writel(tmp, host->ctl + UNIPHIER_SD_VOLT); 520 521 pinctrl_select_state(priv->pinctrl, pinstate); 522 523 return 0; 524 } 525 526 static int uniphier_sd_uhs_init(struct tmio_mmc_host *host, 527 struct uniphier_sd_priv *priv) 528 { 529 priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc)); 530 if (IS_ERR(priv->pinctrl)) 531 return PTR_ERR(priv->pinctrl); 532 533 priv->pinstate_default = pinctrl_lookup_state(priv->pinctrl, 534 PINCTRL_STATE_DEFAULT); 535 if (IS_ERR(priv->pinstate_default)) 536 return PTR_ERR(priv->pinstate_default); 537 538 priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs"); 539 if (IS_ERR(priv->pinstate_uhs)) 540 return PTR_ERR(priv->pinstate_uhs); 541 542 host->ops.start_signal_voltage_switch = 543 uniphier_sd_start_signal_voltage_switch; 544 545 return 0; 546 } 547 548 static int uniphier_sd_probe(struct platform_device *pdev) 549 { 550 struct device *dev = &pdev->dev; 551 struct uniphier_sd_priv *priv; 552 struct tmio_mmc_data *tmio_data; 553 struct tmio_mmc_host *host; 554 int irq, ret; 555 556 irq = platform_get_irq(pdev, 0); 557 if (irq < 0) { 558 dev_err(dev, "failed to get IRQ number"); 559 return irq; 560 } 561 562 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 563 if (!priv) 564 return -ENOMEM; 565 566 priv->caps = (unsigned long)of_device_get_match_data(dev); 567 568 priv->clk = devm_clk_get(dev, NULL); 569 if (IS_ERR(priv->clk)) { 570 dev_err(dev, "failed to get clock\n"); 571 return PTR_ERR(priv->clk); 572 } 573 574 priv->rst = devm_reset_control_get_shared(dev, "host"); 575 if (IS_ERR(priv->rst)) { 576 dev_err(dev, "failed to get host reset\n"); 577 return PTR_ERR(priv->rst); 578 } 579 580 /* old version has one more reset */ 581 if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) { 582 priv->rst_br = devm_reset_control_get_shared(dev, "bridge"); 583 if (IS_ERR(priv->rst_br)) { 584 dev_err(dev, "failed to get bridge reset\n"); 585 return PTR_ERR(priv->rst_br); 586 } 587 } 588 589 tmio_data = &priv->tmio_data; 590 tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT; 591 592 host = tmio_mmc_host_alloc(pdev, tmio_data); 593 if (IS_ERR(host)) 594 return PTR_ERR(host); 595 596 if (host->mmc->caps & MMC_CAP_HW_RESET) { 597 priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw"); 598 if (IS_ERR(priv->rst_hw)) { 599 dev_err(dev, "failed to get hw reset\n"); 600 ret = PTR_ERR(priv->rst_hw); 601 goto free_host; 602 } 603 host->hw_reset = uniphier_sd_hw_reset; 604 } 605 606 if (host->mmc->caps & MMC_CAP_UHS) { 607 ret = uniphier_sd_uhs_init(host, priv); 608 if (ret) { 609 dev_warn(dev, 610 "failed to setup UHS (error %d). Disabling UHS.", 611 ret); 612 host->mmc->caps &= ~MMC_CAP_UHS; 613 } 614 } 615 616 ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED, 617 dev_name(dev), host); 618 if (ret) 619 goto free_host; 620 621 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 622 host->dma_ops = &uniphier_sd_internal_dma_ops; 623 else 624 host->dma_ops = &uniphier_sd_external_dma_ops; 625 626 host->bus_shift = 1; 627 host->clk_enable = uniphier_sd_clk_enable; 628 host->clk_disable = uniphier_sd_clk_disable; 629 host->set_clock = uniphier_sd_set_clock; 630 631 ret = uniphier_sd_clk_enable(host); 632 if (ret) 633 goto free_host; 634 635 uniphier_sd_host_init(host); 636 637 tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; 638 if (host->mmc->caps & MMC_CAP_UHS) 639 tmio_data->ocr_mask |= MMC_VDD_165_195; 640 641 tmio_data->max_segs = 1; 642 tmio_data->max_blk_count = U16_MAX; 643 644 ret = tmio_mmc_host_probe(host); 645 if (ret) 646 goto free_host; 647 648 return 0; 649 650 free_host: 651 tmio_mmc_host_free(host); 652 653 return ret; 654 } 655 656 static int uniphier_sd_remove(struct platform_device *pdev) 657 { 658 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 659 660 tmio_mmc_host_remove(host); 661 uniphier_sd_clk_disable(host); 662 663 return 0; 664 } 665 666 static const struct of_device_id uniphier_sd_match[] = { 667 { 668 .compatible = "socionext,uniphier-sd-v2.91", 669 }, 670 { 671 .compatible = "socionext,uniphier-sd-v3.1", 672 .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP | 673 UNIPHIER_SD_CAP_BROKEN_DMA_RX), 674 }, 675 { 676 .compatible = "socionext,uniphier-sd-v3.1.1", 677 .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP, 678 }, 679 { /* sentinel */ } 680 }; 681 MODULE_DEVICE_TABLE(of, uniphier_sd_match); 682 683 static struct platform_driver uniphier_sd_driver = { 684 .probe = uniphier_sd_probe, 685 .remove = uniphier_sd_remove, 686 .driver = { 687 .name = "uniphier-sd", 688 .of_match_table = uniphier_sd_match, 689 }, 690 }; 691 module_platform_driver(uniphier_sd_driver); 692 693 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 694 MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver"); 695 MODULE_LICENSE("GPL v2"); 696