1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2017-2018 Socionext Inc. 4 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/mfd/tmio.h> 13 #include <linux/mmc/host.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 22 #include "tmio_mmc.h" 23 24 #define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16) 25 #define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10) 26 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop 27 #define UNIPHIER_SD_CC_EXT_MODE 0x1b0 28 #define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1) 29 #define UNIPHIER_SD_HOST_MODE 0x1c8 30 #define UNIPHIER_SD_VOLT 0x1e4 31 #define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0) 32 #define UNIPHIER_SD_VOLT_OFF 0 33 #define UNIPHIER_SD_VOLT_330 1 // 3.3V signal 34 #define UNIPHIER_SD_VOLT_180 2 // 1.8V signal 35 #define UNIPHIER_SD_DMA_MODE 0x410 36 #define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16) 37 #define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0 38 #define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1 39 #define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4) 40 #define UNIPHIER_SD_DMA_MODE_WIDTH_8 0 41 #define UNIPHIER_SD_DMA_MODE_WIDTH_16 1 42 #define UNIPHIER_SD_DMA_MODE_WIDTH_32 2 43 #define UNIPHIER_SD_DMA_MODE_WIDTH_64 3 44 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed 45 #define UNIPHIER_SD_DMA_CTL 0x414 46 #define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared) 47 #define UNIPHIER_SD_DMA_RST 0x418 48 #define UNIPHIER_SD_DMA_RST_CH1 BIT(9) 49 #define UNIPHIER_SD_DMA_RST_CH0 BIT(8) 50 #define UNIPHIER_SD_DMA_ADDR_L 0x440 51 #define UNIPHIER_SD_DMA_ADDR_H 0x444 52 53 /* SD control */ 54 #define UNIPHIER_SDCTRL_CHOFFSET 0x200 55 #define UNIPHIER_SDCTRL_MODE 0x30 56 #define UNIPHIER_SDCTRL_MODE_UHS1MOD BIT(15) 57 #define UNIPHIER_SDCTRL_MODE_SDRSEL BIT(14) 58 59 /* 60 * IP is extended to support various features: built-in DMA engine, 61 * 1/1024 divisor, etc. 62 */ 63 #define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0) 64 /* RX channel of the built-in DMA controller is broken (Pro5) */ 65 #define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1) 66 67 struct uniphier_sd_priv { 68 struct tmio_mmc_data tmio_data; 69 struct pinctrl *pinctrl; 70 struct pinctrl_state *pinstate_uhs; 71 struct clk *clk; 72 struct reset_control *rst; 73 struct reset_control *rst_br; 74 struct reset_control *rst_hw; 75 struct dma_chan *chan; 76 enum dma_data_direction dma_dir; 77 struct regmap *sdctrl_regmap; 78 u32 sdctrl_ch; 79 unsigned long clk_rate; 80 unsigned long caps; 81 }; 82 83 static void *uniphier_sd_priv(struct tmio_mmc_host *host) 84 { 85 return container_of(host->pdata, struct uniphier_sd_priv, tmio_data); 86 } 87 88 static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable) 89 { 90 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 91 } 92 93 /* external DMA engine */ 94 static void uniphier_sd_external_dma_issue(struct tasklet_struct *t) 95 { 96 struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue); 97 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 98 99 uniphier_sd_dma_endisable(host, 1); 100 dma_async_issue_pending(priv->chan); 101 } 102 103 static void uniphier_sd_external_dma_callback(void *param, 104 const struct dmaengine_result *result) 105 { 106 struct tmio_mmc_host *host = param; 107 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 108 unsigned long flags; 109 110 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 111 priv->dma_dir); 112 113 spin_lock_irqsave(&host->lock, flags); 114 115 if (result->result == DMA_TRANS_NOERROR) { 116 /* 117 * When the external DMA engine is enabled, strangely enough, 118 * the DATAEND flag can be asserted even if the DMA engine has 119 * not been kicked yet. Enable the TMIO_STAT_DATAEND irq only 120 * after we make sure the DMA engine finishes the transfer, 121 * hence, in this callback. 122 */ 123 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 124 } else { 125 host->data->error = -ETIMEDOUT; 126 tmio_mmc_do_data_irq(host); 127 } 128 129 spin_unlock_irqrestore(&host->lock, flags); 130 } 131 132 static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host, 133 struct mmc_data *data) 134 { 135 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 136 enum dma_transfer_direction dma_tx_dir; 137 struct dma_async_tx_descriptor *desc; 138 dma_cookie_t cookie; 139 int sg_len; 140 141 if (!priv->chan) 142 goto force_pio; 143 144 if (data->flags & MMC_DATA_READ) { 145 priv->dma_dir = DMA_FROM_DEVICE; 146 dma_tx_dir = DMA_DEV_TO_MEM; 147 } else { 148 priv->dma_dir = DMA_TO_DEVICE; 149 dma_tx_dir = DMA_MEM_TO_DEV; 150 } 151 152 sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 153 priv->dma_dir); 154 if (sg_len == 0) 155 goto force_pio; 156 157 desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len, 158 dma_tx_dir, DMA_CTRL_ACK); 159 if (!desc) 160 goto unmap_sg; 161 162 desc->callback_result = uniphier_sd_external_dma_callback; 163 desc->callback_param = host; 164 165 cookie = dmaengine_submit(desc); 166 if (cookie < 0) 167 goto unmap_sg; 168 169 host->dma_on = true; 170 171 return; 172 173 unmap_sg: 174 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 175 priv->dma_dir); 176 force_pio: 177 uniphier_sd_dma_endisable(host, 0); 178 } 179 180 static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host, 181 bool enable) 182 { 183 } 184 185 static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host, 186 struct tmio_mmc_data *pdata) 187 { 188 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 189 struct dma_chan *chan; 190 191 chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx"); 192 if (IS_ERR(chan)) { 193 dev_warn(mmc_dev(host->mmc), 194 "failed to request DMA channel. falling back to PIO\n"); 195 return; /* just use PIO even for -EPROBE_DEFER */ 196 } 197 198 /* this driver uses a single channel for both RX an TX */ 199 priv->chan = chan; 200 host->chan_rx = chan; 201 host->chan_tx = chan; 202 203 tasklet_setup(&host->dma_issue, uniphier_sd_external_dma_issue); 204 } 205 206 static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host) 207 { 208 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 209 210 if (priv->chan) 211 dma_release_channel(priv->chan); 212 } 213 214 static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host) 215 { 216 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 217 218 uniphier_sd_dma_endisable(host, 0); 219 220 if (priv->chan) 221 dmaengine_terminate_sync(priv->chan); 222 } 223 224 static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host) 225 { 226 uniphier_sd_dma_endisable(host, 0); 227 228 tmio_mmc_do_data_irq(host); 229 } 230 231 static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = { 232 .start = uniphier_sd_external_dma_start, 233 .enable = uniphier_sd_external_dma_enable, 234 .request = uniphier_sd_external_dma_request, 235 .release = uniphier_sd_external_dma_release, 236 .abort = uniphier_sd_external_dma_abort, 237 .dataend = uniphier_sd_external_dma_dataend, 238 }; 239 240 static void uniphier_sd_internal_dma_issue(struct tasklet_struct *t) 241 { 242 struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue); 243 unsigned long flags; 244 245 spin_lock_irqsave(&host->lock, flags); 246 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 247 spin_unlock_irqrestore(&host->lock, flags); 248 249 uniphier_sd_dma_endisable(host, 1); 250 writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL); 251 } 252 253 static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host, 254 struct mmc_data *data) 255 { 256 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 257 struct scatterlist *sg = host->sg_ptr; 258 dma_addr_t dma_addr; 259 unsigned int dma_mode_dir; 260 u32 dma_mode; 261 int sg_len; 262 263 if ((data->flags & MMC_DATA_READ) && !host->chan_rx) 264 goto force_pio; 265 266 if (WARN_ON(host->sg_len != 1)) 267 goto force_pio; 268 269 if (!IS_ALIGNED(sg->offset, 8)) 270 goto force_pio; 271 272 if (data->flags & MMC_DATA_READ) { 273 priv->dma_dir = DMA_FROM_DEVICE; 274 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV; 275 } else { 276 priv->dma_dir = DMA_TO_DEVICE; 277 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV; 278 } 279 280 sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir); 281 if (sg_len == 0) 282 goto force_pio; 283 284 dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir); 285 dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK, 286 UNIPHIER_SD_DMA_MODE_WIDTH_64); 287 dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC; 288 289 writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE); 290 291 dma_addr = sg_dma_address(data->sg); 292 writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L); 293 writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H); 294 295 host->dma_on = true; 296 297 return; 298 force_pio: 299 uniphier_sd_dma_endisable(host, 0); 300 } 301 302 static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host, 303 bool enable) 304 { 305 } 306 307 static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host, 308 struct tmio_mmc_data *pdata) 309 { 310 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 311 312 /* 313 * Due to a hardware bug, Pro5 cannot use DMA for RX. 314 * We can still use DMA for TX, but PIO for RX. 315 */ 316 if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX)) 317 host->chan_rx = (void *)0xdeadbeaf; 318 319 host->chan_tx = (void *)0xdeadbeaf; 320 321 tasklet_setup(&host->dma_issue, uniphier_sd_internal_dma_issue); 322 } 323 324 static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host) 325 { 326 /* Each value is set to zero to assume "disabling" each DMA */ 327 host->chan_rx = NULL; 328 host->chan_tx = NULL; 329 } 330 331 static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host) 332 { 333 u32 tmp; 334 335 uniphier_sd_dma_endisable(host, 0); 336 337 tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST); 338 tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0); 339 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); 340 341 tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0; 342 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); 343 } 344 345 static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host) 346 { 347 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 348 349 uniphier_sd_dma_endisable(host, 0); 350 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir); 351 352 tmio_mmc_do_data_irq(host); 353 } 354 355 static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = { 356 .start = uniphier_sd_internal_dma_start, 357 .enable = uniphier_sd_internal_dma_enable, 358 .request = uniphier_sd_internal_dma_request, 359 .release = uniphier_sd_internal_dma_release, 360 .abort = uniphier_sd_internal_dma_abort, 361 .dataend = uniphier_sd_internal_dma_dataend, 362 }; 363 364 static int uniphier_sd_clk_enable(struct tmio_mmc_host *host) 365 { 366 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 367 struct mmc_host *mmc = host->mmc; 368 int ret; 369 370 ret = clk_prepare_enable(priv->clk); 371 if (ret) 372 return ret; 373 374 ret = clk_set_rate(priv->clk, ULONG_MAX); 375 if (ret) 376 goto disable_clk; 377 378 priv->clk_rate = clk_get_rate(priv->clk); 379 380 /* If max-frequency property is set, use it. */ 381 if (!mmc->f_max) 382 mmc->f_max = priv->clk_rate; 383 384 /* 385 * 1/512 is the finest divisor in the original IP. Newer versions 386 * also supports 1/1024 divisor. (UniPhier-specific extension) 387 */ 388 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 389 mmc->f_min = priv->clk_rate / 1024; 390 else 391 mmc->f_min = priv->clk_rate / 512; 392 393 ret = reset_control_deassert(priv->rst); 394 if (ret) 395 goto disable_clk; 396 397 ret = reset_control_deassert(priv->rst_br); 398 if (ret) 399 goto assert_rst; 400 401 return 0; 402 403 assert_rst: 404 reset_control_assert(priv->rst); 405 disable_clk: 406 clk_disable_unprepare(priv->clk); 407 408 return ret; 409 } 410 411 static void uniphier_sd_clk_disable(struct tmio_mmc_host *host) 412 { 413 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 414 415 reset_control_assert(priv->rst_br); 416 reset_control_assert(priv->rst); 417 clk_disable_unprepare(priv->clk); 418 } 419 420 static void uniphier_sd_hw_reset(struct mmc_host *mmc) 421 { 422 struct tmio_mmc_host *host = mmc_priv(mmc); 423 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 424 425 reset_control_assert(priv->rst_hw); 426 /* For eMMC, minimum is 1us but give it 9us for good measure */ 427 udelay(9); 428 reset_control_deassert(priv->rst_hw); 429 /* For eMMC, minimum is 200us but give it 300us for good measure */ 430 usleep_range(300, 1000); 431 } 432 433 static void uniphier_sd_speed_switch(struct tmio_mmc_host *host) 434 { 435 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 436 unsigned int offset; 437 u32 val = 0; 438 439 if (!(host->mmc->caps & MMC_CAP_UHS)) 440 return; 441 442 if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR50 || 443 host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) 444 val = UNIPHIER_SDCTRL_MODE_SDRSEL; 445 446 offset = UNIPHIER_SDCTRL_CHOFFSET * priv->sdctrl_ch 447 + UNIPHIER_SDCTRL_MODE; 448 regmap_write_bits(priv->sdctrl_regmap, offset, 449 UNIPHIER_SDCTRL_MODE_SDRSEL, val); 450 } 451 452 static void uniphier_sd_uhs_enable(struct tmio_mmc_host *host, bool uhs_en) 453 { 454 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 455 unsigned int offset; 456 u32 val; 457 458 if (!(host->mmc->caps & MMC_CAP_UHS)) 459 return; 460 461 val = (uhs_en) ? UNIPHIER_SDCTRL_MODE_UHS1MOD : 0; 462 463 offset = UNIPHIER_SDCTRL_CHOFFSET * priv->sdctrl_ch 464 + UNIPHIER_SDCTRL_MODE; 465 regmap_write_bits(priv->sdctrl_regmap, offset, 466 UNIPHIER_SDCTRL_MODE_UHS1MOD, val); 467 } 468 469 static void uniphier_sd_set_clock(struct tmio_mmc_host *host, 470 unsigned int clock) 471 { 472 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 473 unsigned long divisor; 474 u32 tmp; 475 476 tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 477 478 /* stop the clock before changing its rate to avoid a glitch signal */ 479 tmp &= ~CLK_CTL_SCLKEN; 480 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 481 482 uniphier_sd_speed_switch(host); 483 484 if (clock == 0) 485 return; 486 487 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024; 488 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1; 489 tmp &= ~CLK_CTL_DIV_MASK; 490 491 divisor = priv->clk_rate / clock; 492 493 /* 494 * In the original IP, bit[7:0] represents the divisor. 495 * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 496 * 497 * The IP does not define a way to achieve 1/1. For UniPhier variants, 498 * bit10 is used for 1/1. Newer versions of UniPhier variants use 499 * bit16 for 1/1024. 500 */ 501 if (divisor <= 1) 502 tmp |= UNIPHIER_SD_CLK_CTL_DIV1; 503 else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512) 504 tmp |= UNIPHIER_SD_CLK_CTL_DIV1024; 505 else 506 tmp |= roundup_pow_of_two(divisor) >> 2; 507 508 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 509 510 tmp |= CLK_CTL_SCLKEN; 511 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 512 } 513 514 static void uniphier_sd_host_init(struct tmio_mmc_host *host) 515 { 516 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 517 u32 val; 518 519 /* 520 * Connected to 32bit AXI. 521 * This register holds settings for SoC-specific internal bus 522 * connection. What is worse, the register spec was changed, 523 * breaking the backward compatibility. Write an appropriate 524 * value depending on a flag associated with a compatible string. 525 */ 526 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 527 val = 0x00000101; 528 else 529 val = 0x00000000; 530 531 writel(val, host->ctl + UNIPHIER_SD_HOST_MODE); 532 533 val = 0; 534 /* 535 * If supported, the controller can automatically 536 * enable/disable the clock line to the card. 537 */ 538 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 539 val |= UNIPHIER_SD_CLKCTL_OFFEN; 540 541 writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 542 } 543 544 static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc, 545 struct mmc_ios *ios) 546 { 547 struct tmio_mmc_host *host = mmc_priv(mmc); 548 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 549 struct pinctrl_state *pinstate = NULL; 550 u32 val, tmp; 551 bool uhs_en; 552 553 switch (ios->signal_voltage) { 554 case MMC_SIGNAL_VOLTAGE_330: 555 val = UNIPHIER_SD_VOLT_330; 556 uhs_en = false; 557 break; 558 case MMC_SIGNAL_VOLTAGE_180: 559 val = UNIPHIER_SD_VOLT_180; 560 pinstate = priv->pinstate_uhs; 561 uhs_en = true; 562 break; 563 default: 564 return -ENOTSUPP; 565 } 566 567 tmp = readl(host->ctl + UNIPHIER_SD_VOLT); 568 tmp &= ~UNIPHIER_SD_VOLT_MASK; 569 tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val); 570 writel(tmp, host->ctl + UNIPHIER_SD_VOLT); 571 572 if (pinstate) 573 pinctrl_select_state(priv->pinctrl, pinstate); 574 else 575 pinctrl_select_default_state(mmc_dev(mmc)); 576 577 uniphier_sd_uhs_enable(host, uhs_en); 578 579 return 0; 580 } 581 582 static int uniphier_sd_uhs_init(struct tmio_mmc_host *host) 583 { 584 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 585 struct device *dev = &host->pdev->dev; 586 struct device_node *np = dev->of_node; 587 struct of_phandle_args args; 588 int ret; 589 590 priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc)); 591 if (IS_ERR(priv->pinctrl)) 592 return PTR_ERR(priv->pinctrl); 593 594 priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs"); 595 if (IS_ERR(priv->pinstate_uhs)) 596 return PTR_ERR(priv->pinstate_uhs); 597 598 ret = of_parse_phandle_with_fixed_args(np, 599 "socionext,syscon-uhs-mode", 600 1, 0, &args); 601 if (ret) { 602 dev_err(dev, "Can't get syscon-uhs-mode property\n"); 603 return ret; 604 } 605 priv->sdctrl_regmap = syscon_node_to_regmap(args.np); 606 of_node_put(args.np); 607 if (IS_ERR(priv->sdctrl_regmap)) { 608 dev_err(dev, "Can't map syscon-uhs-mode\n"); 609 return PTR_ERR(priv->sdctrl_regmap); 610 } 611 priv->sdctrl_ch = args.args[0]; 612 613 return 0; 614 } 615 616 static int uniphier_sd_probe(struct platform_device *pdev) 617 { 618 struct device *dev = &pdev->dev; 619 struct uniphier_sd_priv *priv; 620 struct tmio_mmc_data *tmio_data; 621 struct tmio_mmc_host *host; 622 int irq, ret; 623 624 irq = platform_get_irq(pdev, 0); 625 if (irq < 0) 626 return irq; 627 628 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 629 if (!priv) 630 return -ENOMEM; 631 632 priv->caps = (unsigned long)of_device_get_match_data(dev); 633 634 priv->clk = devm_clk_get(dev, NULL); 635 if (IS_ERR(priv->clk)) { 636 dev_err(dev, "failed to get clock\n"); 637 return PTR_ERR(priv->clk); 638 } 639 640 priv->rst = devm_reset_control_get_shared(dev, "host"); 641 if (IS_ERR(priv->rst)) { 642 dev_err(dev, "failed to get host reset\n"); 643 return PTR_ERR(priv->rst); 644 } 645 646 /* old version has one more reset */ 647 if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) { 648 priv->rst_br = devm_reset_control_get_shared(dev, "bridge"); 649 if (IS_ERR(priv->rst_br)) { 650 dev_err(dev, "failed to get bridge reset\n"); 651 return PTR_ERR(priv->rst_br); 652 } 653 } 654 655 tmio_data = &priv->tmio_data; 656 tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT; 657 tmio_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 658 659 host = tmio_mmc_host_alloc(pdev, tmio_data); 660 if (IS_ERR(host)) 661 return PTR_ERR(host); 662 663 if (host->mmc->caps & MMC_CAP_HW_RESET) { 664 priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw"); 665 if (IS_ERR(priv->rst_hw)) { 666 dev_err(dev, "failed to get hw reset\n"); 667 ret = PTR_ERR(priv->rst_hw); 668 goto free_host; 669 } 670 host->ops.card_hw_reset = uniphier_sd_hw_reset; 671 } 672 673 if (host->mmc->caps & MMC_CAP_UHS) { 674 ret = uniphier_sd_uhs_init(host); 675 if (ret) { 676 dev_warn(dev, 677 "failed to setup UHS (error %d). Disabling UHS.", 678 ret); 679 host->mmc->caps &= ~MMC_CAP_UHS; 680 } else { 681 host->ops.start_signal_voltage_switch = 682 uniphier_sd_start_signal_voltage_switch; 683 } 684 } 685 686 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 687 host->dma_ops = &uniphier_sd_internal_dma_ops; 688 else 689 host->dma_ops = &uniphier_sd_external_dma_ops; 690 691 host->bus_shift = 1; 692 host->clk_enable = uniphier_sd_clk_enable; 693 host->clk_disable = uniphier_sd_clk_disable; 694 host->set_clock = uniphier_sd_set_clock; 695 696 ret = uniphier_sd_clk_enable(host); 697 if (ret) 698 goto free_host; 699 700 uniphier_sd_host_init(host); 701 702 tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; 703 if (host->mmc->caps & MMC_CAP_UHS) 704 tmio_data->ocr_mask |= MMC_VDD_165_195; 705 706 tmio_data->max_segs = 1; 707 tmio_data->max_blk_count = U16_MAX; 708 709 ret = tmio_mmc_host_probe(host); 710 if (ret) 711 goto disable_clk; 712 713 ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED, 714 dev_name(dev), host); 715 if (ret) 716 goto remove_host; 717 718 return 0; 719 720 remove_host: 721 tmio_mmc_host_remove(host); 722 disable_clk: 723 uniphier_sd_clk_disable(host); 724 free_host: 725 tmio_mmc_host_free(host); 726 727 return ret; 728 } 729 730 static int uniphier_sd_remove(struct platform_device *pdev) 731 { 732 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 733 734 tmio_mmc_host_remove(host); 735 uniphier_sd_clk_disable(host); 736 tmio_mmc_host_free(host); 737 738 return 0; 739 } 740 741 static const struct of_device_id uniphier_sd_match[] = { 742 { 743 .compatible = "socionext,uniphier-sd-v2.91", 744 }, 745 { 746 .compatible = "socionext,uniphier-sd-v3.1", 747 .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP | 748 UNIPHIER_SD_CAP_BROKEN_DMA_RX), 749 }, 750 { 751 .compatible = "socionext,uniphier-sd-v3.1.1", 752 .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP, 753 }, 754 { /* sentinel */ } 755 }; 756 MODULE_DEVICE_TABLE(of, uniphier_sd_match); 757 758 static struct platform_driver uniphier_sd_driver = { 759 .probe = uniphier_sd_probe, 760 .remove = uniphier_sd_remove, 761 .driver = { 762 .name = "uniphier-sd", 763 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 764 .of_match_table = uniphier_sd_match, 765 }, 766 }; 767 module_platform_driver(uniphier_sd_driver); 768 769 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 770 MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver"); 771 MODULE_LICENSE("GPL v2"); 772