1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2017-2018 Socionext Inc. 4 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/mfd/tmio.h> 13 #include <linux/mmc/host.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 22 #include "tmio_mmc.h" 23 24 #define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16) 25 #define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10) 26 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop 27 #define UNIPHIER_SD_CC_EXT_MODE 0x1b0 28 #define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1) 29 #define UNIPHIER_SD_HOST_MODE 0x1c8 30 #define UNIPHIER_SD_VOLT 0x1e4 31 #define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0) 32 #define UNIPHIER_SD_VOLT_OFF 0 33 #define UNIPHIER_SD_VOLT_330 1 // 3.3V signal 34 #define UNIPHIER_SD_VOLT_180 2 // 1.8V signal 35 #define UNIPHIER_SD_DMA_MODE 0x410 36 #define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16) 37 #define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0 38 #define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1 39 #define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4) 40 #define UNIPHIER_SD_DMA_MODE_WIDTH_8 0 41 #define UNIPHIER_SD_DMA_MODE_WIDTH_16 1 42 #define UNIPHIER_SD_DMA_MODE_WIDTH_32 2 43 #define UNIPHIER_SD_DMA_MODE_WIDTH_64 3 44 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed 45 #define UNIPHIER_SD_DMA_CTL 0x414 46 #define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared) 47 #define UNIPHIER_SD_DMA_RST 0x418 48 #define UNIPHIER_SD_DMA_RST_CH1 BIT(9) 49 #define UNIPHIER_SD_DMA_RST_CH0 BIT(8) 50 #define UNIPHIER_SD_DMA_ADDR_L 0x440 51 #define UNIPHIER_SD_DMA_ADDR_H 0x444 52 53 /* SD control */ 54 #define UNIPHIER_SDCTRL_CHOFFSET 0x200 55 #define UNIPHIER_SDCTRL_MODE 0x30 56 #define UNIPHIER_SDCTRL_MODE_UHS1MOD BIT(15) 57 58 /* 59 * IP is extended to support various features: built-in DMA engine, 60 * 1/1024 divisor, etc. 61 */ 62 #define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0) 63 /* RX channel of the built-in DMA controller is broken (Pro5) */ 64 #define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1) 65 66 struct uniphier_sd_priv { 67 struct tmio_mmc_data tmio_data; 68 struct pinctrl *pinctrl; 69 struct pinctrl_state *pinstate_uhs; 70 struct clk *clk; 71 struct reset_control *rst; 72 struct reset_control *rst_br; 73 struct reset_control *rst_hw; 74 struct dma_chan *chan; 75 enum dma_data_direction dma_dir; 76 struct regmap *sdctrl_regmap; 77 u32 sdctrl_ch; 78 unsigned long clk_rate; 79 unsigned long caps; 80 }; 81 82 static void *uniphier_sd_priv(struct tmio_mmc_host *host) 83 { 84 return container_of(host->pdata, struct uniphier_sd_priv, tmio_data); 85 } 86 87 static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable) 88 { 89 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 90 } 91 92 /* external DMA engine */ 93 static void uniphier_sd_external_dma_issue(struct tasklet_struct *t) 94 { 95 struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue); 96 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 97 98 uniphier_sd_dma_endisable(host, 1); 99 dma_async_issue_pending(priv->chan); 100 } 101 102 static void uniphier_sd_external_dma_callback(void *param, 103 const struct dmaengine_result *result) 104 { 105 struct tmio_mmc_host *host = param; 106 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 107 unsigned long flags; 108 109 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 110 priv->dma_dir); 111 112 spin_lock_irqsave(&host->lock, flags); 113 114 if (result->result == DMA_TRANS_NOERROR) { 115 /* 116 * When the external DMA engine is enabled, strangely enough, 117 * the DATAEND flag can be asserted even if the DMA engine has 118 * not been kicked yet. Enable the TMIO_STAT_DATAEND irq only 119 * after we make sure the DMA engine finishes the transfer, 120 * hence, in this callback. 121 */ 122 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 123 } else { 124 host->data->error = -ETIMEDOUT; 125 tmio_mmc_do_data_irq(host); 126 } 127 128 spin_unlock_irqrestore(&host->lock, flags); 129 } 130 131 static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host, 132 struct mmc_data *data) 133 { 134 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 135 enum dma_transfer_direction dma_tx_dir; 136 struct dma_async_tx_descriptor *desc; 137 dma_cookie_t cookie; 138 int sg_len; 139 140 if (!priv->chan) 141 goto force_pio; 142 143 if (data->flags & MMC_DATA_READ) { 144 priv->dma_dir = DMA_FROM_DEVICE; 145 dma_tx_dir = DMA_DEV_TO_MEM; 146 } else { 147 priv->dma_dir = DMA_TO_DEVICE; 148 dma_tx_dir = DMA_MEM_TO_DEV; 149 } 150 151 sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 152 priv->dma_dir); 153 if (sg_len == 0) 154 goto force_pio; 155 156 desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len, 157 dma_tx_dir, DMA_CTRL_ACK); 158 if (!desc) 159 goto unmap_sg; 160 161 desc->callback_result = uniphier_sd_external_dma_callback; 162 desc->callback_param = host; 163 164 cookie = dmaengine_submit(desc); 165 if (cookie < 0) 166 goto unmap_sg; 167 168 host->dma_on = true; 169 170 return; 171 172 unmap_sg: 173 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 174 priv->dma_dir); 175 force_pio: 176 uniphier_sd_dma_endisable(host, 0); 177 } 178 179 static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host, 180 bool enable) 181 { 182 } 183 184 static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host, 185 struct tmio_mmc_data *pdata) 186 { 187 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 188 struct dma_chan *chan; 189 190 chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx"); 191 if (IS_ERR(chan)) { 192 dev_warn(mmc_dev(host->mmc), 193 "failed to request DMA channel. falling back to PIO\n"); 194 return; /* just use PIO even for -EPROBE_DEFER */ 195 } 196 197 /* this driver uses a single channel for both RX an TX */ 198 priv->chan = chan; 199 host->chan_rx = chan; 200 host->chan_tx = chan; 201 202 tasklet_setup(&host->dma_issue, uniphier_sd_external_dma_issue); 203 } 204 205 static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host) 206 { 207 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 208 209 if (priv->chan) 210 dma_release_channel(priv->chan); 211 } 212 213 static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host) 214 { 215 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 216 217 uniphier_sd_dma_endisable(host, 0); 218 219 if (priv->chan) 220 dmaengine_terminate_sync(priv->chan); 221 } 222 223 static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host) 224 { 225 uniphier_sd_dma_endisable(host, 0); 226 227 tmio_mmc_do_data_irq(host); 228 } 229 230 static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = { 231 .start = uniphier_sd_external_dma_start, 232 .enable = uniphier_sd_external_dma_enable, 233 .request = uniphier_sd_external_dma_request, 234 .release = uniphier_sd_external_dma_release, 235 .abort = uniphier_sd_external_dma_abort, 236 .dataend = uniphier_sd_external_dma_dataend, 237 }; 238 239 static void uniphier_sd_internal_dma_issue(struct tasklet_struct *t) 240 { 241 struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue); 242 unsigned long flags; 243 244 spin_lock_irqsave(&host->lock, flags); 245 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 246 spin_unlock_irqrestore(&host->lock, flags); 247 248 uniphier_sd_dma_endisable(host, 1); 249 writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL); 250 } 251 252 static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host, 253 struct mmc_data *data) 254 { 255 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 256 struct scatterlist *sg = host->sg_ptr; 257 dma_addr_t dma_addr; 258 unsigned int dma_mode_dir; 259 u32 dma_mode; 260 int sg_len; 261 262 if ((data->flags & MMC_DATA_READ) && !host->chan_rx) 263 goto force_pio; 264 265 if (WARN_ON(host->sg_len != 1)) 266 goto force_pio; 267 268 if (!IS_ALIGNED(sg->offset, 8)) 269 goto force_pio; 270 271 if (data->flags & MMC_DATA_READ) { 272 priv->dma_dir = DMA_FROM_DEVICE; 273 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV; 274 } else { 275 priv->dma_dir = DMA_TO_DEVICE; 276 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV; 277 } 278 279 sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir); 280 if (sg_len == 0) 281 goto force_pio; 282 283 dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir); 284 dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK, 285 UNIPHIER_SD_DMA_MODE_WIDTH_64); 286 dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC; 287 288 writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE); 289 290 dma_addr = sg_dma_address(data->sg); 291 writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L); 292 writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H); 293 294 host->dma_on = true; 295 296 return; 297 force_pio: 298 uniphier_sd_dma_endisable(host, 0); 299 } 300 301 static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host, 302 bool enable) 303 { 304 } 305 306 static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host, 307 struct tmio_mmc_data *pdata) 308 { 309 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 310 311 /* 312 * Due to a hardware bug, Pro5 cannot use DMA for RX. 313 * We can still use DMA for TX, but PIO for RX. 314 */ 315 if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX)) 316 host->chan_rx = (void *)0xdeadbeaf; 317 318 host->chan_tx = (void *)0xdeadbeaf; 319 320 tasklet_setup(&host->dma_issue, uniphier_sd_internal_dma_issue); 321 } 322 323 static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host) 324 { 325 /* Each value is set to zero to assume "disabling" each DMA */ 326 host->chan_rx = NULL; 327 host->chan_tx = NULL; 328 } 329 330 static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host) 331 { 332 u32 tmp; 333 334 uniphier_sd_dma_endisable(host, 0); 335 336 tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST); 337 tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0); 338 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); 339 340 tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0; 341 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); 342 } 343 344 static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host) 345 { 346 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 347 348 uniphier_sd_dma_endisable(host, 0); 349 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir); 350 351 tmio_mmc_do_data_irq(host); 352 } 353 354 static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = { 355 .start = uniphier_sd_internal_dma_start, 356 .enable = uniphier_sd_internal_dma_enable, 357 .request = uniphier_sd_internal_dma_request, 358 .release = uniphier_sd_internal_dma_release, 359 .abort = uniphier_sd_internal_dma_abort, 360 .dataend = uniphier_sd_internal_dma_dataend, 361 }; 362 363 static int uniphier_sd_clk_enable(struct tmio_mmc_host *host) 364 { 365 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 366 struct mmc_host *mmc = host->mmc; 367 int ret; 368 369 ret = clk_prepare_enable(priv->clk); 370 if (ret) 371 return ret; 372 373 ret = clk_set_rate(priv->clk, ULONG_MAX); 374 if (ret) 375 goto disable_clk; 376 377 priv->clk_rate = clk_get_rate(priv->clk); 378 379 /* If max-frequency property is set, use it. */ 380 if (!mmc->f_max) 381 mmc->f_max = priv->clk_rate; 382 383 /* 384 * 1/512 is the finest divisor in the original IP. Newer versions 385 * also supports 1/1024 divisor. (UniPhier-specific extension) 386 */ 387 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 388 mmc->f_min = priv->clk_rate / 1024; 389 else 390 mmc->f_min = priv->clk_rate / 512; 391 392 ret = reset_control_deassert(priv->rst); 393 if (ret) 394 goto disable_clk; 395 396 ret = reset_control_deassert(priv->rst_br); 397 if (ret) 398 goto assert_rst; 399 400 return 0; 401 402 assert_rst: 403 reset_control_assert(priv->rst); 404 disable_clk: 405 clk_disable_unprepare(priv->clk); 406 407 return ret; 408 } 409 410 static void uniphier_sd_clk_disable(struct tmio_mmc_host *host) 411 { 412 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 413 414 reset_control_assert(priv->rst_br); 415 reset_control_assert(priv->rst); 416 clk_disable_unprepare(priv->clk); 417 } 418 419 static void uniphier_sd_hw_reset(struct mmc_host *mmc) 420 { 421 struct tmio_mmc_host *host = mmc_priv(mmc); 422 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 423 424 reset_control_assert(priv->rst_hw); 425 /* For eMMC, minimum is 1us but give it 9us for good measure */ 426 udelay(9); 427 reset_control_deassert(priv->rst_hw); 428 /* For eMMC, minimum is 200us but give it 300us for good measure */ 429 usleep_range(300, 1000); 430 } 431 432 static void uniphier_sd_uhs_enable(struct tmio_mmc_host *host, bool uhs_en) 433 { 434 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 435 unsigned int offset; 436 u32 val; 437 438 if (!(host->mmc->caps & MMC_CAP_UHS)) 439 return; 440 441 val = (uhs_en) ? UNIPHIER_SDCTRL_MODE_UHS1MOD : 0; 442 443 offset = UNIPHIER_SDCTRL_CHOFFSET * priv->sdctrl_ch 444 + UNIPHIER_SDCTRL_MODE; 445 regmap_write_bits(priv->sdctrl_regmap, offset, 446 UNIPHIER_SDCTRL_MODE_UHS1MOD, val); 447 } 448 449 static void uniphier_sd_set_clock(struct tmio_mmc_host *host, 450 unsigned int clock) 451 { 452 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 453 unsigned long divisor; 454 u32 tmp; 455 456 tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 457 458 /* stop the clock before changing its rate to avoid a glitch signal */ 459 tmp &= ~CLK_CTL_SCLKEN; 460 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 461 462 if (clock == 0) 463 return; 464 465 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024; 466 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1; 467 tmp &= ~CLK_CTL_DIV_MASK; 468 469 divisor = priv->clk_rate / clock; 470 471 /* 472 * In the original IP, bit[7:0] represents the divisor. 473 * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 474 * 475 * The IP does not define a way to achieve 1/1. For UniPhier variants, 476 * bit10 is used for 1/1. Newer versions of UniPhier variants use 477 * bit16 for 1/1024. 478 */ 479 if (divisor <= 1) 480 tmp |= UNIPHIER_SD_CLK_CTL_DIV1; 481 else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512) 482 tmp |= UNIPHIER_SD_CLK_CTL_DIV1024; 483 else 484 tmp |= roundup_pow_of_two(divisor) >> 2; 485 486 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 487 488 tmp |= CLK_CTL_SCLKEN; 489 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 490 } 491 492 static void uniphier_sd_host_init(struct tmio_mmc_host *host) 493 { 494 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 495 u32 val; 496 497 /* 498 * Connected to 32bit AXI. 499 * This register holds settings for SoC-specific internal bus 500 * connection. What is worse, the register spec was changed, 501 * breaking the backward compatibility. Write an appropriate 502 * value depending on a flag associated with a compatible string. 503 */ 504 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 505 val = 0x00000101; 506 else 507 val = 0x00000000; 508 509 writel(val, host->ctl + UNIPHIER_SD_HOST_MODE); 510 511 val = 0; 512 /* 513 * If supported, the controller can automatically 514 * enable/disable the clock line to the card. 515 */ 516 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 517 val |= UNIPHIER_SD_CLKCTL_OFFEN; 518 519 writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 520 } 521 522 static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc, 523 struct mmc_ios *ios) 524 { 525 struct tmio_mmc_host *host = mmc_priv(mmc); 526 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 527 struct pinctrl_state *pinstate = NULL; 528 u32 val, tmp; 529 bool uhs_en; 530 531 switch (ios->signal_voltage) { 532 case MMC_SIGNAL_VOLTAGE_330: 533 val = UNIPHIER_SD_VOLT_330; 534 uhs_en = false; 535 break; 536 case MMC_SIGNAL_VOLTAGE_180: 537 val = UNIPHIER_SD_VOLT_180; 538 pinstate = priv->pinstate_uhs; 539 uhs_en = true; 540 break; 541 default: 542 return -ENOTSUPP; 543 } 544 545 tmp = readl(host->ctl + UNIPHIER_SD_VOLT); 546 tmp &= ~UNIPHIER_SD_VOLT_MASK; 547 tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val); 548 writel(tmp, host->ctl + UNIPHIER_SD_VOLT); 549 550 if (pinstate) 551 pinctrl_select_state(priv->pinctrl, pinstate); 552 else 553 pinctrl_select_default_state(mmc_dev(mmc)); 554 555 uniphier_sd_uhs_enable(host, uhs_en); 556 557 return 0; 558 } 559 560 static int uniphier_sd_uhs_init(struct tmio_mmc_host *host) 561 { 562 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 563 struct device *dev = &host->pdev->dev; 564 struct device_node *np = dev->of_node; 565 struct of_phandle_args args; 566 int ret; 567 568 priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc)); 569 if (IS_ERR(priv->pinctrl)) 570 return PTR_ERR(priv->pinctrl); 571 572 priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs"); 573 if (IS_ERR(priv->pinstate_uhs)) 574 return PTR_ERR(priv->pinstate_uhs); 575 576 ret = of_parse_phandle_with_fixed_args(np, 577 "socionext,syscon-uhs-mode", 578 1, 0, &args); 579 if (ret) { 580 dev_err(dev, "Can't get syscon-uhs-mode property\n"); 581 return ret; 582 } 583 priv->sdctrl_regmap = syscon_node_to_regmap(args.np); 584 of_node_put(args.np); 585 if (IS_ERR(priv->sdctrl_regmap)) { 586 dev_err(dev, "Can't map syscon-uhs-mode\n"); 587 return PTR_ERR(priv->sdctrl_regmap); 588 } 589 priv->sdctrl_ch = args.args[0]; 590 591 return 0; 592 } 593 594 static int uniphier_sd_probe(struct platform_device *pdev) 595 { 596 struct device *dev = &pdev->dev; 597 struct uniphier_sd_priv *priv; 598 struct tmio_mmc_data *tmio_data; 599 struct tmio_mmc_host *host; 600 int irq, ret; 601 602 irq = platform_get_irq(pdev, 0); 603 if (irq < 0) 604 return irq; 605 606 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 607 if (!priv) 608 return -ENOMEM; 609 610 priv->caps = (unsigned long)of_device_get_match_data(dev); 611 612 priv->clk = devm_clk_get(dev, NULL); 613 if (IS_ERR(priv->clk)) { 614 dev_err(dev, "failed to get clock\n"); 615 return PTR_ERR(priv->clk); 616 } 617 618 priv->rst = devm_reset_control_get_shared(dev, "host"); 619 if (IS_ERR(priv->rst)) { 620 dev_err(dev, "failed to get host reset\n"); 621 return PTR_ERR(priv->rst); 622 } 623 624 /* old version has one more reset */ 625 if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) { 626 priv->rst_br = devm_reset_control_get_shared(dev, "bridge"); 627 if (IS_ERR(priv->rst_br)) { 628 dev_err(dev, "failed to get bridge reset\n"); 629 return PTR_ERR(priv->rst_br); 630 } 631 } 632 633 tmio_data = &priv->tmio_data; 634 tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT; 635 tmio_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 636 637 host = tmio_mmc_host_alloc(pdev, tmio_data); 638 if (IS_ERR(host)) 639 return PTR_ERR(host); 640 641 if (host->mmc->caps & MMC_CAP_HW_RESET) { 642 priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw"); 643 if (IS_ERR(priv->rst_hw)) { 644 dev_err(dev, "failed to get hw reset\n"); 645 ret = PTR_ERR(priv->rst_hw); 646 goto free_host; 647 } 648 host->ops.card_hw_reset = uniphier_sd_hw_reset; 649 } 650 651 if (host->mmc->caps & MMC_CAP_UHS) { 652 ret = uniphier_sd_uhs_init(host); 653 if (ret) { 654 dev_warn(dev, 655 "failed to setup UHS (error %d). Disabling UHS.", 656 ret); 657 host->mmc->caps &= ~MMC_CAP_UHS; 658 } else { 659 host->ops.start_signal_voltage_switch = 660 uniphier_sd_start_signal_voltage_switch; 661 } 662 } 663 664 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 665 host->dma_ops = &uniphier_sd_internal_dma_ops; 666 else 667 host->dma_ops = &uniphier_sd_external_dma_ops; 668 669 host->bus_shift = 1; 670 host->clk_enable = uniphier_sd_clk_enable; 671 host->clk_disable = uniphier_sd_clk_disable; 672 host->set_clock = uniphier_sd_set_clock; 673 674 ret = uniphier_sd_clk_enable(host); 675 if (ret) 676 goto free_host; 677 678 uniphier_sd_host_init(host); 679 680 tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; 681 if (host->mmc->caps & MMC_CAP_UHS) 682 tmio_data->ocr_mask |= MMC_VDD_165_195; 683 684 tmio_data->max_segs = 1; 685 tmio_data->max_blk_count = U16_MAX; 686 687 ret = tmio_mmc_host_probe(host); 688 if (ret) 689 goto disable_clk; 690 691 ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED, 692 dev_name(dev), host); 693 if (ret) 694 goto remove_host; 695 696 return 0; 697 698 remove_host: 699 tmio_mmc_host_remove(host); 700 disable_clk: 701 uniphier_sd_clk_disable(host); 702 free_host: 703 tmio_mmc_host_free(host); 704 705 return ret; 706 } 707 708 static int uniphier_sd_remove(struct platform_device *pdev) 709 { 710 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 711 712 tmio_mmc_host_remove(host); 713 uniphier_sd_clk_disable(host); 714 tmio_mmc_host_free(host); 715 716 return 0; 717 } 718 719 static const struct of_device_id uniphier_sd_match[] = { 720 { 721 .compatible = "socionext,uniphier-sd-v2.91", 722 }, 723 { 724 .compatible = "socionext,uniphier-sd-v3.1", 725 .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP | 726 UNIPHIER_SD_CAP_BROKEN_DMA_RX), 727 }, 728 { 729 .compatible = "socionext,uniphier-sd-v3.1.1", 730 .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP, 731 }, 732 { /* sentinel */ } 733 }; 734 MODULE_DEVICE_TABLE(of, uniphier_sd_match); 735 736 static struct platform_driver uniphier_sd_driver = { 737 .probe = uniphier_sd_probe, 738 .remove = uniphier_sd_remove, 739 .driver = { 740 .name = "uniphier-sd", 741 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 742 .of_match_table = uniphier_sd_match, 743 }, 744 }; 745 module_platform_driver(uniphier_sd_driver); 746 747 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 748 MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver"); 749 MODULE_LICENSE("GPL v2"); 750