13fd784f7SMasahiro Yamada // SPDX-License-Identifier: GPL-2.0
23fd784f7SMasahiro Yamada //
33fd784f7SMasahiro Yamada // Copyright (C) 2017-2018 Socionext Inc.
43fd784f7SMasahiro Yamada // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
53fd784f7SMasahiro Yamada
63fd784f7SMasahiro Yamada #include <linux/bitfield.h>
73fd784f7SMasahiro Yamada #include <linux/bitops.h>
83fd784f7SMasahiro Yamada #include <linux/clk.h>
93fd784f7SMasahiro Yamada #include <linux/delay.h>
103fd784f7SMasahiro Yamada #include <linux/dma-mapping.h>
111c325ed9SKunihiko Hayashi #include <linux/mfd/syscon.h>
123fd784f7SMasahiro Yamada #include <linux/mfd/tmio.h>
133fd784f7SMasahiro Yamada #include <linux/mmc/host.h>
143fd784f7SMasahiro Yamada #include <linux/module.h>
153fd784f7SMasahiro Yamada #include <linux/of.h>
163fd784f7SMasahiro Yamada #include <linux/pinctrl/consumer.h>
173fd784f7SMasahiro Yamada #include <linux/platform_device.h>
181c325ed9SKunihiko Hayashi #include <linux/regmap.h>
193fd784f7SMasahiro Yamada #include <linux/reset.h>
203fd784f7SMasahiro Yamada
213fd784f7SMasahiro Yamada #include "tmio_mmc.h"
223fd784f7SMasahiro Yamada
233fd784f7SMasahiro Yamada #define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16)
243fd784f7SMasahiro Yamada #define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10)
253fd784f7SMasahiro Yamada #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
263fd784f7SMasahiro Yamada #define UNIPHIER_SD_CC_EXT_MODE 0x1b0
273fd784f7SMasahiro Yamada #define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1)
283fd784f7SMasahiro Yamada #define UNIPHIER_SD_HOST_MODE 0x1c8
293fd784f7SMasahiro Yamada #define UNIPHIER_SD_VOLT 0x1e4
303fd784f7SMasahiro Yamada #define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0)
313fd784f7SMasahiro Yamada #define UNIPHIER_SD_VOLT_OFF 0
323fd784f7SMasahiro Yamada #define UNIPHIER_SD_VOLT_330 1 // 3.3V signal
333fd784f7SMasahiro Yamada #define UNIPHIER_SD_VOLT_180 2 // 1.8V signal
343fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE 0x410
353fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16)
363fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0
373fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1
383fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4)
393fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE_WIDTH_8 0
403fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE_WIDTH_16 1
413fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE_WIDTH_32 2
423fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE_WIDTH_64 3
433fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed
443fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_CTL 0x414
453fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared)
463fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_RST 0x418
473fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_RST_CH1 BIT(9)
483fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_RST_CH0 BIT(8)
493fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_ADDR_L 0x440
503fd784f7SMasahiro Yamada #define UNIPHIER_SD_DMA_ADDR_H 0x444
513fd784f7SMasahiro Yamada
521c325ed9SKunihiko Hayashi /* SD control */
531c325ed9SKunihiko Hayashi #define UNIPHIER_SDCTRL_CHOFFSET 0x200
541c325ed9SKunihiko Hayashi #define UNIPHIER_SDCTRL_MODE 0x30
551c325ed9SKunihiko Hayashi #define UNIPHIER_SDCTRL_MODE_UHS1MOD BIT(15)
562cda1de0SKunihiko Hayashi #define UNIPHIER_SDCTRL_MODE_SDRSEL BIT(14)
571c325ed9SKunihiko Hayashi
583fd784f7SMasahiro Yamada /*
593fd784f7SMasahiro Yamada * IP is extended to support various features: built-in DMA engine,
603fd784f7SMasahiro Yamada * 1/1024 divisor, etc.
613fd784f7SMasahiro Yamada */
623fd784f7SMasahiro Yamada #define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0)
633fd784f7SMasahiro Yamada /* RX channel of the built-in DMA controller is broken (Pro5) */
643fd784f7SMasahiro Yamada #define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1)
653fd784f7SMasahiro Yamada
663fd784f7SMasahiro Yamada struct uniphier_sd_priv {
673fd784f7SMasahiro Yamada struct tmio_mmc_data tmio_data;
683fd784f7SMasahiro Yamada struct pinctrl *pinctrl;
693fd784f7SMasahiro Yamada struct pinctrl_state *pinstate_uhs;
703fd784f7SMasahiro Yamada struct clk *clk;
713fd784f7SMasahiro Yamada struct reset_control *rst;
723fd784f7SMasahiro Yamada struct reset_control *rst_br;
733fd784f7SMasahiro Yamada struct reset_control *rst_hw;
743fd784f7SMasahiro Yamada struct dma_chan *chan;
753fd784f7SMasahiro Yamada enum dma_data_direction dma_dir;
761c325ed9SKunihiko Hayashi struct regmap *sdctrl_regmap;
771c325ed9SKunihiko Hayashi u32 sdctrl_ch;
783fd784f7SMasahiro Yamada unsigned long clk_rate;
793fd784f7SMasahiro Yamada unsigned long caps;
803fd784f7SMasahiro Yamada };
813fd784f7SMasahiro Yamada
uniphier_sd_priv(struct tmio_mmc_host * host)823fd784f7SMasahiro Yamada static void *uniphier_sd_priv(struct tmio_mmc_host *host)
833fd784f7SMasahiro Yamada {
843fd784f7SMasahiro Yamada return container_of(host->pdata, struct uniphier_sd_priv, tmio_data);
853fd784f7SMasahiro Yamada }
863fd784f7SMasahiro Yamada
uniphier_sd_dma_endisable(struct tmio_mmc_host * host,int enable)873fd784f7SMasahiro Yamada static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable)
883fd784f7SMasahiro Yamada {
89b7ced877SMasahiro Yamada sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
903fd784f7SMasahiro Yamada }
913fd784f7SMasahiro Yamada
923fd784f7SMasahiro Yamada /* external DMA engine */
uniphier_sd_external_dma_issue(struct tasklet_struct * t)9339d2969dSEmil Renner Berthing static void uniphier_sd_external_dma_issue(struct tasklet_struct *t)
943fd784f7SMasahiro Yamada {
9539d2969dSEmil Renner Berthing struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue);
963fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
973fd784f7SMasahiro Yamada
983fd784f7SMasahiro Yamada uniphier_sd_dma_endisable(host, 1);
993fd784f7SMasahiro Yamada dma_async_issue_pending(priv->chan);
1003fd784f7SMasahiro Yamada }
1013fd784f7SMasahiro Yamada
uniphier_sd_external_dma_callback(void * param,const struct dmaengine_result * result)1023fd784f7SMasahiro Yamada static void uniphier_sd_external_dma_callback(void *param,
1033fd784f7SMasahiro Yamada const struct dmaengine_result *result)
1043fd784f7SMasahiro Yamada {
1053fd784f7SMasahiro Yamada struct tmio_mmc_host *host = param;
1063fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
1073fd784f7SMasahiro Yamada unsigned long flags;
1083fd784f7SMasahiro Yamada
1093fd784f7SMasahiro Yamada dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
1103fd784f7SMasahiro Yamada priv->dma_dir);
1113fd784f7SMasahiro Yamada
1123fd784f7SMasahiro Yamada spin_lock_irqsave(&host->lock, flags);
1133fd784f7SMasahiro Yamada
1143fd784f7SMasahiro Yamada if (result->result == DMA_TRANS_NOERROR) {
1153fd784f7SMasahiro Yamada /*
1163fd784f7SMasahiro Yamada * When the external DMA engine is enabled, strangely enough,
1173fd784f7SMasahiro Yamada * the DATAEND flag can be asserted even if the DMA engine has
1183fd784f7SMasahiro Yamada * not been kicked yet. Enable the TMIO_STAT_DATAEND irq only
1193fd784f7SMasahiro Yamada * after we make sure the DMA engine finishes the transfer,
1203fd784f7SMasahiro Yamada * hence, in this callback.
1213fd784f7SMasahiro Yamada */
1223fd784f7SMasahiro Yamada tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
1233fd784f7SMasahiro Yamada } else {
1243fd784f7SMasahiro Yamada host->data->error = -ETIMEDOUT;
1253fd784f7SMasahiro Yamada tmio_mmc_do_data_irq(host);
1263fd784f7SMasahiro Yamada }
1273fd784f7SMasahiro Yamada
1283fd784f7SMasahiro Yamada spin_unlock_irqrestore(&host->lock, flags);
1293fd784f7SMasahiro Yamada }
1303fd784f7SMasahiro Yamada
uniphier_sd_external_dma_start(struct tmio_mmc_host * host,struct mmc_data * data)1313fd784f7SMasahiro Yamada static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host,
1323fd784f7SMasahiro Yamada struct mmc_data *data)
1333fd784f7SMasahiro Yamada {
1343fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
1353fd784f7SMasahiro Yamada enum dma_transfer_direction dma_tx_dir;
1363fd784f7SMasahiro Yamada struct dma_async_tx_descriptor *desc;
1373fd784f7SMasahiro Yamada dma_cookie_t cookie;
1383fd784f7SMasahiro Yamada int sg_len;
1393fd784f7SMasahiro Yamada
1403fd784f7SMasahiro Yamada if (!priv->chan)
1413fd784f7SMasahiro Yamada goto force_pio;
1423fd784f7SMasahiro Yamada
1433fd784f7SMasahiro Yamada if (data->flags & MMC_DATA_READ) {
1443fd784f7SMasahiro Yamada priv->dma_dir = DMA_FROM_DEVICE;
1453fd784f7SMasahiro Yamada dma_tx_dir = DMA_DEV_TO_MEM;
1463fd784f7SMasahiro Yamada } else {
1473fd784f7SMasahiro Yamada priv->dma_dir = DMA_TO_DEVICE;
1483fd784f7SMasahiro Yamada dma_tx_dir = DMA_MEM_TO_DEV;
1493fd784f7SMasahiro Yamada }
1503fd784f7SMasahiro Yamada
1513fd784f7SMasahiro Yamada sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
1523fd784f7SMasahiro Yamada priv->dma_dir);
1533fd784f7SMasahiro Yamada if (sg_len == 0)
1543fd784f7SMasahiro Yamada goto force_pio;
1553fd784f7SMasahiro Yamada
1563fd784f7SMasahiro Yamada desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len,
1573fd784f7SMasahiro Yamada dma_tx_dir, DMA_CTRL_ACK);
1583fd784f7SMasahiro Yamada if (!desc)
1593fd784f7SMasahiro Yamada goto unmap_sg;
1603fd784f7SMasahiro Yamada
1613fd784f7SMasahiro Yamada desc->callback_result = uniphier_sd_external_dma_callback;
1623fd784f7SMasahiro Yamada desc->callback_param = host;
1633fd784f7SMasahiro Yamada
1643fd784f7SMasahiro Yamada cookie = dmaengine_submit(desc);
1653fd784f7SMasahiro Yamada if (cookie < 0)
1663fd784f7SMasahiro Yamada goto unmap_sg;
1673fd784f7SMasahiro Yamada
168d3dd5db0SMasahiro Yamada host->dma_on = true;
169d3dd5db0SMasahiro Yamada
1703fd784f7SMasahiro Yamada return;
1713fd784f7SMasahiro Yamada
1723fd784f7SMasahiro Yamada unmap_sg:
1733fd784f7SMasahiro Yamada dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
1743fd784f7SMasahiro Yamada priv->dma_dir);
1753fd784f7SMasahiro Yamada force_pio:
1763fd784f7SMasahiro Yamada uniphier_sd_dma_endisable(host, 0);
1773fd784f7SMasahiro Yamada }
1783fd784f7SMasahiro Yamada
uniphier_sd_external_dma_enable(struct tmio_mmc_host * host,bool enable)1793fd784f7SMasahiro Yamada static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host,
1803fd784f7SMasahiro Yamada bool enable)
1813fd784f7SMasahiro Yamada {
1823fd784f7SMasahiro Yamada }
1833fd784f7SMasahiro Yamada
uniphier_sd_external_dma_request(struct tmio_mmc_host * host,struct tmio_mmc_data * pdata)1843fd784f7SMasahiro Yamada static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
1853fd784f7SMasahiro Yamada struct tmio_mmc_data *pdata)
1863fd784f7SMasahiro Yamada {
1873fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
1883fd784f7SMasahiro Yamada struct dma_chan *chan;
1893fd784f7SMasahiro Yamada
1903fd784f7SMasahiro Yamada chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
1913fd784f7SMasahiro Yamada if (IS_ERR(chan)) {
1923fd784f7SMasahiro Yamada dev_warn(mmc_dev(host->mmc),
1933fd784f7SMasahiro Yamada "failed to request DMA channel. falling back to PIO\n");
1943fd784f7SMasahiro Yamada return; /* just use PIO even for -EPROBE_DEFER */
1953fd784f7SMasahiro Yamada }
1963fd784f7SMasahiro Yamada
1973fd784f7SMasahiro Yamada /* this driver uses a single channel for both RX an TX */
1983fd784f7SMasahiro Yamada priv->chan = chan;
1993fd784f7SMasahiro Yamada host->chan_rx = chan;
2003fd784f7SMasahiro Yamada host->chan_tx = chan;
2013fd784f7SMasahiro Yamada
20239d2969dSEmil Renner Berthing tasklet_setup(&host->dma_issue, uniphier_sd_external_dma_issue);
2033fd784f7SMasahiro Yamada }
2043fd784f7SMasahiro Yamada
uniphier_sd_external_dma_release(struct tmio_mmc_host * host)2053fd784f7SMasahiro Yamada static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host)
2063fd784f7SMasahiro Yamada {
2073fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
2083fd784f7SMasahiro Yamada
2093fd784f7SMasahiro Yamada if (priv->chan)
2103fd784f7SMasahiro Yamada dma_release_channel(priv->chan);
2113fd784f7SMasahiro Yamada }
2123fd784f7SMasahiro Yamada
uniphier_sd_external_dma_abort(struct tmio_mmc_host * host)2133fd784f7SMasahiro Yamada static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host)
2143fd784f7SMasahiro Yamada {
2153fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
2163fd784f7SMasahiro Yamada
2173fd784f7SMasahiro Yamada uniphier_sd_dma_endisable(host, 0);
2183fd784f7SMasahiro Yamada
2193fd784f7SMasahiro Yamada if (priv->chan)
2203fd784f7SMasahiro Yamada dmaengine_terminate_sync(priv->chan);
2213fd784f7SMasahiro Yamada }
2223fd784f7SMasahiro Yamada
uniphier_sd_external_dma_dataend(struct tmio_mmc_host * host)2233fd784f7SMasahiro Yamada static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host)
2243fd784f7SMasahiro Yamada {
2253fd784f7SMasahiro Yamada uniphier_sd_dma_endisable(host, 0);
2263fd784f7SMasahiro Yamada
2273fd784f7SMasahiro Yamada tmio_mmc_do_data_irq(host);
2283fd784f7SMasahiro Yamada }
2293fd784f7SMasahiro Yamada
2303fd784f7SMasahiro Yamada static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = {
2313fd784f7SMasahiro Yamada .start = uniphier_sd_external_dma_start,
2323fd784f7SMasahiro Yamada .enable = uniphier_sd_external_dma_enable,
2333fd784f7SMasahiro Yamada .request = uniphier_sd_external_dma_request,
2343fd784f7SMasahiro Yamada .release = uniphier_sd_external_dma_release,
2353fd784f7SMasahiro Yamada .abort = uniphier_sd_external_dma_abort,
2363fd784f7SMasahiro Yamada .dataend = uniphier_sd_external_dma_dataend,
2373fd784f7SMasahiro Yamada };
2383fd784f7SMasahiro Yamada
uniphier_sd_internal_dma_issue(struct tasklet_struct * t)23939d2969dSEmil Renner Berthing static void uniphier_sd_internal_dma_issue(struct tasklet_struct *t)
2403fd784f7SMasahiro Yamada {
24139d2969dSEmil Renner Berthing struct tmio_mmc_host *host = from_tasklet(host, t, dma_issue);
2423fd784f7SMasahiro Yamada unsigned long flags;
2433fd784f7SMasahiro Yamada
2443fd784f7SMasahiro Yamada spin_lock_irqsave(&host->lock, flags);
2453fd784f7SMasahiro Yamada tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
2463fd784f7SMasahiro Yamada spin_unlock_irqrestore(&host->lock, flags);
2473fd784f7SMasahiro Yamada
2483fd784f7SMasahiro Yamada uniphier_sd_dma_endisable(host, 1);
2493fd784f7SMasahiro Yamada writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL);
2503fd784f7SMasahiro Yamada }
2513fd784f7SMasahiro Yamada
uniphier_sd_internal_dma_start(struct tmio_mmc_host * host,struct mmc_data * data)2523fd784f7SMasahiro Yamada static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host,
2533fd784f7SMasahiro Yamada struct mmc_data *data)
2543fd784f7SMasahiro Yamada {
2553fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
2563fd784f7SMasahiro Yamada struct scatterlist *sg = host->sg_ptr;
2573fd784f7SMasahiro Yamada dma_addr_t dma_addr;
2583fd784f7SMasahiro Yamada unsigned int dma_mode_dir;
2593fd784f7SMasahiro Yamada u32 dma_mode;
2603fd784f7SMasahiro Yamada int sg_len;
2613fd784f7SMasahiro Yamada
26290f83541SMasahiro Yamada if ((data->flags & MMC_DATA_READ) && !host->chan_rx)
26390f83541SMasahiro Yamada goto force_pio;
26490f83541SMasahiro Yamada
2653fd784f7SMasahiro Yamada if (WARN_ON(host->sg_len != 1))
2663fd784f7SMasahiro Yamada goto force_pio;
2673fd784f7SMasahiro Yamada
2683fd784f7SMasahiro Yamada if (!IS_ALIGNED(sg->offset, 8))
2693fd784f7SMasahiro Yamada goto force_pio;
2703fd784f7SMasahiro Yamada
2713fd784f7SMasahiro Yamada if (data->flags & MMC_DATA_READ) {
2723fd784f7SMasahiro Yamada priv->dma_dir = DMA_FROM_DEVICE;
2733fd784f7SMasahiro Yamada dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV;
2743fd784f7SMasahiro Yamada } else {
2753fd784f7SMasahiro Yamada priv->dma_dir = DMA_TO_DEVICE;
2763fd784f7SMasahiro Yamada dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV;
2773fd784f7SMasahiro Yamada }
2783fd784f7SMasahiro Yamada
2793fd784f7SMasahiro Yamada sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir);
2803fd784f7SMasahiro Yamada if (sg_len == 0)
2813fd784f7SMasahiro Yamada goto force_pio;
2823fd784f7SMasahiro Yamada
2833fd784f7SMasahiro Yamada dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir);
2843fd784f7SMasahiro Yamada dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK,
2853fd784f7SMasahiro Yamada UNIPHIER_SD_DMA_MODE_WIDTH_64);
2863fd784f7SMasahiro Yamada dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
2873fd784f7SMasahiro Yamada
2883fd784f7SMasahiro Yamada writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE);
2893fd784f7SMasahiro Yamada
2903fd784f7SMasahiro Yamada dma_addr = sg_dma_address(data->sg);
2913fd784f7SMasahiro Yamada writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L);
2923fd784f7SMasahiro Yamada writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H);
2933fd784f7SMasahiro Yamada
294d3dd5db0SMasahiro Yamada host->dma_on = true;
295d3dd5db0SMasahiro Yamada
2963fd784f7SMasahiro Yamada return;
2973fd784f7SMasahiro Yamada force_pio:
2983fd784f7SMasahiro Yamada uniphier_sd_dma_endisable(host, 0);
2993fd784f7SMasahiro Yamada }
3003fd784f7SMasahiro Yamada
uniphier_sd_internal_dma_enable(struct tmio_mmc_host * host,bool enable)3013fd784f7SMasahiro Yamada static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host,
3023fd784f7SMasahiro Yamada bool enable)
3033fd784f7SMasahiro Yamada {
3043fd784f7SMasahiro Yamada }
3053fd784f7SMasahiro Yamada
uniphier_sd_internal_dma_request(struct tmio_mmc_host * host,struct tmio_mmc_data * pdata)3063fd784f7SMasahiro Yamada static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host,
3073fd784f7SMasahiro Yamada struct tmio_mmc_data *pdata)
3083fd784f7SMasahiro Yamada {
3093fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
3103fd784f7SMasahiro Yamada
3113fd784f7SMasahiro Yamada /*
3123fd784f7SMasahiro Yamada * Due to a hardware bug, Pro5 cannot use DMA for RX.
3133fd784f7SMasahiro Yamada * We can still use DMA for TX, but PIO for RX.
3143fd784f7SMasahiro Yamada */
3153fd784f7SMasahiro Yamada if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX))
3163fd784f7SMasahiro Yamada host->chan_rx = (void *)0xdeadbeaf;
3173fd784f7SMasahiro Yamada
3183fd784f7SMasahiro Yamada host->chan_tx = (void *)0xdeadbeaf;
3193fd784f7SMasahiro Yamada
32039d2969dSEmil Renner Berthing tasklet_setup(&host->dma_issue, uniphier_sd_internal_dma_issue);
3213fd784f7SMasahiro Yamada }
3223fd784f7SMasahiro Yamada
uniphier_sd_internal_dma_release(struct tmio_mmc_host * host)3233fd784f7SMasahiro Yamada static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host)
3243fd784f7SMasahiro Yamada {
3253fd784f7SMasahiro Yamada /* Each value is set to zero to assume "disabling" each DMA */
3263fd784f7SMasahiro Yamada host->chan_rx = NULL;
3273fd784f7SMasahiro Yamada host->chan_tx = NULL;
3283fd784f7SMasahiro Yamada }
3293fd784f7SMasahiro Yamada
uniphier_sd_internal_dma_abort(struct tmio_mmc_host * host)3303fd784f7SMasahiro Yamada static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host)
3313fd784f7SMasahiro Yamada {
3323fd784f7SMasahiro Yamada u32 tmp;
3333fd784f7SMasahiro Yamada
3343fd784f7SMasahiro Yamada uniphier_sd_dma_endisable(host, 0);
3353fd784f7SMasahiro Yamada
3363fd784f7SMasahiro Yamada tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST);
3373fd784f7SMasahiro Yamada tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0);
3383fd784f7SMasahiro Yamada writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
3393fd784f7SMasahiro Yamada
3403fd784f7SMasahiro Yamada tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0;
3413fd784f7SMasahiro Yamada writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
3423fd784f7SMasahiro Yamada }
3433fd784f7SMasahiro Yamada
uniphier_sd_internal_dma_dataend(struct tmio_mmc_host * host)3443fd784f7SMasahiro Yamada static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host)
3453fd784f7SMasahiro Yamada {
3463fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
3473fd784f7SMasahiro Yamada
3483fd784f7SMasahiro Yamada uniphier_sd_dma_endisable(host, 0);
3493fd784f7SMasahiro Yamada dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir);
3503fd784f7SMasahiro Yamada
3513fd784f7SMasahiro Yamada tmio_mmc_do_data_irq(host);
3523fd784f7SMasahiro Yamada }
3533fd784f7SMasahiro Yamada
3543fd784f7SMasahiro Yamada static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = {
3553fd784f7SMasahiro Yamada .start = uniphier_sd_internal_dma_start,
3563fd784f7SMasahiro Yamada .enable = uniphier_sd_internal_dma_enable,
3573fd784f7SMasahiro Yamada .request = uniphier_sd_internal_dma_request,
3583fd784f7SMasahiro Yamada .release = uniphier_sd_internal_dma_release,
3593fd784f7SMasahiro Yamada .abort = uniphier_sd_internal_dma_abort,
3603fd784f7SMasahiro Yamada .dataend = uniphier_sd_internal_dma_dataend,
3613fd784f7SMasahiro Yamada };
3623fd784f7SMasahiro Yamada
uniphier_sd_clk_enable(struct tmio_mmc_host * host)3633fd784f7SMasahiro Yamada static int uniphier_sd_clk_enable(struct tmio_mmc_host *host)
3643fd784f7SMasahiro Yamada {
3653fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
3663fd784f7SMasahiro Yamada struct mmc_host *mmc = host->mmc;
3673fd784f7SMasahiro Yamada int ret;
3683fd784f7SMasahiro Yamada
3693fd784f7SMasahiro Yamada ret = clk_prepare_enable(priv->clk);
3703fd784f7SMasahiro Yamada if (ret)
3713fd784f7SMasahiro Yamada return ret;
3723fd784f7SMasahiro Yamada
3733fd784f7SMasahiro Yamada ret = clk_set_rate(priv->clk, ULONG_MAX);
3743fd784f7SMasahiro Yamada if (ret)
3753fd784f7SMasahiro Yamada goto disable_clk;
3763fd784f7SMasahiro Yamada
3773fd784f7SMasahiro Yamada priv->clk_rate = clk_get_rate(priv->clk);
3783fd784f7SMasahiro Yamada
3793fd784f7SMasahiro Yamada /* If max-frequency property is set, use it. */
3803fd784f7SMasahiro Yamada if (!mmc->f_max)
3813fd784f7SMasahiro Yamada mmc->f_max = priv->clk_rate;
3823fd784f7SMasahiro Yamada
3833fd784f7SMasahiro Yamada /*
3843fd784f7SMasahiro Yamada * 1/512 is the finest divisor in the original IP. Newer versions
3853fd784f7SMasahiro Yamada * also supports 1/1024 divisor. (UniPhier-specific extension)
3863fd784f7SMasahiro Yamada */
3873fd784f7SMasahiro Yamada if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
3883fd784f7SMasahiro Yamada mmc->f_min = priv->clk_rate / 1024;
3893fd784f7SMasahiro Yamada else
3903fd784f7SMasahiro Yamada mmc->f_min = priv->clk_rate / 512;
3913fd784f7SMasahiro Yamada
3923fd784f7SMasahiro Yamada ret = reset_control_deassert(priv->rst);
3933fd784f7SMasahiro Yamada if (ret)
3943fd784f7SMasahiro Yamada goto disable_clk;
3953fd784f7SMasahiro Yamada
3963fd784f7SMasahiro Yamada ret = reset_control_deassert(priv->rst_br);
3973fd784f7SMasahiro Yamada if (ret)
3983fd784f7SMasahiro Yamada goto assert_rst;
3993fd784f7SMasahiro Yamada
4003fd784f7SMasahiro Yamada return 0;
4013fd784f7SMasahiro Yamada
4023fd784f7SMasahiro Yamada assert_rst:
4033fd784f7SMasahiro Yamada reset_control_assert(priv->rst);
4043fd784f7SMasahiro Yamada disable_clk:
4053fd784f7SMasahiro Yamada clk_disable_unprepare(priv->clk);
4063fd784f7SMasahiro Yamada
4073fd784f7SMasahiro Yamada return ret;
4083fd784f7SMasahiro Yamada }
4093fd784f7SMasahiro Yamada
uniphier_sd_clk_disable(struct tmio_mmc_host * host)4103fd784f7SMasahiro Yamada static void uniphier_sd_clk_disable(struct tmio_mmc_host *host)
4113fd784f7SMasahiro Yamada {
4123fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
4133fd784f7SMasahiro Yamada
4143fd784f7SMasahiro Yamada reset_control_assert(priv->rst_br);
4153fd784f7SMasahiro Yamada reset_control_assert(priv->rst);
4163fd784f7SMasahiro Yamada clk_disable_unprepare(priv->clk);
4173fd784f7SMasahiro Yamada }
4183fd784f7SMasahiro Yamada
uniphier_sd_hw_reset(struct mmc_host * mmc)419a8c83064SWolfram Sang static void uniphier_sd_hw_reset(struct mmc_host *mmc)
4203fd784f7SMasahiro Yamada {
421a8c83064SWolfram Sang struct tmio_mmc_host *host = mmc_priv(mmc);
4223fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
4233fd784f7SMasahiro Yamada
4243fd784f7SMasahiro Yamada reset_control_assert(priv->rst_hw);
4253fd784f7SMasahiro Yamada /* For eMMC, minimum is 1us but give it 9us for good measure */
4263fd784f7SMasahiro Yamada udelay(9);
4273fd784f7SMasahiro Yamada reset_control_deassert(priv->rst_hw);
4283fd784f7SMasahiro Yamada /* For eMMC, minimum is 200us but give it 300us for good measure */
4293fd784f7SMasahiro Yamada usleep_range(300, 1000);
4303fd784f7SMasahiro Yamada }
4313fd784f7SMasahiro Yamada
uniphier_sd_speed_switch(struct tmio_mmc_host * host)4322cda1de0SKunihiko Hayashi static void uniphier_sd_speed_switch(struct tmio_mmc_host *host)
4332cda1de0SKunihiko Hayashi {
4342cda1de0SKunihiko Hayashi struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
4352cda1de0SKunihiko Hayashi unsigned int offset;
4362cda1de0SKunihiko Hayashi u32 val = 0;
4372cda1de0SKunihiko Hayashi
4382cda1de0SKunihiko Hayashi if (!(host->mmc->caps & MMC_CAP_UHS))
4392cda1de0SKunihiko Hayashi return;
4402cda1de0SKunihiko Hayashi
4412cda1de0SKunihiko Hayashi if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR50 ||
4422cda1de0SKunihiko Hayashi host->mmc->ios.timing == MMC_TIMING_UHS_SDR104)
4432cda1de0SKunihiko Hayashi val = UNIPHIER_SDCTRL_MODE_SDRSEL;
4442cda1de0SKunihiko Hayashi
4452cda1de0SKunihiko Hayashi offset = UNIPHIER_SDCTRL_CHOFFSET * priv->sdctrl_ch
4462cda1de0SKunihiko Hayashi + UNIPHIER_SDCTRL_MODE;
4472cda1de0SKunihiko Hayashi regmap_write_bits(priv->sdctrl_regmap, offset,
4482cda1de0SKunihiko Hayashi UNIPHIER_SDCTRL_MODE_SDRSEL, val);
4492cda1de0SKunihiko Hayashi }
4502cda1de0SKunihiko Hayashi
uniphier_sd_uhs_enable(struct tmio_mmc_host * host,bool uhs_en)4511c325ed9SKunihiko Hayashi static void uniphier_sd_uhs_enable(struct tmio_mmc_host *host, bool uhs_en)
4521c325ed9SKunihiko Hayashi {
4531c325ed9SKunihiko Hayashi struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
4541c325ed9SKunihiko Hayashi unsigned int offset;
4551c325ed9SKunihiko Hayashi u32 val;
4561c325ed9SKunihiko Hayashi
4571c325ed9SKunihiko Hayashi if (!(host->mmc->caps & MMC_CAP_UHS))
4581c325ed9SKunihiko Hayashi return;
4591c325ed9SKunihiko Hayashi
4601c325ed9SKunihiko Hayashi val = (uhs_en) ? UNIPHIER_SDCTRL_MODE_UHS1MOD : 0;
4611c325ed9SKunihiko Hayashi
4621c325ed9SKunihiko Hayashi offset = UNIPHIER_SDCTRL_CHOFFSET * priv->sdctrl_ch
4631c325ed9SKunihiko Hayashi + UNIPHIER_SDCTRL_MODE;
4641c325ed9SKunihiko Hayashi regmap_write_bits(priv->sdctrl_regmap, offset,
4651c325ed9SKunihiko Hayashi UNIPHIER_SDCTRL_MODE_UHS1MOD, val);
4661c325ed9SKunihiko Hayashi }
4671c325ed9SKunihiko Hayashi
uniphier_sd_set_clock(struct tmio_mmc_host * host,unsigned int clock)4683fd784f7SMasahiro Yamada static void uniphier_sd_set_clock(struct tmio_mmc_host *host,
4693fd784f7SMasahiro Yamada unsigned int clock)
4703fd784f7SMasahiro Yamada {
4713fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
4723fd784f7SMasahiro Yamada unsigned long divisor;
4733fd784f7SMasahiro Yamada u32 tmp;
4743fd784f7SMasahiro Yamada
4753fd784f7SMasahiro Yamada tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
4763fd784f7SMasahiro Yamada
4773fd784f7SMasahiro Yamada /* stop the clock before changing its rate to avoid a glitch signal */
4783fd784f7SMasahiro Yamada tmp &= ~CLK_CTL_SCLKEN;
4793fd784f7SMasahiro Yamada writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
4803fd784f7SMasahiro Yamada
4812cda1de0SKunihiko Hayashi uniphier_sd_speed_switch(host);
4822cda1de0SKunihiko Hayashi
4833fd784f7SMasahiro Yamada if (clock == 0)
4843fd784f7SMasahiro Yamada return;
4853fd784f7SMasahiro Yamada
4863fd784f7SMasahiro Yamada tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024;
4873fd784f7SMasahiro Yamada tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1;
4883fd784f7SMasahiro Yamada tmp &= ~CLK_CTL_DIV_MASK;
4893fd784f7SMasahiro Yamada
4903fd784f7SMasahiro Yamada divisor = priv->clk_rate / clock;
4913fd784f7SMasahiro Yamada
4923fd784f7SMasahiro Yamada /*
4933fd784f7SMasahiro Yamada * In the original IP, bit[7:0] represents the divisor.
4943fd784f7SMasahiro Yamada * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2
4953fd784f7SMasahiro Yamada *
4963fd784f7SMasahiro Yamada * The IP does not define a way to achieve 1/1. For UniPhier variants,
4973fd784f7SMasahiro Yamada * bit10 is used for 1/1. Newer versions of UniPhier variants use
4983fd784f7SMasahiro Yamada * bit16 for 1/1024.
4993fd784f7SMasahiro Yamada */
5003fd784f7SMasahiro Yamada if (divisor <= 1)
5013fd784f7SMasahiro Yamada tmp |= UNIPHIER_SD_CLK_CTL_DIV1;
5023fd784f7SMasahiro Yamada else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512)
5033fd784f7SMasahiro Yamada tmp |= UNIPHIER_SD_CLK_CTL_DIV1024;
5043fd784f7SMasahiro Yamada else
5053fd784f7SMasahiro Yamada tmp |= roundup_pow_of_two(divisor) >> 2;
5063fd784f7SMasahiro Yamada
5073fd784f7SMasahiro Yamada writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
5083fd784f7SMasahiro Yamada
5093fd784f7SMasahiro Yamada tmp |= CLK_CTL_SCLKEN;
5103fd784f7SMasahiro Yamada writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
5113fd784f7SMasahiro Yamada }
5123fd784f7SMasahiro Yamada
uniphier_sd_host_init(struct tmio_mmc_host * host)5133fd784f7SMasahiro Yamada static void uniphier_sd_host_init(struct tmio_mmc_host *host)
5143fd784f7SMasahiro Yamada {
5153fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
5163fd784f7SMasahiro Yamada u32 val;
5173fd784f7SMasahiro Yamada
5183fd784f7SMasahiro Yamada /*
5193fd784f7SMasahiro Yamada * Connected to 32bit AXI.
5203fd784f7SMasahiro Yamada * This register holds settings for SoC-specific internal bus
5213fd784f7SMasahiro Yamada * connection. What is worse, the register spec was changed,
5223fd784f7SMasahiro Yamada * breaking the backward compatibility. Write an appropriate
5233fd784f7SMasahiro Yamada * value depending on a flag associated with a compatible string.
5243fd784f7SMasahiro Yamada */
5253fd784f7SMasahiro Yamada if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
5263fd784f7SMasahiro Yamada val = 0x00000101;
5273fd784f7SMasahiro Yamada else
5283fd784f7SMasahiro Yamada val = 0x00000000;
5293fd784f7SMasahiro Yamada
5303fd784f7SMasahiro Yamada writel(val, host->ctl + UNIPHIER_SD_HOST_MODE);
5313fd784f7SMasahiro Yamada
5323fd784f7SMasahiro Yamada val = 0;
5333fd784f7SMasahiro Yamada /*
5343fd784f7SMasahiro Yamada * If supported, the controller can automatically
5353fd784f7SMasahiro Yamada * enable/disable the clock line to the card.
5363fd784f7SMasahiro Yamada */
5373fd784f7SMasahiro Yamada if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
5383fd784f7SMasahiro Yamada val |= UNIPHIER_SD_CLKCTL_OFFEN;
5393fd784f7SMasahiro Yamada
5403fd784f7SMasahiro Yamada writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
5413fd784f7SMasahiro Yamada }
5423fd784f7SMasahiro Yamada
uniphier_sd_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)5433fd784f7SMasahiro Yamada static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc,
5443fd784f7SMasahiro Yamada struct mmc_ios *ios)
5453fd784f7SMasahiro Yamada {
5463fd784f7SMasahiro Yamada struct tmio_mmc_host *host = mmc_priv(mmc);
5473fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
5488e9a9936SUlf Hansson struct pinctrl_state *pinstate = NULL;
5493fd784f7SMasahiro Yamada u32 val, tmp;
5501c325ed9SKunihiko Hayashi bool uhs_en;
5513fd784f7SMasahiro Yamada
5523fd784f7SMasahiro Yamada switch (ios->signal_voltage) {
5533fd784f7SMasahiro Yamada case MMC_SIGNAL_VOLTAGE_330:
5543fd784f7SMasahiro Yamada val = UNIPHIER_SD_VOLT_330;
5551c325ed9SKunihiko Hayashi uhs_en = false;
5563fd784f7SMasahiro Yamada break;
5573fd784f7SMasahiro Yamada case MMC_SIGNAL_VOLTAGE_180:
5583fd784f7SMasahiro Yamada val = UNIPHIER_SD_VOLT_180;
5593fd784f7SMasahiro Yamada pinstate = priv->pinstate_uhs;
5601c325ed9SKunihiko Hayashi uhs_en = true;
5613fd784f7SMasahiro Yamada break;
5623fd784f7SMasahiro Yamada default:
5633fd784f7SMasahiro Yamada return -ENOTSUPP;
5643fd784f7SMasahiro Yamada }
5653fd784f7SMasahiro Yamada
5663fd784f7SMasahiro Yamada tmp = readl(host->ctl + UNIPHIER_SD_VOLT);
5673fd784f7SMasahiro Yamada tmp &= ~UNIPHIER_SD_VOLT_MASK;
5683fd784f7SMasahiro Yamada tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val);
5693fd784f7SMasahiro Yamada writel(tmp, host->ctl + UNIPHIER_SD_VOLT);
5703fd784f7SMasahiro Yamada
5718e9a9936SUlf Hansson if (pinstate)
5723fd784f7SMasahiro Yamada pinctrl_select_state(priv->pinctrl, pinstate);
5738e9a9936SUlf Hansson else
5748e9a9936SUlf Hansson pinctrl_select_default_state(mmc_dev(mmc));
5753fd784f7SMasahiro Yamada
5761c325ed9SKunihiko Hayashi uniphier_sd_uhs_enable(host, uhs_en);
5771c325ed9SKunihiko Hayashi
5783fd784f7SMasahiro Yamada return 0;
5793fd784f7SMasahiro Yamada }
5803fd784f7SMasahiro Yamada
uniphier_sd_uhs_init(struct tmio_mmc_host * host)5811c325ed9SKunihiko Hayashi static int uniphier_sd_uhs_init(struct tmio_mmc_host *host)
5823fd784f7SMasahiro Yamada {
5831c325ed9SKunihiko Hayashi struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
5841c325ed9SKunihiko Hayashi struct device *dev = &host->pdev->dev;
5851c325ed9SKunihiko Hayashi struct device_node *np = dev->of_node;
5861c325ed9SKunihiko Hayashi struct of_phandle_args args;
5871c325ed9SKunihiko Hayashi int ret;
5881c325ed9SKunihiko Hayashi
5893fd784f7SMasahiro Yamada priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc));
5903fd784f7SMasahiro Yamada if (IS_ERR(priv->pinctrl))
5913fd784f7SMasahiro Yamada return PTR_ERR(priv->pinctrl);
5923fd784f7SMasahiro Yamada
5933fd784f7SMasahiro Yamada priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs");
5943fd784f7SMasahiro Yamada if (IS_ERR(priv->pinstate_uhs))
5953fd784f7SMasahiro Yamada return PTR_ERR(priv->pinstate_uhs);
5963fd784f7SMasahiro Yamada
5971c325ed9SKunihiko Hayashi ret = of_parse_phandle_with_fixed_args(np,
5981c325ed9SKunihiko Hayashi "socionext,syscon-uhs-mode",
5991c325ed9SKunihiko Hayashi 1, 0, &args);
6001c325ed9SKunihiko Hayashi if (ret) {
6011c325ed9SKunihiko Hayashi dev_err(dev, "Can't get syscon-uhs-mode property\n");
6021c325ed9SKunihiko Hayashi return ret;
6031c325ed9SKunihiko Hayashi }
6041c325ed9SKunihiko Hayashi priv->sdctrl_regmap = syscon_node_to_regmap(args.np);
6051c325ed9SKunihiko Hayashi of_node_put(args.np);
6061c325ed9SKunihiko Hayashi if (IS_ERR(priv->sdctrl_regmap)) {
6071c325ed9SKunihiko Hayashi dev_err(dev, "Can't map syscon-uhs-mode\n");
6081c325ed9SKunihiko Hayashi return PTR_ERR(priv->sdctrl_regmap);
6091c325ed9SKunihiko Hayashi }
6101c325ed9SKunihiko Hayashi priv->sdctrl_ch = args.args[0];
6113fd784f7SMasahiro Yamada
6123fd784f7SMasahiro Yamada return 0;
6133fd784f7SMasahiro Yamada }
6143fd784f7SMasahiro Yamada
uniphier_sd_probe(struct platform_device * pdev)6153fd784f7SMasahiro Yamada static int uniphier_sd_probe(struct platform_device *pdev)
6163fd784f7SMasahiro Yamada {
6173fd784f7SMasahiro Yamada struct device *dev = &pdev->dev;
6183fd784f7SMasahiro Yamada struct uniphier_sd_priv *priv;
6193fd784f7SMasahiro Yamada struct tmio_mmc_data *tmio_data;
6203fd784f7SMasahiro Yamada struct tmio_mmc_host *host;
6213fd784f7SMasahiro Yamada int irq, ret;
6223fd784f7SMasahiro Yamada
6233fd784f7SMasahiro Yamada irq = platform_get_irq(pdev, 0);
6249a7957d0SStephen Boyd if (irq < 0)
6253fd784f7SMasahiro Yamada return irq;
6263fd784f7SMasahiro Yamada
6273fd784f7SMasahiro Yamada priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
6283fd784f7SMasahiro Yamada if (!priv)
6293fd784f7SMasahiro Yamada return -ENOMEM;
6303fd784f7SMasahiro Yamada
6313fd784f7SMasahiro Yamada priv->caps = (unsigned long)of_device_get_match_data(dev);
6323fd784f7SMasahiro Yamada
6333fd784f7SMasahiro Yamada priv->clk = devm_clk_get(dev, NULL);
6343fd784f7SMasahiro Yamada if (IS_ERR(priv->clk)) {
6353fd784f7SMasahiro Yamada dev_err(dev, "failed to get clock\n");
6363fd784f7SMasahiro Yamada return PTR_ERR(priv->clk);
6373fd784f7SMasahiro Yamada }
6383fd784f7SMasahiro Yamada
6393fd784f7SMasahiro Yamada priv->rst = devm_reset_control_get_shared(dev, "host");
6403fd784f7SMasahiro Yamada if (IS_ERR(priv->rst)) {
6413fd784f7SMasahiro Yamada dev_err(dev, "failed to get host reset\n");
6423fd784f7SMasahiro Yamada return PTR_ERR(priv->rst);
6433fd784f7SMasahiro Yamada }
6443fd784f7SMasahiro Yamada
6453fd784f7SMasahiro Yamada /* old version has one more reset */
6463fd784f7SMasahiro Yamada if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) {
6473fd784f7SMasahiro Yamada priv->rst_br = devm_reset_control_get_shared(dev, "bridge");
6483fd784f7SMasahiro Yamada if (IS_ERR(priv->rst_br)) {
6493fd784f7SMasahiro Yamada dev_err(dev, "failed to get bridge reset\n");
6503fd784f7SMasahiro Yamada return PTR_ERR(priv->rst_br);
6513fd784f7SMasahiro Yamada }
6523fd784f7SMasahiro Yamada }
6533fd784f7SMasahiro Yamada
6543fd784f7SMasahiro Yamada tmio_data = &priv->tmio_data;
6553fd784f7SMasahiro Yamada tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT;
65630ae3e13SWolfram Sang tmio_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
6573fd784f7SMasahiro Yamada
6583fd784f7SMasahiro Yamada host = tmio_mmc_host_alloc(pdev, tmio_data);
6593fd784f7SMasahiro Yamada if (IS_ERR(host))
6603fd784f7SMasahiro Yamada return PTR_ERR(host);
6613fd784f7SMasahiro Yamada
6623fd784f7SMasahiro Yamada if (host->mmc->caps & MMC_CAP_HW_RESET) {
6633fd784f7SMasahiro Yamada priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw");
6643fd784f7SMasahiro Yamada if (IS_ERR(priv->rst_hw)) {
6653fd784f7SMasahiro Yamada dev_err(dev, "failed to get hw reset\n");
6663fd784f7SMasahiro Yamada ret = PTR_ERR(priv->rst_hw);
6673fd784f7SMasahiro Yamada goto free_host;
6683fd784f7SMasahiro Yamada }
66932f18e59SWolfram Sang host->ops.card_hw_reset = uniphier_sd_hw_reset;
6703fd784f7SMasahiro Yamada }
6713fd784f7SMasahiro Yamada
6723fd784f7SMasahiro Yamada if (host->mmc->caps & MMC_CAP_UHS) {
6731c325ed9SKunihiko Hayashi ret = uniphier_sd_uhs_init(host);
6743fd784f7SMasahiro Yamada if (ret) {
6753fd784f7SMasahiro Yamada dev_warn(dev,
6763fd784f7SMasahiro Yamada "failed to setup UHS (error %d). Disabling UHS.",
6773fd784f7SMasahiro Yamada ret);
6783fd784f7SMasahiro Yamada host->mmc->caps &= ~MMC_CAP_UHS;
6791c325ed9SKunihiko Hayashi } else {
6801c325ed9SKunihiko Hayashi host->ops.start_signal_voltage_switch =
6811c325ed9SKunihiko Hayashi uniphier_sd_start_signal_voltage_switch;
6823fd784f7SMasahiro Yamada }
6833fd784f7SMasahiro Yamada }
6843fd784f7SMasahiro Yamada
6853fd784f7SMasahiro Yamada if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
6863fd784f7SMasahiro Yamada host->dma_ops = &uniphier_sd_internal_dma_ops;
6873fd784f7SMasahiro Yamada else
6883fd784f7SMasahiro Yamada host->dma_ops = &uniphier_sd_external_dma_ops;
6893fd784f7SMasahiro Yamada
6903fd784f7SMasahiro Yamada host->bus_shift = 1;
6913fd784f7SMasahiro Yamada host->clk_enable = uniphier_sd_clk_enable;
6923fd784f7SMasahiro Yamada host->clk_disable = uniphier_sd_clk_disable;
6933fd784f7SMasahiro Yamada host->set_clock = uniphier_sd_set_clock;
6943fd784f7SMasahiro Yamada
6953fd784f7SMasahiro Yamada ret = uniphier_sd_clk_enable(host);
6963fd784f7SMasahiro Yamada if (ret)
6973fd784f7SMasahiro Yamada goto free_host;
6983fd784f7SMasahiro Yamada
6993fd784f7SMasahiro Yamada uniphier_sd_host_init(host);
7003fd784f7SMasahiro Yamada
7013fd784f7SMasahiro Yamada tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34;
7023fd784f7SMasahiro Yamada if (host->mmc->caps & MMC_CAP_UHS)
7033fd784f7SMasahiro Yamada tmio_data->ocr_mask |= MMC_VDD_165_195;
7043fd784f7SMasahiro Yamada
7053fd784f7SMasahiro Yamada tmio_data->max_segs = 1;
7063fd784f7SMasahiro Yamada tmio_data->max_blk_count = U16_MAX;
7073fd784f7SMasahiro Yamada
708a5d8de1cSWolfram Sang sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_ALL);
7093fd784f7SMasahiro Yamada
7105d1f42e1SMasahiro Yamada ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED,
7115d1f42e1SMasahiro Yamada dev_name(dev), host);
7125d1f42e1SMasahiro Yamada if (ret)
713a5d8de1cSWolfram Sang goto disable_clk;
714a5d8de1cSWolfram Sang
715a5d8de1cSWolfram Sang ret = tmio_mmc_host_probe(host);
716a5d8de1cSWolfram Sang if (ret)
717a5d8de1cSWolfram Sang goto disable_clk;
7185d1f42e1SMasahiro Yamada
7193fd784f7SMasahiro Yamada return 0;
7203fd784f7SMasahiro Yamada
721b03aec1cSChristophe JAILLET disable_clk:
722b03aec1cSChristophe JAILLET uniphier_sd_clk_disable(host);
7233fd784f7SMasahiro Yamada free_host:
7243fd784f7SMasahiro Yamada tmio_mmc_host_free(host);
7253fd784f7SMasahiro Yamada
7263fd784f7SMasahiro Yamada return ret;
7273fd784f7SMasahiro Yamada }
7283fd784f7SMasahiro Yamada
uniphier_sd_remove(struct platform_device * pdev)729*8d777034SYangtao Li static void uniphier_sd_remove(struct platform_device *pdev)
7303fd784f7SMasahiro Yamada {
7313fd784f7SMasahiro Yamada struct tmio_mmc_host *host = platform_get_drvdata(pdev);
7323fd784f7SMasahiro Yamada
7333fd784f7SMasahiro Yamada tmio_mmc_host_remove(host);
7343fd784f7SMasahiro Yamada uniphier_sd_clk_disable(host);
735e29c8485SChristophe JAILLET tmio_mmc_host_free(host);
7363fd784f7SMasahiro Yamada }
7373fd784f7SMasahiro Yamada
7383fd784f7SMasahiro Yamada static const struct of_device_id uniphier_sd_match[] = {
7393fd784f7SMasahiro Yamada {
7403fd784f7SMasahiro Yamada .compatible = "socionext,uniphier-sd-v2.91",
7413fd784f7SMasahiro Yamada },
7423fd784f7SMasahiro Yamada {
7433fd784f7SMasahiro Yamada .compatible = "socionext,uniphier-sd-v3.1",
7443fd784f7SMasahiro Yamada .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP |
7453fd784f7SMasahiro Yamada UNIPHIER_SD_CAP_BROKEN_DMA_RX),
7463fd784f7SMasahiro Yamada },
7473fd784f7SMasahiro Yamada {
7483fd784f7SMasahiro Yamada .compatible = "socionext,uniphier-sd-v3.1.1",
7493fd784f7SMasahiro Yamada .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP,
7503fd784f7SMasahiro Yamada },
7513fd784f7SMasahiro Yamada { /* sentinel */ }
7523fd784f7SMasahiro Yamada };
7533fd784f7SMasahiro Yamada MODULE_DEVICE_TABLE(of, uniphier_sd_match);
7543fd784f7SMasahiro Yamada
7553fd784f7SMasahiro Yamada static struct platform_driver uniphier_sd_driver = {
7563fd784f7SMasahiro Yamada .probe = uniphier_sd_probe,
757*8d777034SYangtao Li .remove_new = uniphier_sd_remove,
7583fd784f7SMasahiro Yamada .driver = {
7593fd784f7SMasahiro Yamada .name = "uniphier-sd",
760d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
7613fd784f7SMasahiro Yamada .of_match_table = uniphier_sd_match,
7623fd784f7SMasahiro Yamada },
7633fd784f7SMasahiro Yamada };
7643fd784f7SMasahiro Yamada module_platform_driver(uniphier_sd_driver);
7653fd784f7SMasahiro Yamada
7663fd784f7SMasahiro Yamada MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
7673fd784f7SMasahiro Yamada MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver");
7683fd784f7SMasahiro Yamada MODULE_LICENSE("GPL v2");
769