1 /* 2 * Driver for sunxi SD/MMC host controllers 3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 6 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch> 7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 8 * (C) Copyright 2017 Sootech SA 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/clk/sunxi-ng.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/err.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/mmc/card.h> 26 #include <linux/mmc/core.h> 27 #include <linux/mmc/host.h> 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/sd.h> 30 #include <linux/mmc/sdio.h> 31 #include <linux/mmc/slot-gpio.h> 32 #include <linux/module.h> 33 #include <linux/of_address.h> 34 #include <linux/of_platform.h> 35 #include <linux/platform_device.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/reset.h> 39 #include <linux/scatterlist.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 43 /* register offset definitions */ 44 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 45 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 46 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 47 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 48 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 49 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 50 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 51 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 52 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 53 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 54 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 55 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 56 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 57 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 58 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 59 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 60 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 61 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 62 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 63 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 64 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 65 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 66 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 67 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 68 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 69 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 70 #define SDXC_REG_CHDA (0x90) 71 #define SDXC_REG_CBDA (0x94) 72 73 /* New registers introduced in A64 */ 74 #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ 75 #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ 76 #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ 77 #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ 78 #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ 79 80 #define mmc_readl(host, reg) \ 81 readl((host)->reg_base + SDXC_##reg) 82 #define mmc_writel(host, reg, value) \ 83 writel((value), (host)->reg_base + SDXC_##reg) 84 85 /* global control register bits */ 86 #define SDXC_SOFT_RESET BIT(0) 87 #define SDXC_FIFO_RESET BIT(1) 88 #define SDXC_DMA_RESET BIT(2) 89 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 90 #define SDXC_DMA_ENABLE_BIT BIT(5) 91 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 92 #define SDXC_POSEDGE_LATCH_DATA BIT(9) 93 #define SDXC_DDR_MODE BIT(10) 94 #define SDXC_MEMORY_ACCESS_DONE BIT(29) 95 #define SDXC_ACCESS_DONE_DIRECT BIT(30) 96 #define SDXC_ACCESS_BY_AHB BIT(31) 97 #define SDXC_ACCESS_BY_DMA (0 << 31) 98 #define SDXC_HARDWARE_RESET \ 99 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 100 101 /* clock control bits */ 102 #define SDXC_MASK_DATA0 BIT(31) 103 #define SDXC_CARD_CLOCK_ON BIT(16) 104 #define SDXC_LOW_POWER_ON BIT(17) 105 106 /* bus width */ 107 #define SDXC_WIDTH1 0 108 #define SDXC_WIDTH4 1 109 #define SDXC_WIDTH8 2 110 111 /* smc command bits */ 112 #define SDXC_RESP_EXPIRE BIT(6) 113 #define SDXC_LONG_RESPONSE BIT(7) 114 #define SDXC_CHECK_RESPONSE_CRC BIT(8) 115 #define SDXC_DATA_EXPIRE BIT(9) 116 #define SDXC_WRITE BIT(10) 117 #define SDXC_SEQUENCE_MODE BIT(11) 118 #define SDXC_SEND_AUTO_STOP BIT(12) 119 #define SDXC_WAIT_PRE_OVER BIT(13) 120 #define SDXC_STOP_ABORT_CMD BIT(14) 121 #define SDXC_SEND_INIT_SEQUENCE BIT(15) 122 #define SDXC_UPCLK_ONLY BIT(21) 123 #define SDXC_READ_CEATA_DEV BIT(22) 124 #define SDXC_CCS_EXPIRE BIT(23) 125 #define SDXC_ENABLE_BIT_BOOT BIT(24) 126 #define SDXC_ALT_BOOT_OPTIONS BIT(25) 127 #define SDXC_BOOT_ACK_EXPIRE BIT(26) 128 #define SDXC_BOOT_ABORT BIT(27) 129 #define SDXC_VOLTAGE_SWITCH BIT(28) 130 #define SDXC_USE_HOLD_REGISTER BIT(29) 131 #define SDXC_START BIT(31) 132 133 /* interrupt bits */ 134 #define SDXC_RESP_ERROR BIT(1) 135 #define SDXC_COMMAND_DONE BIT(2) 136 #define SDXC_DATA_OVER BIT(3) 137 #define SDXC_TX_DATA_REQUEST BIT(4) 138 #define SDXC_RX_DATA_REQUEST BIT(5) 139 #define SDXC_RESP_CRC_ERROR BIT(6) 140 #define SDXC_DATA_CRC_ERROR BIT(7) 141 #define SDXC_RESP_TIMEOUT BIT(8) 142 #define SDXC_DATA_TIMEOUT BIT(9) 143 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 144 #define SDXC_FIFO_RUN_ERROR BIT(11) 145 #define SDXC_HARD_WARE_LOCKED BIT(12) 146 #define SDXC_START_BIT_ERROR BIT(13) 147 #define SDXC_AUTO_COMMAND_DONE BIT(14) 148 #define SDXC_END_BIT_ERROR BIT(15) 149 #define SDXC_SDIO_INTERRUPT BIT(16) 150 #define SDXC_CARD_INSERT BIT(30) 151 #define SDXC_CARD_REMOVE BIT(31) 152 #define SDXC_INTERRUPT_ERROR_BIT \ 153 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 154 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 155 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 156 #define SDXC_INTERRUPT_DONE_BIT \ 157 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 158 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 159 160 /* status */ 161 #define SDXC_RXWL_FLAG BIT(0) 162 #define SDXC_TXWL_FLAG BIT(1) 163 #define SDXC_FIFO_EMPTY BIT(2) 164 #define SDXC_FIFO_FULL BIT(3) 165 #define SDXC_CARD_PRESENT BIT(8) 166 #define SDXC_CARD_DATA_BUSY BIT(9) 167 #define SDXC_DATA_FSM_BUSY BIT(10) 168 #define SDXC_DMA_REQUEST BIT(31) 169 #define SDXC_FIFO_SIZE 16 170 171 /* Function select */ 172 #define SDXC_CEATA_ON (0xceaa << 16) 173 #define SDXC_SEND_IRQ_RESPONSE BIT(0) 174 #define SDXC_SDIO_READ_WAIT BIT(1) 175 #define SDXC_ABORT_READ_DATA BIT(2) 176 #define SDXC_SEND_CCSD BIT(8) 177 #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 178 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 179 180 /* IDMA controller bus mod bit field */ 181 #define SDXC_IDMAC_SOFT_RESET BIT(0) 182 #define SDXC_IDMAC_FIX_BURST BIT(1) 183 #define SDXC_IDMAC_IDMA_ON BIT(7) 184 #define SDXC_IDMAC_REFETCH_DES BIT(31) 185 186 /* IDMA status bit field */ 187 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 188 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 189 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 190 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 191 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 192 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 193 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 194 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 195 #define SDXC_IDMAC_IDLE (0 << 13) 196 #define SDXC_IDMAC_SUSPEND (1 << 13) 197 #define SDXC_IDMAC_DESC_READ (2 << 13) 198 #define SDXC_IDMAC_DESC_CHECK (3 << 13) 199 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 200 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 201 #define SDXC_IDMAC_READ (6 << 13) 202 #define SDXC_IDMAC_WRITE (7 << 13) 203 #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 204 205 /* 206 * If the idma-des-size-bits of property is ie 13, bufsize bits are: 207 * Bits 0-12: buf1 size 208 * Bits 13-25: buf2 size 209 * Bits 26-31: not used 210 * Since we only ever set buf1 size, we can simply store it directly. 211 */ 212 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 213 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 214 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 215 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 216 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 217 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 218 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 219 220 #define SDXC_CLK_400K 0 221 #define SDXC_CLK_25M 1 222 #define SDXC_CLK_50M 2 223 #define SDXC_CLK_50M_DDR 3 224 #define SDXC_CLK_50M_DDR_8BIT 4 225 226 #define SDXC_2X_TIMING_MODE BIT(31) 227 228 #define SDXC_CAL_START BIT(15) 229 #define SDXC_CAL_DONE BIT(14) 230 #define SDXC_CAL_DL_SHIFT 8 231 #define SDXC_CAL_DL_SW_EN BIT(7) 232 #define SDXC_CAL_DL_SW_SHIFT 0 233 #define SDXC_CAL_DL_MASK 0x3f 234 235 #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/ 236 237 struct sunxi_mmc_clk_delay { 238 u32 output; 239 u32 sample; 240 }; 241 242 struct sunxi_idma_des { 243 __le32 config; 244 __le32 buf_size; 245 __le32 buf_addr_ptr1; 246 __le32 buf_addr_ptr2; 247 }; 248 249 struct sunxi_mmc_cfg { 250 u32 idma_des_size_bits; 251 const struct sunxi_mmc_clk_delay *clk_delays; 252 253 /* does the IP block support autocalibration? */ 254 bool can_calibrate; 255 256 /* Does DATA0 needs to be masked while the clock is updated */ 257 bool mask_data0; 258 259 /* 260 * hardware only supports new timing mode, either due to lack of 261 * a mode switch in the clock controller, or the mmc controller 262 * is permanently configured in the new timing mode, without the 263 * NTSR mode switch. 264 */ 265 bool needs_new_timings; 266 267 /* clock hardware can switch between old and new timing modes */ 268 bool ccu_has_timings_switch; 269 }; 270 271 struct sunxi_mmc_host { 272 struct device *dev; 273 struct mmc_host *mmc; 274 struct reset_control *reset; 275 const struct sunxi_mmc_cfg *cfg; 276 277 /* IO mapping base */ 278 void __iomem *reg_base; 279 280 /* clock management */ 281 struct clk *clk_ahb; 282 struct clk *clk_mmc; 283 struct clk *clk_sample; 284 struct clk *clk_output; 285 286 /* irq */ 287 spinlock_t lock; 288 int irq; 289 u32 int_sum; 290 u32 sdio_imask; 291 292 /* dma */ 293 dma_addr_t sg_dma; 294 void *sg_cpu; 295 bool wait_dma; 296 297 struct mmc_request *mrq; 298 struct mmc_request *manual_stop_mrq; 299 int ferror; 300 301 /* vqmmc */ 302 bool vqmmc_enabled; 303 304 /* timings */ 305 bool use_new_timings; 306 }; 307 308 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 309 { 310 unsigned long expire = jiffies + msecs_to_jiffies(250); 311 u32 rval; 312 313 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 314 do { 315 rval = mmc_readl(host, REG_GCTRL); 316 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 317 318 if (rval & SDXC_HARDWARE_RESET) { 319 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 320 return -EIO; 321 } 322 323 return 0; 324 } 325 326 static int sunxi_mmc_init_host(struct sunxi_mmc_host *host) 327 { 328 u32 rval; 329 330 if (sunxi_mmc_reset_host(host)) 331 return -EIO; 332 333 /* 334 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8 335 * 336 * TODO: sun9i has a larger FIFO and supports higher trigger values 337 */ 338 mmc_writel(host, REG_FTRGL, 0x20070008); 339 /* Maximum timeout value */ 340 mmc_writel(host, REG_TMOUT, 0xffffffff); 341 /* Unmask SDIO interrupt if needed */ 342 mmc_writel(host, REG_IMASK, host->sdio_imask); 343 /* Clear all pending interrupts */ 344 mmc_writel(host, REG_RINTR, 0xffffffff); 345 /* Debug register? undocumented */ 346 mmc_writel(host, REG_DBGC, 0xdeb); 347 /* Enable CEATA support */ 348 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 349 /* Set DMA descriptor list base address */ 350 mmc_writel(host, REG_DLBA, host->sg_dma); 351 352 rval = mmc_readl(host, REG_GCTRL); 353 rval |= SDXC_INTERRUPT_ENABLE_BIT; 354 /* Undocumented, but found in Allwinner code */ 355 rval &= ~SDXC_ACCESS_DONE_DIRECT; 356 mmc_writel(host, REG_GCTRL, rval); 357 358 return 0; 359 } 360 361 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 362 struct mmc_data *data) 363 { 364 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 365 dma_addr_t next_desc = host->sg_dma; 366 int i, max_len = (1 << host->cfg->idma_des_size_bits); 367 368 for (i = 0; i < data->sg_len; i++) { 369 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | 370 SDXC_IDMAC_DES0_OWN | 371 SDXC_IDMAC_DES0_DIC); 372 373 if (data->sg[i].length == max_len) 374 pdes[i].buf_size = 0; /* 0 == max_len */ 375 else 376 pdes[i].buf_size = cpu_to_le32(data->sg[i].length); 377 378 next_desc += sizeof(struct sunxi_idma_des); 379 pdes[i].buf_addr_ptr1 = 380 cpu_to_le32(sg_dma_address(&data->sg[i])); 381 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc); 382 } 383 384 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); 385 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | 386 SDXC_IDMAC_DES0_ER); 387 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); 388 pdes[i - 1].buf_addr_ptr2 = 0; 389 390 /* 391 * Avoid the io-store starting the idmac hitting io-mem before the 392 * descriptors hit the main-mem. 393 */ 394 wmb(); 395 } 396 397 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 398 struct mmc_data *data) 399 { 400 u32 i, dma_len; 401 struct scatterlist *sg; 402 403 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 404 mmc_get_dma_dir(data)); 405 if (dma_len == 0) { 406 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 407 return -ENOMEM; 408 } 409 410 for_each_sg(data->sg, sg, data->sg_len, i) { 411 if (sg->offset & 3 || sg->length & 3) { 412 dev_err(mmc_dev(host->mmc), 413 "unaligned scatterlist: os %x length %d\n", 414 sg->offset, sg->length); 415 return -EINVAL; 416 } 417 } 418 419 return 0; 420 } 421 422 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 423 struct mmc_data *data) 424 { 425 u32 rval; 426 427 sunxi_mmc_init_idma_des(host, data); 428 429 rval = mmc_readl(host, REG_GCTRL); 430 rval |= SDXC_DMA_ENABLE_BIT; 431 mmc_writel(host, REG_GCTRL, rval); 432 rval |= SDXC_DMA_RESET; 433 mmc_writel(host, REG_GCTRL, rval); 434 435 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 436 437 if (!(data->flags & MMC_DATA_WRITE)) 438 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 439 440 mmc_writel(host, REG_DMAC, 441 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 442 } 443 444 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 445 struct mmc_request *req) 446 { 447 u32 arg, cmd_val, ri; 448 unsigned long expire = jiffies + msecs_to_jiffies(1000); 449 450 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 451 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 452 453 if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 454 cmd_val |= SD_IO_RW_DIRECT; 455 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 456 ((req->cmd->arg >> 28) & 0x7); 457 } else { 458 cmd_val |= MMC_STOP_TRANSMISSION; 459 arg = 0; 460 } 461 462 mmc_writel(host, REG_CARG, arg); 463 mmc_writel(host, REG_CMDR, cmd_val); 464 465 do { 466 ri = mmc_readl(host, REG_RINTR); 467 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 468 time_before(jiffies, expire)); 469 470 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 471 dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 472 if (req->stop) 473 req->stop->resp[0] = -ETIMEDOUT; 474 } else { 475 if (req->stop) 476 req->stop->resp[0] = mmc_readl(host, REG_RESP0); 477 } 478 479 mmc_writel(host, REG_RINTR, 0xffff); 480 } 481 482 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 483 { 484 struct mmc_command *cmd = host->mrq->cmd; 485 struct mmc_data *data = host->mrq->data; 486 487 /* For some cmds timeout is normal with sd/mmc cards */ 488 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 489 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 490 cmd->opcode == SD_IO_RW_DIRECT)) 491 return; 492 493 dev_dbg(mmc_dev(host->mmc), 494 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 495 host->mmc->index, cmd->opcode, 496 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 497 host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 498 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 499 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 500 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 501 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 502 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 503 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 504 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 505 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 506 ); 507 } 508 509 /* Called in interrupt context! */ 510 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 511 { 512 struct mmc_request *mrq = host->mrq; 513 struct mmc_data *data = mrq->data; 514 u32 rval; 515 516 mmc_writel(host, REG_IMASK, host->sdio_imask); 517 mmc_writel(host, REG_IDIE, 0); 518 519 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 520 sunxi_mmc_dump_errinfo(host); 521 mrq->cmd->error = -ETIMEDOUT; 522 523 if (data) { 524 data->error = -ETIMEDOUT; 525 host->manual_stop_mrq = mrq; 526 } 527 528 if (mrq->stop) 529 mrq->stop->error = -ETIMEDOUT; 530 } else { 531 if (mrq->cmd->flags & MMC_RSP_136) { 532 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 533 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 534 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 535 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 536 } else { 537 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 538 } 539 540 if (data) 541 data->bytes_xfered = data->blocks * data->blksz; 542 } 543 544 if (data) { 545 mmc_writel(host, REG_IDST, 0x337); 546 mmc_writel(host, REG_DMAC, 0); 547 rval = mmc_readl(host, REG_GCTRL); 548 rval |= SDXC_DMA_RESET; 549 mmc_writel(host, REG_GCTRL, rval); 550 rval &= ~SDXC_DMA_ENABLE_BIT; 551 mmc_writel(host, REG_GCTRL, rval); 552 rval |= SDXC_FIFO_RESET; 553 mmc_writel(host, REG_GCTRL, rval); 554 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 555 mmc_get_dma_dir(data)); 556 } 557 558 mmc_writel(host, REG_RINTR, 0xffff); 559 560 host->mrq = NULL; 561 host->int_sum = 0; 562 host->wait_dma = false; 563 564 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 565 } 566 567 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 568 { 569 struct sunxi_mmc_host *host = dev_id; 570 struct mmc_request *mrq; 571 u32 msk_int, idma_int; 572 bool finalize = false; 573 bool sdio_int = false; 574 irqreturn_t ret = IRQ_HANDLED; 575 576 spin_lock(&host->lock); 577 578 idma_int = mmc_readl(host, REG_IDST); 579 msk_int = mmc_readl(host, REG_MISTA); 580 581 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 582 host->mrq, msk_int, idma_int); 583 584 mrq = host->mrq; 585 if (mrq) { 586 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 587 host->wait_dma = false; 588 589 host->int_sum |= msk_int; 590 591 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 592 if ((host->int_sum & SDXC_RESP_TIMEOUT) && 593 !(host->int_sum & SDXC_COMMAND_DONE)) 594 mmc_writel(host, REG_IMASK, 595 host->sdio_imask | SDXC_COMMAND_DONE); 596 /* Don't wait for dma on error */ 597 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 598 finalize = true; 599 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 600 !host->wait_dma) 601 finalize = true; 602 } 603 604 if (msk_int & SDXC_SDIO_INTERRUPT) 605 sdio_int = true; 606 607 mmc_writel(host, REG_RINTR, msk_int); 608 mmc_writel(host, REG_IDST, idma_int); 609 610 if (finalize) 611 ret = sunxi_mmc_finalize_request(host); 612 613 spin_unlock(&host->lock); 614 615 if (finalize && ret == IRQ_HANDLED) 616 mmc_request_done(host->mmc, mrq); 617 618 if (sdio_int) 619 mmc_signal_sdio_irq(host->mmc); 620 621 return ret; 622 } 623 624 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 625 { 626 struct sunxi_mmc_host *host = dev_id; 627 struct mmc_request *mrq; 628 unsigned long iflags; 629 630 spin_lock_irqsave(&host->lock, iflags); 631 mrq = host->manual_stop_mrq; 632 spin_unlock_irqrestore(&host->lock, iflags); 633 634 if (!mrq) { 635 dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 636 return IRQ_HANDLED; 637 } 638 639 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 640 641 /* 642 * We will never have more than one outstanding request, 643 * and we do not complete the request until after 644 * we've cleared host->manual_stop_mrq so we do not need to 645 * spin lock this function. 646 * Additionally we have wait states within this function 647 * so having it in a lock is a very bad idea. 648 */ 649 sunxi_mmc_send_manual_stop(host, mrq); 650 651 spin_lock_irqsave(&host->lock, iflags); 652 host->manual_stop_mrq = NULL; 653 spin_unlock_irqrestore(&host->lock, iflags); 654 655 mmc_request_done(host->mmc, mrq); 656 657 return IRQ_HANDLED; 658 } 659 660 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 661 { 662 unsigned long expire = jiffies + msecs_to_jiffies(750); 663 u32 rval; 664 665 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n", 666 oclk_en ? "en" : "dis"); 667 668 rval = mmc_readl(host, REG_CLKCR); 669 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0); 670 671 if (oclk_en) 672 rval |= SDXC_CARD_CLOCK_ON; 673 if (host->cfg->mask_data0) 674 rval |= SDXC_MASK_DATA0; 675 676 mmc_writel(host, REG_CLKCR, rval); 677 678 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 679 mmc_writel(host, REG_CMDR, rval); 680 681 do { 682 rval = mmc_readl(host, REG_CMDR); 683 } while (time_before(jiffies, expire) && (rval & SDXC_START)); 684 685 /* clear irq status bits set by the command */ 686 mmc_writel(host, REG_RINTR, 687 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 688 689 if (rval & SDXC_START) { 690 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 691 return -EIO; 692 } 693 694 if (host->cfg->mask_data0) { 695 rval = mmc_readl(host, REG_CLKCR); 696 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0); 697 } 698 699 return 0; 700 } 701 702 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) 703 { 704 if (!host->cfg->can_calibrate) 705 return 0; 706 707 /* 708 * FIXME: 709 * This is not clear how the calibration is supposed to work 710 * yet. The best rate have been obtained by simply setting the 711 * delay to 0, as Allwinner does in its BSP. 712 * 713 * The only mode that doesn't have such a delay is HS400, that 714 * is in itself a TODO. 715 */ 716 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); 717 718 return 0; 719 } 720 721 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 722 struct mmc_ios *ios, u32 rate) 723 { 724 int index; 725 726 /* clk controller delays not used under new timings mode */ 727 if (host->use_new_timings) 728 return 0; 729 730 /* some old controllers don't support delays */ 731 if (!host->cfg->clk_delays) 732 return 0; 733 734 /* determine delays */ 735 if (rate <= 400000) { 736 index = SDXC_CLK_400K; 737 } else if (rate <= 25000000) { 738 index = SDXC_CLK_25M; 739 } else if (rate <= 52000000) { 740 if (ios->timing != MMC_TIMING_UHS_DDR50 && 741 ios->timing != MMC_TIMING_MMC_DDR52) { 742 index = SDXC_CLK_50M; 743 } else if (ios->bus_width == MMC_BUS_WIDTH_8) { 744 index = SDXC_CLK_50M_DDR_8BIT; 745 } else { 746 index = SDXC_CLK_50M_DDR; 747 } 748 } else { 749 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n"); 750 return -EINVAL; 751 } 752 753 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); 754 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); 755 756 return 0; 757 } 758 759 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 760 struct mmc_ios *ios) 761 { 762 struct mmc_host *mmc = host->mmc; 763 long rate; 764 u32 rval, clock = ios->clock, div = 1; 765 int ret; 766 767 ret = sunxi_mmc_oclk_onoff(host, 0); 768 if (ret) 769 return ret; 770 771 /* Our clock is gated now */ 772 mmc->actual_clock = 0; 773 774 if (!ios->clock) 775 return 0; 776 777 /* 778 * Under the old timing mode, 8 bit DDR requires the module 779 * clock to be double the card clock. Under the new timing 780 * mode, all DDR modes require a doubled module clock. 781 * 782 * We currently only support the standard MMC DDR52 mode. 783 * This block should be updated once support for other DDR 784 * modes is added. 785 */ 786 if (ios->timing == MMC_TIMING_MMC_DDR52 && 787 (host->use_new_timings || 788 ios->bus_width == MMC_BUS_WIDTH_8)) { 789 div = 2; 790 clock <<= 1; 791 } 792 793 if (host->use_new_timings && host->cfg->ccu_has_timings_switch) { 794 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 795 if (ret) { 796 dev_err(mmc_dev(mmc), 797 "error setting new timing mode\n"); 798 return ret; 799 } 800 } 801 802 rate = clk_round_rate(host->clk_mmc, clock); 803 if (rate < 0) { 804 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n", 805 clock, rate); 806 return rate; 807 } 808 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n", 809 clock, rate); 810 811 /* setting clock rate */ 812 ret = clk_set_rate(host->clk_mmc, rate); 813 if (ret) { 814 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n", 815 rate, ret); 816 return ret; 817 } 818 819 /* set internal divider */ 820 rval = mmc_readl(host, REG_CLKCR); 821 rval &= ~0xff; 822 rval |= div - 1; 823 mmc_writel(host, REG_CLKCR, rval); 824 825 /* update card clock rate to account for internal divider */ 826 rate /= div; 827 828 /* 829 * Configure the controller to use the new timing mode if needed. 830 * On controllers that only support the new timing mode, such as 831 * the eMMC controller on the A64, this register does not exist, 832 * and any writes to it are ignored. 833 */ 834 if (host->use_new_timings) { 835 /* Don't touch the delay bits */ 836 rval = mmc_readl(host, REG_SD_NTSR); 837 rval |= SDXC_2X_TIMING_MODE; 838 mmc_writel(host, REG_SD_NTSR, rval); 839 } 840 841 /* sunxi_mmc_clk_set_phase expects the actual card clock rate */ 842 ret = sunxi_mmc_clk_set_phase(host, ios, rate); 843 if (ret) 844 return ret; 845 846 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); 847 if (ret) 848 return ret; 849 850 /* 851 * FIXME: 852 * 853 * In HS400 we'll also need to calibrate the data strobe 854 * signal. This should only happen on the MMC2 controller (at 855 * least on the A64). 856 */ 857 858 ret = sunxi_mmc_oclk_onoff(host, 1); 859 if (ret) 860 return ret; 861 862 /* And we just enabled our clock back */ 863 mmc->actual_clock = rate; 864 865 return 0; 866 } 867 868 static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host, 869 unsigned char width) 870 { 871 switch (width) { 872 case MMC_BUS_WIDTH_1: 873 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 874 break; 875 case MMC_BUS_WIDTH_4: 876 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 877 break; 878 case MMC_BUS_WIDTH_8: 879 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 880 break; 881 } 882 } 883 884 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios) 885 { 886 u32 rval; 887 888 /* set ddr mode */ 889 rval = mmc_readl(host, REG_GCTRL); 890 if (ios->timing == MMC_TIMING_UHS_DDR50 || 891 ios->timing == MMC_TIMING_MMC_DDR52) 892 rval |= SDXC_DDR_MODE; 893 else 894 rval &= ~SDXC_DDR_MODE; 895 mmc_writel(host, REG_GCTRL, rval); 896 897 host->ferror = sunxi_mmc_clk_set_rate(host, ios); 898 /* Android code had a usleep_range(50000, 55000); here */ 899 } 900 901 static void sunxi_mmc_card_power(struct sunxi_mmc_host *host, 902 struct mmc_ios *ios) 903 { 904 struct mmc_host *mmc = host->mmc; 905 906 switch (ios->power_mode) { 907 case MMC_POWER_UP: 908 dev_dbg(mmc_dev(mmc), "Powering card up\n"); 909 910 if (!IS_ERR(mmc->supply.vmmc)) { 911 host->ferror = mmc_regulator_set_ocr(mmc, 912 mmc->supply.vmmc, 913 ios->vdd); 914 if (host->ferror) 915 return; 916 } 917 918 if (!IS_ERR(mmc->supply.vqmmc)) { 919 host->ferror = regulator_enable(mmc->supply.vqmmc); 920 if (host->ferror) { 921 dev_err(mmc_dev(mmc), 922 "failed to enable vqmmc\n"); 923 return; 924 } 925 host->vqmmc_enabled = true; 926 } 927 break; 928 929 case MMC_POWER_OFF: 930 dev_dbg(mmc_dev(mmc), "Powering card off\n"); 931 932 if (!IS_ERR(mmc->supply.vmmc)) 933 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 934 935 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) 936 regulator_disable(mmc->supply.vqmmc); 937 938 host->vqmmc_enabled = false; 939 break; 940 941 default: 942 dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n"); 943 break; 944 } 945 } 946 947 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 948 { 949 struct sunxi_mmc_host *host = mmc_priv(mmc); 950 951 sunxi_mmc_card_power(host, ios); 952 sunxi_mmc_set_bus_width(host, ios->bus_width); 953 sunxi_mmc_set_clk(host, ios); 954 } 955 956 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 957 { 958 /* vqmmc regulator is available */ 959 if (!IS_ERR(mmc->supply.vqmmc)) 960 return mmc_regulator_set_vqmmc(mmc, ios); 961 962 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 963 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) 964 return 0; 965 966 return -EINVAL; 967 } 968 969 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 970 { 971 struct sunxi_mmc_host *host = mmc_priv(mmc); 972 unsigned long flags; 973 u32 imask; 974 975 if (enable) 976 pm_runtime_get_noresume(host->dev); 977 978 spin_lock_irqsave(&host->lock, flags); 979 980 imask = mmc_readl(host, REG_IMASK); 981 if (enable) { 982 host->sdio_imask = SDXC_SDIO_INTERRUPT; 983 imask |= SDXC_SDIO_INTERRUPT; 984 } else { 985 host->sdio_imask = 0; 986 imask &= ~SDXC_SDIO_INTERRUPT; 987 } 988 mmc_writel(host, REG_IMASK, imask); 989 spin_unlock_irqrestore(&host->lock, flags); 990 991 if (!enable) 992 pm_runtime_put_noidle(host->mmc->parent); 993 } 994 995 static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 996 { 997 struct sunxi_mmc_host *host = mmc_priv(mmc); 998 mmc_writel(host, REG_HWRST, 0); 999 udelay(10); 1000 mmc_writel(host, REG_HWRST, 1); 1001 udelay(300); 1002 } 1003 1004 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 1005 { 1006 struct sunxi_mmc_host *host = mmc_priv(mmc); 1007 struct mmc_command *cmd = mrq->cmd; 1008 struct mmc_data *data = mrq->data; 1009 unsigned long iflags; 1010 u32 imask = SDXC_INTERRUPT_ERROR_BIT; 1011 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 1012 bool wait_dma = host->wait_dma; 1013 int ret; 1014 1015 /* Check for set_ios errors (should never happen) */ 1016 if (host->ferror) { 1017 mrq->cmd->error = host->ferror; 1018 mmc_request_done(mmc, mrq); 1019 return; 1020 } 1021 1022 if (data) { 1023 ret = sunxi_mmc_map_dma(host, data); 1024 if (ret < 0) { 1025 dev_err(mmc_dev(mmc), "map DMA failed\n"); 1026 cmd->error = ret; 1027 data->error = ret; 1028 mmc_request_done(mmc, mrq); 1029 return; 1030 } 1031 } 1032 1033 if (cmd->opcode == MMC_GO_IDLE_STATE) { 1034 cmd_val |= SDXC_SEND_INIT_SEQUENCE; 1035 imask |= SDXC_COMMAND_DONE; 1036 } 1037 1038 if (cmd->flags & MMC_RSP_PRESENT) { 1039 cmd_val |= SDXC_RESP_EXPIRE; 1040 if (cmd->flags & MMC_RSP_136) 1041 cmd_val |= SDXC_LONG_RESPONSE; 1042 if (cmd->flags & MMC_RSP_CRC) 1043 cmd_val |= SDXC_CHECK_RESPONSE_CRC; 1044 1045 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 1046 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 1047 1048 if (cmd->data->stop) { 1049 imask |= SDXC_AUTO_COMMAND_DONE; 1050 cmd_val |= SDXC_SEND_AUTO_STOP; 1051 } else { 1052 imask |= SDXC_DATA_OVER; 1053 } 1054 1055 if (cmd->data->flags & MMC_DATA_WRITE) 1056 cmd_val |= SDXC_WRITE; 1057 else 1058 wait_dma = true; 1059 } else { 1060 imask |= SDXC_COMMAND_DONE; 1061 } 1062 } else { 1063 imask |= SDXC_COMMAND_DONE; 1064 } 1065 1066 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 1067 cmd_val & 0x3f, cmd_val, cmd->arg, imask, 1068 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 1069 1070 spin_lock_irqsave(&host->lock, iflags); 1071 1072 if (host->mrq || host->manual_stop_mrq) { 1073 spin_unlock_irqrestore(&host->lock, iflags); 1074 1075 if (data) 1076 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 1077 mmc_get_dma_dir(data)); 1078 1079 dev_err(mmc_dev(mmc), "request already pending\n"); 1080 mrq->cmd->error = -EBUSY; 1081 mmc_request_done(mmc, mrq); 1082 return; 1083 } 1084 1085 if (data) { 1086 mmc_writel(host, REG_BLKSZ, data->blksz); 1087 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 1088 sunxi_mmc_start_dma(host, data); 1089 } 1090 1091 host->mrq = mrq; 1092 host->wait_dma = wait_dma; 1093 mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 1094 mmc_writel(host, REG_CARG, cmd->arg); 1095 mmc_writel(host, REG_CMDR, cmd_val); 1096 1097 spin_unlock_irqrestore(&host->lock, iflags); 1098 } 1099 1100 static int sunxi_mmc_card_busy(struct mmc_host *mmc) 1101 { 1102 struct sunxi_mmc_host *host = mmc_priv(mmc); 1103 1104 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); 1105 } 1106 1107 static const struct mmc_host_ops sunxi_mmc_ops = { 1108 .request = sunxi_mmc_request, 1109 .set_ios = sunxi_mmc_set_ios, 1110 .get_ro = mmc_gpio_get_ro, 1111 .get_cd = mmc_gpio_get_cd, 1112 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 1113 .start_signal_voltage_switch = sunxi_mmc_volt_switch, 1114 .hw_reset = sunxi_mmc_hw_reset, 1115 .card_busy = sunxi_mmc_card_busy, 1116 }; 1117 1118 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { 1119 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1120 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1121 [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, 1122 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, 1123 /* Value from A83T "new timing mode". Works but might not be right. */ 1124 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, 1125 }; 1126 1127 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 1128 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1129 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1130 [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, 1131 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, 1132 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, 1133 }; 1134 1135 static const struct sunxi_mmc_cfg sun4i_a10_cfg = { 1136 .idma_des_size_bits = 13, 1137 .clk_delays = NULL, 1138 .can_calibrate = false, 1139 }; 1140 1141 static const struct sunxi_mmc_cfg sun5i_a13_cfg = { 1142 .idma_des_size_bits = 16, 1143 .clk_delays = NULL, 1144 .can_calibrate = false, 1145 }; 1146 1147 static const struct sunxi_mmc_cfg sun7i_a20_cfg = { 1148 .idma_des_size_bits = 16, 1149 .clk_delays = sunxi_mmc_clk_delays, 1150 .can_calibrate = false, 1151 }; 1152 1153 static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = { 1154 .idma_des_size_bits = 16, 1155 .clk_delays = sunxi_mmc_clk_delays, 1156 .can_calibrate = false, 1157 .ccu_has_timings_switch = true, 1158 }; 1159 1160 static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 1161 .idma_des_size_bits = 16, 1162 .clk_delays = sun9i_mmc_clk_delays, 1163 .can_calibrate = false, 1164 }; 1165 1166 static const struct sunxi_mmc_cfg sun50i_a64_cfg = { 1167 .idma_des_size_bits = 16, 1168 .clk_delays = NULL, 1169 .can_calibrate = true, 1170 .mask_data0 = true, 1171 .needs_new_timings = true, 1172 }; 1173 1174 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = { 1175 .idma_des_size_bits = 13, 1176 .clk_delays = NULL, 1177 .can_calibrate = true, 1178 .needs_new_timings = true, 1179 }; 1180 1181 static const struct of_device_id sunxi_mmc_of_match[] = { 1182 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, 1183 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, 1184 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, 1185 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg }, 1186 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, 1187 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, 1188 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, 1189 { /* sentinel */ } 1190 }; 1191 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 1192 1193 static int sunxi_mmc_enable(struct sunxi_mmc_host *host) 1194 { 1195 int ret; 1196 1197 if (!IS_ERR(host->reset)) { 1198 ret = reset_control_reset(host->reset); 1199 if (ret) { 1200 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n", 1201 ret); 1202 return ret; 1203 } 1204 } 1205 1206 ret = clk_prepare_enable(host->clk_ahb); 1207 if (ret) { 1208 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret); 1209 goto error_assert_reset; 1210 } 1211 1212 ret = clk_prepare_enable(host->clk_mmc); 1213 if (ret) { 1214 dev_err(host->dev, "Enable mmc clk err %d\n", ret); 1215 goto error_disable_clk_ahb; 1216 } 1217 1218 ret = clk_prepare_enable(host->clk_output); 1219 if (ret) { 1220 dev_err(host->dev, "Enable output clk err %d\n", ret); 1221 goto error_disable_clk_mmc; 1222 } 1223 1224 ret = clk_prepare_enable(host->clk_sample); 1225 if (ret) { 1226 dev_err(host->dev, "Enable sample clk err %d\n", ret); 1227 goto error_disable_clk_output; 1228 } 1229 1230 /* 1231 * Sometimes the controller asserts the irq on boot for some reason, 1232 * make sure the controller is in a sane state before enabling irqs. 1233 */ 1234 ret = sunxi_mmc_reset_host(host); 1235 if (ret) 1236 goto error_disable_clk_sample; 1237 1238 return 0; 1239 1240 error_disable_clk_sample: 1241 clk_disable_unprepare(host->clk_sample); 1242 error_disable_clk_output: 1243 clk_disable_unprepare(host->clk_output); 1244 error_disable_clk_mmc: 1245 clk_disable_unprepare(host->clk_mmc); 1246 error_disable_clk_ahb: 1247 clk_disable_unprepare(host->clk_ahb); 1248 error_assert_reset: 1249 if (!IS_ERR(host->reset)) 1250 reset_control_assert(host->reset); 1251 return ret; 1252 } 1253 1254 static void sunxi_mmc_disable(struct sunxi_mmc_host *host) 1255 { 1256 sunxi_mmc_reset_host(host); 1257 1258 clk_disable_unprepare(host->clk_sample); 1259 clk_disable_unprepare(host->clk_output); 1260 clk_disable_unprepare(host->clk_mmc); 1261 clk_disable_unprepare(host->clk_ahb); 1262 1263 if (!IS_ERR(host->reset)) 1264 reset_control_assert(host->reset); 1265 } 1266 1267 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 1268 struct platform_device *pdev) 1269 { 1270 int ret; 1271 1272 host->cfg = of_device_get_match_data(&pdev->dev); 1273 if (!host->cfg) 1274 return -EINVAL; 1275 1276 ret = mmc_regulator_get_supply(host->mmc); 1277 if (ret) 1278 return ret; 1279 1280 host->reg_base = devm_ioremap_resource(&pdev->dev, 1281 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 1282 if (IS_ERR(host->reg_base)) 1283 return PTR_ERR(host->reg_base); 1284 1285 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1286 if (IS_ERR(host->clk_ahb)) { 1287 dev_err(&pdev->dev, "Could not get ahb clock\n"); 1288 return PTR_ERR(host->clk_ahb); 1289 } 1290 1291 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 1292 if (IS_ERR(host->clk_mmc)) { 1293 dev_err(&pdev->dev, "Could not get mmc clock\n"); 1294 return PTR_ERR(host->clk_mmc); 1295 } 1296 1297 if (host->cfg->clk_delays) { 1298 host->clk_output = devm_clk_get(&pdev->dev, "output"); 1299 if (IS_ERR(host->clk_output)) { 1300 dev_err(&pdev->dev, "Could not get output clock\n"); 1301 return PTR_ERR(host->clk_output); 1302 } 1303 1304 host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 1305 if (IS_ERR(host->clk_sample)) { 1306 dev_err(&pdev->dev, "Could not get sample clock\n"); 1307 return PTR_ERR(host->clk_sample); 1308 } 1309 } 1310 1311 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1312 "ahb"); 1313 if (PTR_ERR(host->reset) == -EPROBE_DEFER) 1314 return PTR_ERR(host->reset); 1315 1316 ret = sunxi_mmc_enable(host); 1317 if (ret) 1318 return ret; 1319 1320 host->irq = platform_get_irq(pdev, 0); 1321 if (host->irq <= 0) { 1322 ret = -EINVAL; 1323 goto error_disable_mmc; 1324 } 1325 1326 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 1327 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 1328 1329 error_disable_mmc: 1330 sunxi_mmc_disable(host); 1331 return ret; 1332 } 1333 1334 static int sunxi_mmc_probe(struct platform_device *pdev) 1335 { 1336 struct sunxi_mmc_host *host; 1337 struct mmc_host *mmc; 1338 int ret; 1339 1340 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 1341 if (!mmc) { 1342 dev_err(&pdev->dev, "mmc alloc host failed\n"); 1343 return -ENOMEM; 1344 } 1345 platform_set_drvdata(pdev, mmc); 1346 1347 host = mmc_priv(mmc); 1348 host->dev = &pdev->dev; 1349 host->mmc = mmc; 1350 spin_lock_init(&host->lock); 1351 1352 ret = sunxi_mmc_resource_request(host, pdev); 1353 if (ret) 1354 goto error_free_host; 1355 1356 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 1357 &host->sg_dma, GFP_KERNEL); 1358 if (!host->sg_cpu) { 1359 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 1360 ret = -ENOMEM; 1361 goto error_free_host; 1362 } 1363 1364 if (host->cfg->ccu_has_timings_switch) { 1365 /* 1366 * Supports both old and new timing modes. 1367 * Try setting the clk to new timing mode. 1368 */ 1369 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 1370 1371 /* And check the result */ 1372 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc); 1373 if (ret < 0) { 1374 /* 1375 * For whatever reason we were not able to get 1376 * the current active mode. Default to old mode. 1377 */ 1378 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n"); 1379 host->use_new_timings = false; 1380 } else { 1381 host->use_new_timings = !!ret; 1382 } 1383 } else if (host->cfg->needs_new_timings) { 1384 /* Supports new timing mode only */ 1385 host->use_new_timings = true; 1386 } 1387 1388 mmc->ops = &sunxi_mmc_ops; 1389 mmc->max_blk_count = 8192; 1390 mmc->max_blk_size = 4096; 1391 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 1392 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); 1393 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 1394 /* 400kHz ~ 52MHz */ 1395 mmc->f_min = 400000; 1396 mmc->f_max = 52000000; 1397 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1398 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; 1399 1400 /* 1401 * Some H5 devices do not have signal traces precise enough to 1402 * use HS DDR mode for their eMMC chips. 1403 * 1404 * We still enable HS DDR modes for all the other controller 1405 * variants that support them. 1406 */ 1407 if ((host->cfg->clk_delays || host->use_new_timings) && 1408 !of_device_is_compatible(pdev->dev.of_node, 1409 "allwinner,sun50i-h5-emmc")) 1410 mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1411 1412 ret = mmc_of_parse(mmc); 1413 if (ret) 1414 goto error_free_dma; 1415 1416 /* 1417 * If we don't support delay chains in the SoC, we can't use any 1418 * of the higher speed modes. Mask them out in case the device 1419 * tree specifies the properties for them, which gets added to 1420 * the caps by mmc_of_parse() above. 1421 */ 1422 if (!(host->cfg->clk_delays || host->use_new_timings)) { 1423 mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | 1424 MMC_CAP_1_2V_DDR | MMC_CAP_UHS); 1425 mmc->caps2 &= ~MMC_CAP2_HS200; 1426 } 1427 1428 /* TODO: This driver doesn't support HS400 mode yet */ 1429 mmc->caps2 &= ~MMC_CAP2_HS400; 1430 1431 ret = sunxi_mmc_init_host(host); 1432 if (ret) 1433 goto error_free_dma; 1434 1435 pm_runtime_set_active(&pdev->dev); 1436 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1437 pm_runtime_use_autosuspend(&pdev->dev); 1438 pm_runtime_enable(&pdev->dev); 1439 1440 ret = mmc_add_host(mmc); 1441 if (ret) 1442 goto error_free_dma; 1443 1444 dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n", 1445 mmc->max_req_size >> 10, 1446 host->use_new_timings ? ", uses new timings mode" : ""); 1447 1448 return 0; 1449 1450 error_free_dma: 1451 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1452 error_free_host: 1453 mmc_free_host(mmc); 1454 return ret; 1455 } 1456 1457 static int sunxi_mmc_remove(struct platform_device *pdev) 1458 { 1459 struct mmc_host *mmc = platform_get_drvdata(pdev); 1460 struct sunxi_mmc_host *host = mmc_priv(mmc); 1461 1462 mmc_remove_host(mmc); 1463 pm_runtime_force_suspend(&pdev->dev); 1464 disable_irq(host->irq); 1465 sunxi_mmc_disable(host); 1466 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1467 mmc_free_host(mmc); 1468 1469 return 0; 1470 } 1471 1472 #ifdef CONFIG_PM 1473 static int sunxi_mmc_runtime_resume(struct device *dev) 1474 { 1475 struct mmc_host *mmc = dev_get_drvdata(dev); 1476 struct sunxi_mmc_host *host = mmc_priv(mmc); 1477 int ret; 1478 1479 ret = sunxi_mmc_enable(host); 1480 if (ret) 1481 return ret; 1482 1483 sunxi_mmc_init_host(host); 1484 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width); 1485 sunxi_mmc_set_clk(host, &mmc->ios); 1486 enable_irq(host->irq); 1487 1488 return 0; 1489 } 1490 1491 static int sunxi_mmc_runtime_suspend(struct device *dev) 1492 { 1493 struct mmc_host *mmc = dev_get_drvdata(dev); 1494 struct sunxi_mmc_host *host = mmc_priv(mmc); 1495 1496 /* 1497 * When clocks are off, it's possible receiving 1498 * fake interrupts, which will stall the system. 1499 * Disabling the irq will prevent this. 1500 */ 1501 disable_irq(host->irq); 1502 sunxi_mmc_reset_host(host); 1503 sunxi_mmc_disable(host); 1504 1505 return 0; 1506 } 1507 #endif 1508 1509 static const struct dev_pm_ops sunxi_mmc_pm_ops = { 1510 SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend, 1511 sunxi_mmc_runtime_resume, 1512 NULL) 1513 }; 1514 1515 static struct platform_driver sunxi_mmc_driver = { 1516 .driver = { 1517 .name = "sunxi-mmc", 1518 .of_match_table = of_match_ptr(sunxi_mmc_of_match), 1519 .pm = &sunxi_mmc_pm_ops, 1520 }, 1521 .probe = sunxi_mmc_probe, 1522 .remove = sunxi_mmc_remove, 1523 }; 1524 module_platform_driver(sunxi_mmc_driver); 1525 1526 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 1527 MODULE_LICENSE("GPL v2"); 1528 MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>"); 1529 MODULE_ALIAS("platform:sunxi-mmc"); 1530