1 /* 2 * Driver for sunxi SD/MMC host controllers 3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 6 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch> 7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 8 * (C) Copyright 2017 Sootech SA 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/clk/sunxi-ng.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/err.h> 22 #include <linux/gpio.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/core.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/sd.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 #include <linux/module.h> 34 #include <linux/of_address.h> 35 #include <linux/of_gpio.h> 36 #include <linux/of_platform.h> 37 #include <linux/platform_device.h> 38 #include <linux/pm_runtime.h> 39 #include <linux/regulator/consumer.h> 40 #include <linux/reset.h> 41 #include <linux/scatterlist.h> 42 #include <linux/slab.h> 43 #include <linux/spinlock.h> 44 45 /* register offset definitions */ 46 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 47 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 48 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 49 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 50 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 51 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 52 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 53 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 54 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 55 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 56 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 57 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 58 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 59 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 60 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 61 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 62 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 63 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 64 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 65 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 66 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 67 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 68 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 69 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 70 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 71 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 72 #define SDXC_REG_CHDA (0x90) 73 #define SDXC_REG_CBDA (0x94) 74 75 /* New registers introduced in A64 */ 76 #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ 77 #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ 78 #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ 79 #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ 80 #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ 81 82 #define mmc_readl(host, reg) \ 83 readl((host)->reg_base + SDXC_##reg) 84 #define mmc_writel(host, reg, value) \ 85 writel((value), (host)->reg_base + SDXC_##reg) 86 87 /* global control register bits */ 88 #define SDXC_SOFT_RESET BIT(0) 89 #define SDXC_FIFO_RESET BIT(1) 90 #define SDXC_DMA_RESET BIT(2) 91 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 92 #define SDXC_DMA_ENABLE_BIT BIT(5) 93 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 94 #define SDXC_POSEDGE_LATCH_DATA BIT(9) 95 #define SDXC_DDR_MODE BIT(10) 96 #define SDXC_MEMORY_ACCESS_DONE BIT(29) 97 #define SDXC_ACCESS_DONE_DIRECT BIT(30) 98 #define SDXC_ACCESS_BY_AHB BIT(31) 99 #define SDXC_ACCESS_BY_DMA (0 << 31) 100 #define SDXC_HARDWARE_RESET \ 101 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 102 103 /* clock control bits */ 104 #define SDXC_MASK_DATA0 BIT(31) 105 #define SDXC_CARD_CLOCK_ON BIT(16) 106 #define SDXC_LOW_POWER_ON BIT(17) 107 108 /* bus width */ 109 #define SDXC_WIDTH1 0 110 #define SDXC_WIDTH4 1 111 #define SDXC_WIDTH8 2 112 113 /* smc command bits */ 114 #define SDXC_RESP_EXPIRE BIT(6) 115 #define SDXC_LONG_RESPONSE BIT(7) 116 #define SDXC_CHECK_RESPONSE_CRC BIT(8) 117 #define SDXC_DATA_EXPIRE BIT(9) 118 #define SDXC_WRITE BIT(10) 119 #define SDXC_SEQUENCE_MODE BIT(11) 120 #define SDXC_SEND_AUTO_STOP BIT(12) 121 #define SDXC_WAIT_PRE_OVER BIT(13) 122 #define SDXC_STOP_ABORT_CMD BIT(14) 123 #define SDXC_SEND_INIT_SEQUENCE BIT(15) 124 #define SDXC_UPCLK_ONLY BIT(21) 125 #define SDXC_READ_CEATA_DEV BIT(22) 126 #define SDXC_CCS_EXPIRE BIT(23) 127 #define SDXC_ENABLE_BIT_BOOT BIT(24) 128 #define SDXC_ALT_BOOT_OPTIONS BIT(25) 129 #define SDXC_BOOT_ACK_EXPIRE BIT(26) 130 #define SDXC_BOOT_ABORT BIT(27) 131 #define SDXC_VOLTAGE_SWITCH BIT(28) 132 #define SDXC_USE_HOLD_REGISTER BIT(29) 133 #define SDXC_START BIT(31) 134 135 /* interrupt bits */ 136 #define SDXC_RESP_ERROR BIT(1) 137 #define SDXC_COMMAND_DONE BIT(2) 138 #define SDXC_DATA_OVER BIT(3) 139 #define SDXC_TX_DATA_REQUEST BIT(4) 140 #define SDXC_RX_DATA_REQUEST BIT(5) 141 #define SDXC_RESP_CRC_ERROR BIT(6) 142 #define SDXC_DATA_CRC_ERROR BIT(7) 143 #define SDXC_RESP_TIMEOUT BIT(8) 144 #define SDXC_DATA_TIMEOUT BIT(9) 145 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 146 #define SDXC_FIFO_RUN_ERROR BIT(11) 147 #define SDXC_HARD_WARE_LOCKED BIT(12) 148 #define SDXC_START_BIT_ERROR BIT(13) 149 #define SDXC_AUTO_COMMAND_DONE BIT(14) 150 #define SDXC_END_BIT_ERROR BIT(15) 151 #define SDXC_SDIO_INTERRUPT BIT(16) 152 #define SDXC_CARD_INSERT BIT(30) 153 #define SDXC_CARD_REMOVE BIT(31) 154 #define SDXC_INTERRUPT_ERROR_BIT \ 155 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 156 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 157 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 158 #define SDXC_INTERRUPT_DONE_BIT \ 159 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 160 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 161 162 /* status */ 163 #define SDXC_RXWL_FLAG BIT(0) 164 #define SDXC_TXWL_FLAG BIT(1) 165 #define SDXC_FIFO_EMPTY BIT(2) 166 #define SDXC_FIFO_FULL BIT(3) 167 #define SDXC_CARD_PRESENT BIT(8) 168 #define SDXC_CARD_DATA_BUSY BIT(9) 169 #define SDXC_DATA_FSM_BUSY BIT(10) 170 #define SDXC_DMA_REQUEST BIT(31) 171 #define SDXC_FIFO_SIZE 16 172 173 /* Function select */ 174 #define SDXC_CEATA_ON (0xceaa << 16) 175 #define SDXC_SEND_IRQ_RESPONSE BIT(0) 176 #define SDXC_SDIO_READ_WAIT BIT(1) 177 #define SDXC_ABORT_READ_DATA BIT(2) 178 #define SDXC_SEND_CCSD BIT(8) 179 #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 180 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 181 182 /* IDMA controller bus mod bit field */ 183 #define SDXC_IDMAC_SOFT_RESET BIT(0) 184 #define SDXC_IDMAC_FIX_BURST BIT(1) 185 #define SDXC_IDMAC_IDMA_ON BIT(7) 186 #define SDXC_IDMAC_REFETCH_DES BIT(31) 187 188 /* IDMA status bit field */ 189 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 190 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 191 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 192 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 193 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 194 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 195 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 196 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 197 #define SDXC_IDMAC_IDLE (0 << 13) 198 #define SDXC_IDMAC_SUSPEND (1 << 13) 199 #define SDXC_IDMAC_DESC_READ (2 << 13) 200 #define SDXC_IDMAC_DESC_CHECK (3 << 13) 201 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 202 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 203 #define SDXC_IDMAC_READ (6 << 13) 204 #define SDXC_IDMAC_WRITE (7 << 13) 205 #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 206 207 /* 208 * If the idma-des-size-bits of property is ie 13, bufsize bits are: 209 * Bits 0-12: buf1 size 210 * Bits 13-25: buf2 size 211 * Bits 26-31: not used 212 * Since we only ever set buf1 size, we can simply store it directly. 213 */ 214 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 215 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 216 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 217 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 218 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 219 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 220 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 221 222 #define SDXC_CLK_400K 0 223 #define SDXC_CLK_25M 1 224 #define SDXC_CLK_50M 2 225 #define SDXC_CLK_50M_DDR 3 226 #define SDXC_CLK_50M_DDR_8BIT 4 227 228 #define SDXC_2X_TIMING_MODE BIT(31) 229 230 #define SDXC_CAL_START BIT(15) 231 #define SDXC_CAL_DONE BIT(14) 232 #define SDXC_CAL_DL_SHIFT 8 233 #define SDXC_CAL_DL_SW_EN BIT(7) 234 #define SDXC_CAL_DL_SW_SHIFT 0 235 #define SDXC_CAL_DL_MASK 0x3f 236 237 #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/ 238 239 struct sunxi_mmc_clk_delay { 240 u32 output; 241 u32 sample; 242 }; 243 244 struct sunxi_idma_des { 245 __le32 config; 246 __le32 buf_size; 247 __le32 buf_addr_ptr1; 248 __le32 buf_addr_ptr2; 249 }; 250 251 struct sunxi_mmc_cfg { 252 u32 idma_des_size_bits; 253 const struct sunxi_mmc_clk_delay *clk_delays; 254 255 /* does the IP block support autocalibration? */ 256 bool can_calibrate; 257 258 /* Does DATA0 needs to be masked while the clock is updated */ 259 bool mask_data0; 260 261 /* 262 * hardware only supports new timing mode, either due to lack of 263 * a mode switch in the clock controller, or the mmc controller 264 * is permanently configured in the new timing mode, without the 265 * NTSR mode switch. 266 */ 267 bool needs_new_timings; 268 269 /* clock hardware can switch between old and new timing modes */ 270 bool ccu_has_timings_switch; 271 }; 272 273 struct sunxi_mmc_host { 274 struct device *dev; 275 struct mmc_host *mmc; 276 struct reset_control *reset; 277 const struct sunxi_mmc_cfg *cfg; 278 279 /* IO mapping base */ 280 void __iomem *reg_base; 281 282 /* clock management */ 283 struct clk *clk_ahb; 284 struct clk *clk_mmc; 285 struct clk *clk_sample; 286 struct clk *clk_output; 287 288 /* irq */ 289 spinlock_t lock; 290 int irq; 291 u32 int_sum; 292 u32 sdio_imask; 293 294 /* dma */ 295 dma_addr_t sg_dma; 296 void *sg_cpu; 297 bool wait_dma; 298 299 struct mmc_request *mrq; 300 struct mmc_request *manual_stop_mrq; 301 int ferror; 302 303 /* vqmmc */ 304 bool vqmmc_enabled; 305 306 /* timings */ 307 bool use_new_timings; 308 }; 309 310 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 311 { 312 unsigned long expire = jiffies + msecs_to_jiffies(250); 313 u32 rval; 314 315 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 316 do { 317 rval = mmc_readl(host, REG_GCTRL); 318 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 319 320 if (rval & SDXC_HARDWARE_RESET) { 321 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 322 return -EIO; 323 } 324 325 return 0; 326 } 327 328 static int sunxi_mmc_init_host(struct sunxi_mmc_host *host) 329 { 330 u32 rval; 331 332 if (sunxi_mmc_reset_host(host)) 333 return -EIO; 334 335 /* 336 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8 337 * 338 * TODO: sun9i has a larger FIFO and supports higher trigger values 339 */ 340 mmc_writel(host, REG_FTRGL, 0x20070008); 341 /* Maximum timeout value */ 342 mmc_writel(host, REG_TMOUT, 0xffffffff); 343 /* Unmask SDIO interrupt if needed */ 344 mmc_writel(host, REG_IMASK, host->sdio_imask); 345 /* Clear all pending interrupts */ 346 mmc_writel(host, REG_RINTR, 0xffffffff); 347 /* Debug register? undocumented */ 348 mmc_writel(host, REG_DBGC, 0xdeb); 349 /* Enable CEATA support */ 350 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 351 /* Set DMA descriptor list base address */ 352 mmc_writel(host, REG_DLBA, host->sg_dma); 353 354 rval = mmc_readl(host, REG_GCTRL); 355 rval |= SDXC_INTERRUPT_ENABLE_BIT; 356 /* Undocumented, but found in Allwinner code */ 357 rval &= ~SDXC_ACCESS_DONE_DIRECT; 358 mmc_writel(host, REG_GCTRL, rval); 359 360 return 0; 361 } 362 363 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 364 struct mmc_data *data) 365 { 366 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 367 dma_addr_t next_desc = host->sg_dma; 368 int i, max_len = (1 << host->cfg->idma_des_size_bits); 369 370 for (i = 0; i < data->sg_len; i++) { 371 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | 372 SDXC_IDMAC_DES0_OWN | 373 SDXC_IDMAC_DES0_DIC); 374 375 if (data->sg[i].length == max_len) 376 pdes[i].buf_size = 0; /* 0 == max_len */ 377 else 378 pdes[i].buf_size = cpu_to_le32(data->sg[i].length); 379 380 next_desc += sizeof(struct sunxi_idma_des); 381 pdes[i].buf_addr_ptr1 = 382 cpu_to_le32(sg_dma_address(&data->sg[i])); 383 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc); 384 } 385 386 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); 387 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | 388 SDXC_IDMAC_DES0_ER); 389 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); 390 pdes[i - 1].buf_addr_ptr2 = 0; 391 392 /* 393 * Avoid the io-store starting the idmac hitting io-mem before the 394 * descriptors hit the main-mem. 395 */ 396 wmb(); 397 } 398 399 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 400 struct mmc_data *data) 401 { 402 u32 i, dma_len; 403 struct scatterlist *sg; 404 405 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 406 mmc_get_dma_dir(data)); 407 if (dma_len == 0) { 408 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 409 return -ENOMEM; 410 } 411 412 for_each_sg(data->sg, sg, data->sg_len, i) { 413 if (sg->offset & 3 || sg->length & 3) { 414 dev_err(mmc_dev(host->mmc), 415 "unaligned scatterlist: os %x length %d\n", 416 sg->offset, sg->length); 417 return -EINVAL; 418 } 419 } 420 421 return 0; 422 } 423 424 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 425 struct mmc_data *data) 426 { 427 u32 rval; 428 429 sunxi_mmc_init_idma_des(host, data); 430 431 rval = mmc_readl(host, REG_GCTRL); 432 rval |= SDXC_DMA_ENABLE_BIT; 433 mmc_writel(host, REG_GCTRL, rval); 434 rval |= SDXC_DMA_RESET; 435 mmc_writel(host, REG_GCTRL, rval); 436 437 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 438 439 if (!(data->flags & MMC_DATA_WRITE)) 440 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 441 442 mmc_writel(host, REG_DMAC, 443 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 444 } 445 446 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 447 struct mmc_request *req) 448 { 449 u32 arg, cmd_val, ri; 450 unsigned long expire = jiffies + msecs_to_jiffies(1000); 451 452 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 453 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 454 455 if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 456 cmd_val |= SD_IO_RW_DIRECT; 457 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 458 ((req->cmd->arg >> 28) & 0x7); 459 } else { 460 cmd_val |= MMC_STOP_TRANSMISSION; 461 arg = 0; 462 } 463 464 mmc_writel(host, REG_CARG, arg); 465 mmc_writel(host, REG_CMDR, cmd_val); 466 467 do { 468 ri = mmc_readl(host, REG_RINTR); 469 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 470 time_before(jiffies, expire)); 471 472 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 473 dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 474 if (req->stop) 475 req->stop->resp[0] = -ETIMEDOUT; 476 } else { 477 if (req->stop) 478 req->stop->resp[0] = mmc_readl(host, REG_RESP0); 479 } 480 481 mmc_writel(host, REG_RINTR, 0xffff); 482 } 483 484 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 485 { 486 struct mmc_command *cmd = host->mrq->cmd; 487 struct mmc_data *data = host->mrq->data; 488 489 /* For some cmds timeout is normal with sd/mmc cards */ 490 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 491 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 492 cmd->opcode == SD_IO_RW_DIRECT)) 493 return; 494 495 dev_dbg(mmc_dev(host->mmc), 496 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 497 host->mmc->index, cmd->opcode, 498 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 499 host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 500 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 501 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 502 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 503 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 504 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 505 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 506 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 507 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 508 ); 509 } 510 511 /* Called in interrupt context! */ 512 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 513 { 514 struct mmc_request *mrq = host->mrq; 515 struct mmc_data *data = mrq->data; 516 u32 rval; 517 518 mmc_writel(host, REG_IMASK, host->sdio_imask); 519 mmc_writel(host, REG_IDIE, 0); 520 521 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 522 sunxi_mmc_dump_errinfo(host); 523 mrq->cmd->error = -ETIMEDOUT; 524 525 if (data) { 526 data->error = -ETIMEDOUT; 527 host->manual_stop_mrq = mrq; 528 } 529 530 if (mrq->stop) 531 mrq->stop->error = -ETIMEDOUT; 532 } else { 533 if (mrq->cmd->flags & MMC_RSP_136) { 534 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 535 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 536 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 537 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 538 } else { 539 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 540 } 541 542 if (data) 543 data->bytes_xfered = data->blocks * data->blksz; 544 } 545 546 if (data) { 547 mmc_writel(host, REG_IDST, 0x337); 548 mmc_writel(host, REG_DMAC, 0); 549 rval = mmc_readl(host, REG_GCTRL); 550 rval |= SDXC_DMA_RESET; 551 mmc_writel(host, REG_GCTRL, rval); 552 rval &= ~SDXC_DMA_ENABLE_BIT; 553 mmc_writel(host, REG_GCTRL, rval); 554 rval |= SDXC_FIFO_RESET; 555 mmc_writel(host, REG_GCTRL, rval); 556 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 557 mmc_get_dma_dir(data)); 558 } 559 560 mmc_writel(host, REG_RINTR, 0xffff); 561 562 host->mrq = NULL; 563 host->int_sum = 0; 564 host->wait_dma = false; 565 566 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 567 } 568 569 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 570 { 571 struct sunxi_mmc_host *host = dev_id; 572 struct mmc_request *mrq; 573 u32 msk_int, idma_int; 574 bool finalize = false; 575 bool sdio_int = false; 576 irqreturn_t ret = IRQ_HANDLED; 577 578 spin_lock(&host->lock); 579 580 idma_int = mmc_readl(host, REG_IDST); 581 msk_int = mmc_readl(host, REG_MISTA); 582 583 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 584 host->mrq, msk_int, idma_int); 585 586 mrq = host->mrq; 587 if (mrq) { 588 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 589 host->wait_dma = false; 590 591 host->int_sum |= msk_int; 592 593 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 594 if ((host->int_sum & SDXC_RESP_TIMEOUT) && 595 !(host->int_sum & SDXC_COMMAND_DONE)) 596 mmc_writel(host, REG_IMASK, 597 host->sdio_imask | SDXC_COMMAND_DONE); 598 /* Don't wait for dma on error */ 599 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 600 finalize = true; 601 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 602 !host->wait_dma) 603 finalize = true; 604 } 605 606 if (msk_int & SDXC_SDIO_INTERRUPT) 607 sdio_int = true; 608 609 mmc_writel(host, REG_RINTR, msk_int); 610 mmc_writel(host, REG_IDST, idma_int); 611 612 if (finalize) 613 ret = sunxi_mmc_finalize_request(host); 614 615 spin_unlock(&host->lock); 616 617 if (finalize && ret == IRQ_HANDLED) 618 mmc_request_done(host->mmc, mrq); 619 620 if (sdio_int) 621 mmc_signal_sdio_irq(host->mmc); 622 623 return ret; 624 } 625 626 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 627 { 628 struct sunxi_mmc_host *host = dev_id; 629 struct mmc_request *mrq; 630 unsigned long iflags; 631 632 spin_lock_irqsave(&host->lock, iflags); 633 mrq = host->manual_stop_mrq; 634 spin_unlock_irqrestore(&host->lock, iflags); 635 636 if (!mrq) { 637 dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 638 return IRQ_HANDLED; 639 } 640 641 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 642 643 /* 644 * We will never have more than one outstanding request, 645 * and we do not complete the request until after 646 * we've cleared host->manual_stop_mrq so we do not need to 647 * spin lock this function. 648 * Additionally we have wait states within this function 649 * so having it in a lock is a very bad idea. 650 */ 651 sunxi_mmc_send_manual_stop(host, mrq); 652 653 spin_lock_irqsave(&host->lock, iflags); 654 host->manual_stop_mrq = NULL; 655 spin_unlock_irqrestore(&host->lock, iflags); 656 657 mmc_request_done(host->mmc, mrq); 658 659 return IRQ_HANDLED; 660 } 661 662 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 663 { 664 unsigned long expire = jiffies + msecs_to_jiffies(750); 665 u32 rval; 666 667 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n", 668 oclk_en ? "en" : "dis"); 669 670 rval = mmc_readl(host, REG_CLKCR); 671 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0); 672 673 if (oclk_en) 674 rval |= SDXC_CARD_CLOCK_ON; 675 if (host->cfg->mask_data0) 676 rval |= SDXC_MASK_DATA0; 677 678 mmc_writel(host, REG_CLKCR, rval); 679 680 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 681 mmc_writel(host, REG_CMDR, rval); 682 683 do { 684 rval = mmc_readl(host, REG_CMDR); 685 } while (time_before(jiffies, expire) && (rval & SDXC_START)); 686 687 /* clear irq status bits set by the command */ 688 mmc_writel(host, REG_RINTR, 689 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 690 691 if (rval & SDXC_START) { 692 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 693 return -EIO; 694 } 695 696 if (host->cfg->mask_data0) { 697 rval = mmc_readl(host, REG_CLKCR); 698 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0); 699 } 700 701 return 0; 702 } 703 704 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) 705 { 706 if (!host->cfg->can_calibrate) 707 return 0; 708 709 /* 710 * FIXME: 711 * This is not clear how the calibration is supposed to work 712 * yet. The best rate have been obtained by simply setting the 713 * delay to 0, as Allwinner does in its BSP. 714 * 715 * The only mode that doesn't have such a delay is HS400, that 716 * is in itself a TODO. 717 */ 718 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); 719 720 return 0; 721 } 722 723 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 724 struct mmc_ios *ios, u32 rate) 725 { 726 int index; 727 728 /* clk controller delays not used under new timings mode */ 729 if (host->use_new_timings) 730 return 0; 731 732 /* some old controllers don't support delays */ 733 if (!host->cfg->clk_delays) 734 return 0; 735 736 /* determine delays */ 737 if (rate <= 400000) { 738 index = SDXC_CLK_400K; 739 } else if (rate <= 25000000) { 740 index = SDXC_CLK_25M; 741 } else if (rate <= 52000000) { 742 if (ios->timing != MMC_TIMING_UHS_DDR50 && 743 ios->timing != MMC_TIMING_MMC_DDR52) { 744 index = SDXC_CLK_50M; 745 } else if (ios->bus_width == MMC_BUS_WIDTH_8) { 746 index = SDXC_CLK_50M_DDR_8BIT; 747 } else { 748 index = SDXC_CLK_50M_DDR; 749 } 750 } else { 751 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n"); 752 return -EINVAL; 753 } 754 755 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); 756 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); 757 758 return 0; 759 } 760 761 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 762 struct mmc_ios *ios) 763 { 764 struct mmc_host *mmc = host->mmc; 765 long rate; 766 u32 rval, clock = ios->clock, div = 1; 767 int ret; 768 769 ret = sunxi_mmc_oclk_onoff(host, 0); 770 if (ret) 771 return ret; 772 773 /* Our clock is gated now */ 774 mmc->actual_clock = 0; 775 776 if (!ios->clock) 777 return 0; 778 779 /* 780 * Under the old timing mode, 8 bit DDR requires the module 781 * clock to be double the card clock. Under the new timing 782 * mode, all DDR modes require a doubled module clock. 783 * 784 * We currently only support the standard MMC DDR52 mode. 785 * This block should be updated once support for other DDR 786 * modes is added. 787 */ 788 if (ios->timing == MMC_TIMING_MMC_DDR52 && 789 (host->use_new_timings || 790 ios->bus_width == MMC_BUS_WIDTH_8)) { 791 div = 2; 792 clock <<= 1; 793 } 794 795 if (host->use_new_timings && host->cfg->ccu_has_timings_switch) { 796 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 797 if (ret) { 798 dev_err(mmc_dev(mmc), 799 "error setting new timing mode\n"); 800 return ret; 801 } 802 } 803 804 rate = clk_round_rate(host->clk_mmc, clock); 805 if (rate < 0) { 806 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n", 807 clock, rate); 808 return rate; 809 } 810 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n", 811 clock, rate); 812 813 /* setting clock rate */ 814 ret = clk_set_rate(host->clk_mmc, rate); 815 if (ret) { 816 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n", 817 rate, ret); 818 return ret; 819 } 820 821 /* set internal divider */ 822 rval = mmc_readl(host, REG_CLKCR); 823 rval &= ~0xff; 824 rval |= div - 1; 825 mmc_writel(host, REG_CLKCR, rval); 826 827 /* update card clock rate to account for internal divider */ 828 rate /= div; 829 830 /* 831 * Configure the controller to use the new timing mode if needed. 832 * On controllers that only support the new timing mode, such as 833 * the eMMC controller on the A64, this register does not exist, 834 * and any writes to it are ignored. 835 */ 836 if (host->use_new_timings) { 837 /* Don't touch the delay bits */ 838 rval = mmc_readl(host, REG_SD_NTSR); 839 rval |= SDXC_2X_TIMING_MODE; 840 mmc_writel(host, REG_SD_NTSR, rval); 841 } 842 843 /* sunxi_mmc_clk_set_phase expects the actual card clock rate */ 844 ret = sunxi_mmc_clk_set_phase(host, ios, rate); 845 if (ret) 846 return ret; 847 848 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); 849 if (ret) 850 return ret; 851 852 /* 853 * FIXME: 854 * 855 * In HS400 we'll also need to calibrate the data strobe 856 * signal. This should only happen on the MMC2 controller (at 857 * least on the A64). 858 */ 859 860 ret = sunxi_mmc_oclk_onoff(host, 1); 861 if (ret) 862 return ret; 863 864 /* And we just enabled our clock back */ 865 mmc->actual_clock = rate; 866 867 return 0; 868 } 869 870 static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host, 871 unsigned char width) 872 { 873 switch (width) { 874 case MMC_BUS_WIDTH_1: 875 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 876 break; 877 case MMC_BUS_WIDTH_4: 878 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 879 break; 880 case MMC_BUS_WIDTH_8: 881 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 882 break; 883 } 884 } 885 886 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios) 887 { 888 u32 rval; 889 890 /* set ddr mode */ 891 rval = mmc_readl(host, REG_GCTRL); 892 if (ios->timing == MMC_TIMING_UHS_DDR50 || 893 ios->timing == MMC_TIMING_MMC_DDR52) 894 rval |= SDXC_DDR_MODE; 895 else 896 rval &= ~SDXC_DDR_MODE; 897 mmc_writel(host, REG_GCTRL, rval); 898 899 host->ferror = sunxi_mmc_clk_set_rate(host, ios); 900 /* Android code had a usleep_range(50000, 55000); here */ 901 } 902 903 static void sunxi_mmc_card_power(struct sunxi_mmc_host *host, 904 struct mmc_ios *ios) 905 { 906 struct mmc_host *mmc = host->mmc; 907 908 switch (ios->power_mode) { 909 case MMC_POWER_UP: 910 dev_dbg(mmc_dev(mmc), "Powering card up\n"); 911 912 if (!IS_ERR(mmc->supply.vmmc)) { 913 host->ferror = mmc_regulator_set_ocr(mmc, 914 mmc->supply.vmmc, 915 ios->vdd); 916 if (host->ferror) 917 return; 918 } 919 920 if (!IS_ERR(mmc->supply.vqmmc)) { 921 host->ferror = regulator_enable(mmc->supply.vqmmc); 922 if (host->ferror) { 923 dev_err(mmc_dev(mmc), 924 "failed to enable vqmmc\n"); 925 return; 926 } 927 host->vqmmc_enabled = true; 928 } 929 break; 930 931 case MMC_POWER_OFF: 932 dev_dbg(mmc_dev(mmc), "Powering card off\n"); 933 934 if (!IS_ERR(mmc->supply.vmmc)) 935 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 936 937 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) 938 regulator_disable(mmc->supply.vqmmc); 939 940 host->vqmmc_enabled = false; 941 break; 942 943 default: 944 dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n"); 945 break; 946 } 947 } 948 949 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 950 { 951 struct sunxi_mmc_host *host = mmc_priv(mmc); 952 953 sunxi_mmc_card_power(host, ios); 954 sunxi_mmc_set_bus_width(host, ios->bus_width); 955 sunxi_mmc_set_clk(host, ios); 956 } 957 958 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 959 { 960 /* vqmmc regulator is available */ 961 if (!IS_ERR(mmc->supply.vqmmc)) 962 return mmc_regulator_set_vqmmc(mmc, ios); 963 964 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 965 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) 966 return 0; 967 968 return -EINVAL; 969 } 970 971 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 972 { 973 struct sunxi_mmc_host *host = mmc_priv(mmc); 974 unsigned long flags; 975 u32 imask; 976 977 if (enable) 978 pm_runtime_get_noresume(host->dev); 979 980 spin_lock_irqsave(&host->lock, flags); 981 982 imask = mmc_readl(host, REG_IMASK); 983 if (enable) { 984 host->sdio_imask = SDXC_SDIO_INTERRUPT; 985 imask |= SDXC_SDIO_INTERRUPT; 986 } else { 987 host->sdio_imask = 0; 988 imask &= ~SDXC_SDIO_INTERRUPT; 989 } 990 mmc_writel(host, REG_IMASK, imask); 991 spin_unlock_irqrestore(&host->lock, flags); 992 993 if (!enable) 994 pm_runtime_put_noidle(host->mmc->parent); 995 } 996 997 static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 998 { 999 struct sunxi_mmc_host *host = mmc_priv(mmc); 1000 mmc_writel(host, REG_HWRST, 0); 1001 udelay(10); 1002 mmc_writel(host, REG_HWRST, 1); 1003 udelay(300); 1004 } 1005 1006 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 1007 { 1008 struct sunxi_mmc_host *host = mmc_priv(mmc); 1009 struct mmc_command *cmd = mrq->cmd; 1010 struct mmc_data *data = mrq->data; 1011 unsigned long iflags; 1012 u32 imask = SDXC_INTERRUPT_ERROR_BIT; 1013 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 1014 bool wait_dma = host->wait_dma; 1015 int ret; 1016 1017 /* Check for set_ios errors (should never happen) */ 1018 if (host->ferror) { 1019 mrq->cmd->error = host->ferror; 1020 mmc_request_done(mmc, mrq); 1021 return; 1022 } 1023 1024 if (data) { 1025 ret = sunxi_mmc_map_dma(host, data); 1026 if (ret < 0) { 1027 dev_err(mmc_dev(mmc), "map DMA failed\n"); 1028 cmd->error = ret; 1029 data->error = ret; 1030 mmc_request_done(mmc, mrq); 1031 return; 1032 } 1033 } 1034 1035 if (cmd->opcode == MMC_GO_IDLE_STATE) { 1036 cmd_val |= SDXC_SEND_INIT_SEQUENCE; 1037 imask |= SDXC_COMMAND_DONE; 1038 } 1039 1040 if (cmd->flags & MMC_RSP_PRESENT) { 1041 cmd_val |= SDXC_RESP_EXPIRE; 1042 if (cmd->flags & MMC_RSP_136) 1043 cmd_val |= SDXC_LONG_RESPONSE; 1044 if (cmd->flags & MMC_RSP_CRC) 1045 cmd_val |= SDXC_CHECK_RESPONSE_CRC; 1046 1047 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 1048 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 1049 1050 if (cmd->data->stop) { 1051 imask |= SDXC_AUTO_COMMAND_DONE; 1052 cmd_val |= SDXC_SEND_AUTO_STOP; 1053 } else { 1054 imask |= SDXC_DATA_OVER; 1055 } 1056 1057 if (cmd->data->flags & MMC_DATA_WRITE) 1058 cmd_val |= SDXC_WRITE; 1059 else 1060 wait_dma = true; 1061 } else { 1062 imask |= SDXC_COMMAND_DONE; 1063 } 1064 } else { 1065 imask |= SDXC_COMMAND_DONE; 1066 } 1067 1068 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 1069 cmd_val & 0x3f, cmd_val, cmd->arg, imask, 1070 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 1071 1072 spin_lock_irqsave(&host->lock, iflags); 1073 1074 if (host->mrq || host->manual_stop_mrq) { 1075 spin_unlock_irqrestore(&host->lock, iflags); 1076 1077 if (data) 1078 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 1079 mmc_get_dma_dir(data)); 1080 1081 dev_err(mmc_dev(mmc), "request already pending\n"); 1082 mrq->cmd->error = -EBUSY; 1083 mmc_request_done(mmc, mrq); 1084 return; 1085 } 1086 1087 if (data) { 1088 mmc_writel(host, REG_BLKSZ, data->blksz); 1089 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 1090 sunxi_mmc_start_dma(host, data); 1091 } 1092 1093 host->mrq = mrq; 1094 host->wait_dma = wait_dma; 1095 mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 1096 mmc_writel(host, REG_CARG, cmd->arg); 1097 mmc_writel(host, REG_CMDR, cmd_val); 1098 1099 spin_unlock_irqrestore(&host->lock, iflags); 1100 } 1101 1102 static int sunxi_mmc_card_busy(struct mmc_host *mmc) 1103 { 1104 struct sunxi_mmc_host *host = mmc_priv(mmc); 1105 1106 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); 1107 } 1108 1109 static const struct mmc_host_ops sunxi_mmc_ops = { 1110 .request = sunxi_mmc_request, 1111 .set_ios = sunxi_mmc_set_ios, 1112 .get_ro = mmc_gpio_get_ro, 1113 .get_cd = mmc_gpio_get_cd, 1114 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 1115 .start_signal_voltage_switch = sunxi_mmc_volt_switch, 1116 .hw_reset = sunxi_mmc_hw_reset, 1117 .card_busy = sunxi_mmc_card_busy, 1118 }; 1119 1120 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { 1121 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1122 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1123 [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, 1124 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, 1125 /* Value from A83T "new timing mode". Works but might not be right. */ 1126 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, 1127 }; 1128 1129 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 1130 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1131 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1132 [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, 1133 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, 1134 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, 1135 }; 1136 1137 static const struct sunxi_mmc_cfg sun4i_a10_cfg = { 1138 .idma_des_size_bits = 13, 1139 .clk_delays = NULL, 1140 .can_calibrate = false, 1141 }; 1142 1143 static const struct sunxi_mmc_cfg sun5i_a13_cfg = { 1144 .idma_des_size_bits = 16, 1145 .clk_delays = NULL, 1146 .can_calibrate = false, 1147 }; 1148 1149 static const struct sunxi_mmc_cfg sun7i_a20_cfg = { 1150 .idma_des_size_bits = 16, 1151 .clk_delays = sunxi_mmc_clk_delays, 1152 .can_calibrate = false, 1153 }; 1154 1155 static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = { 1156 .idma_des_size_bits = 16, 1157 .clk_delays = sunxi_mmc_clk_delays, 1158 .can_calibrate = false, 1159 .ccu_has_timings_switch = true, 1160 }; 1161 1162 static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 1163 .idma_des_size_bits = 16, 1164 .clk_delays = sun9i_mmc_clk_delays, 1165 .can_calibrate = false, 1166 }; 1167 1168 static const struct sunxi_mmc_cfg sun50i_a64_cfg = { 1169 .idma_des_size_bits = 16, 1170 .clk_delays = NULL, 1171 .can_calibrate = true, 1172 .mask_data0 = true, 1173 .needs_new_timings = true, 1174 }; 1175 1176 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = { 1177 .idma_des_size_bits = 13, 1178 .clk_delays = NULL, 1179 .can_calibrate = true, 1180 .needs_new_timings = true, 1181 }; 1182 1183 static const struct of_device_id sunxi_mmc_of_match[] = { 1184 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, 1185 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, 1186 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, 1187 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg }, 1188 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, 1189 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, 1190 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, 1191 { /* sentinel */ } 1192 }; 1193 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 1194 1195 static int sunxi_mmc_enable(struct sunxi_mmc_host *host) 1196 { 1197 int ret; 1198 1199 if (!IS_ERR(host->reset)) { 1200 ret = reset_control_reset(host->reset); 1201 if (ret) { 1202 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n", 1203 ret); 1204 return ret; 1205 } 1206 } 1207 1208 ret = clk_prepare_enable(host->clk_ahb); 1209 if (ret) { 1210 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret); 1211 goto error_assert_reset; 1212 } 1213 1214 ret = clk_prepare_enable(host->clk_mmc); 1215 if (ret) { 1216 dev_err(host->dev, "Enable mmc clk err %d\n", ret); 1217 goto error_disable_clk_ahb; 1218 } 1219 1220 ret = clk_prepare_enable(host->clk_output); 1221 if (ret) { 1222 dev_err(host->dev, "Enable output clk err %d\n", ret); 1223 goto error_disable_clk_mmc; 1224 } 1225 1226 ret = clk_prepare_enable(host->clk_sample); 1227 if (ret) { 1228 dev_err(host->dev, "Enable sample clk err %d\n", ret); 1229 goto error_disable_clk_output; 1230 } 1231 1232 /* 1233 * Sometimes the controller asserts the irq on boot for some reason, 1234 * make sure the controller is in a sane state before enabling irqs. 1235 */ 1236 ret = sunxi_mmc_reset_host(host); 1237 if (ret) 1238 goto error_disable_clk_sample; 1239 1240 return 0; 1241 1242 error_disable_clk_sample: 1243 clk_disable_unprepare(host->clk_sample); 1244 error_disable_clk_output: 1245 clk_disable_unprepare(host->clk_output); 1246 error_disable_clk_mmc: 1247 clk_disable_unprepare(host->clk_mmc); 1248 error_disable_clk_ahb: 1249 clk_disable_unprepare(host->clk_ahb); 1250 error_assert_reset: 1251 if (!IS_ERR(host->reset)) 1252 reset_control_assert(host->reset); 1253 return ret; 1254 } 1255 1256 static void sunxi_mmc_disable(struct sunxi_mmc_host *host) 1257 { 1258 sunxi_mmc_reset_host(host); 1259 1260 clk_disable_unprepare(host->clk_sample); 1261 clk_disable_unprepare(host->clk_output); 1262 clk_disable_unprepare(host->clk_mmc); 1263 clk_disable_unprepare(host->clk_ahb); 1264 1265 if (!IS_ERR(host->reset)) 1266 reset_control_assert(host->reset); 1267 } 1268 1269 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 1270 struct platform_device *pdev) 1271 { 1272 int ret; 1273 1274 host->cfg = of_device_get_match_data(&pdev->dev); 1275 if (!host->cfg) 1276 return -EINVAL; 1277 1278 ret = mmc_regulator_get_supply(host->mmc); 1279 if (ret) 1280 return ret; 1281 1282 host->reg_base = devm_ioremap_resource(&pdev->dev, 1283 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 1284 if (IS_ERR(host->reg_base)) 1285 return PTR_ERR(host->reg_base); 1286 1287 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1288 if (IS_ERR(host->clk_ahb)) { 1289 dev_err(&pdev->dev, "Could not get ahb clock\n"); 1290 return PTR_ERR(host->clk_ahb); 1291 } 1292 1293 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 1294 if (IS_ERR(host->clk_mmc)) { 1295 dev_err(&pdev->dev, "Could not get mmc clock\n"); 1296 return PTR_ERR(host->clk_mmc); 1297 } 1298 1299 if (host->cfg->clk_delays) { 1300 host->clk_output = devm_clk_get(&pdev->dev, "output"); 1301 if (IS_ERR(host->clk_output)) { 1302 dev_err(&pdev->dev, "Could not get output clock\n"); 1303 return PTR_ERR(host->clk_output); 1304 } 1305 1306 host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 1307 if (IS_ERR(host->clk_sample)) { 1308 dev_err(&pdev->dev, "Could not get sample clock\n"); 1309 return PTR_ERR(host->clk_sample); 1310 } 1311 } 1312 1313 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1314 "ahb"); 1315 if (PTR_ERR(host->reset) == -EPROBE_DEFER) 1316 return PTR_ERR(host->reset); 1317 1318 ret = sunxi_mmc_enable(host); 1319 if (ret) 1320 return ret; 1321 1322 host->irq = platform_get_irq(pdev, 0); 1323 if (host->irq <= 0) { 1324 ret = -EINVAL; 1325 goto error_disable_mmc; 1326 } 1327 1328 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 1329 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 1330 1331 error_disable_mmc: 1332 sunxi_mmc_disable(host); 1333 return ret; 1334 } 1335 1336 static int sunxi_mmc_probe(struct platform_device *pdev) 1337 { 1338 struct sunxi_mmc_host *host; 1339 struct mmc_host *mmc; 1340 int ret; 1341 1342 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 1343 if (!mmc) { 1344 dev_err(&pdev->dev, "mmc alloc host failed\n"); 1345 return -ENOMEM; 1346 } 1347 platform_set_drvdata(pdev, mmc); 1348 1349 host = mmc_priv(mmc); 1350 host->dev = &pdev->dev; 1351 host->mmc = mmc; 1352 spin_lock_init(&host->lock); 1353 1354 ret = sunxi_mmc_resource_request(host, pdev); 1355 if (ret) 1356 goto error_free_host; 1357 1358 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 1359 &host->sg_dma, GFP_KERNEL); 1360 if (!host->sg_cpu) { 1361 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 1362 ret = -ENOMEM; 1363 goto error_free_host; 1364 } 1365 1366 if (host->cfg->ccu_has_timings_switch) { 1367 /* 1368 * Supports both old and new timing modes. 1369 * Try setting the clk to new timing mode. 1370 */ 1371 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 1372 1373 /* And check the result */ 1374 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc); 1375 if (ret < 0) { 1376 /* 1377 * For whatever reason we were not able to get 1378 * the current active mode. Default to old mode. 1379 */ 1380 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n"); 1381 host->use_new_timings = false; 1382 } else { 1383 host->use_new_timings = !!ret; 1384 } 1385 } else if (host->cfg->needs_new_timings) { 1386 /* Supports new timing mode only */ 1387 host->use_new_timings = true; 1388 } 1389 1390 mmc->ops = &sunxi_mmc_ops; 1391 mmc->max_blk_count = 8192; 1392 mmc->max_blk_size = 4096; 1393 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 1394 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); 1395 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 1396 /* 400kHz ~ 52MHz */ 1397 mmc->f_min = 400000; 1398 mmc->f_max = 52000000; 1399 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1400 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; 1401 1402 /* 1403 * Some H5 devices do not have signal traces precise enough to 1404 * use HS DDR mode for their eMMC chips. 1405 * 1406 * We still enable HS DDR modes for all the other controller 1407 * variants that support them. 1408 */ 1409 if ((host->cfg->clk_delays || host->use_new_timings) && 1410 !of_device_is_compatible(pdev->dev.of_node, 1411 "allwinner,sun50i-h5-emmc")) 1412 mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1413 1414 ret = mmc_of_parse(mmc); 1415 if (ret) 1416 goto error_free_dma; 1417 1418 ret = sunxi_mmc_init_host(host); 1419 if (ret) 1420 goto error_free_dma; 1421 1422 pm_runtime_set_active(&pdev->dev); 1423 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1424 pm_runtime_use_autosuspend(&pdev->dev); 1425 pm_runtime_enable(&pdev->dev); 1426 1427 ret = mmc_add_host(mmc); 1428 if (ret) 1429 goto error_free_dma; 1430 1431 dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n", 1432 mmc->max_req_size >> 10, 1433 host->use_new_timings ? ", uses new timings mode" : ""); 1434 1435 return 0; 1436 1437 error_free_dma: 1438 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1439 error_free_host: 1440 mmc_free_host(mmc); 1441 return ret; 1442 } 1443 1444 static int sunxi_mmc_remove(struct platform_device *pdev) 1445 { 1446 struct mmc_host *mmc = platform_get_drvdata(pdev); 1447 struct sunxi_mmc_host *host = mmc_priv(mmc); 1448 1449 mmc_remove_host(mmc); 1450 pm_runtime_force_suspend(&pdev->dev); 1451 disable_irq(host->irq); 1452 sunxi_mmc_disable(host); 1453 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1454 mmc_free_host(mmc); 1455 1456 return 0; 1457 } 1458 1459 #ifdef CONFIG_PM 1460 static int sunxi_mmc_runtime_resume(struct device *dev) 1461 { 1462 struct mmc_host *mmc = dev_get_drvdata(dev); 1463 struct sunxi_mmc_host *host = mmc_priv(mmc); 1464 int ret; 1465 1466 ret = sunxi_mmc_enable(host); 1467 if (ret) 1468 return ret; 1469 1470 sunxi_mmc_init_host(host); 1471 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width); 1472 sunxi_mmc_set_clk(host, &mmc->ios); 1473 enable_irq(host->irq); 1474 1475 return 0; 1476 } 1477 1478 static int sunxi_mmc_runtime_suspend(struct device *dev) 1479 { 1480 struct mmc_host *mmc = dev_get_drvdata(dev); 1481 struct sunxi_mmc_host *host = mmc_priv(mmc); 1482 1483 /* 1484 * When clocks are off, it's possible receiving 1485 * fake interrupts, which will stall the system. 1486 * Disabling the irq will prevent this. 1487 */ 1488 disable_irq(host->irq); 1489 sunxi_mmc_reset_host(host); 1490 sunxi_mmc_disable(host); 1491 1492 return 0; 1493 } 1494 #endif 1495 1496 static const struct dev_pm_ops sunxi_mmc_pm_ops = { 1497 SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend, 1498 sunxi_mmc_runtime_resume, 1499 NULL) 1500 }; 1501 1502 static struct platform_driver sunxi_mmc_driver = { 1503 .driver = { 1504 .name = "sunxi-mmc", 1505 .of_match_table = of_match_ptr(sunxi_mmc_of_match), 1506 .pm = &sunxi_mmc_pm_ops, 1507 }, 1508 .probe = sunxi_mmc_probe, 1509 .remove = sunxi_mmc_remove, 1510 }; 1511 module_platform_driver(sunxi_mmc_driver); 1512 1513 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 1514 MODULE_LICENSE("GPL v2"); 1515 MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>"); 1516 MODULE_ALIAS("platform:sunxi-mmc"); 1517