1 /* 2 * Driver for sunxi SD/MMC host controllers 3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 6 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch> 7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 8 * (C) Copyright 2017 Sootech SA 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/clk/sunxi-ng.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/err.h> 22 #include <linux/gpio.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/core.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/sd.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 #include <linux/module.h> 34 #include <linux/of_address.h> 35 #include <linux/of_gpio.h> 36 #include <linux/of_platform.h> 37 #include <linux/platform_device.h> 38 #include <linux/regulator/consumer.h> 39 #include <linux/reset.h> 40 #include <linux/scatterlist.h> 41 #include <linux/slab.h> 42 #include <linux/spinlock.h> 43 44 /* register offset definitions */ 45 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 46 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 47 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 48 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 49 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 50 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 51 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 52 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 53 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 54 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 55 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 56 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 57 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 58 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 59 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 60 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 61 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 62 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 63 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 64 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 65 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 66 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 67 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 68 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 69 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 70 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 71 #define SDXC_REG_CHDA (0x90) 72 #define SDXC_REG_CBDA (0x94) 73 74 /* New registers introduced in A64 */ 75 #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ 76 #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ 77 #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ 78 #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ 79 #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ 80 81 #define mmc_readl(host, reg) \ 82 readl((host)->reg_base + SDXC_##reg) 83 #define mmc_writel(host, reg, value) \ 84 writel((value), (host)->reg_base + SDXC_##reg) 85 86 /* global control register bits */ 87 #define SDXC_SOFT_RESET BIT(0) 88 #define SDXC_FIFO_RESET BIT(1) 89 #define SDXC_DMA_RESET BIT(2) 90 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 91 #define SDXC_DMA_ENABLE_BIT BIT(5) 92 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 93 #define SDXC_POSEDGE_LATCH_DATA BIT(9) 94 #define SDXC_DDR_MODE BIT(10) 95 #define SDXC_MEMORY_ACCESS_DONE BIT(29) 96 #define SDXC_ACCESS_DONE_DIRECT BIT(30) 97 #define SDXC_ACCESS_BY_AHB BIT(31) 98 #define SDXC_ACCESS_BY_DMA (0 << 31) 99 #define SDXC_HARDWARE_RESET \ 100 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 101 102 /* clock control bits */ 103 #define SDXC_MASK_DATA0 BIT(31) 104 #define SDXC_CARD_CLOCK_ON BIT(16) 105 #define SDXC_LOW_POWER_ON BIT(17) 106 107 /* bus width */ 108 #define SDXC_WIDTH1 0 109 #define SDXC_WIDTH4 1 110 #define SDXC_WIDTH8 2 111 112 /* smc command bits */ 113 #define SDXC_RESP_EXPIRE BIT(6) 114 #define SDXC_LONG_RESPONSE BIT(7) 115 #define SDXC_CHECK_RESPONSE_CRC BIT(8) 116 #define SDXC_DATA_EXPIRE BIT(9) 117 #define SDXC_WRITE BIT(10) 118 #define SDXC_SEQUENCE_MODE BIT(11) 119 #define SDXC_SEND_AUTO_STOP BIT(12) 120 #define SDXC_WAIT_PRE_OVER BIT(13) 121 #define SDXC_STOP_ABORT_CMD BIT(14) 122 #define SDXC_SEND_INIT_SEQUENCE BIT(15) 123 #define SDXC_UPCLK_ONLY BIT(21) 124 #define SDXC_READ_CEATA_DEV BIT(22) 125 #define SDXC_CCS_EXPIRE BIT(23) 126 #define SDXC_ENABLE_BIT_BOOT BIT(24) 127 #define SDXC_ALT_BOOT_OPTIONS BIT(25) 128 #define SDXC_BOOT_ACK_EXPIRE BIT(26) 129 #define SDXC_BOOT_ABORT BIT(27) 130 #define SDXC_VOLTAGE_SWITCH BIT(28) 131 #define SDXC_USE_HOLD_REGISTER BIT(29) 132 #define SDXC_START BIT(31) 133 134 /* interrupt bits */ 135 #define SDXC_RESP_ERROR BIT(1) 136 #define SDXC_COMMAND_DONE BIT(2) 137 #define SDXC_DATA_OVER BIT(3) 138 #define SDXC_TX_DATA_REQUEST BIT(4) 139 #define SDXC_RX_DATA_REQUEST BIT(5) 140 #define SDXC_RESP_CRC_ERROR BIT(6) 141 #define SDXC_DATA_CRC_ERROR BIT(7) 142 #define SDXC_RESP_TIMEOUT BIT(8) 143 #define SDXC_DATA_TIMEOUT BIT(9) 144 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 145 #define SDXC_FIFO_RUN_ERROR BIT(11) 146 #define SDXC_HARD_WARE_LOCKED BIT(12) 147 #define SDXC_START_BIT_ERROR BIT(13) 148 #define SDXC_AUTO_COMMAND_DONE BIT(14) 149 #define SDXC_END_BIT_ERROR BIT(15) 150 #define SDXC_SDIO_INTERRUPT BIT(16) 151 #define SDXC_CARD_INSERT BIT(30) 152 #define SDXC_CARD_REMOVE BIT(31) 153 #define SDXC_INTERRUPT_ERROR_BIT \ 154 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 155 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 156 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 157 #define SDXC_INTERRUPT_DONE_BIT \ 158 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 159 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 160 161 /* status */ 162 #define SDXC_RXWL_FLAG BIT(0) 163 #define SDXC_TXWL_FLAG BIT(1) 164 #define SDXC_FIFO_EMPTY BIT(2) 165 #define SDXC_FIFO_FULL BIT(3) 166 #define SDXC_CARD_PRESENT BIT(8) 167 #define SDXC_CARD_DATA_BUSY BIT(9) 168 #define SDXC_DATA_FSM_BUSY BIT(10) 169 #define SDXC_DMA_REQUEST BIT(31) 170 #define SDXC_FIFO_SIZE 16 171 172 /* Function select */ 173 #define SDXC_CEATA_ON (0xceaa << 16) 174 #define SDXC_SEND_IRQ_RESPONSE BIT(0) 175 #define SDXC_SDIO_READ_WAIT BIT(1) 176 #define SDXC_ABORT_READ_DATA BIT(2) 177 #define SDXC_SEND_CCSD BIT(8) 178 #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 179 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 180 181 /* IDMA controller bus mod bit field */ 182 #define SDXC_IDMAC_SOFT_RESET BIT(0) 183 #define SDXC_IDMAC_FIX_BURST BIT(1) 184 #define SDXC_IDMAC_IDMA_ON BIT(7) 185 #define SDXC_IDMAC_REFETCH_DES BIT(31) 186 187 /* IDMA status bit field */ 188 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 189 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 190 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 191 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 192 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 193 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 194 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 195 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 196 #define SDXC_IDMAC_IDLE (0 << 13) 197 #define SDXC_IDMAC_SUSPEND (1 << 13) 198 #define SDXC_IDMAC_DESC_READ (2 << 13) 199 #define SDXC_IDMAC_DESC_CHECK (3 << 13) 200 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 201 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 202 #define SDXC_IDMAC_READ (6 << 13) 203 #define SDXC_IDMAC_WRITE (7 << 13) 204 #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 205 206 /* 207 * If the idma-des-size-bits of property is ie 13, bufsize bits are: 208 * Bits 0-12: buf1 size 209 * Bits 13-25: buf2 size 210 * Bits 26-31: not used 211 * Since we only ever set buf1 size, we can simply store it directly. 212 */ 213 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 214 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 215 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 216 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 217 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 218 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 219 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 220 221 #define SDXC_CLK_400K 0 222 #define SDXC_CLK_25M 1 223 #define SDXC_CLK_50M 2 224 #define SDXC_CLK_50M_DDR 3 225 #define SDXC_CLK_50M_DDR_8BIT 4 226 227 #define SDXC_2X_TIMING_MODE BIT(31) 228 229 #define SDXC_CAL_START BIT(15) 230 #define SDXC_CAL_DONE BIT(14) 231 #define SDXC_CAL_DL_SHIFT 8 232 #define SDXC_CAL_DL_SW_EN BIT(7) 233 #define SDXC_CAL_DL_SW_SHIFT 0 234 #define SDXC_CAL_DL_MASK 0x3f 235 236 #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/ 237 238 struct sunxi_mmc_clk_delay { 239 u32 output; 240 u32 sample; 241 }; 242 243 struct sunxi_idma_des { 244 __le32 config; 245 __le32 buf_size; 246 __le32 buf_addr_ptr1; 247 __le32 buf_addr_ptr2; 248 }; 249 250 struct sunxi_mmc_cfg { 251 u32 idma_des_size_bits; 252 const struct sunxi_mmc_clk_delay *clk_delays; 253 254 /* does the IP block support autocalibration? */ 255 bool can_calibrate; 256 257 /* Does DATA0 needs to be masked while the clock is updated */ 258 bool mask_data0; 259 260 /* hardware only supports new timing mode */ 261 bool needs_new_timings; 262 263 /* hardware can switch between old and new timing modes */ 264 bool has_timings_switch; 265 }; 266 267 struct sunxi_mmc_host { 268 struct device *dev; 269 struct mmc_host *mmc; 270 struct reset_control *reset; 271 const struct sunxi_mmc_cfg *cfg; 272 273 /* IO mapping base */ 274 void __iomem *reg_base; 275 276 /* clock management */ 277 struct clk *clk_ahb; 278 struct clk *clk_mmc; 279 struct clk *clk_sample; 280 struct clk *clk_output; 281 282 /* irq */ 283 spinlock_t lock; 284 int irq; 285 u32 int_sum; 286 u32 sdio_imask; 287 288 /* dma */ 289 dma_addr_t sg_dma; 290 void *sg_cpu; 291 bool wait_dma; 292 293 struct mmc_request *mrq; 294 struct mmc_request *manual_stop_mrq; 295 int ferror; 296 297 /* vqmmc */ 298 bool vqmmc_enabled; 299 300 /* timings */ 301 bool use_new_timings; 302 }; 303 304 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 305 { 306 unsigned long expire = jiffies + msecs_to_jiffies(250); 307 u32 rval; 308 309 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 310 do { 311 rval = mmc_readl(host, REG_GCTRL); 312 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 313 314 if (rval & SDXC_HARDWARE_RESET) { 315 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 316 return -EIO; 317 } 318 319 return 0; 320 } 321 322 static int sunxi_mmc_init_host(struct mmc_host *mmc) 323 { 324 u32 rval; 325 struct sunxi_mmc_host *host = mmc_priv(mmc); 326 327 if (sunxi_mmc_reset_host(host)) 328 return -EIO; 329 330 /* 331 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8 332 * 333 * TODO: sun9i has a larger FIFO and supports higher trigger values 334 */ 335 mmc_writel(host, REG_FTRGL, 0x20070008); 336 /* Maximum timeout value */ 337 mmc_writel(host, REG_TMOUT, 0xffffffff); 338 /* Unmask SDIO interrupt if needed */ 339 mmc_writel(host, REG_IMASK, host->sdio_imask); 340 /* Clear all pending interrupts */ 341 mmc_writel(host, REG_RINTR, 0xffffffff); 342 /* Debug register? undocumented */ 343 mmc_writel(host, REG_DBGC, 0xdeb); 344 /* Enable CEATA support */ 345 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 346 /* Set DMA descriptor list base address */ 347 mmc_writel(host, REG_DLBA, host->sg_dma); 348 349 rval = mmc_readl(host, REG_GCTRL); 350 rval |= SDXC_INTERRUPT_ENABLE_BIT; 351 /* Undocumented, but found in Allwinner code */ 352 rval &= ~SDXC_ACCESS_DONE_DIRECT; 353 mmc_writel(host, REG_GCTRL, rval); 354 355 return 0; 356 } 357 358 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 359 struct mmc_data *data) 360 { 361 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 362 dma_addr_t next_desc = host->sg_dma; 363 int i, max_len = (1 << host->cfg->idma_des_size_bits); 364 365 for (i = 0; i < data->sg_len; i++) { 366 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | 367 SDXC_IDMAC_DES0_OWN | 368 SDXC_IDMAC_DES0_DIC); 369 370 if (data->sg[i].length == max_len) 371 pdes[i].buf_size = 0; /* 0 == max_len */ 372 else 373 pdes[i].buf_size = cpu_to_le32(data->sg[i].length); 374 375 next_desc += sizeof(struct sunxi_idma_des); 376 pdes[i].buf_addr_ptr1 = 377 cpu_to_le32(sg_dma_address(&data->sg[i])); 378 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc); 379 } 380 381 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); 382 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | 383 SDXC_IDMAC_DES0_ER); 384 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); 385 pdes[i - 1].buf_addr_ptr2 = 0; 386 387 /* 388 * Avoid the io-store starting the idmac hitting io-mem before the 389 * descriptors hit the main-mem. 390 */ 391 wmb(); 392 } 393 394 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 395 struct mmc_data *data) 396 { 397 u32 i, dma_len; 398 struct scatterlist *sg; 399 400 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 401 mmc_get_dma_dir(data)); 402 if (dma_len == 0) { 403 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 404 return -ENOMEM; 405 } 406 407 for_each_sg(data->sg, sg, data->sg_len, i) { 408 if (sg->offset & 3 || sg->length & 3) { 409 dev_err(mmc_dev(host->mmc), 410 "unaligned scatterlist: os %x length %d\n", 411 sg->offset, sg->length); 412 return -EINVAL; 413 } 414 } 415 416 return 0; 417 } 418 419 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 420 struct mmc_data *data) 421 { 422 u32 rval; 423 424 sunxi_mmc_init_idma_des(host, data); 425 426 rval = mmc_readl(host, REG_GCTRL); 427 rval |= SDXC_DMA_ENABLE_BIT; 428 mmc_writel(host, REG_GCTRL, rval); 429 rval |= SDXC_DMA_RESET; 430 mmc_writel(host, REG_GCTRL, rval); 431 432 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 433 434 if (!(data->flags & MMC_DATA_WRITE)) 435 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 436 437 mmc_writel(host, REG_DMAC, 438 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 439 } 440 441 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 442 struct mmc_request *req) 443 { 444 u32 arg, cmd_val, ri; 445 unsigned long expire = jiffies + msecs_to_jiffies(1000); 446 447 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 448 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 449 450 if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 451 cmd_val |= SD_IO_RW_DIRECT; 452 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 453 ((req->cmd->arg >> 28) & 0x7); 454 } else { 455 cmd_val |= MMC_STOP_TRANSMISSION; 456 arg = 0; 457 } 458 459 mmc_writel(host, REG_CARG, arg); 460 mmc_writel(host, REG_CMDR, cmd_val); 461 462 do { 463 ri = mmc_readl(host, REG_RINTR); 464 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 465 time_before(jiffies, expire)); 466 467 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 468 dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 469 if (req->stop) 470 req->stop->resp[0] = -ETIMEDOUT; 471 } else { 472 if (req->stop) 473 req->stop->resp[0] = mmc_readl(host, REG_RESP0); 474 } 475 476 mmc_writel(host, REG_RINTR, 0xffff); 477 } 478 479 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 480 { 481 struct mmc_command *cmd = host->mrq->cmd; 482 struct mmc_data *data = host->mrq->data; 483 484 /* For some cmds timeout is normal with sd/mmc cards */ 485 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 486 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 487 cmd->opcode == SD_IO_RW_DIRECT)) 488 return; 489 490 dev_dbg(mmc_dev(host->mmc), 491 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 492 host->mmc->index, cmd->opcode, 493 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 494 host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 495 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 496 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 497 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 498 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 499 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 500 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 501 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 502 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 503 ); 504 } 505 506 /* Called in interrupt context! */ 507 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 508 { 509 struct mmc_request *mrq = host->mrq; 510 struct mmc_data *data = mrq->data; 511 u32 rval; 512 513 mmc_writel(host, REG_IMASK, host->sdio_imask); 514 mmc_writel(host, REG_IDIE, 0); 515 516 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 517 sunxi_mmc_dump_errinfo(host); 518 mrq->cmd->error = -ETIMEDOUT; 519 520 if (data) { 521 data->error = -ETIMEDOUT; 522 host->manual_stop_mrq = mrq; 523 } 524 525 if (mrq->stop) 526 mrq->stop->error = -ETIMEDOUT; 527 } else { 528 if (mrq->cmd->flags & MMC_RSP_136) { 529 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 530 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 531 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 532 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 533 } else { 534 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 535 } 536 537 if (data) 538 data->bytes_xfered = data->blocks * data->blksz; 539 } 540 541 if (data) { 542 mmc_writel(host, REG_IDST, 0x337); 543 mmc_writel(host, REG_DMAC, 0); 544 rval = mmc_readl(host, REG_GCTRL); 545 rval |= SDXC_DMA_RESET; 546 mmc_writel(host, REG_GCTRL, rval); 547 rval &= ~SDXC_DMA_ENABLE_BIT; 548 mmc_writel(host, REG_GCTRL, rval); 549 rval |= SDXC_FIFO_RESET; 550 mmc_writel(host, REG_GCTRL, rval); 551 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 552 mmc_get_dma_dir(data)); 553 } 554 555 mmc_writel(host, REG_RINTR, 0xffff); 556 557 host->mrq = NULL; 558 host->int_sum = 0; 559 host->wait_dma = false; 560 561 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 562 } 563 564 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 565 { 566 struct sunxi_mmc_host *host = dev_id; 567 struct mmc_request *mrq; 568 u32 msk_int, idma_int; 569 bool finalize = false; 570 bool sdio_int = false; 571 irqreturn_t ret = IRQ_HANDLED; 572 573 spin_lock(&host->lock); 574 575 idma_int = mmc_readl(host, REG_IDST); 576 msk_int = mmc_readl(host, REG_MISTA); 577 578 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 579 host->mrq, msk_int, idma_int); 580 581 mrq = host->mrq; 582 if (mrq) { 583 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 584 host->wait_dma = false; 585 586 host->int_sum |= msk_int; 587 588 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 589 if ((host->int_sum & SDXC_RESP_TIMEOUT) && 590 !(host->int_sum & SDXC_COMMAND_DONE)) 591 mmc_writel(host, REG_IMASK, 592 host->sdio_imask | SDXC_COMMAND_DONE); 593 /* Don't wait for dma on error */ 594 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 595 finalize = true; 596 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 597 !host->wait_dma) 598 finalize = true; 599 } 600 601 if (msk_int & SDXC_SDIO_INTERRUPT) 602 sdio_int = true; 603 604 mmc_writel(host, REG_RINTR, msk_int); 605 mmc_writel(host, REG_IDST, idma_int); 606 607 if (finalize) 608 ret = sunxi_mmc_finalize_request(host); 609 610 spin_unlock(&host->lock); 611 612 if (finalize && ret == IRQ_HANDLED) 613 mmc_request_done(host->mmc, mrq); 614 615 if (sdio_int) 616 mmc_signal_sdio_irq(host->mmc); 617 618 return ret; 619 } 620 621 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 622 { 623 struct sunxi_mmc_host *host = dev_id; 624 struct mmc_request *mrq; 625 unsigned long iflags; 626 627 spin_lock_irqsave(&host->lock, iflags); 628 mrq = host->manual_stop_mrq; 629 spin_unlock_irqrestore(&host->lock, iflags); 630 631 if (!mrq) { 632 dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 633 return IRQ_HANDLED; 634 } 635 636 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 637 638 /* 639 * We will never have more than one outstanding request, 640 * and we do not complete the request until after 641 * we've cleared host->manual_stop_mrq so we do not need to 642 * spin lock this function. 643 * Additionally we have wait states within this function 644 * so having it in a lock is a very bad idea. 645 */ 646 sunxi_mmc_send_manual_stop(host, mrq); 647 648 spin_lock_irqsave(&host->lock, iflags); 649 host->manual_stop_mrq = NULL; 650 spin_unlock_irqrestore(&host->lock, iflags); 651 652 mmc_request_done(host->mmc, mrq); 653 654 return IRQ_HANDLED; 655 } 656 657 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 658 { 659 unsigned long expire = jiffies + msecs_to_jiffies(750); 660 u32 rval; 661 662 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n", 663 oclk_en ? "en" : "dis"); 664 665 rval = mmc_readl(host, REG_CLKCR); 666 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0); 667 668 if (oclk_en) 669 rval |= SDXC_CARD_CLOCK_ON; 670 if (host->cfg->mask_data0) 671 rval |= SDXC_MASK_DATA0; 672 673 mmc_writel(host, REG_CLKCR, rval); 674 675 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 676 mmc_writel(host, REG_CMDR, rval); 677 678 do { 679 rval = mmc_readl(host, REG_CMDR); 680 } while (time_before(jiffies, expire) && (rval & SDXC_START)); 681 682 /* clear irq status bits set by the command */ 683 mmc_writel(host, REG_RINTR, 684 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 685 686 if (rval & SDXC_START) { 687 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 688 return -EIO; 689 } 690 691 if (host->cfg->mask_data0) { 692 rval = mmc_readl(host, REG_CLKCR); 693 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0); 694 } 695 696 return 0; 697 } 698 699 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) 700 { 701 if (!host->cfg->can_calibrate) 702 return 0; 703 704 /* 705 * FIXME: 706 * This is not clear how the calibration is supposed to work 707 * yet. The best rate have been obtained by simply setting the 708 * delay to 0, as Allwinner does in its BSP. 709 * 710 * The only mode that doesn't have such a delay is HS400, that 711 * is in itself a TODO. 712 */ 713 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); 714 715 return 0; 716 } 717 718 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 719 struct mmc_ios *ios, u32 rate) 720 { 721 int index; 722 723 /* clk controller delays not used under new timings mode */ 724 if (host->use_new_timings) 725 return 0; 726 727 /* some old controllers don't support delays */ 728 if (!host->cfg->clk_delays) 729 return 0; 730 731 /* determine delays */ 732 if (rate <= 400000) { 733 index = SDXC_CLK_400K; 734 } else if (rate <= 25000000) { 735 index = SDXC_CLK_25M; 736 } else if (rate <= 52000000) { 737 if (ios->timing != MMC_TIMING_UHS_DDR50 && 738 ios->timing != MMC_TIMING_MMC_DDR52) { 739 index = SDXC_CLK_50M; 740 } else if (ios->bus_width == MMC_BUS_WIDTH_8) { 741 index = SDXC_CLK_50M_DDR_8BIT; 742 } else { 743 index = SDXC_CLK_50M_DDR; 744 } 745 } else { 746 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n"); 747 return -EINVAL; 748 } 749 750 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); 751 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); 752 753 return 0; 754 } 755 756 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 757 struct mmc_ios *ios) 758 { 759 struct mmc_host *mmc = host->mmc; 760 long rate; 761 u32 rval, clock = ios->clock, div = 1; 762 int ret; 763 764 ret = sunxi_mmc_oclk_onoff(host, 0); 765 if (ret) 766 return ret; 767 768 /* Our clock is gated now */ 769 mmc->actual_clock = 0; 770 771 if (!ios->clock) 772 return 0; 773 774 /* 775 * Under the old timing mode, 8 bit DDR requires the module 776 * clock to be double the card clock. Under the new timing 777 * mode, all DDR modes require a doubled module clock. 778 * 779 * We currently only support the standard MMC DDR52 mode. 780 * This block should be updated once support for other DDR 781 * modes is added. 782 */ 783 if (ios->timing == MMC_TIMING_MMC_DDR52 && 784 (host->use_new_timings || 785 ios->bus_width == MMC_BUS_WIDTH_8)) { 786 div = 2; 787 clock <<= 1; 788 } 789 790 if (host->use_new_timings && host->cfg->has_timings_switch) { 791 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 792 if (ret) { 793 dev_err(mmc_dev(mmc), 794 "error setting new timing mode\n"); 795 return ret; 796 } 797 } 798 799 rate = clk_round_rate(host->clk_mmc, clock); 800 if (rate < 0) { 801 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n", 802 clock, rate); 803 return rate; 804 } 805 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n", 806 clock, rate); 807 808 /* setting clock rate */ 809 ret = clk_set_rate(host->clk_mmc, rate); 810 if (ret) { 811 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n", 812 rate, ret); 813 return ret; 814 } 815 816 /* set internal divider */ 817 rval = mmc_readl(host, REG_CLKCR); 818 rval &= ~0xff; 819 rval |= div - 1; 820 mmc_writel(host, REG_CLKCR, rval); 821 822 /* update card clock rate to account for internal divider */ 823 rate /= div; 824 825 if (host->use_new_timings) { 826 /* Don't touch the delay bits */ 827 rval = mmc_readl(host, REG_SD_NTSR); 828 rval |= SDXC_2X_TIMING_MODE; 829 mmc_writel(host, REG_SD_NTSR, rval); 830 } 831 832 /* sunxi_mmc_clk_set_phase expects the actual card clock rate */ 833 ret = sunxi_mmc_clk_set_phase(host, ios, rate); 834 if (ret) 835 return ret; 836 837 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); 838 if (ret) 839 return ret; 840 841 /* 842 * FIXME: 843 * 844 * In HS400 we'll also need to calibrate the data strobe 845 * signal. This should only happen on the MMC2 controller (at 846 * least on the A64). 847 */ 848 849 ret = sunxi_mmc_oclk_onoff(host, 1); 850 if (ret) 851 return ret; 852 853 /* And we just enabled our clock back */ 854 mmc->actual_clock = rate; 855 856 return 0; 857 } 858 859 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 860 { 861 struct sunxi_mmc_host *host = mmc_priv(mmc); 862 u32 rval; 863 864 /* Set the power state */ 865 switch (ios->power_mode) { 866 case MMC_POWER_ON: 867 break; 868 869 case MMC_POWER_UP: 870 if (!IS_ERR(mmc->supply.vmmc)) { 871 host->ferror = mmc_regulator_set_ocr(mmc, 872 mmc->supply.vmmc, 873 ios->vdd); 874 if (host->ferror) 875 return; 876 } 877 878 if (!IS_ERR(mmc->supply.vqmmc)) { 879 host->ferror = regulator_enable(mmc->supply.vqmmc); 880 if (host->ferror) { 881 dev_err(mmc_dev(mmc), 882 "failed to enable vqmmc\n"); 883 return; 884 } 885 host->vqmmc_enabled = true; 886 } 887 888 host->ferror = sunxi_mmc_init_host(mmc); 889 if (host->ferror) 890 return; 891 892 dev_dbg(mmc_dev(mmc), "power on!\n"); 893 break; 894 895 case MMC_POWER_OFF: 896 dev_dbg(mmc_dev(mmc), "power off!\n"); 897 sunxi_mmc_reset_host(host); 898 if (!IS_ERR(mmc->supply.vmmc)) 899 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 900 901 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) 902 regulator_disable(mmc->supply.vqmmc); 903 host->vqmmc_enabled = false; 904 break; 905 } 906 907 /* set bus width */ 908 switch (ios->bus_width) { 909 case MMC_BUS_WIDTH_1: 910 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 911 break; 912 case MMC_BUS_WIDTH_4: 913 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 914 break; 915 case MMC_BUS_WIDTH_8: 916 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 917 break; 918 } 919 920 /* set ddr mode */ 921 rval = mmc_readl(host, REG_GCTRL); 922 if (ios->timing == MMC_TIMING_UHS_DDR50 || 923 ios->timing == MMC_TIMING_MMC_DDR52) 924 rval |= SDXC_DDR_MODE; 925 else 926 rval &= ~SDXC_DDR_MODE; 927 mmc_writel(host, REG_GCTRL, rval); 928 929 /* set up clock */ 930 if (ios->power_mode) { 931 host->ferror = sunxi_mmc_clk_set_rate(host, ios); 932 /* Android code had a usleep_range(50000, 55000); here */ 933 } 934 } 935 936 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 937 { 938 /* vqmmc regulator is available */ 939 if (!IS_ERR(mmc->supply.vqmmc)) 940 return mmc_regulator_set_vqmmc(mmc, ios); 941 942 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 943 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) 944 return 0; 945 946 return -EINVAL; 947 } 948 949 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 950 { 951 struct sunxi_mmc_host *host = mmc_priv(mmc); 952 unsigned long flags; 953 u32 imask; 954 955 spin_lock_irqsave(&host->lock, flags); 956 957 imask = mmc_readl(host, REG_IMASK); 958 if (enable) { 959 host->sdio_imask = SDXC_SDIO_INTERRUPT; 960 imask |= SDXC_SDIO_INTERRUPT; 961 } else { 962 host->sdio_imask = 0; 963 imask &= ~SDXC_SDIO_INTERRUPT; 964 } 965 mmc_writel(host, REG_IMASK, imask); 966 spin_unlock_irqrestore(&host->lock, flags); 967 } 968 969 static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 970 { 971 struct sunxi_mmc_host *host = mmc_priv(mmc); 972 mmc_writel(host, REG_HWRST, 0); 973 udelay(10); 974 mmc_writel(host, REG_HWRST, 1); 975 udelay(300); 976 } 977 978 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 979 { 980 struct sunxi_mmc_host *host = mmc_priv(mmc); 981 struct mmc_command *cmd = mrq->cmd; 982 struct mmc_data *data = mrq->data; 983 unsigned long iflags; 984 u32 imask = SDXC_INTERRUPT_ERROR_BIT; 985 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 986 bool wait_dma = host->wait_dma; 987 int ret; 988 989 /* Check for set_ios errors (should never happen) */ 990 if (host->ferror) { 991 mrq->cmd->error = host->ferror; 992 mmc_request_done(mmc, mrq); 993 return; 994 } 995 996 if (data) { 997 ret = sunxi_mmc_map_dma(host, data); 998 if (ret < 0) { 999 dev_err(mmc_dev(mmc), "map DMA failed\n"); 1000 cmd->error = ret; 1001 data->error = ret; 1002 mmc_request_done(mmc, mrq); 1003 return; 1004 } 1005 } 1006 1007 if (cmd->opcode == MMC_GO_IDLE_STATE) { 1008 cmd_val |= SDXC_SEND_INIT_SEQUENCE; 1009 imask |= SDXC_COMMAND_DONE; 1010 } 1011 1012 if (cmd->flags & MMC_RSP_PRESENT) { 1013 cmd_val |= SDXC_RESP_EXPIRE; 1014 if (cmd->flags & MMC_RSP_136) 1015 cmd_val |= SDXC_LONG_RESPONSE; 1016 if (cmd->flags & MMC_RSP_CRC) 1017 cmd_val |= SDXC_CHECK_RESPONSE_CRC; 1018 1019 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 1020 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 1021 1022 if (cmd->data->stop) { 1023 imask |= SDXC_AUTO_COMMAND_DONE; 1024 cmd_val |= SDXC_SEND_AUTO_STOP; 1025 } else { 1026 imask |= SDXC_DATA_OVER; 1027 } 1028 1029 if (cmd->data->flags & MMC_DATA_WRITE) 1030 cmd_val |= SDXC_WRITE; 1031 else 1032 wait_dma = true; 1033 } else { 1034 imask |= SDXC_COMMAND_DONE; 1035 } 1036 } else { 1037 imask |= SDXC_COMMAND_DONE; 1038 } 1039 1040 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 1041 cmd_val & 0x3f, cmd_val, cmd->arg, imask, 1042 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 1043 1044 spin_lock_irqsave(&host->lock, iflags); 1045 1046 if (host->mrq || host->manual_stop_mrq) { 1047 spin_unlock_irqrestore(&host->lock, iflags); 1048 1049 if (data) 1050 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 1051 mmc_get_dma_dir(data)); 1052 1053 dev_err(mmc_dev(mmc), "request already pending\n"); 1054 mrq->cmd->error = -EBUSY; 1055 mmc_request_done(mmc, mrq); 1056 return; 1057 } 1058 1059 if (data) { 1060 mmc_writel(host, REG_BLKSZ, data->blksz); 1061 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 1062 sunxi_mmc_start_dma(host, data); 1063 } 1064 1065 host->mrq = mrq; 1066 host->wait_dma = wait_dma; 1067 mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 1068 mmc_writel(host, REG_CARG, cmd->arg); 1069 mmc_writel(host, REG_CMDR, cmd_val); 1070 1071 spin_unlock_irqrestore(&host->lock, iflags); 1072 } 1073 1074 static int sunxi_mmc_card_busy(struct mmc_host *mmc) 1075 { 1076 struct sunxi_mmc_host *host = mmc_priv(mmc); 1077 1078 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); 1079 } 1080 1081 static const struct mmc_host_ops sunxi_mmc_ops = { 1082 .request = sunxi_mmc_request, 1083 .set_ios = sunxi_mmc_set_ios, 1084 .get_ro = mmc_gpio_get_ro, 1085 .get_cd = mmc_gpio_get_cd, 1086 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 1087 .start_signal_voltage_switch = sunxi_mmc_volt_switch, 1088 .hw_reset = sunxi_mmc_hw_reset, 1089 .card_busy = sunxi_mmc_card_busy, 1090 }; 1091 1092 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { 1093 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1094 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1095 [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, 1096 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, 1097 /* Value from A83T "new timing mode". Works but might not be right. */ 1098 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, 1099 }; 1100 1101 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 1102 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1103 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1104 [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, 1105 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, 1106 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, 1107 }; 1108 1109 static const struct sunxi_mmc_cfg sun4i_a10_cfg = { 1110 .idma_des_size_bits = 13, 1111 .clk_delays = NULL, 1112 .can_calibrate = false, 1113 }; 1114 1115 static const struct sunxi_mmc_cfg sun5i_a13_cfg = { 1116 .idma_des_size_bits = 16, 1117 .clk_delays = NULL, 1118 .can_calibrate = false, 1119 }; 1120 1121 static const struct sunxi_mmc_cfg sun7i_a20_cfg = { 1122 .idma_des_size_bits = 16, 1123 .clk_delays = sunxi_mmc_clk_delays, 1124 .can_calibrate = false, 1125 }; 1126 1127 static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = { 1128 .idma_des_size_bits = 16, 1129 .clk_delays = sunxi_mmc_clk_delays, 1130 .can_calibrate = false, 1131 .has_timings_switch = true, 1132 }; 1133 1134 static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 1135 .idma_des_size_bits = 16, 1136 .clk_delays = sun9i_mmc_clk_delays, 1137 .can_calibrate = false, 1138 }; 1139 1140 static const struct sunxi_mmc_cfg sun50i_a64_cfg = { 1141 .idma_des_size_bits = 16, 1142 .clk_delays = NULL, 1143 .can_calibrate = true, 1144 .mask_data0 = true, 1145 .needs_new_timings = true, 1146 }; 1147 1148 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = { 1149 .idma_des_size_bits = 13, 1150 .clk_delays = NULL, 1151 .can_calibrate = true, 1152 }; 1153 1154 static const struct of_device_id sunxi_mmc_of_match[] = { 1155 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, 1156 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, 1157 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, 1158 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg }, 1159 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, 1160 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, 1161 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, 1162 { /* sentinel */ } 1163 }; 1164 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 1165 1166 static int sunxi_mmc_enable(struct sunxi_mmc_host *host) 1167 { 1168 int ret; 1169 1170 if (!IS_ERR(host->reset)) { 1171 ret = reset_control_reset(host->reset); 1172 if (ret) { 1173 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n", 1174 ret); 1175 return ret; 1176 } 1177 } 1178 1179 ret = clk_prepare_enable(host->clk_ahb); 1180 if (ret) { 1181 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret); 1182 goto error_assert_reset; 1183 } 1184 1185 ret = clk_prepare_enable(host->clk_mmc); 1186 if (ret) { 1187 dev_err(host->dev, "Enable mmc clk err %d\n", ret); 1188 goto error_disable_clk_ahb; 1189 } 1190 1191 ret = clk_prepare_enable(host->clk_output); 1192 if (ret) { 1193 dev_err(host->dev, "Enable output clk err %d\n", ret); 1194 goto error_disable_clk_mmc; 1195 } 1196 1197 ret = clk_prepare_enable(host->clk_sample); 1198 if (ret) { 1199 dev_err(host->dev, "Enable sample clk err %d\n", ret); 1200 goto error_disable_clk_output; 1201 } 1202 1203 /* 1204 * Sometimes the controller asserts the irq on boot for some reason, 1205 * make sure the controller is in a sane state before enabling irqs. 1206 */ 1207 ret = sunxi_mmc_reset_host(host); 1208 if (ret) 1209 goto error_disable_clk_sample; 1210 1211 return 0; 1212 1213 error_disable_clk_sample: 1214 clk_disable_unprepare(host->clk_sample); 1215 error_disable_clk_output: 1216 clk_disable_unprepare(host->clk_output); 1217 error_disable_clk_mmc: 1218 clk_disable_unprepare(host->clk_mmc); 1219 error_disable_clk_ahb: 1220 clk_disable_unprepare(host->clk_ahb); 1221 error_assert_reset: 1222 if (!IS_ERR(host->reset)) 1223 reset_control_assert(host->reset); 1224 return ret; 1225 } 1226 1227 static void sunxi_mmc_disable(struct sunxi_mmc_host *host) 1228 { 1229 sunxi_mmc_reset_host(host); 1230 1231 clk_disable_unprepare(host->clk_sample); 1232 clk_disable_unprepare(host->clk_output); 1233 clk_disable_unprepare(host->clk_mmc); 1234 clk_disable_unprepare(host->clk_ahb); 1235 1236 if (!IS_ERR(host->reset)) 1237 reset_control_assert(host->reset); 1238 } 1239 1240 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 1241 struct platform_device *pdev) 1242 { 1243 int ret; 1244 1245 host->cfg = of_device_get_match_data(&pdev->dev); 1246 if (!host->cfg) 1247 return -EINVAL; 1248 1249 ret = mmc_regulator_get_supply(host->mmc); 1250 if (ret) 1251 return ret; 1252 1253 host->reg_base = devm_ioremap_resource(&pdev->dev, 1254 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 1255 if (IS_ERR(host->reg_base)) 1256 return PTR_ERR(host->reg_base); 1257 1258 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1259 if (IS_ERR(host->clk_ahb)) { 1260 dev_err(&pdev->dev, "Could not get ahb clock\n"); 1261 return PTR_ERR(host->clk_ahb); 1262 } 1263 1264 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 1265 if (IS_ERR(host->clk_mmc)) { 1266 dev_err(&pdev->dev, "Could not get mmc clock\n"); 1267 return PTR_ERR(host->clk_mmc); 1268 } 1269 1270 if (host->cfg->clk_delays) { 1271 host->clk_output = devm_clk_get(&pdev->dev, "output"); 1272 if (IS_ERR(host->clk_output)) { 1273 dev_err(&pdev->dev, "Could not get output clock\n"); 1274 return PTR_ERR(host->clk_output); 1275 } 1276 1277 host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 1278 if (IS_ERR(host->clk_sample)) { 1279 dev_err(&pdev->dev, "Could not get sample clock\n"); 1280 return PTR_ERR(host->clk_sample); 1281 } 1282 } 1283 1284 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1285 "ahb"); 1286 if (PTR_ERR(host->reset) == -EPROBE_DEFER) 1287 return PTR_ERR(host->reset); 1288 1289 ret = sunxi_mmc_enable(host); 1290 if (ret) 1291 return ret; 1292 1293 host->irq = platform_get_irq(pdev, 0); 1294 if (host->irq <= 0) { 1295 ret = -EINVAL; 1296 goto error_disable_mmc; 1297 } 1298 1299 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 1300 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 1301 1302 error_disable_mmc: 1303 sunxi_mmc_disable(host); 1304 return ret; 1305 } 1306 1307 static int sunxi_mmc_probe(struct platform_device *pdev) 1308 { 1309 struct sunxi_mmc_host *host; 1310 struct mmc_host *mmc; 1311 int ret; 1312 1313 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 1314 if (!mmc) { 1315 dev_err(&pdev->dev, "mmc alloc host failed\n"); 1316 return -ENOMEM; 1317 } 1318 platform_set_drvdata(pdev, mmc); 1319 1320 host = mmc_priv(mmc); 1321 host->dev = &pdev->dev; 1322 host->mmc = mmc; 1323 spin_lock_init(&host->lock); 1324 1325 ret = sunxi_mmc_resource_request(host, pdev); 1326 if (ret) 1327 goto error_free_host; 1328 1329 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 1330 &host->sg_dma, GFP_KERNEL); 1331 if (!host->sg_cpu) { 1332 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 1333 ret = -ENOMEM; 1334 goto error_free_host; 1335 } 1336 1337 if (host->cfg->has_timings_switch) { 1338 /* 1339 * Supports both old and new timing modes. 1340 * Try setting the clk to new timing mode. 1341 */ 1342 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 1343 1344 /* And check the result */ 1345 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc); 1346 if (ret < 0) { 1347 /* 1348 * For whatever reason we were not able to get 1349 * the current active mode. Default to old mode. 1350 */ 1351 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n"); 1352 host->use_new_timings = false; 1353 } else { 1354 host->use_new_timings = !!ret; 1355 } 1356 } else if (host->cfg->needs_new_timings) { 1357 /* Supports new timing mode only */ 1358 host->use_new_timings = true; 1359 } 1360 1361 mmc->ops = &sunxi_mmc_ops; 1362 mmc->max_blk_count = 8192; 1363 mmc->max_blk_size = 4096; 1364 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 1365 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); 1366 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 1367 /* 400kHz ~ 52MHz */ 1368 mmc->f_min = 400000; 1369 mmc->f_max = 52000000; 1370 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1371 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; 1372 1373 if (host->cfg->clk_delays || host->use_new_timings) 1374 mmc->caps |= MMC_CAP_1_8V_DDR; 1375 1376 ret = mmc_of_parse(mmc); 1377 if (ret) 1378 goto error_free_dma; 1379 1380 ret = mmc_add_host(mmc); 1381 if (ret) 1382 goto error_free_dma; 1383 1384 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq); 1385 return 0; 1386 1387 error_free_dma: 1388 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1389 error_free_host: 1390 mmc_free_host(mmc); 1391 return ret; 1392 } 1393 1394 static int sunxi_mmc_remove(struct platform_device *pdev) 1395 { 1396 struct mmc_host *mmc = platform_get_drvdata(pdev); 1397 struct sunxi_mmc_host *host = mmc_priv(mmc); 1398 1399 mmc_remove_host(mmc); 1400 disable_irq(host->irq); 1401 sunxi_mmc_disable(host); 1402 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1403 mmc_free_host(mmc); 1404 1405 return 0; 1406 } 1407 1408 static struct platform_driver sunxi_mmc_driver = { 1409 .driver = { 1410 .name = "sunxi-mmc", 1411 .of_match_table = of_match_ptr(sunxi_mmc_of_match), 1412 }, 1413 .probe = sunxi_mmc_probe, 1414 .remove = sunxi_mmc_remove, 1415 }; 1416 module_platform_driver(sunxi_mmc_driver); 1417 1418 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 1419 MODULE_LICENSE("GPL v2"); 1420 MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>"); 1421 MODULE_ALIAS("platform:sunxi-mmc"); 1422